1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of_net.h> 11 #include <linux/netdevice.h> 12 #include <linux/phylink.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_platform.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/skbuff.h> 17 #include <net/switchdev.h> 18 19 #include <soc/mscc/ocelot_vcap.h> 20 #include <soc/mscc/ocelot_hsio.h> 21 #include "ocelot.h" 22 23 static const u32 ocelot_ana_regmap[] = { 24 REG(ANA_ADVLEARN, 0x009000), 25 REG(ANA_VLANMASK, 0x009004), 26 REG(ANA_PORT_B_DOMAIN, 0x009008), 27 REG(ANA_ANAGEFIL, 0x00900c), 28 REG(ANA_ANEVENTS, 0x009010), 29 REG(ANA_STORMLIMIT_BURST, 0x009014), 30 REG(ANA_STORMLIMIT_CFG, 0x009018), 31 REG(ANA_ISOLATED_PORTS, 0x009028), 32 REG(ANA_COMMUNITY_PORTS, 0x00902c), 33 REG(ANA_AUTOAGE, 0x009030), 34 REG(ANA_MACTOPTIONS, 0x009034), 35 REG(ANA_LEARNDISC, 0x009038), 36 REG(ANA_AGENCTRL, 0x00903c), 37 REG(ANA_MIRRORPORTS, 0x009040), 38 REG(ANA_EMIRRORPORTS, 0x009044), 39 REG(ANA_FLOODING, 0x009048), 40 REG(ANA_FLOODING_IPMC, 0x00904c), 41 REG(ANA_SFLOW_CFG, 0x009050), 42 REG(ANA_PORT_MODE, 0x009080), 43 REG(ANA_PGID_PGID, 0x008c00), 44 REG(ANA_TABLES_ANMOVED, 0x008b30), 45 REG(ANA_TABLES_MACHDATA, 0x008b34), 46 REG(ANA_TABLES_MACLDATA, 0x008b38), 47 REG(ANA_TABLES_MACACCESS, 0x008b3c), 48 REG(ANA_TABLES_MACTINDX, 0x008b40), 49 REG(ANA_TABLES_VLANACCESS, 0x008b44), 50 REG(ANA_TABLES_VLANTIDX, 0x008b48), 51 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 52 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 53 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 54 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 55 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 56 REG(ANA_MSTI_STATE, 0x008e00), 57 REG(ANA_PORT_VLAN_CFG, 0x007000), 58 REG(ANA_PORT_DROP_CFG, 0x007004), 59 REG(ANA_PORT_QOS_CFG, 0x007008), 60 REG(ANA_PORT_VCAP_CFG, 0x00700c), 61 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 62 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 63 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 64 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 65 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 66 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 67 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 68 REG(ANA_PORT_PORT_CFG, 0x007070), 69 REG(ANA_PORT_POL_CFG, 0x007074), 70 REG(ANA_PORT_PTP_CFG, 0x007078), 71 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 72 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 73 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 74 REG(ANA_PFC_PFC_CFG, 0x008800), 75 REG(ANA_PFC_PFC_TIMER, 0x008804), 76 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 77 REG(ANA_IPT_IPT, 0x008004), 78 REG(ANA_PPT_PPT, 0x008ac0), 79 REG(ANA_FID_MAP_FID_MAP, 0x000000), 80 REG(ANA_AGGR_CFG, 0x0090b4), 81 REG(ANA_CPUQ_CFG, 0x0090b8), 82 REG(ANA_CPUQ_CFG2, 0x0090bc), 83 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 84 REG(ANA_DSCP_CFG, 0x009100), 85 REG(ANA_DSCP_REWR_CFG, 0x009200), 86 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 87 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 88 REG(ANA_VRAP_CFG, 0x009280), 89 REG(ANA_VRAP_HDR_DATA, 0x009284), 90 REG(ANA_VRAP_HDR_MASK, 0x009288), 91 REG(ANA_DISCARD_CFG, 0x00928c), 92 REG(ANA_FID_CFG, 0x009290), 93 REG(ANA_POL_PIR_CFG, 0x004000), 94 REG(ANA_POL_CIR_CFG, 0x004004), 95 REG(ANA_POL_MODE_CFG, 0x004008), 96 REG(ANA_POL_PIR_STATE, 0x00400c), 97 REG(ANA_POL_CIR_STATE, 0x004010), 98 REG(ANA_POL_STATE, 0x004014), 99 REG(ANA_POL_FLOWC, 0x008b80), 100 REG(ANA_POL_HYST, 0x008bec), 101 REG(ANA_POL_MISC_CFG, 0x008bf0), 102 }; 103 104 static const u32 ocelot_qs_regmap[] = { 105 REG(QS_XTR_GRP_CFG, 0x000000), 106 REG(QS_XTR_RD, 0x000008), 107 REG(QS_XTR_FRM_PRUNING, 0x000010), 108 REG(QS_XTR_FLUSH, 0x000018), 109 REG(QS_XTR_DATA_PRESENT, 0x00001c), 110 REG(QS_XTR_CFG, 0x000020), 111 REG(QS_INJ_GRP_CFG, 0x000024), 112 REG(QS_INJ_WR, 0x00002c), 113 REG(QS_INJ_CTRL, 0x000034), 114 REG(QS_INJ_STATUS, 0x00003c), 115 REG(QS_INJ_ERR, 0x000040), 116 REG(QS_INH_DBG, 0x000048), 117 }; 118 119 static const u32 ocelot_qsys_regmap[] = { 120 REG(QSYS_PORT_MODE, 0x011200), 121 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 122 REG(QSYS_STAT_CNT_CFG, 0x011264), 123 REG(QSYS_EEE_CFG, 0x011268), 124 REG(QSYS_EEE_THRES, 0x011294), 125 REG(QSYS_IGR_NO_SHARING, 0x011298), 126 REG(QSYS_EGR_NO_SHARING, 0x01129c), 127 REG(QSYS_SW_STATUS, 0x0112a0), 128 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 129 REG(QSYS_PAD_CFG, 0x0112d4), 130 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 131 REG(QSYS_QMAP, 0x0112dc), 132 REG(QSYS_ISDX_SGRP, 0x011400), 133 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 134 REG(QSYS_TFRM_MISC, 0x011310), 135 REG(QSYS_TFRM_PORT_DLY, 0x011314), 136 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 137 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 138 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 139 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 140 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 141 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 142 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 143 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 144 REG(QSYS_RED_PROFILE, 0x011338), 145 REG(QSYS_RES_QOS_MODE, 0x011378), 146 REG(QSYS_RES_CFG, 0x012000), 147 REG(QSYS_RES_STAT, 0x012004), 148 REG(QSYS_EGR_DROP_MODE, 0x01137c), 149 REG(QSYS_EQ_CTRL, 0x011380), 150 REG(QSYS_EVENTS_CORE, 0x011384), 151 REG(QSYS_CIR_CFG, 0x000000), 152 REG(QSYS_EIR_CFG, 0x000004), 153 REG(QSYS_SE_CFG, 0x000008), 154 REG(QSYS_SE_DWRR_CFG, 0x00000c), 155 REG(QSYS_SE_CONNECT, 0x00003c), 156 REG(QSYS_SE_DLB_SENSE, 0x000040), 157 REG(QSYS_CIR_STATE, 0x000044), 158 REG(QSYS_EIR_STATE, 0x000048), 159 REG(QSYS_SE_STATE, 0x00004c), 160 REG(QSYS_HSCH_MISC_CFG, 0x011388), 161 }; 162 163 static const u32 ocelot_rew_regmap[] = { 164 REG(REW_PORT_VLAN_CFG, 0x000000), 165 REG(REW_TAG_CFG, 0x000004), 166 REG(REW_PORT_CFG, 0x000008), 167 REG(REW_DSCP_CFG, 0x00000c), 168 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 169 REG(REW_PTP_CFG, 0x000050), 170 REG(REW_PTP_DLY1_CFG, 0x000054), 171 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 172 REG(REW_DSCP_REMAP_CFG, 0x000790), 173 REG(REW_STAT_CFG, 0x000890), 174 REG(REW_PPT, 0x000680), 175 }; 176 177 static const u32 ocelot_sys_regmap[] = { 178 REG(SYS_COUNT_RX_OCTETS, 0x000000), 179 REG(SYS_COUNT_RX_UNICAST, 0x000004), 180 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 181 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 182 REG(SYS_COUNT_RX_SHORTS, 0x000010), 183 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 184 REG(SYS_COUNT_RX_JABBERS, 0x000018), 185 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 186 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 187 REG(SYS_COUNT_RX_64, 0x000024), 188 REG(SYS_COUNT_RX_65_127, 0x000028), 189 REG(SYS_COUNT_RX_128_255, 0x00002c), 190 REG(SYS_COUNT_RX_256_1023, 0x000030), 191 REG(SYS_COUNT_RX_1024_1526, 0x000034), 192 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 193 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 194 REG(SYS_COUNT_RX_CONTROL, 0x000040), 195 REG(SYS_COUNT_RX_LONGS, 0x000044), 196 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 197 REG(SYS_COUNT_TX_OCTETS, 0x000100), 198 REG(SYS_COUNT_TX_UNICAST, 0x000104), 199 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 200 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 201 REG(SYS_COUNT_TX_COLLISION, 0x000110), 202 REG(SYS_COUNT_TX_DROPS, 0x000114), 203 REG(SYS_COUNT_TX_PAUSE, 0x000118), 204 REG(SYS_COUNT_TX_64, 0x00011c), 205 REG(SYS_COUNT_TX_65_127, 0x000120), 206 REG(SYS_COUNT_TX_128_511, 0x000124), 207 REG(SYS_COUNT_TX_512_1023, 0x000128), 208 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 209 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 210 REG(SYS_COUNT_TX_AGING, 0x000170), 211 REG(SYS_RESET_CFG, 0x000508), 212 REG(SYS_CMID, 0x00050c), 213 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 214 REG(SYS_PORT_MODE, 0x000514), 215 REG(SYS_FRONT_PORT_MODE, 0x000548), 216 REG(SYS_FRM_AGING, 0x000574), 217 REG(SYS_STAT_CFG, 0x000578), 218 REG(SYS_SW_STATUS, 0x00057c), 219 REG(SYS_MISC_CFG, 0x0005ac), 220 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 221 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 222 REG(SYS_CM_ADDR, 0x000500), 223 REG(SYS_CM_DATA, 0x000504), 224 REG(SYS_PAUSE_CFG, 0x000608), 225 REG(SYS_PAUSE_TOT_CFG, 0x000638), 226 REG(SYS_ATOP, 0x00063c), 227 REG(SYS_ATOP_TOT_CFG, 0x00066c), 228 REG(SYS_MAC_FC_CFG, 0x000670), 229 REG(SYS_MMGT, 0x00069c), 230 REG(SYS_MMGT_FAST, 0x0006a0), 231 REG(SYS_EVENTS_DIF, 0x0006a4), 232 REG(SYS_EVENTS_CORE, 0x0006b4), 233 REG(SYS_CNT, 0x000000), 234 REG(SYS_PTP_STATUS, 0x0006b8), 235 REG(SYS_PTP_TXSTAMP, 0x0006bc), 236 REG(SYS_PTP_NXT, 0x0006c0), 237 REG(SYS_PTP_CFG, 0x0006c4), 238 }; 239 240 static const u32 ocelot_vcap_regmap[] = { 241 /* VCAP_CORE_CFG */ 242 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 243 REG(VCAP_CORE_MV_CFG, 0x000004), 244 /* VCAP_CORE_CACHE */ 245 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 246 REG(VCAP_CACHE_MASK_DAT, 0x000108), 247 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 248 REG(VCAP_CACHE_CNT_DAT, 0x000308), 249 REG(VCAP_CACHE_TG_DAT, 0x000388), 250 /* VCAP_CONST */ 251 REG(VCAP_CONST_VCAP_VER, 0x000398), 252 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 253 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 254 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 255 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 256 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 257 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 258 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 259 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 260 REG(VCAP_CONST_IF_CNT, 0x0003bc), 261 }; 262 263 static const u32 ocelot_ptp_regmap[] = { 264 REG(PTP_PIN_CFG, 0x000000), 265 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 266 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 267 REG(PTP_PIN_TOD_NSEC, 0x00000c), 268 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 269 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 270 REG(PTP_CFG_MISC, 0x0000a0), 271 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 272 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 273 }; 274 275 static const u32 ocelot_dev_gmii_regmap[] = { 276 REG(DEV_CLOCK_CFG, 0x0), 277 REG(DEV_PORT_MISC, 0x4), 278 REG(DEV_EVENTS, 0x8), 279 REG(DEV_EEE_CFG, 0xc), 280 REG(DEV_RX_PATH_DELAY, 0x10), 281 REG(DEV_TX_PATH_DELAY, 0x14), 282 REG(DEV_PTP_PREDICT_CFG, 0x18), 283 REG(DEV_MAC_ENA_CFG, 0x1c), 284 REG(DEV_MAC_MODE_CFG, 0x20), 285 REG(DEV_MAC_MAXLEN_CFG, 0x24), 286 REG(DEV_MAC_TAGS_CFG, 0x28), 287 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 288 REG(DEV_MAC_IFG_CFG, 0x30), 289 REG(DEV_MAC_HDX_CFG, 0x34), 290 REG(DEV_MAC_DBG_CFG, 0x38), 291 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 292 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 293 REG(DEV_MAC_STICKY, 0x44), 294 REG(PCS1G_CFG, 0x48), 295 REG(PCS1G_MODE_CFG, 0x4c), 296 REG(PCS1G_SD_CFG, 0x50), 297 REG(PCS1G_ANEG_CFG, 0x54), 298 REG(PCS1G_ANEG_NP_CFG, 0x58), 299 REG(PCS1G_LB_CFG, 0x5c), 300 REG(PCS1G_DBG_CFG, 0x60), 301 REG(PCS1G_CDET_CFG, 0x64), 302 REG(PCS1G_ANEG_STATUS, 0x68), 303 REG(PCS1G_ANEG_NP_STATUS, 0x6c), 304 REG(PCS1G_LINK_STATUS, 0x70), 305 REG(PCS1G_LINK_DOWN_CNT, 0x74), 306 REG(PCS1G_STICKY, 0x78), 307 REG(PCS1G_DEBUG_STATUS, 0x7c), 308 REG(PCS1G_LPI_CFG, 0x80), 309 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 310 REG(PCS1G_LPI_STATUS, 0x88), 311 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 312 REG(PCS1G_TSTPAT_STATUS, 0x90), 313 REG(DEV_PCS_FX100_CFG, 0x94), 314 REG(DEV_PCS_FX100_STATUS, 0x98), 315 }; 316 317 static const u32 *ocelot_regmap[TARGET_MAX] = { 318 [ANA] = ocelot_ana_regmap, 319 [QS] = ocelot_qs_regmap, 320 [QSYS] = ocelot_qsys_regmap, 321 [REW] = ocelot_rew_regmap, 322 [SYS] = ocelot_sys_regmap, 323 [S0] = ocelot_vcap_regmap, 324 [S1] = ocelot_vcap_regmap, 325 [S2] = ocelot_vcap_regmap, 326 [PTP] = ocelot_ptp_regmap, 327 [DEV_GMII] = ocelot_dev_gmii_regmap, 328 }; 329 330 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 331 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 332 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 333 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 334 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 335 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 336 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 337 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 338 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 339 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 340 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 341 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 342 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 343 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 344 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 345 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 346 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 347 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 348 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 349 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 350 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 351 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 352 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 353 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 354 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 355 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 356 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 357 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 358 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 359 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 360 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 361 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 362 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 363 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 364 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 365 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 366 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 367 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 368 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 369 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 370 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 371 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 372 /* Replicated per number of ports (12), register size 4 per port */ 373 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 374 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 375 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 376 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 377 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 378 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 379 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 380 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 381 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 382 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 383 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 384 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 385 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 386 }; 387 388 static const struct ocelot_stat_layout ocelot_stats_layout[] = { 389 { .name = "rx_octets", .offset = 0x00, }, 390 { .name = "rx_unicast", .offset = 0x01, }, 391 { .name = "rx_multicast", .offset = 0x02, }, 392 { .name = "rx_broadcast", .offset = 0x03, }, 393 { .name = "rx_shorts", .offset = 0x04, }, 394 { .name = "rx_fragments", .offset = 0x05, }, 395 { .name = "rx_jabbers", .offset = 0x06, }, 396 { .name = "rx_crc_align_errs", .offset = 0x07, }, 397 { .name = "rx_sym_errs", .offset = 0x08, }, 398 { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 399 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 400 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 401 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 402 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 403 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 404 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 405 { .name = "rx_pause", .offset = 0x10, }, 406 { .name = "rx_control", .offset = 0x11, }, 407 { .name = "rx_longs", .offset = 0x12, }, 408 { .name = "rx_classified_drops", .offset = 0x13, }, 409 { .name = "rx_red_prio_0", .offset = 0x14, }, 410 { .name = "rx_red_prio_1", .offset = 0x15, }, 411 { .name = "rx_red_prio_2", .offset = 0x16, }, 412 { .name = "rx_red_prio_3", .offset = 0x17, }, 413 { .name = "rx_red_prio_4", .offset = 0x18, }, 414 { .name = "rx_red_prio_5", .offset = 0x19, }, 415 { .name = "rx_red_prio_6", .offset = 0x1A, }, 416 { .name = "rx_red_prio_7", .offset = 0x1B, }, 417 { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 418 { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 419 { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 420 { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 421 { .name = "rx_yellow_prio_4", .offset = 0x20, }, 422 { .name = "rx_yellow_prio_5", .offset = 0x21, }, 423 { .name = "rx_yellow_prio_6", .offset = 0x22, }, 424 { .name = "rx_yellow_prio_7", .offset = 0x23, }, 425 { .name = "rx_green_prio_0", .offset = 0x24, }, 426 { .name = "rx_green_prio_1", .offset = 0x25, }, 427 { .name = "rx_green_prio_2", .offset = 0x26, }, 428 { .name = "rx_green_prio_3", .offset = 0x27, }, 429 { .name = "rx_green_prio_4", .offset = 0x28, }, 430 { .name = "rx_green_prio_5", .offset = 0x29, }, 431 { .name = "rx_green_prio_6", .offset = 0x2A, }, 432 { .name = "rx_green_prio_7", .offset = 0x2B, }, 433 { .name = "tx_octets", .offset = 0x40, }, 434 { .name = "tx_unicast", .offset = 0x41, }, 435 { .name = "tx_multicast", .offset = 0x42, }, 436 { .name = "tx_broadcast", .offset = 0x43, }, 437 { .name = "tx_collision", .offset = 0x44, }, 438 { .name = "tx_drops", .offset = 0x45, }, 439 { .name = "tx_pause", .offset = 0x46, }, 440 { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 441 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 442 { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 443 { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 444 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 445 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 446 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 447 { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 448 { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 449 { .name = "tx_yellow_prio_2", .offset = 0x50, }, 450 { .name = "tx_yellow_prio_3", .offset = 0x51, }, 451 { .name = "tx_yellow_prio_4", .offset = 0x52, }, 452 { .name = "tx_yellow_prio_5", .offset = 0x53, }, 453 { .name = "tx_yellow_prio_6", .offset = 0x54, }, 454 { .name = "tx_yellow_prio_7", .offset = 0x55, }, 455 { .name = "tx_green_prio_0", .offset = 0x56, }, 456 { .name = "tx_green_prio_1", .offset = 0x57, }, 457 { .name = "tx_green_prio_2", .offset = 0x58, }, 458 { .name = "tx_green_prio_3", .offset = 0x59, }, 459 { .name = "tx_green_prio_4", .offset = 0x5A, }, 460 { .name = "tx_green_prio_5", .offset = 0x5B, }, 461 { .name = "tx_green_prio_6", .offset = 0x5C, }, 462 { .name = "tx_green_prio_7", .offset = 0x5D, }, 463 { .name = "tx_aged", .offset = 0x5E, }, 464 { .name = "drop_local", .offset = 0x80, }, 465 { .name = "drop_tail", .offset = 0x81, }, 466 { .name = "drop_yellow_prio_0", .offset = 0x82, }, 467 { .name = "drop_yellow_prio_1", .offset = 0x83, }, 468 { .name = "drop_yellow_prio_2", .offset = 0x84, }, 469 { .name = "drop_yellow_prio_3", .offset = 0x85, }, 470 { .name = "drop_yellow_prio_4", .offset = 0x86, }, 471 { .name = "drop_yellow_prio_5", .offset = 0x87, }, 472 { .name = "drop_yellow_prio_6", .offset = 0x88, }, 473 { .name = "drop_yellow_prio_7", .offset = 0x89, }, 474 { .name = "drop_green_prio_0", .offset = 0x8A, }, 475 { .name = "drop_green_prio_1", .offset = 0x8B, }, 476 { .name = "drop_green_prio_2", .offset = 0x8C, }, 477 { .name = "drop_green_prio_3", .offset = 0x8D, }, 478 { .name = "drop_green_prio_4", .offset = 0x8E, }, 479 { .name = "drop_green_prio_5", .offset = 0x8F, }, 480 { .name = "drop_green_prio_6", .offset = 0x90, }, 481 { .name = "drop_green_prio_7", .offset = 0x91, }, 482 }; 483 484 static void ocelot_pll5_init(struct ocelot *ocelot) 485 { 486 /* Configure PLL5. This will need a proper CCF driver 487 * The values are coming from the VTSS API for Ocelot 488 */ 489 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 490 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 491 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 492 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 493 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 494 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 495 HSIO_PLL5G_CFG0_ENA_BIAS | 496 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 497 HSIO_PLL5G_CFG0_ENA_CP1 | 498 HSIO_PLL5G_CFG0_SELCPI(2) | 499 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 500 HSIO_PLL5G_CFG0_SELBGV820(4) | 501 HSIO_PLL5G_CFG0_DIV4 | 502 HSIO_PLL5G_CFG0_ENA_CLKTREE | 503 HSIO_PLL5G_CFG0_ENA_LANE); 504 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 505 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 506 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 507 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 508 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 509 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 510 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 511 } 512 513 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 514 { 515 int ret; 516 517 ocelot->map = ocelot_regmap; 518 ocelot->stats_layout = ocelot_stats_layout; 519 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 520 ocelot->num_mact_rows = 1024; 521 ocelot->ops = ops; 522 523 ret = ocelot_regfields_init(ocelot, ocelot_regfields); 524 if (ret) 525 return ret; 526 527 ocelot_pll5_init(ocelot); 528 529 eth_random_addr(ocelot->base_mac); 530 ocelot->base_mac[5] &= 0xf0; 531 532 return 0; 533 } 534 535 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 536 { 537 struct ocelot *ocelot = arg; 538 int grp = 0, err; 539 540 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 541 struct sk_buff *skb; 542 543 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 544 if (err) 545 goto out; 546 547 skb->dev->stats.rx_bytes += skb->len; 548 skb->dev->stats.rx_packets++; 549 550 if (!skb_defer_rx_timestamp(skb)) 551 netif_rx(skb); 552 } 553 554 out: 555 if (err < 0) 556 ocelot_drain_cpu_queue(ocelot, 0); 557 558 return IRQ_HANDLED; 559 } 560 561 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 562 { 563 struct ocelot *ocelot = arg; 564 565 ocelot_get_txtstamp(ocelot); 566 567 return IRQ_HANDLED; 568 } 569 570 static const struct of_device_id mscc_ocelot_match[] = { 571 { .compatible = "mscc,vsc7514-switch" }, 572 { } 573 }; 574 MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 575 576 static int ocelot_reset(struct ocelot *ocelot) 577 { 578 int retries = 100; 579 u32 val; 580 581 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 582 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 583 584 do { 585 msleep(1); 586 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 587 &val); 588 } while (val && --retries); 589 590 if (!retries) 591 return -ETIMEDOUT; 592 593 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 594 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 595 596 return 0; 597 } 598 599 /* Watermark encode 600 * Bit 8: Unit; 0:1, 1:16 601 * Bit 7-0: Value to be multiplied with unit 602 */ 603 static u16 ocelot_wm_enc(u16 value) 604 { 605 WARN_ON(value >= 16 * BIT(8)); 606 607 if (value >= BIT(8)) 608 return BIT(8) | (value / 16); 609 610 return value; 611 } 612 613 static u16 ocelot_wm_dec(u16 wm) 614 { 615 if (wm & BIT(8)) 616 return (wm & GENMASK(7, 0)) * 16; 617 618 return wm; 619 } 620 621 static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 622 { 623 *inuse = (val & GENMASK(23, 12)) >> 12; 624 *maxuse = val & GENMASK(11, 0); 625 } 626 627 static const struct ocelot_ops ocelot_ops = { 628 .reset = ocelot_reset, 629 .wm_enc = ocelot_wm_enc, 630 .wm_dec = ocelot_wm_dec, 631 .wm_stat = ocelot_wm_stat, 632 .port_to_netdev = ocelot_port_to_netdev, 633 .netdev_to_port = ocelot_netdev_to_port, 634 }; 635 636 static const struct vcap_field vsc7514_vcap_es0_keys[] = { 637 [VCAP_ES0_EGR_PORT] = { 0, 4}, 638 [VCAP_ES0_IGR_PORT] = { 4, 4}, 639 [VCAP_ES0_RSV] = { 8, 2}, 640 [VCAP_ES0_L2_MC] = { 10, 1}, 641 [VCAP_ES0_L2_BC] = { 11, 1}, 642 [VCAP_ES0_VID] = { 12, 12}, 643 [VCAP_ES0_DP] = { 24, 1}, 644 [VCAP_ES0_PCP] = { 25, 3}, 645 }; 646 647 static const struct vcap_field vsc7514_vcap_es0_actions[] = { 648 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 649 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 650 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 651 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 652 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 653 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 654 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 655 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 656 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 657 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 658 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 659 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 660 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 661 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 662 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 663 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 664 [VCAP_ES0_ACT_RSV] = { 49, 24}, 665 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 666 }; 667 668 static const struct vcap_field vsc7514_vcap_is1_keys[] = { 669 [VCAP_IS1_HK_TYPE] = { 0, 1}, 670 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 671 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12}, 672 [VCAP_IS1_HK_RSV] = { 15, 9}, 673 [VCAP_IS1_HK_OAM_Y1731] = { 24, 1}, 674 [VCAP_IS1_HK_L2_MC] = { 25, 1}, 675 [VCAP_IS1_HK_L2_BC] = { 26, 1}, 676 [VCAP_IS1_HK_IP_MC] = { 27, 1}, 677 [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1}, 678 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1}, 679 [VCAP_IS1_HK_TPID] = { 30, 1}, 680 [VCAP_IS1_HK_VID] = { 31, 12}, 681 [VCAP_IS1_HK_DEI] = { 43, 1}, 682 [VCAP_IS1_HK_PCP] = { 44, 3}, 683 /* Specific Fields for IS1 Half Key S1_NORMAL */ 684 [VCAP_IS1_HK_L2_SMAC] = { 47, 48}, 685 [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1}, 686 [VCAP_IS1_HK_ETYPE] = { 96, 16}, 687 [VCAP_IS1_HK_IP_SNAP] = {112, 1}, 688 [VCAP_IS1_HK_IP4] = {113, 1}, 689 /* Layer-3 Information */ 690 [VCAP_IS1_HK_L3_FRAGMENT] = {114, 1}, 691 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {115, 1}, 692 [VCAP_IS1_HK_L3_OPTIONS] = {116, 1}, 693 [VCAP_IS1_HK_L3_DSCP] = {117, 6}, 694 [VCAP_IS1_HK_L3_IP4_SIP] = {123, 32}, 695 /* Layer-4 Information */ 696 [VCAP_IS1_HK_TCP_UDP] = {155, 1}, 697 [VCAP_IS1_HK_TCP] = {156, 1}, 698 [VCAP_IS1_HK_L4_SPORT] = {157, 16}, 699 [VCAP_IS1_HK_L4_RNG] = {173, 8}, 700 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 701 [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1}, 702 [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12}, 703 [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1}, 704 [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3}, 705 [VCAP_IS1_HK_IP4_IP4] = { 64, 1}, 706 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1}, 707 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1}, 708 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1}, 709 [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6}, 710 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32}, 711 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {106, 32}, 712 [VCAP_IS1_HK_IP4_L3_PROTO] = {138, 8}, 713 [VCAP_IS1_HK_IP4_TCP_UDP] = {146, 1}, 714 [VCAP_IS1_HK_IP4_TCP] = {147, 1}, 715 [VCAP_IS1_HK_IP4_L4_RNG] = {148, 8}, 716 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {156, 32}, 717 }; 718 719 static const struct vcap_field vsc7514_vcap_is1_actions[] = { 720 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 721 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 722 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 723 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 724 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 725 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 726 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 727 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 728 [VCAP_IS1_ACT_RSV] = { 29, 9}, 729 /* The fields below are incorrectly shifted by 2 in the manual */ 730 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 731 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 732 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 733 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 734 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 735 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 736 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 737 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 738 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 739 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 740 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 741 }; 742 743 static const struct vcap_field vsc7514_vcap_is2_keys[] = { 744 /* Common: 46 bits */ 745 [VCAP_IS2_TYPE] = { 0, 4}, 746 [VCAP_IS2_HK_FIRST] = { 4, 1}, 747 [VCAP_IS2_HK_PAG] = { 5, 8}, 748 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 749 [VCAP_IS2_HK_RSV2] = { 25, 1}, 750 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 751 [VCAP_IS2_HK_L2_MC] = { 27, 1}, 752 [VCAP_IS2_HK_L2_BC] = { 28, 1}, 753 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 754 [VCAP_IS2_HK_VID] = { 30, 12}, 755 [VCAP_IS2_HK_DEI] = { 42, 1}, 756 [VCAP_IS2_HK_PCP] = { 43, 3}, 757 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 758 [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 759 [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 760 /* MAC_ETYPE (TYPE=000) */ 761 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 762 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 763 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 764 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 765 /* MAC_LLC (TYPE=001) */ 766 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 767 /* MAC_SNAP (TYPE=010) */ 768 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 769 /* MAC_ARP (TYPE=011) */ 770 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 771 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 772 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 773 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 774 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 775 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 776 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 777 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 778 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 779 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 780 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 781 /* IP4_TCP_UDP / IP4_OTHER common */ 782 [VCAP_IS2_HK_IP4] = { 46, 1}, 783 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 784 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 785 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 786 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 787 [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 788 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 789 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 790 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 791 /* IP4_TCP_UDP (TYPE=100) */ 792 [VCAP_IS2_HK_TCP] = {124, 1}, 793 [VCAP_IS2_HK_L4_DPORT] = {125, 16}, 794 [VCAP_IS2_HK_L4_SPORT] = {141, 16}, 795 [VCAP_IS2_HK_L4_RNG] = {157, 8}, 796 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 797 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 798 [VCAP_IS2_HK_L4_FIN] = {167, 1}, 799 [VCAP_IS2_HK_L4_SYN] = {168, 1}, 800 [VCAP_IS2_HK_L4_RST] = {169, 1}, 801 [VCAP_IS2_HK_L4_PSH] = {170, 1}, 802 [VCAP_IS2_HK_L4_ACK] = {171, 1}, 803 [VCAP_IS2_HK_L4_URG] = {172, 1}, 804 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 805 [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 806 /* IP4_OTHER (TYPE=101) */ 807 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 808 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 809 /* IP6_STD (TYPE=110) */ 810 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 811 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 812 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 813 /* OAM (TYPE=111) */ 814 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 815 [VCAP_IS2_HK_OAM_VER] = {149, 5}, 816 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 817 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 818 [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 819 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 820 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 821 }; 822 823 static const struct vcap_field vsc7514_vcap_is2_actions[] = { 824 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 825 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 826 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 827 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 828 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 829 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 830 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 831 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 832 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 833 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 834 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 835 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 836 [VCAP_IS2_ACT_RSV] = { 41, 2}, 837 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 838 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 839 }; 840 841 static struct vcap_props vsc7514_vcap_props[] = { 842 [VCAP_ES0] = { 843 .action_type_width = 0, 844 .action_table = { 845 [ES0_ACTION_TYPE_NORMAL] = { 846 .width = 73, /* HIT_STICKY not included */ 847 .count = 1, 848 }, 849 }, 850 .target = S0, 851 .keys = vsc7514_vcap_es0_keys, 852 .actions = vsc7514_vcap_es0_actions, 853 }, 854 [VCAP_IS1] = { 855 .action_type_width = 0, 856 .action_table = { 857 [IS1_ACTION_TYPE_NORMAL] = { 858 .width = 78, /* HIT_STICKY not included */ 859 .count = 4, 860 }, 861 }, 862 .target = S1, 863 .keys = vsc7514_vcap_is1_keys, 864 .actions = vsc7514_vcap_is1_actions, 865 }, 866 [VCAP_IS2] = { 867 .action_type_width = 1, 868 .action_table = { 869 [IS2_ACTION_TYPE_NORMAL] = { 870 .width = 49, 871 .count = 2 872 }, 873 [IS2_ACTION_TYPE_SMAC_SIP] = { 874 .width = 6, 875 .count = 4 876 }, 877 }, 878 .target = S2, 879 .keys = vsc7514_vcap_is2_keys, 880 .actions = vsc7514_vcap_is2_actions, 881 }, 882 }; 883 884 static struct ptp_clock_info ocelot_ptp_clock_info = { 885 .owner = THIS_MODULE, 886 .name = "ocelot ptp", 887 .max_adj = 0x7fffffff, 888 .n_alarm = 0, 889 .n_ext_ts = 0, 890 .n_per_out = OCELOT_PTP_PINS_NUM, 891 .n_pins = OCELOT_PTP_PINS_NUM, 892 .pps = 0, 893 .gettime64 = ocelot_ptp_gettime64, 894 .settime64 = ocelot_ptp_settime64, 895 .adjtime = ocelot_ptp_adjtime, 896 .adjfine = ocelot_ptp_adjfine, 897 .verify = ocelot_ptp_verify, 898 .enable = ocelot_ptp_enable, 899 }; 900 901 static void mscc_ocelot_teardown_devlink_ports(struct ocelot *ocelot) 902 { 903 int port; 904 905 for (port = 0; port < ocelot->num_phys_ports; port++) 906 ocelot_port_devlink_teardown(ocelot, port); 907 } 908 909 static void mscc_ocelot_release_ports(struct ocelot *ocelot) 910 { 911 int port; 912 913 for (port = 0; port < ocelot->num_phys_ports; port++) { 914 struct ocelot_port *ocelot_port; 915 916 ocelot_port = ocelot->ports[port]; 917 if (!ocelot_port) 918 continue; 919 920 ocelot_deinit_port(ocelot, port); 921 ocelot_release_port(ocelot_port); 922 } 923 } 924 925 static int mscc_ocelot_init_ports(struct platform_device *pdev, 926 struct device_node *ports) 927 { 928 struct ocelot *ocelot = platform_get_drvdata(pdev); 929 u32 devlink_ports_registered = 0; 930 struct device_node *portnp; 931 int port, err; 932 u32 reg; 933 934 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 935 sizeof(struct ocelot_port *), GFP_KERNEL); 936 if (!ocelot->ports) 937 return -ENOMEM; 938 939 ocelot->devlink_ports = devm_kcalloc(ocelot->dev, 940 ocelot->num_phys_ports, 941 sizeof(*ocelot->devlink_ports), 942 GFP_KERNEL); 943 if (!ocelot->devlink_ports) 944 return -ENOMEM; 945 946 for_each_available_child_of_node(ports, portnp) { 947 struct ocelot_port_private *priv; 948 struct ocelot_port *ocelot_port; 949 struct devlink_port *dlp; 950 struct regmap *target; 951 struct resource *res; 952 char res_name[8]; 953 954 if (of_property_read_u32(portnp, "reg", ®)) 955 continue; 956 957 port = reg; 958 if (port < 0 || port >= ocelot->num_phys_ports) { 959 dev_err(ocelot->dev, 960 "invalid port number: %d >= %d\n", port, 961 ocelot->num_phys_ports); 962 continue; 963 } 964 965 snprintf(res_name, sizeof(res_name), "port%d", port); 966 967 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 968 res_name); 969 target = ocelot_regmap_init(ocelot, res); 970 if (IS_ERR(target)) { 971 err = PTR_ERR(target); 972 of_node_put(portnp); 973 goto out_teardown; 974 } 975 976 err = ocelot_port_devlink_init(ocelot, port, 977 DEVLINK_PORT_FLAVOUR_PHYSICAL); 978 if (err) { 979 of_node_put(portnp); 980 goto out_teardown; 981 } 982 983 err = ocelot_probe_port(ocelot, port, target, portnp); 984 if (err) { 985 ocelot_port_devlink_teardown(ocelot, port); 986 continue; 987 } 988 989 devlink_ports_registered |= BIT(port); 990 991 ocelot_port = ocelot->ports[port]; 992 priv = container_of(ocelot_port, struct ocelot_port_private, 993 port); 994 dlp = &ocelot->devlink_ports[port]; 995 devlink_port_type_eth_set(dlp, priv->dev); 996 } 997 998 /* Initialize unused devlink ports at the end */ 999 for (port = 0; port < ocelot->num_phys_ports; port++) { 1000 if (devlink_ports_registered & BIT(port)) 1001 continue; 1002 1003 err = ocelot_port_devlink_init(ocelot, port, 1004 DEVLINK_PORT_FLAVOUR_UNUSED); 1005 if (err) 1006 goto out_teardown; 1007 1008 devlink_ports_registered |= BIT(port); 1009 } 1010 1011 return 0; 1012 1013 out_teardown: 1014 /* Unregister the network interfaces */ 1015 mscc_ocelot_release_ports(ocelot); 1016 /* Tear down devlink ports for the registered network interfaces */ 1017 for (port = 0; port < ocelot->num_phys_ports; port++) { 1018 if (devlink_ports_registered & BIT(port)) 1019 ocelot_port_devlink_teardown(ocelot, port); 1020 } 1021 return err; 1022 } 1023 1024 static int mscc_ocelot_probe(struct platform_device *pdev) 1025 { 1026 struct device_node *np = pdev->dev.of_node; 1027 int err, irq_xtr, irq_ptp_rdy; 1028 struct device_node *ports; 1029 struct devlink *devlink; 1030 struct ocelot *ocelot; 1031 struct regmap *hsio; 1032 unsigned int i; 1033 1034 struct { 1035 enum ocelot_target id; 1036 char *name; 1037 u8 optional:1; 1038 } io_target[] = { 1039 { SYS, "sys" }, 1040 { REW, "rew" }, 1041 { QSYS, "qsys" }, 1042 { ANA, "ana" }, 1043 { QS, "qs" }, 1044 { S0, "s0" }, 1045 { S1, "s1" }, 1046 { S2, "s2" }, 1047 { PTP, "ptp", 1 }, 1048 }; 1049 1050 if (!np && !pdev->dev.platform_data) 1051 return -ENODEV; 1052 1053 devlink = 1054 devlink_alloc(&ocelot_devlink_ops, sizeof(*ocelot), &pdev->dev); 1055 if (!devlink) 1056 return -ENOMEM; 1057 1058 ocelot = devlink_priv(devlink); 1059 ocelot->devlink = priv_to_devlink(ocelot); 1060 platform_set_drvdata(pdev, ocelot); 1061 ocelot->dev = &pdev->dev; 1062 1063 for (i = 0; i < ARRAY_SIZE(io_target); i++) { 1064 struct regmap *target; 1065 struct resource *res; 1066 1067 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1068 io_target[i].name); 1069 1070 target = ocelot_regmap_init(ocelot, res); 1071 if (IS_ERR(target)) { 1072 if (io_target[i].optional) { 1073 ocelot->targets[io_target[i].id] = NULL; 1074 continue; 1075 } 1076 err = PTR_ERR(target); 1077 goto out_free_devlink; 1078 } 1079 1080 ocelot->targets[io_target[i].id] = target; 1081 } 1082 1083 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 1084 if (IS_ERR(hsio)) { 1085 dev_err(&pdev->dev, "missing hsio syscon\n"); 1086 err = PTR_ERR(hsio); 1087 goto out_free_devlink; 1088 } 1089 1090 ocelot->targets[HSIO] = hsio; 1091 1092 err = ocelot_chip_init(ocelot, &ocelot_ops); 1093 if (err) 1094 goto out_free_devlink; 1095 1096 irq_xtr = platform_get_irq_byname(pdev, "xtr"); 1097 if (irq_xtr < 0) { 1098 err = irq_xtr; 1099 goto out_free_devlink; 1100 } 1101 1102 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 1103 ocelot_xtr_irq_handler, IRQF_ONESHOT, 1104 "frame extraction", ocelot); 1105 if (err) 1106 goto out_free_devlink; 1107 1108 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 1109 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 1110 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 1111 ocelot_ptp_rdy_irq_handler, 1112 IRQF_ONESHOT, "ptp ready", 1113 ocelot); 1114 if (err) 1115 goto out_free_devlink; 1116 1117 /* Both the PTP interrupt and the PTP bank are available */ 1118 ocelot->ptp = 1; 1119 } 1120 1121 ports = of_get_child_by_name(np, "ethernet-ports"); 1122 if (!ports) { 1123 dev_err(ocelot->dev, "no ethernet-ports child node found\n"); 1124 err = -ENODEV; 1125 goto out_free_devlink; 1126 } 1127 1128 ocelot->num_phys_ports = of_get_child_count(ports); 1129 ocelot->num_flooding_pgids = 1; 1130 1131 ocelot->vcap = vsc7514_vcap_props; 1132 ocelot->npi = -1; 1133 1134 err = ocelot_init(ocelot); 1135 if (err) 1136 goto out_put_ports; 1137 1138 err = mscc_ocelot_init_ports(pdev, ports); 1139 if (err) 1140 goto out_ocelot_devlink_unregister; 1141 1142 err = ocelot_devlink_sb_register(ocelot); 1143 if (err) 1144 goto out_ocelot_release_ports; 1145 1146 if (ocelot->ptp) { 1147 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1148 if (err) { 1149 dev_err(ocelot->dev, 1150 "Timestamp initialization failed\n"); 1151 ocelot->ptp = 0; 1152 } 1153 } 1154 1155 register_netdevice_notifier(&ocelot_netdevice_nb); 1156 register_switchdev_notifier(&ocelot_switchdev_nb); 1157 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1158 1159 of_node_put(ports); 1160 devlink_register(devlink); 1161 1162 dev_info(&pdev->dev, "Ocelot switch probed\n"); 1163 1164 return 0; 1165 1166 out_ocelot_release_ports: 1167 mscc_ocelot_release_ports(ocelot); 1168 mscc_ocelot_teardown_devlink_ports(ocelot); 1169 out_ocelot_devlink_unregister: 1170 ocelot_deinit(ocelot); 1171 out_put_ports: 1172 of_node_put(ports); 1173 out_free_devlink: 1174 devlink_free(devlink); 1175 return err; 1176 } 1177 1178 static int mscc_ocelot_remove(struct platform_device *pdev) 1179 { 1180 struct ocelot *ocelot = platform_get_drvdata(pdev); 1181 1182 devlink_unregister(ocelot->devlink); 1183 ocelot_deinit_timestamp(ocelot); 1184 ocelot_devlink_sb_unregister(ocelot); 1185 mscc_ocelot_release_ports(ocelot); 1186 mscc_ocelot_teardown_devlink_ports(ocelot); 1187 ocelot_deinit(ocelot); 1188 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1189 unregister_switchdev_notifier(&ocelot_switchdev_nb); 1190 unregister_netdevice_notifier(&ocelot_netdevice_nb); 1191 devlink_free(ocelot->devlink); 1192 1193 return 0; 1194 } 1195 1196 static struct platform_driver mscc_ocelot_driver = { 1197 .probe = mscc_ocelot_probe, 1198 .remove = mscc_ocelot_remove, 1199 .driver = { 1200 .name = "ocelot-switch", 1201 .of_match_table = mscc_ocelot_match, 1202 }, 1203 }; 1204 1205 module_platform_driver(mscc_ocelot_driver); 1206 1207 MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1208 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1209 MODULE_LICENSE("Dual MIT/GPL"); 1210