1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of_net.h> 11 #include <linux/netdevice.h> 12 #include <linux/phylink.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_platform.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/skbuff.h> 17 #include <net/switchdev.h> 18 19 #include <soc/mscc/ocelot_vcap.h> 20 #include <soc/mscc/ocelot_hsio.h> 21 #include "ocelot.h" 22 23 #define VSC7514_VCAP_POLICER_BASE 128 24 #define VSC7514_VCAP_POLICER_MAX 191 25 26 static const u32 ocelot_ana_regmap[] = { 27 REG(ANA_ADVLEARN, 0x009000), 28 REG(ANA_VLANMASK, 0x009004), 29 REG(ANA_PORT_B_DOMAIN, 0x009008), 30 REG(ANA_ANAGEFIL, 0x00900c), 31 REG(ANA_ANEVENTS, 0x009010), 32 REG(ANA_STORMLIMIT_BURST, 0x009014), 33 REG(ANA_STORMLIMIT_CFG, 0x009018), 34 REG(ANA_ISOLATED_PORTS, 0x009028), 35 REG(ANA_COMMUNITY_PORTS, 0x00902c), 36 REG(ANA_AUTOAGE, 0x009030), 37 REG(ANA_MACTOPTIONS, 0x009034), 38 REG(ANA_LEARNDISC, 0x009038), 39 REG(ANA_AGENCTRL, 0x00903c), 40 REG(ANA_MIRRORPORTS, 0x009040), 41 REG(ANA_EMIRRORPORTS, 0x009044), 42 REG(ANA_FLOODING, 0x009048), 43 REG(ANA_FLOODING_IPMC, 0x00904c), 44 REG(ANA_SFLOW_CFG, 0x009050), 45 REG(ANA_PORT_MODE, 0x009080), 46 REG(ANA_PGID_PGID, 0x008c00), 47 REG(ANA_TABLES_ANMOVED, 0x008b30), 48 REG(ANA_TABLES_MACHDATA, 0x008b34), 49 REG(ANA_TABLES_MACLDATA, 0x008b38), 50 REG(ANA_TABLES_MACACCESS, 0x008b3c), 51 REG(ANA_TABLES_MACTINDX, 0x008b40), 52 REG(ANA_TABLES_VLANACCESS, 0x008b44), 53 REG(ANA_TABLES_VLANTIDX, 0x008b48), 54 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 55 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 56 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 57 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 58 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 59 REG(ANA_MSTI_STATE, 0x008e00), 60 REG(ANA_PORT_VLAN_CFG, 0x007000), 61 REG(ANA_PORT_DROP_CFG, 0x007004), 62 REG(ANA_PORT_QOS_CFG, 0x007008), 63 REG(ANA_PORT_VCAP_CFG, 0x00700c), 64 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 65 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 66 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 67 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 68 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 69 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 70 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 71 REG(ANA_PORT_PORT_CFG, 0x007070), 72 REG(ANA_PORT_POL_CFG, 0x007074), 73 REG(ANA_PORT_PTP_CFG, 0x007078), 74 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 75 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 76 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 77 REG(ANA_PFC_PFC_CFG, 0x008800), 78 REG(ANA_PFC_PFC_TIMER, 0x008804), 79 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 80 REG(ANA_IPT_IPT, 0x008004), 81 REG(ANA_PPT_PPT, 0x008ac0), 82 REG(ANA_FID_MAP_FID_MAP, 0x000000), 83 REG(ANA_AGGR_CFG, 0x0090b4), 84 REG(ANA_CPUQ_CFG, 0x0090b8), 85 REG(ANA_CPUQ_CFG2, 0x0090bc), 86 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 87 REG(ANA_DSCP_CFG, 0x009100), 88 REG(ANA_DSCP_REWR_CFG, 0x009200), 89 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 90 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 91 REG(ANA_VRAP_CFG, 0x009280), 92 REG(ANA_VRAP_HDR_DATA, 0x009284), 93 REG(ANA_VRAP_HDR_MASK, 0x009288), 94 REG(ANA_DISCARD_CFG, 0x00928c), 95 REG(ANA_FID_CFG, 0x009290), 96 REG(ANA_POL_PIR_CFG, 0x004000), 97 REG(ANA_POL_CIR_CFG, 0x004004), 98 REG(ANA_POL_MODE_CFG, 0x004008), 99 REG(ANA_POL_PIR_STATE, 0x00400c), 100 REG(ANA_POL_CIR_STATE, 0x004010), 101 REG(ANA_POL_STATE, 0x004014), 102 REG(ANA_POL_FLOWC, 0x008b80), 103 REG(ANA_POL_HYST, 0x008bec), 104 REG(ANA_POL_MISC_CFG, 0x008bf0), 105 }; 106 107 static const u32 ocelot_qs_regmap[] = { 108 REG(QS_XTR_GRP_CFG, 0x000000), 109 REG(QS_XTR_RD, 0x000008), 110 REG(QS_XTR_FRM_PRUNING, 0x000010), 111 REG(QS_XTR_FLUSH, 0x000018), 112 REG(QS_XTR_DATA_PRESENT, 0x00001c), 113 REG(QS_XTR_CFG, 0x000020), 114 REG(QS_INJ_GRP_CFG, 0x000024), 115 REG(QS_INJ_WR, 0x00002c), 116 REG(QS_INJ_CTRL, 0x000034), 117 REG(QS_INJ_STATUS, 0x00003c), 118 REG(QS_INJ_ERR, 0x000040), 119 REG(QS_INH_DBG, 0x000048), 120 }; 121 122 static const u32 ocelot_qsys_regmap[] = { 123 REG(QSYS_PORT_MODE, 0x011200), 124 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 125 REG(QSYS_STAT_CNT_CFG, 0x011264), 126 REG(QSYS_EEE_CFG, 0x011268), 127 REG(QSYS_EEE_THRES, 0x011294), 128 REG(QSYS_IGR_NO_SHARING, 0x011298), 129 REG(QSYS_EGR_NO_SHARING, 0x01129c), 130 REG(QSYS_SW_STATUS, 0x0112a0), 131 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 132 REG(QSYS_PAD_CFG, 0x0112d4), 133 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 134 REG(QSYS_QMAP, 0x0112dc), 135 REG(QSYS_ISDX_SGRP, 0x011400), 136 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 137 REG(QSYS_TFRM_MISC, 0x011310), 138 REG(QSYS_TFRM_PORT_DLY, 0x011314), 139 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 140 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 141 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 142 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 143 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 144 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 145 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 146 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 147 REG(QSYS_RED_PROFILE, 0x011338), 148 REG(QSYS_RES_QOS_MODE, 0x011378), 149 REG(QSYS_RES_CFG, 0x012000), 150 REG(QSYS_RES_STAT, 0x012004), 151 REG(QSYS_EGR_DROP_MODE, 0x01137c), 152 REG(QSYS_EQ_CTRL, 0x011380), 153 REG(QSYS_EVENTS_CORE, 0x011384), 154 REG(QSYS_CIR_CFG, 0x000000), 155 REG(QSYS_EIR_CFG, 0x000004), 156 REG(QSYS_SE_CFG, 0x000008), 157 REG(QSYS_SE_DWRR_CFG, 0x00000c), 158 REG(QSYS_SE_CONNECT, 0x00003c), 159 REG(QSYS_SE_DLB_SENSE, 0x000040), 160 REG(QSYS_CIR_STATE, 0x000044), 161 REG(QSYS_EIR_STATE, 0x000048), 162 REG(QSYS_SE_STATE, 0x00004c), 163 REG(QSYS_HSCH_MISC_CFG, 0x011388), 164 }; 165 166 static const u32 ocelot_rew_regmap[] = { 167 REG(REW_PORT_VLAN_CFG, 0x000000), 168 REG(REW_TAG_CFG, 0x000004), 169 REG(REW_PORT_CFG, 0x000008), 170 REG(REW_DSCP_CFG, 0x00000c), 171 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 172 REG(REW_PTP_CFG, 0x000050), 173 REG(REW_PTP_DLY1_CFG, 0x000054), 174 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 175 REG(REW_DSCP_REMAP_CFG, 0x000790), 176 REG(REW_STAT_CFG, 0x000890), 177 REG(REW_PPT, 0x000680), 178 }; 179 180 static const u32 ocelot_sys_regmap[] = { 181 REG(SYS_COUNT_RX_OCTETS, 0x000000), 182 REG(SYS_COUNT_RX_UNICAST, 0x000004), 183 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 184 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 185 REG(SYS_COUNT_RX_SHORTS, 0x000010), 186 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 187 REG(SYS_COUNT_RX_JABBERS, 0x000018), 188 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 189 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 190 REG(SYS_COUNT_RX_64, 0x000024), 191 REG(SYS_COUNT_RX_65_127, 0x000028), 192 REG(SYS_COUNT_RX_128_255, 0x00002c), 193 REG(SYS_COUNT_RX_256_1023, 0x000030), 194 REG(SYS_COUNT_RX_1024_1526, 0x000034), 195 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 196 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 197 REG(SYS_COUNT_RX_CONTROL, 0x000040), 198 REG(SYS_COUNT_RX_LONGS, 0x000044), 199 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 200 REG(SYS_COUNT_TX_OCTETS, 0x000100), 201 REG(SYS_COUNT_TX_UNICAST, 0x000104), 202 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 203 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 204 REG(SYS_COUNT_TX_COLLISION, 0x000110), 205 REG(SYS_COUNT_TX_DROPS, 0x000114), 206 REG(SYS_COUNT_TX_PAUSE, 0x000118), 207 REG(SYS_COUNT_TX_64, 0x00011c), 208 REG(SYS_COUNT_TX_65_127, 0x000120), 209 REG(SYS_COUNT_TX_128_511, 0x000124), 210 REG(SYS_COUNT_TX_512_1023, 0x000128), 211 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 212 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 213 REG(SYS_COUNT_TX_AGING, 0x000170), 214 REG(SYS_RESET_CFG, 0x000508), 215 REG(SYS_CMID, 0x00050c), 216 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 217 REG(SYS_PORT_MODE, 0x000514), 218 REG(SYS_FRONT_PORT_MODE, 0x000548), 219 REG(SYS_FRM_AGING, 0x000574), 220 REG(SYS_STAT_CFG, 0x000578), 221 REG(SYS_SW_STATUS, 0x00057c), 222 REG(SYS_MISC_CFG, 0x0005ac), 223 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 224 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 225 REG(SYS_CM_ADDR, 0x000500), 226 REG(SYS_CM_DATA, 0x000504), 227 REG(SYS_PAUSE_CFG, 0x000608), 228 REG(SYS_PAUSE_TOT_CFG, 0x000638), 229 REG(SYS_ATOP, 0x00063c), 230 REG(SYS_ATOP_TOT_CFG, 0x00066c), 231 REG(SYS_MAC_FC_CFG, 0x000670), 232 REG(SYS_MMGT, 0x00069c), 233 REG(SYS_MMGT_FAST, 0x0006a0), 234 REG(SYS_EVENTS_DIF, 0x0006a4), 235 REG(SYS_EVENTS_CORE, 0x0006b4), 236 REG(SYS_CNT, 0x000000), 237 REG(SYS_PTP_STATUS, 0x0006b8), 238 REG(SYS_PTP_TXSTAMP, 0x0006bc), 239 REG(SYS_PTP_NXT, 0x0006c0), 240 REG(SYS_PTP_CFG, 0x0006c4), 241 }; 242 243 static const u32 ocelot_vcap_regmap[] = { 244 /* VCAP_CORE_CFG */ 245 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 246 REG(VCAP_CORE_MV_CFG, 0x000004), 247 /* VCAP_CORE_CACHE */ 248 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 249 REG(VCAP_CACHE_MASK_DAT, 0x000108), 250 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 251 REG(VCAP_CACHE_CNT_DAT, 0x000308), 252 REG(VCAP_CACHE_TG_DAT, 0x000388), 253 /* VCAP_CONST */ 254 REG(VCAP_CONST_VCAP_VER, 0x000398), 255 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 256 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 257 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 258 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 259 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 260 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 261 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 262 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 263 REG(VCAP_CONST_IF_CNT, 0x0003bc), 264 }; 265 266 static const u32 ocelot_ptp_regmap[] = { 267 REG(PTP_PIN_CFG, 0x000000), 268 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 269 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 270 REG(PTP_PIN_TOD_NSEC, 0x00000c), 271 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 272 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 273 REG(PTP_CFG_MISC, 0x0000a0), 274 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 275 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 276 }; 277 278 static const u32 ocelot_dev_gmii_regmap[] = { 279 REG(DEV_CLOCK_CFG, 0x0), 280 REG(DEV_PORT_MISC, 0x4), 281 REG(DEV_EVENTS, 0x8), 282 REG(DEV_EEE_CFG, 0xc), 283 REG(DEV_RX_PATH_DELAY, 0x10), 284 REG(DEV_TX_PATH_DELAY, 0x14), 285 REG(DEV_PTP_PREDICT_CFG, 0x18), 286 REG(DEV_MAC_ENA_CFG, 0x1c), 287 REG(DEV_MAC_MODE_CFG, 0x20), 288 REG(DEV_MAC_MAXLEN_CFG, 0x24), 289 REG(DEV_MAC_TAGS_CFG, 0x28), 290 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 291 REG(DEV_MAC_IFG_CFG, 0x30), 292 REG(DEV_MAC_HDX_CFG, 0x34), 293 REG(DEV_MAC_DBG_CFG, 0x38), 294 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 295 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 296 REG(DEV_MAC_STICKY, 0x44), 297 REG(PCS1G_CFG, 0x48), 298 REG(PCS1G_MODE_CFG, 0x4c), 299 REG(PCS1G_SD_CFG, 0x50), 300 REG(PCS1G_ANEG_CFG, 0x54), 301 REG(PCS1G_ANEG_NP_CFG, 0x58), 302 REG(PCS1G_LB_CFG, 0x5c), 303 REG(PCS1G_DBG_CFG, 0x60), 304 REG(PCS1G_CDET_CFG, 0x64), 305 REG(PCS1G_ANEG_STATUS, 0x68), 306 REG(PCS1G_ANEG_NP_STATUS, 0x6c), 307 REG(PCS1G_LINK_STATUS, 0x70), 308 REG(PCS1G_LINK_DOWN_CNT, 0x74), 309 REG(PCS1G_STICKY, 0x78), 310 REG(PCS1G_DEBUG_STATUS, 0x7c), 311 REG(PCS1G_LPI_CFG, 0x80), 312 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 313 REG(PCS1G_LPI_STATUS, 0x88), 314 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 315 REG(PCS1G_TSTPAT_STATUS, 0x90), 316 REG(DEV_PCS_FX100_CFG, 0x94), 317 REG(DEV_PCS_FX100_STATUS, 0x98), 318 }; 319 320 static const u32 *ocelot_regmap[TARGET_MAX] = { 321 [ANA] = ocelot_ana_regmap, 322 [QS] = ocelot_qs_regmap, 323 [QSYS] = ocelot_qsys_regmap, 324 [REW] = ocelot_rew_regmap, 325 [SYS] = ocelot_sys_regmap, 326 [S0] = ocelot_vcap_regmap, 327 [S1] = ocelot_vcap_regmap, 328 [S2] = ocelot_vcap_regmap, 329 [PTP] = ocelot_ptp_regmap, 330 [DEV_GMII] = ocelot_dev_gmii_regmap, 331 }; 332 333 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 334 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 335 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 336 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 337 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 338 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 339 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 340 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 341 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 342 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 343 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 344 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 345 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 346 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 347 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 348 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 349 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 350 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 351 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 352 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 353 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 354 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 355 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 356 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 357 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 358 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 359 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 360 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 361 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 362 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 363 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 364 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 365 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 366 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 367 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 368 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 369 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 370 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 371 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 372 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 373 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 374 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 375 /* Replicated per number of ports (12), register size 4 per port */ 376 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 377 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 378 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 379 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 380 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 381 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 382 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 383 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 384 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 385 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 386 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 387 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 388 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 389 }; 390 391 static const struct ocelot_stat_layout ocelot_stats_layout[] = { 392 { .name = "rx_octets", .offset = 0x00, }, 393 { .name = "rx_unicast", .offset = 0x01, }, 394 { .name = "rx_multicast", .offset = 0x02, }, 395 { .name = "rx_broadcast", .offset = 0x03, }, 396 { .name = "rx_shorts", .offset = 0x04, }, 397 { .name = "rx_fragments", .offset = 0x05, }, 398 { .name = "rx_jabbers", .offset = 0x06, }, 399 { .name = "rx_crc_align_errs", .offset = 0x07, }, 400 { .name = "rx_sym_errs", .offset = 0x08, }, 401 { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 402 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 403 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 404 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 405 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 406 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 407 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 408 { .name = "rx_pause", .offset = 0x10, }, 409 { .name = "rx_control", .offset = 0x11, }, 410 { .name = "rx_longs", .offset = 0x12, }, 411 { .name = "rx_classified_drops", .offset = 0x13, }, 412 { .name = "rx_red_prio_0", .offset = 0x14, }, 413 { .name = "rx_red_prio_1", .offset = 0x15, }, 414 { .name = "rx_red_prio_2", .offset = 0x16, }, 415 { .name = "rx_red_prio_3", .offset = 0x17, }, 416 { .name = "rx_red_prio_4", .offset = 0x18, }, 417 { .name = "rx_red_prio_5", .offset = 0x19, }, 418 { .name = "rx_red_prio_6", .offset = 0x1A, }, 419 { .name = "rx_red_prio_7", .offset = 0x1B, }, 420 { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 421 { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 422 { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 423 { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 424 { .name = "rx_yellow_prio_4", .offset = 0x20, }, 425 { .name = "rx_yellow_prio_5", .offset = 0x21, }, 426 { .name = "rx_yellow_prio_6", .offset = 0x22, }, 427 { .name = "rx_yellow_prio_7", .offset = 0x23, }, 428 { .name = "rx_green_prio_0", .offset = 0x24, }, 429 { .name = "rx_green_prio_1", .offset = 0x25, }, 430 { .name = "rx_green_prio_2", .offset = 0x26, }, 431 { .name = "rx_green_prio_3", .offset = 0x27, }, 432 { .name = "rx_green_prio_4", .offset = 0x28, }, 433 { .name = "rx_green_prio_5", .offset = 0x29, }, 434 { .name = "rx_green_prio_6", .offset = 0x2A, }, 435 { .name = "rx_green_prio_7", .offset = 0x2B, }, 436 { .name = "tx_octets", .offset = 0x40, }, 437 { .name = "tx_unicast", .offset = 0x41, }, 438 { .name = "tx_multicast", .offset = 0x42, }, 439 { .name = "tx_broadcast", .offset = 0x43, }, 440 { .name = "tx_collision", .offset = 0x44, }, 441 { .name = "tx_drops", .offset = 0x45, }, 442 { .name = "tx_pause", .offset = 0x46, }, 443 { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 444 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 445 { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 446 { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 447 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 448 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 449 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 450 { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 451 { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 452 { .name = "tx_yellow_prio_2", .offset = 0x50, }, 453 { .name = "tx_yellow_prio_3", .offset = 0x51, }, 454 { .name = "tx_yellow_prio_4", .offset = 0x52, }, 455 { .name = "tx_yellow_prio_5", .offset = 0x53, }, 456 { .name = "tx_yellow_prio_6", .offset = 0x54, }, 457 { .name = "tx_yellow_prio_7", .offset = 0x55, }, 458 { .name = "tx_green_prio_0", .offset = 0x56, }, 459 { .name = "tx_green_prio_1", .offset = 0x57, }, 460 { .name = "tx_green_prio_2", .offset = 0x58, }, 461 { .name = "tx_green_prio_3", .offset = 0x59, }, 462 { .name = "tx_green_prio_4", .offset = 0x5A, }, 463 { .name = "tx_green_prio_5", .offset = 0x5B, }, 464 { .name = "tx_green_prio_6", .offset = 0x5C, }, 465 { .name = "tx_green_prio_7", .offset = 0x5D, }, 466 { .name = "tx_aged", .offset = 0x5E, }, 467 { .name = "drop_local", .offset = 0x80, }, 468 { .name = "drop_tail", .offset = 0x81, }, 469 { .name = "drop_yellow_prio_0", .offset = 0x82, }, 470 { .name = "drop_yellow_prio_1", .offset = 0x83, }, 471 { .name = "drop_yellow_prio_2", .offset = 0x84, }, 472 { .name = "drop_yellow_prio_3", .offset = 0x85, }, 473 { .name = "drop_yellow_prio_4", .offset = 0x86, }, 474 { .name = "drop_yellow_prio_5", .offset = 0x87, }, 475 { .name = "drop_yellow_prio_6", .offset = 0x88, }, 476 { .name = "drop_yellow_prio_7", .offset = 0x89, }, 477 { .name = "drop_green_prio_0", .offset = 0x8A, }, 478 { .name = "drop_green_prio_1", .offset = 0x8B, }, 479 { .name = "drop_green_prio_2", .offset = 0x8C, }, 480 { .name = "drop_green_prio_3", .offset = 0x8D, }, 481 { .name = "drop_green_prio_4", .offset = 0x8E, }, 482 { .name = "drop_green_prio_5", .offset = 0x8F, }, 483 { .name = "drop_green_prio_6", .offset = 0x90, }, 484 { .name = "drop_green_prio_7", .offset = 0x91, }, 485 }; 486 487 static void ocelot_pll5_init(struct ocelot *ocelot) 488 { 489 /* Configure PLL5. This will need a proper CCF driver 490 * The values are coming from the VTSS API for Ocelot 491 */ 492 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 493 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 494 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 495 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 496 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 497 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 498 HSIO_PLL5G_CFG0_ENA_BIAS | 499 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 500 HSIO_PLL5G_CFG0_ENA_CP1 | 501 HSIO_PLL5G_CFG0_SELCPI(2) | 502 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 503 HSIO_PLL5G_CFG0_SELBGV820(4) | 504 HSIO_PLL5G_CFG0_DIV4 | 505 HSIO_PLL5G_CFG0_ENA_CLKTREE | 506 HSIO_PLL5G_CFG0_ENA_LANE); 507 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 508 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 509 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 510 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 511 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 512 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 513 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 514 } 515 516 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 517 { 518 int ret; 519 520 ocelot->map = ocelot_regmap; 521 ocelot->stats_layout = ocelot_stats_layout; 522 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 523 ocelot->num_mact_rows = 1024; 524 ocelot->ops = ops; 525 526 ret = ocelot_regfields_init(ocelot, ocelot_regfields); 527 if (ret) 528 return ret; 529 530 ocelot_pll5_init(ocelot); 531 532 eth_random_addr(ocelot->base_mac); 533 ocelot->base_mac[5] &= 0xf0; 534 535 return 0; 536 } 537 538 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 539 { 540 struct ocelot *ocelot = arg; 541 int grp = 0, err; 542 543 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 544 struct sk_buff *skb; 545 546 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 547 if (err) 548 goto out; 549 550 skb->dev->stats.rx_bytes += skb->len; 551 skb->dev->stats.rx_packets++; 552 553 if (!skb_defer_rx_timestamp(skb)) 554 netif_rx(skb); 555 } 556 557 out: 558 if (err < 0) 559 ocelot_drain_cpu_queue(ocelot, 0); 560 561 return IRQ_HANDLED; 562 } 563 564 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 565 { 566 struct ocelot *ocelot = arg; 567 568 ocelot_get_txtstamp(ocelot); 569 570 return IRQ_HANDLED; 571 } 572 573 static const struct of_device_id mscc_ocelot_match[] = { 574 { .compatible = "mscc,vsc7514-switch" }, 575 { } 576 }; 577 MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 578 579 static int ocelot_reset(struct ocelot *ocelot) 580 { 581 int retries = 100; 582 u32 val; 583 584 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 585 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 586 587 do { 588 msleep(1); 589 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 590 &val); 591 } while (val && --retries); 592 593 if (!retries) 594 return -ETIMEDOUT; 595 596 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 597 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 598 599 return 0; 600 } 601 602 /* Watermark encode 603 * Bit 8: Unit; 0:1, 1:16 604 * Bit 7-0: Value to be multiplied with unit 605 */ 606 static u16 ocelot_wm_enc(u16 value) 607 { 608 WARN_ON(value >= 16 * BIT(8)); 609 610 if (value >= BIT(8)) 611 return BIT(8) | (value / 16); 612 613 return value; 614 } 615 616 static u16 ocelot_wm_dec(u16 wm) 617 { 618 if (wm & BIT(8)) 619 return (wm & GENMASK(7, 0)) * 16; 620 621 return wm; 622 } 623 624 static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 625 { 626 *inuse = (val & GENMASK(23, 12)) >> 12; 627 *maxuse = val & GENMASK(11, 0); 628 } 629 630 static const struct ocelot_ops ocelot_ops = { 631 .reset = ocelot_reset, 632 .wm_enc = ocelot_wm_enc, 633 .wm_dec = ocelot_wm_dec, 634 .wm_stat = ocelot_wm_stat, 635 .port_to_netdev = ocelot_port_to_netdev, 636 .netdev_to_port = ocelot_netdev_to_port, 637 }; 638 639 static const struct vcap_field vsc7514_vcap_es0_keys[] = { 640 [VCAP_ES0_EGR_PORT] = { 0, 4}, 641 [VCAP_ES0_IGR_PORT] = { 4, 4}, 642 [VCAP_ES0_RSV] = { 8, 2}, 643 [VCAP_ES0_L2_MC] = { 10, 1}, 644 [VCAP_ES0_L2_BC] = { 11, 1}, 645 [VCAP_ES0_VID] = { 12, 12}, 646 [VCAP_ES0_DP] = { 24, 1}, 647 [VCAP_ES0_PCP] = { 25, 3}, 648 }; 649 650 static const struct vcap_field vsc7514_vcap_es0_actions[] = { 651 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 652 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 653 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 654 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 655 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 656 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 657 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 658 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 659 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 660 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 661 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 662 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 663 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 664 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 665 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 666 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 667 [VCAP_ES0_ACT_RSV] = { 49, 24}, 668 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 669 }; 670 671 static const struct vcap_field vsc7514_vcap_is1_keys[] = { 672 [VCAP_IS1_HK_TYPE] = { 0, 1}, 673 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 674 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12}, 675 [VCAP_IS1_HK_RSV] = { 15, 9}, 676 [VCAP_IS1_HK_OAM_Y1731] = { 24, 1}, 677 [VCAP_IS1_HK_L2_MC] = { 25, 1}, 678 [VCAP_IS1_HK_L2_BC] = { 26, 1}, 679 [VCAP_IS1_HK_IP_MC] = { 27, 1}, 680 [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1}, 681 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1}, 682 [VCAP_IS1_HK_TPID] = { 30, 1}, 683 [VCAP_IS1_HK_VID] = { 31, 12}, 684 [VCAP_IS1_HK_DEI] = { 43, 1}, 685 [VCAP_IS1_HK_PCP] = { 44, 3}, 686 /* Specific Fields for IS1 Half Key S1_NORMAL */ 687 [VCAP_IS1_HK_L2_SMAC] = { 47, 48}, 688 [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1}, 689 [VCAP_IS1_HK_ETYPE] = { 96, 16}, 690 [VCAP_IS1_HK_IP_SNAP] = {112, 1}, 691 [VCAP_IS1_HK_IP4] = {113, 1}, 692 /* Layer-3 Information */ 693 [VCAP_IS1_HK_L3_FRAGMENT] = {114, 1}, 694 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {115, 1}, 695 [VCAP_IS1_HK_L3_OPTIONS] = {116, 1}, 696 [VCAP_IS1_HK_L3_DSCP] = {117, 6}, 697 [VCAP_IS1_HK_L3_IP4_SIP] = {123, 32}, 698 /* Layer-4 Information */ 699 [VCAP_IS1_HK_TCP_UDP] = {155, 1}, 700 [VCAP_IS1_HK_TCP] = {156, 1}, 701 [VCAP_IS1_HK_L4_SPORT] = {157, 16}, 702 [VCAP_IS1_HK_L4_RNG] = {173, 8}, 703 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 704 [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1}, 705 [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12}, 706 [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1}, 707 [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3}, 708 [VCAP_IS1_HK_IP4_IP4] = { 64, 1}, 709 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1}, 710 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1}, 711 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1}, 712 [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6}, 713 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32}, 714 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {106, 32}, 715 [VCAP_IS1_HK_IP4_L3_PROTO] = {138, 8}, 716 [VCAP_IS1_HK_IP4_TCP_UDP] = {146, 1}, 717 [VCAP_IS1_HK_IP4_TCP] = {147, 1}, 718 [VCAP_IS1_HK_IP4_L4_RNG] = {148, 8}, 719 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {156, 32}, 720 }; 721 722 static const struct vcap_field vsc7514_vcap_is1_actions[] = { 723 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 724 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 725 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 726 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 727 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 728 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 729 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 730 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 731 [VCAP_IS1_ACT_RSV] = { 29, 9}, 732 /* The fields below are incorrectly shifted by 2 in the manual */ 733 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 734 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 735 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 736 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 737 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 738 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 739 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 740 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 741 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 742 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 743 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 744 }; 745 746 static const struct vcap_field vsc7514_vcap_is2_keys[] = { 747 /* Common: 46 bits */ 748 [VCAP_IS2_TYPE] = { 0, 4}, 749 [VCAP_IS2_HK_FIRST] = { 4, 1}, 750 [VCAP_IS2_HK_PAG] = { 5, 8}, 751 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 752 [VCAP_IS2_HK_RSV2] = { 25, 1}, 753 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 754 [VCAP_IS2_HK_L2_MC] = { 27, 1}, 755 [VCAP_IS2_HK_L2_BC] = { 28, 1}, 756 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 757 [VCAP_IS2_HK_VID] = { 30, 12}, 758 [VCAP_IS2_HK_DEI] = { 42, 1}, 759 [VCAP_IS2_HK_PCP] = { 43, 3}, 760 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 761 [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 762 [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 763 /* MAC_ETYPE (TYPE=000) */ 764 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 765 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 766 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 767 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 768 /* MAC_LLC (TYPE=001) */ 769 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 770 /* MAC_SNAP (TYPE=010) */ 771 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 772 /* MAC_ARP (TYPE=011) */ 773 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 774 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 775 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 776 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 777 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 778 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 779 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 780 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 781 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 782 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 783 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 784 /* IP4_TCP_UDP / IP4_OTHER common */ 785 [VCAP_IS2_HK_IP4] = { 46, 1}, 786 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 787 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 788 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 789 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 790 [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 791 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 792 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 793 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 794 /* IP4_TCP_UDP (TYPE=100) */ 795 [VCAP_IS2_HK_TCP] = {124, 1}, 796 [VCAP_IS2_HK_L4_DPORT] = {125, 16}, 797 [VCAP_IS2_HK_L4_SPORT] = {141, 16}, 798 [VCAP_IS2_HK_L4_RNG] = {157, 8}, 799 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 800 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 801 [VCAP_IS2_HK_L4_FIN] = {167, 1}, 802 [VCAP_IS2_HK_L4_SYN] = {168, 1}, 803 [VCAP_IS2_HK_L4_RST] = {169, 1}, 804 [VCAP_IS2_HK_L4_PSH] = {170, 1}, 805 [VCAP_IS2_HK_L4_ACK] = {171, 1}, 806 [VCAP_IS2_HK_L4_URG] = {172, 1}, 807 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 808 [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 809 /* IP4_OTHER (TYPE=101) */ 810 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 811 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 812 /* IP6_STD (TYPE=110) */ 813 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 814 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 815 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 816 /* OAM (TYPE=111) */ 817 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 818 [VCAP_IS2_HK_OAM_VER] = {149, 5}, 819 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 820 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 821 [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 822 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 823 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 824 }; 825 826 static const struct vcap_field vsc7514_vcap_is2_actions[] = { 827 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 828 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 829 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 830 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 831 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 832 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 833 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 834 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 835 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 836 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 837 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 838 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 839 [VCAP_IS2_ACT_RSV] = { 41, 2}, 840 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 841 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 842 }; 843 844 static struct vcap_props vsc7514_vcap_props[] = { 845 [VCAP_ES0] = { 846 .action_type_width = 0, 847 .action_table = { 848 [ES0_ACTION_TYPE_NORMAL] = { 849 .width = 73, /* HIT_STICKY not included */ 850 .count = 1, 851 }, 852 }, 853 .target = S0, 854 .keys = vsc7514_vcap_es0_keys, 855 .actions = vsc7514_vcap_es0_actions, 856 }, 857 [VCAP_IS1] = { 858 .action_type_width = 0, 859 .action_table = { 860 [IS1_ACTION_TYPE_NORMAL] = { 861 .width = 78, /* HIT_STICKY not included */ 862 .count = 4, 863 }, 864 }, 865 .target = S1, 866 .keys = vsc7514_vcap_is1_keys, 867 .actions = vsc7514_vcap_is1_actions, 868 }, 869 [VCAP_IS2] = { 870 .action_type_width = 1, 871 .action_table = { 872 [IS2_ACTION_TYPE_NORMAL] = { 873 .width = 49, 874 .count = 2 875 }, 876 [IS2_ACTION_TYPE_SMAC_SIP] = { 877 .width = 6, 878 .count = 4 879 }, 880 }, 881 .target = S2, 882 .keys = vsc7514_vcap_is2_keys, 883 .actions = vsc7514_vcap_is2_actions, 884 }, 885 }; 886 887 static struct ptp_clock_info ocelot_ptp_clock_info = { 888 .owner = THIS_MODULE, 889 .name = "ocelot ptp", 890 .max_adj = 0x7fffffff, 891 .n_alarm = 0, 892 .n_ext_ts = 0, 893 .n_per_out = OCELOT_PTP_PINS_NUM, 894 .n_pins = OCELOT_PTP_PINS_NUM, 895 .pps = 0, 896 .gettime64 = ocelot_ptp_gettime64, 897 .settime64 = ocelot_ptp_settime64, 898 .adjtime = ocelot_ptp_adjtime, 899 .adjfine = ocelot_ptp_adjfine, 900 .verify = ocelot_ptp_verify, 901 .enable = ocelot_ptp_enable, 902 }; 903 904 static void mscc_ocelot_teardown_devlink_ports(struct ocelot *ocelot) 905 { 906 int port; 907 908 for (port = 0; port < ocelot->num_phys_ports; port++) 909 ocelot_port_devlink_teardown(ocelot, port); 910 } 911 912 static void mscc_ocelot_release_ports(struct ocelot *ocelot) 913 { 914 int port; 915 916 for (port = 0; port < ocelot->num_phys_ports; port++) { 917 struct ocelot_port *ocelot_port; 918 919 ocelot_port = ocelot->ports[port]; 920 if (!ocelot_port) 921 continue; 922 923 ocelot_deinit_port(ocelot, port); 924 ocelot_release_port(ocelot_port); 925 } 926 } 927 928 static int mscc_ocelot_init_ports(struct platform_device *pdev, 929 struct device_node *ports) 930 { 931 struct ocelot *ocelot = platform_get_drvdata(pdev); 932 u32 devlink_ports_registered = 0; 933 struct device_node *portnp; 934 int port, err; 935 u32 reg; 936 937 ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 938 sizeof(struct ocelot_port *), GFP_KERNEL); 939 if (!ocelot->ports) 940 return -ENOMEM; 941 942 ocelot->devlink_ports = devm_kcalloc(ocelot->dev, 943 ocelot->num_phys_ports, 944 sizeof(*ocelot->devlink_ports), 945 GFP_KERNEL); 946 if (!ocelot->devlink_ports) 947 return -ENOMEM; 948 949 for_each_available_child_of_node(ports, portnp) { 950 struct ocelot_port_private *priv; 951 struct ocelot_port *ocelot_port; 952 struct devlink_port *dlp; 953 struct regmap *target; 954 struct resource *res; 955 char res_name[8]; 956 957 if (of_property_read_u32(portnp, "reg", ®)) 958 continue; 959 960 port = reg; 961 if (port < 0 || port >= ocelot->num_phys_ports) { 962 dev_err(ocelot->dev, 963 "invalid port number: %d >= %d\n", port, 964 ocelot->num_phys_ports); 965 continue; 966 } 967 968 snprintf(res_name, sizeof(res_name), "port%d", port); 969 970 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 971 res_name); 972 target = ocelot_regmap_init(ocelot, res); 973 if (IS_ERR(target)) { 974 err = PTR_ERR(target); 975 of_node_put(portnp); 976 goto out_teardown; 977 } 978 979 err = ocelot_port_devlink_init(ocelot, port, 980 DEVLINK_PORT_FLAVOUR_PHYSICAL); 981 if (err) { 982 of_node_put(portnp); 983 goto out_teardown; 984 } 985 986 err = ocelot_probe_port(ocelot, port, target, portnp); 987 if (err) { 988 ocelot_port_devlink_teardown(ocelot, port); 989 continue; 990 } 991 992 devlink_ports_registered |= BIT(port); 993 994 ocelot_port = ocelot->ports[port]; 995 priv = container_of(ocelot_port, struct ocelot_port_private, 996 port); 997 dlp = &ocelot->devlink_ports[port]; 998 devlink_port_type_eth_set(dlp, priv->dev); 999 } 1000 1001 /* Initialize unused devlink ports at the end */ 1002 for (port = 0; port < ocelot->num_phys_ports; port++) { 1003 if (devlink_ports_registered & BIT(port)) 1004 continue; 1005 1006 err = ocelot_port_devlink_init(ocelot, port, 1007 DEVLINK_PORT_FLAVOUR_UNUSED); 1008 if (err) 1009 goto out_teardown; 1010 1011 devlink_ports_registered |= BIT(port); 1012 } 1013 1014 return 0; 1015 1016 out_teardown: 1017 /* Unregister the network interfaces */ 1018 mscc_ocelot_release_ports(ocelot); 1019 /* Tear down devlink ports for the registered network interfaces */ 1020 for (port = 0; port < ocelot->num_phys_ports; port++) { 1021 if (devlink_ports_registered & BIT(port)) 1022 ocelot_port_devlink_teardown(ocelot, port); 1023 } 1024 return err; 1025 } 1026 1027 static int mscc_ocelot_probe(struct platform_device *pdev) 1028 { 1029 struct device_node *np = pdev->dev.of_node; 1030 int err, irq_xtr, irq_ptp_rdy; 1031 struct device_node *ports; 1032 struct devlink *devlink; 1033 struct ocelot *ocelot; 1034 struct regmap *hsio; 1035 unsigned int i; 1036 1037 struct { 1038 enum ocelot_target id; 1039 char *name; 1040 u8 optional:1; 1041 } io_target[] = { 1042 { SYS, "sys" }, 1043 { REW, "rew" }, 1044 { QSYS, "qsys" }, 1045 { ANA, "ana" }, 1046 { QS, "qs" }, 1047 { S0, "s0" }, 1048 { S1, "s1" }, 1049 { S2, "s2" }, 1050 { PTP, "ptp", 1 }, 1051 }; 1052 1053 if (!np && !pdev->dev.platform_data) 1054 return -ENODEV; 1055 1056 devlink = 1057 devlink_alloc(&ocelot_devlink_ops, sizeof(*ocelot), &pdev->dev); 1058 if (!devlink) 1059 return -ENOMEM; 1060 1061 ocelot = devlink_priv(devlink); 1062 ocelot->devlink = priv_to_devlink(ocelot); 1063 platform_set_drvdata(pdev, ocelot); 1064 ocelot->dev = &pdev->dev; 1065 1066 for (i = 0; i < ARRAY_SIZE(io_target); i++) { 1067 struct regmap *target; 1068 struct resource *res; 1069 1070 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1071 io_target[i].name); 1072 1073 target = ocelot_regmap_init(ocelot, res); 1074 if (IS_ERR(target)) { 1075 if (io_target[i].optional) { 1076 ocelot->targets[io_target[i].id] = NULL; 1077 continue; 1078 } 1079 err = PTR_ERR(target); 1080 goto out_free_devlink; 1081 } 1082 1083 ocelot->targets[io_target[i].id] = target; 1084 } 1085 1086 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 1087 if (IS_ERR(hsio)) { 1088 dev_err(&pdev->dev, "missing hsio syscon\n"); 1089 err = PTR_ERR(hsio); 1090 goto out_free_devlink; 1091 } 1092 1093 ocelot->targets[HSIO] = hsio; 1094 1095 err = ocelot_chip_init(ocelot, &ocelot_ops); 1096 if (err) 1097 goto out_free_devlink; 1098 1099 irq_xtr = platform_get_irq_byname(pdev, "xtr"); 1100 if (irq_xtr < 0) { 1101 err = irq_xtr; 1102 goto out_free_devlink; 1103 } 1104 1105 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 1106 ocelot_xtr_irq_handler, IRQF_ONESHOT, 1107 "frame extraction", ocelot); 1108 if (err) 1109 goto out_free_devlink; 1110 1111 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 1112 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 1113 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 1114 ocelot_ptp_rdy_irq_handler, 1115 IRQF_ONESHOT, "ptp ready", 1116 ocelot); 1117 if (err) 1118 goto out_free_devlink; 1119 1120 /* Both the PTP interrupt and the PTP bank are available */ 1121 ocelot->ptp = 1; 1122 } 1123 1124 ports = of_get_child_by_name(np, "ethernet-ports"); 1125 if (!ports) { 1126 dev_err(ocelot->dev, "no ethernet-ports child node found\n"); 1127 err = -ENODEV; 1128 goto out_free_devlink; 1129 } 1130 1131 ocelot->num_phys_ports = of_get_child_count(ports); 1132 ocelot->num_flooding_pgids = 1; 1133 1134 ocelot->vcap = vsc7514_vcap_props; 1135 1136 ocelot->vcap_pol.base = VSC7514_VCAP_POLICER_BASE; 1137 ocelot->vcap_pol.max = VSC7514_VCAP_POLICER_MAX; 1138 1139 ocelot->npi = -1; 1140 1141 err = ocelot_init(ocelot); 1142 if (err) 1143 goto out_put_ports; 1144 1145 err = mscc_ocelot_init_ports(pdev, ports); 1146 if (err) 1147 goto out_ocelot_devlink_unregister; 1148 1149 err = ocelot_devlink_sb_register(ocelot); 1150 if (err) 1151 goto out_ocelot_release_ports; 1152 1153 if (ocelot->ptp) { 1154 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1155 if (err) { 1156 dev_err(ocelot->dev, 1157 "Timestamp initialization failed\n"); 1158 ocelot->ptp = 0; 1159 } 1160 } 1161 1162 register_netdevice_notifier(&ocelot_netdevice_nb); 1163 register_switchdev_notifier(&ocelot_switchdev_nb); 1164 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1165 1166 of_node_put(ports); 1167 devlink_register(devlink); 1168 1169 dev_info(&pdev->dev, "Ocelot switch probed\n"); 1170 1171 return 0; 1172 1173 out_ocelot_release_ports: 1174 mscc_ocelot_release_ports(ocelot); 1175 mscc_ocelot_teardown_devlink_ports(ocelot); 1176 out_ocelot_devlink_unregister: 1177 ocelot_deinit(ocelot); 1178 out_put_ports: 1179 of_node_put(ports); 1180 out_free_devlink: 1181 devlink_free(devlink); 1182 return err; 1183 } 1184 1185 static int mscc_ocelot_remove(struct platform_device *pdev) 1186 { 1187 struct ocelot *ocelot = platform_get_drvdata(pdev); 1188 1189 devlink_unregister(ocelot->devlink); 1190 ocelot_deinit_timestamp(ocelot); 1191 ocelot_devlink_sb_unregister(ocelot); 1192 mscc_ocelot_release_ports(ocelot); 1193 mscc_ocelot_teardown_devlink_ports(ocelot); 1194 ocelot_deinit(ocelot); 1195 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1196 unregister_switchdev_notifier(&ocelot_switchdev_nb); 1197 unregister_netdevice_notifier(&ocelot_netdevice_nb); 1198 devlink_free(ocelot->devlink); 1199 1200 return 0; 1201 } 1202 1203 static struct platform_driver mscc_ocelot_driver = { 1204 .probe = mscc_ocelot_probe, 1205 .remove = mscc_ocelot_remove, 1206 .driver = { 1207 .name = "ocelot-switch", 1208 .of_match_table = mscc_ocelot_match, 1209 }, 1210 }; 1211 1212 module_platform_driver(mscc_ocelot_driver); 1213 1214 MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1215 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1216 MODULE_LICENSE("Dual MIT/GPL"); 1217