1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_net.h> 10 #include <linux/netdevice.h> 11 #include <linux/of_mdio.h> 12 #include <linux/of_platform.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/skbuff.h> 15 #include <net/switchdev.h> 16 17 #include <soc/mscc/ocelot_vcap.h> 18 #include <soc/mscc/ocelot_hsio.h> 19 #include "ocelot.h" 20 21 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) 22 #define VSC7514_VCAP_IS2_CNT 64 23 #define VSC7514_VCAP_IS2_ENTRY_WIDTH 376 24 #define VSC7514_VCAP_IS2_ACTION_WIDTH 99 25 #define VSC7514_VCAP_PORT_CNT 11 26 27 static const u32 ocelot_ana_regmap[] = { 28 REG(ANA_ADVLEARN, 0x009000), 29 REG(ANA_VLANMASK, 0x009004), 30 REG(ANA_PORT_B_DOMAIN, 0x009008), 31 REG(ANA_ANAGEFIL, 0x00900c), 32 REG(ANA_ANEVENTS, 0x009010), 33 REG(ANA_STORMLIMIT_BURST, 0x009014), 34 REG(ANA_STORMLIMIT_CFG, 0x009018), 35 REG(ANA_ISOLATED_PORTS, 0x009028), 36 REG(ANA_COMMUNITY_PORTS, 0x00902c), 37 REG(ANA_AUTOAGE, 0x009030), 38 REG(ANA_MACTOPTIONS, 0x009034), 39 REG(ANA_LEARNDISC, 0x009038), 40 REG(ANA_AGENCTRL, 0x00903c), 41 REG(ANA_MIRRORPORTS, 0x009040), 42 REG(ANA_EMIRRORPORTS, 0x009044), 43 REG(ANA_FLOODING, 0x009048), 44 REG(ANA_FLOODING_IPMC, 0x00904c), 45 REG(ANA_SFLOW_CFG, 0x009050), 46 REG(ANA_PORT_MODE, 0x009080), 47 REG(ANA_PGID_PGID, 0x008c00), 48 REG(ANA_TABLES_ANMOVED, 0x008b30), 49 REG(ANA_TABLES_MACHDATA, 0x008b34), 50 REG(ANA_TABLES_MACLDATA, 0x008b38), 51 REG(ANA_TABLES_MACACCESS, 0x008b3c), 52 REG(ANA_TABLES_MACTINDX, 0x008b40), 53 REG(ANA_TABLES_VLANACCESS, 0x008b44), 54 REG(ANA_TABLES_VLANTIDX, 0x008b48), 55 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 56 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 57 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 58 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 59 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 60 REG(ANA_MSTI_STATE, 0x008e00), 61 REG(ANA_PORT_VLAN_CFG, 0x007000), 62 REG(ANA_PORT_DROP_CFG, 0x007004), 63 REG(ANA_PORT_QOS_CFG, 0x007008), 64 REG(ANA_PORT_VCAP_CFG, 0x00700c), 65 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 66 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 67 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 68 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 69 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 70 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 71 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 72 REG(ANA_PORT_PORT_CFG, 0x007070), 73 REG(ANA_PORT_POL_CFG, 0x007074), 74 REG(ANA_PORT_PTP_CFG, 0x007078), 75 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 76 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 77 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 78 REG(ANA_PFC_PFC_CFG, 0x008800), 79 REG(ANA_PFC_PFC_TIMER, 0x008804), 80 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 81 REG(ANA_IPT_IPT, 0x008004), 82 REG(ANA_PPT_PPT, 0x008ac0), 83 REG(ANA_FID_MAP_FID_MAP, 0x000000), 84 REG(ANA_AGGR_CFG, 0x0090b4), 85 REG(ANA_CPUQ_CFG, 0x0090b8), 86 REG(ANA_CPUQ_CFG2, 0x0090bc), 87 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 88 REG(ANA_DSCP_CFG, 0x009100), 89 REG(ANA_DSCP_REWR_CFG, 0x009200), 90 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 91 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 92 REG(ANA_VRAP_CFG, 0x009280), 93 REG(ANA_VRAP_HDR_DATA, 0x009284), 94 REG(ANA_VRAP_HDR_MASK, 0x009288), 95 REG(ANA_DISCARD_CFG, 0x00928c), 96 REG(ANA_FID_CFG, 0x009290), 97 REG(ANA_POL_PIR_CFG, 0x004000), 98 REG(ANA_POL_CIR_CFG, 0x004004), 99 REG(ANA_POL_MODE_CFG, 0x004008), 100 REG(ANA_POL_PIR_STATE, 0x00400c), 101 REG(ANA_POL_CIR_STATE, 0x004010), 102 REG(ANA_POL_STATE, 0x004014), 103 REG(ANA_POL_FLOWC, 0x008b80), 104 REG(ANA_POL_HYST, 0x008bec), 105 REG(ANA_POL_MISC_CFG, 0x008bf0), 106 }; 107 108 static const u32 ocelot_qs_regmap[] = { 109 REG(QS_XTR_GRP_CFG, 0x000000), 110 REG(QS_XTR_RD, 0x000008), 111 REG(QS_XTR_FRM_PRUNING, 0x000010), 112 REG(QS_XTR_FLUSH, 0x000018), 113 REG(QS_XTR_DATA_PRESENT, 0x00001c), 114 REG(QS_XTR_CFG, 0x000020), 115 REG(QS_INJ_GRP_CFG, 0x000024), 116 REG(QS_INJ_WR, 0x00002c), 117 REG(QS_INJ_CTRL, 0x000034), 118 REG(QS_INJ_STATUS, 0x00003c), 119 REG(QS_INJ_ERR, 0x000040), 120 REG(QS_INH_DBG, 0x000048), 121 }; 122 123 static const u32 ocelot_qsys_regmap[] = { 124 REG(QSYS_PORT_MODE, 0x011200), 125 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 126 REG(QSYS_STAT_CNT_CFG, 0x011264), 127 REG(QSYS_EEE_CFG, 0x011268), 128 REG(QSYS_EEE_THRES, 0x011294), 129 REG(QSYS_IGR_NO_SHARING, 0x011298), 130 REG(QSYS_EGR_NO_SHARING, 0x01129c), 131 REG(QSYS_SW_STATUS, 0x0112a0), 132 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 133 REG(QSYS_PAD_CFG, 0x0112d4), 134 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 135 REG(QSYS_QMAP, 0x0112dc), 136 REG(QSYS_ISDX_SGRP, 0x011400), 137 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 138 REG(QSYS_TFRM_MISC, 0x011310), 139 REG(QSYS_TFRM_PORT_DLY, 0x011314), 140 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 141 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 142 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 143 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 144 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 145 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 146 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 147 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 148 REG(QSYS_RED_PROFILE, 0x011338), 149 REG(QSYS_RES_QOS_MODE, 0x011378), 150 REG(QSYS_RES_CFG, 0x012000), 151 REG(QSYS_RES_STAT, 0x012004), 152 REG(QSYS_EGR_DROP_MODE, 0x01137c), 153 REG(QSYS_EQ_CTRL, 0x011380), 154 REG(QSYS_EVENTS_CORE, 0x011384), 155 REG(QSYS_CIR_CFG, 0x000000), 156 REG(QSYS_EIR_CFG, 0x000004), 157 REG(QSYS_SE_CFG, 0x000008), 158 REG(QSYS_SE_DWRR_CFG, 0x00000c), 159 REG(QSYS_SE_CONNECT, 0x00003c), 160 REG(QSYS_SE_DLB_SENSE, 0x000040), 161 REG(QSYS_CIR_STATE, 0x000044), 162 REG(QSYS_EIR_STATE, 0x000048), 163 REG(QSYS_SE_STATE, 0x00004c), 164 REG(QSYS_HSCH_MISC_CFG, 0x011388), 165 }; 166 167 static const u32 ocelot_rew_regmap[] = { 168 REG(REW_PORT_VLAN_CFG, 0x000000), 169 REG(REW_TAG_CFG, 0x000004), 170 REG(REW_PORT_CFG, 0x000008), 171 REG(REW_DSCP_CFG, 0x00000c), 172 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 173 REG(REW_PTP_CFG, 0x000050), 174 REG(REW_PTP_DLY1_CFG, 0x000054), 175 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 176 REG(REW_DSCP_REMAP_CFG, 0x000790), 177 REG(REW_STAT_CFG, 0x000890), 178 REG(REW_PPT, 0x000680), 179 }; 180 181 static const u32 ocelot_sys_regmap[] = { 182 REG(SYS_COUNT_RX_OCTETS, 0x000000), 183 REG(SYS_COUNT_RX_UNICAST, 0x000004), 184 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 185 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 186 REG(SYS_COUNT_RX_SHORTS, 0x000010), 187 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 188 REG(SYS_COUNT_RX_JABBERS, 0x000018), 189 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 190 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 191 REG(SYS_COUNT_RX_64, 0x000024), 192 REG(SYS_COUNT_RX_65_127, 0x000028), 193 REG(SYS_COUNT_RX_128_255, 0x00002c), 194 REG(SYS_COUNT_RX_256_1023, 0x000030), 195 REG(SYS_COUNT_RX_1024_1526, 0x000034), 196 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 197 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 198 REG(SYS_COUNT_RX_CONTROL, 0x000040), 199 REG(SYS_COUNT_RX_LONGS, 0x000044), 200 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 201 REG(SYS_COUNT_TX_OCTETS, 0x000100), 202 REG(SYS_COUNT_TX_UNICAST, 0x000104), 203 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 204 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 205 REG(SYS_COUNT_TX_COLLISION, 0x000110), 206 REG(SYS_COUNT_TX_DROPS, 0x000114), 207 REG(SYS_COUNT_TX_PAUSE, 0x000118), 208 REG(SYS_COUNT_TX_64, 0x00011c), 209 REG(SYS_COUNT_TX_65_127, 0x000120), 210 REG(SYS_COUNT_TX_128_511, 0x000124), 211 REG(SYS_COUNT_TX_512_1023, 0x000128), 212 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 213 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 214 REG(SYS_COUNT_TX_AGING, 0x000170), 215 REG(SYS_RESET_CFG, 0x000508), 216 REG(SYS_CMID, 0x00050c), 217 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 218 REG(SYS_PORT_MODE, 0x000514), 219 REG(SYS_FRONT_PORT_MODE, 0x000548), 220 REG(SYS_FRM_AGING, 0x000574), 221 REG(SYS_STAT_CFG, 0x000578), 222 REG(SYS_SW_STATUS, 0x00057c), 223 REG(SYS_MISC_CFG, 0x0005ac), 224 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 225 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 226 REG(SYS_CM_ADDR, 0x000500), 227 REG(SYS_CM_DATA, 0x000504), 228 REG(SYS_PAUSE_CFG, 0x000608), 229 REG(SYS_PAUSE_TOT_CFG, 0x000638), 230 REG(SYS_ATOP, 0x00063c), 231 REG(SYS_ATOP_TOT_CFG, 0x00066c), 232 REG(SYS_MAC_FC_CFG, 0x000670), 233 REG(SYS_MMGT, 0x00069c), 234 REG(SYS_MMGT_FAST, 0x0006a0), 235 REG(SYS_EVENTS_DIF, 0x0006a4), 236 REG(SYS_EVENTS_CORE, 0x0006b4), 237 REG(SYS_CNT, 0x000000), 238 REG(SYS_PTP_STATUS, 0x0006b8), 239 REG(SYS_PTP_TXSTAMP, 0x0006bc), 240 REG(SYS_PTP_NXT, 0x0006c0), 241 REG(SYS_PTP_CFG, 0x0006c4), 242 }; 243 244 static const u32 ocelot_s2_regmap[] = { 245 REG(S2_CORE_UPDATE_CTRL, 0x000000), 246 REG(S2_CORE_MV_CFG, 0x000004), 247 REG(S2_CACHE_ENTRY_DAT, 0x000008), 248 REG(S2_CACHE_MASK_DAT, 0x000108), 249 REG(S2_CACHE_ACTION_DAT, 0x000208), 250 REG(S2_CACHE_CNT_DAT, 0x000308), 251 REG(S2_CACHE_TG_DAT, 0x000388), 252 }; 253 254 static const u32 ocelot_ptp_regmap[] = { 255 REG(PTP_PIN_CFG, 0x000000), 256 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 257 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 258 REG(PTP_PIN_TOD_NSEC, 0x00000c), 259 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 260 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 261 REG(PTP_CFG_MISC, 0x0000a0), 262 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 263 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 264 }; 265 266 static const u32 ocelot_dev_gmii_regmap[] = { 267 REG(DEV_CLOCK_CFG, 0x0), 268 REG(DEV_PORT_MISC, 0x4), 269 REG(DEV_EVENTS, 0x8), 270 REG(DEV_EEE_CFG, 0xc), 271 REG(DEV_RX_PATH_DELAY, 0x10), 272 REG(DEV_TX_PATH_DELAY, 0x14), 273 REG(DEV_PTP_PREDICT_CFG, 0x18), 274 REG(DEV_MAC_ENA_CFG, 0x1c), 275 REG(DEV_MAC_MODE_CFG, 0x20), 276 REG(DEV_MAC_MAXLEN_CFG, 0x24), 277 REG(DEV_MAC_TAGS_CFG, 0x28), 278 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 279 REG(DEV_MAC_IFG_CFG, 0x30), 280 REG(DEV_MAC_HDX_CFG, 0x34), 281 REG(DEV_MAC_DBG_CFG, 0x38), 282 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 283 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 284 REG(DEV_MAC_STICKY, 0x44), 285 REG(PCS1G_CFG, 0x48), 286 REG(PCS1G_MODE_CFG, 0x4c), 287 REG(PCS1G_SD_CFG, 0x50), 288 REG(PCS1G_ANEG_CFG, 0x54), 289 REG(PCS1G_ANEG_NP_CFG, 0x58), 290 REG(PCS1G_LB_CFG, 0x5c), 291 REG(PCS1G_DBG_CFG, 0x60), 292 REG(PCS1G_CDET_CFG, 0x64), 293 REG(PCS1G_ANEG_STATUS, 0x68), 294 REG(PCS1G_ANEG_NP_STATUS, 0x6c), 295 REG(PCS1G_LINK_STATUS, 0x70), 296 REG(PCS1G_LINK_DOWN_CNT, 0x74), 297 REG(PCS1G_STICKY, 0x78), 298 REG(PCS1G_DEBUG_STATUS, 0x7c), 299 REG(PCS1G_LPI_CFG, 0x80), 300 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 301 REG(PCS1G_LPI_STATUS, 0x88), 302 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 303 REG(PCS1G_TSTPAT_STATUS, 0x90), 304 REG(DEV_PCS_FX100_CFG, 0x94), 305 REG(DEV_PCS_FX100_STATUS, 0x98), 306 }; 307 308 static const u32 *ocelot_regmap[TARGET_MAX] = { 309 [ANA] = ocelot_ana_regmap, 310 [QS] = ocelot_qs_regmap, 311 [QSYS] = ocelot_qsys_regmap, 312 [REW] = ocelot_rew_regmap, 313 [SYS] = ocelot_sys_regmap, 314 [S2] = ocelot_s2_regmap, 315 [PTP] = ocelot_ptp_regmap, 316 [DEV_GMII] = ocelot_dev_gmii_regmap, 317 }; 318 319 static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 320 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 321 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 322 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 323 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 324 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 325 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 326 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 327 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 328 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 329 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 330 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 331 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 332 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 333 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 334 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 335 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 336 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 337 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 338 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 339 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 340 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 341 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 342 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 343 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 344 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 345 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 346 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 347 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 348 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 349 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 350 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 351 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 352 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 353 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 354 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 355 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 356 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 357 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 358 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 359 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 360 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 361 /* Replicated per number of ports (12), register size 4 per port */ 362 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 363 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 364 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 365 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 366 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 367 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 368 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 369 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 370 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 371 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 372 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 373 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 374 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 375 }; 376 377 static const struct ocelot_stat_layout ocelot_stats_layout[] = { 378 { .name = "rx_octets", .offset = 0x00, }, 379 { .name = "rx_unicast", .offset = 0x01, }, 380 { .name = "rx_multicast", .offset = 0x02, }, 381 { .name = "rx_broadcast", .offset = 0x03, }, 382 { .name = "rx_shorts", .offset = 0x04, }, 383 { .name = "rx_fragments", .offset = 0x05, }, 384 { .name = "rx_jabbers", .offset = 0x06, }, 385 { .name = "rx_crc_align_errs", .offset = 0x07, }, 386 { .name = "rx_sym_errs", .offset = 0x08, }, 387 { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 388 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 389 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 390 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 391 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 392 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 393 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 394 { .name = "rx_pause", .offset = 0x10, }, 395 { .name = "rx_control", .offset = 0x11, }, 396 { .name = "rx_longs", .offset = 0x12, }, 397 { .name = "rx_classified_drops", .offset = 0x13, }, 398 { .name = "rx_red_prio_0", .offset = 0x14, }, 399 { .name = "rx_red_prio_1", .offset = 0x15, }, 400 { .name = "rx_red_prio_2", .offset = 0x16, }, 401 { .name = "rx_red_prio_3", .offset = 0x17, }, 402 { .name = "rx_red_prio_4", .offset = 0x18, }, 403 { .name = "rx_red_prio_5", .offset = 0x19, }, 404 { .name = "rx_red_prio_6", .offset = 0x1A, }, 405 { .name = "rx_red_prio_7", .offset = 0x1B, }, 406 { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 407 { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 408 { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 409 { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 410 { .name = "rx_yellow_prio_4", .offset = 0x20, }, 411 { .name = "rx_yellow_prio_5", .offset = 0x21, }, 412 { .name = "rx_yellow_prio_6", .offset = 0x22, }, 413 { .name = "rx_yellow_prio_7", .offset = 0x23, }, 414 { .name = "rx_green_prio_0", .offset = 0x24, }, 415 { .name = "rx_green_prio_1", .offset = 0x25, }, 416 { .name = "rx_green_prio_2", .offset = 0x26, }, 417 { .name = "rx_green_prio_3", .offset = 0x27, }, 418 { .name = "rx_green_prio_4", .offset = 0x28, }, 419 { .name = "rx_green_prio_5", .offset = 0x29, }, 420 { .name = "rx_green_prio_6", .offset = 0x2A, }, 421 { .name = "rx_green_prio_7", .offset = 0x2B, }, 422 { .name = "tx_octets", .offset = 0x40, }, 423 { .name = "tx_unicast", .offset = 0x41, }, 424 { .name = "tx_multicast", .offset = 0x42, }, 425 { .name = "tx_broadcast", .offset = 0x43, }, 426 { .name = "tx_collision", .offset = 0x44, }, 427 { .name = "tx_drops", .offset = 0x45, }, 428 { .name = "tx_pause", .offset = 0x46, }, 429 { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 430 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 431 { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 432 { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 433 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 434 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 435 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 436 { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 437 { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 438 { .name = "tx_yellow_prio_2", .offset = 0x50, }, 439 { .name = "tx_yellow_prio_3", .offset = 0x51, }, 440 { .name = "tx_yellow_prio_4", .offset = 0x52, }, 441 { .name = "tx_yellow_prio_5", .offset = 0x53, }, 442 { .name = "tx_yellow_prio_6", .offset = 0x54, }, 443 { .name = "tx_yellow_prio_7", .offset = 0x55, }, 444 { .name = "tx_green_prio_0", .offset = 0x56, }, 445 { .name = "tx_green_prio_1", .offset = 0x57, }, 446 { .name = "tx_green_prio_2", .offset = 0x58, }, 447 { .name = "tx_green_prio_3", .offset = 0x59, }, 448 { .name = "tx_green_prio_4", .offset = 0x5A, }, 449 { .name = "tx_green_prio_5", .offset = 0x5B, }, 450 { .name = "tx_green_prio_6", .offset = 0x5C, }, 451 { .name = "tx_green_prio_7", .offset = 0x5D, }, 452 { .name = "tx_aged", .offset = 0x5E, }, 453 { .name = "drop_local", .offset = 0x80, }, 454 { .name = "drop_tail", .offset = 0x81, }, 455 { .name = "drop_yellow_prio_0", .offset = 0x82, }, 456 { .name = "drop_yellow_prio_1", .offset = 0x83, }, 457 { .name = "drop_yellow_prio_2", .offset = 0x84, }, 458 { .name = "drop_yellow_prio_3", .offset = 0x85, }, 459 { .name = "drop_yellow_prio_4", .offset = 0x86, }, 460 { .name = "drop_yellow_prio_5", .offset = 0x87, }, 461 { .name = "drop_yellow_prio_6", .offset = 0x88, }, 462 { .name = "drop_yellow_prio_7", .offset = 0x89, }, 463 { .name = "drop_green_prio_0", .offset = 0x8A, }, 464 { .name = "drop_green_prio_1", .offset = 0x8B, }, 465 { .name = "drop_green_prio_2", .offset = 0x8C, }, 466 { .name = "drop_green_prio_3", .offset = 0x8D, }, 467 { .name = "drop_green_prio_4", .offset = 0x8E, }, 468 { .name = "drop_green_prio_5", .offset = 0x8F, }, 469 { .name = "drop_green_prio_6", .offset = 0x90, }, 470 { .name = "drop_green_prio_7", .offset = 0x91, }, 471 }; 472 473 static void ocelot_pll5_init(struct ocelot *ocelot) 474 { 475 /* Configure PLL5. This will need a proper CCF driver 476 * The values are coming from the VTSS API for Ocelot 477 */ 478 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 479 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 480 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 481 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 482 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 483 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 484 HSIO_PLL5G_CFG0_ENA_BIAS | 485 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 486 HSIO_PLL5G_CFG0_ENA_CP1 | 487 HSIO_PLL5G_CFG0_SELCPI(2) | 488 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 489 HSIO_PLL5G_CFG0_SELBGV820(4) | 490 HSIO_PLL5G_CFG0_DIV4 | 491 HSIO_PLL5G_CFG0_ENA_CLKTREE | 492 HSIO_PLL5G_CFG0_ENA_LANE); 493 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 494 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 495 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 496 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 497 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 498 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 499 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 500 } 501 502 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 503 { 504 int ret; 505 506 ocelot->map = ocelot_regmap; 507 ocelot->stats_layout = ocelot_stats_layout; 508 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 509 ocelot->shared_queue_sz = 224 * 1024; 510 ocelot->num_mact_rows = 1024; 511 ocelot->ops = ops; 512 513 ret = ocelot_regfields_init(ocelot, ocelot_regfields); 514 if (ret) 515 return ret; 516 517 ocelot_pll5_init(ocelot); 518 519 eth_random_addr(ocelot->base_mac); 520 ocelot->base_mac[5] &= 0xf0; 521 522 return 0; 523 } 524 525 static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info) 526 { 527 u8 llen, wlen; 528 u64 ifh[2]; 529 530 ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]); 531 ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]); 532 533 wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7, 8); 534 llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15, 6); 535 536 info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80; 537 538 info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32); 539 540 info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4); 541 542 info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16, 1); 543 info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0, 12); 544 545 return 0; 546 } 547 548 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 549 u32 *rval) 550 { 551 u32 val; 552 u32 bytes_valid; 553 554 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 555 if (val == XTR_NOT_READY) { 556 if (ifh) 557 return -EIO; 558 559 do { 560 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 561 } while (val == XTR_NOT_READY); 562 } 563 564 switch (val) { 565 case XTR_ABORT: 566 return -EIO; 567 case XTR_EOF_0: 568 case XTR_EOF_1: 569 case XTR_EOF_2: 570 case XTR_EOF_3: 571 case XTR_PRUNED: 572 bytes_valid = XTR_VALID_BYTES(val); 573 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 574 if (val == XTR_ESCAPE) 575 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 576 else 577 *rval = val; 578 579 return bytes_valid; 580 case XTR_ESCAPE: 581 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 582 583 return 4; 584 default: 585 *rval = val; 586 587 return 4; 588 } 589 } 590 591 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 592 { 593 struct ocelot *ocelot = arg; 594 int i = 0, grp = 0; 595 int err = 0; 596 597 if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) 598 return IRQ_NONE; 599 600 do { 601 struct skb_shared_hwtstamps *shhwtstamps; 602 struct ocelot_port_private *priv; 603 struct ocelot_port *ocelot_port; 604 u64 tod_in_ns, full_ts_in_ns; 605 struct frame_info info = {}; 606 struct net_device *dev; 607 u32 ifh[4], val, *buf; 608 struct timespec64 ts; 609 int sz, len, buf_len; 610 struct sk_buff *skb; 611 612 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 613 err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]); 614 if (err != 4) 615 break; 616 } 617 618 if (err != 4) 619 break; 620 621 /* At this point the IFH was read correctly, so it is safe to 622 * presume that there is no error. The err needs to be reset 623 * otherwise a frame could come in CPU queue between the while 624 * condition and the check for error later on. And in that case 625 * the new frame is just removed and not processed. 626 */ 627 err = 0; 628 629 ocelot_parse_ifh(ifh, &info); 630 631 ocelot_port = ocelot->ports[info.port]; 632 priv = container_of(ocelot_port, struct ocelot_port_private, 633 port); 634 dev = priv->dev; 635 636 skb = netdev_alloc_skb(dev, info.len); 637 638 if (unlikely(!skb)) { 639 netdev_err(dev, "Unable to allocate sk_buff\n"); 640 err = -ENOMEM; 641 break; 642 } 643 buf_len = info.len - ETH_FCS_LEN; 644 buf = (u32 *)skb_put(skb, buf_len); 645 646 len = 0; 647 do { 648 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 649 *buf++ = val; 650 len += sz; 651 } while (len < buf_len); 652 653 /* Read the FCS */ 654 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 655 /* Update the statistics if part of the FCS was read before */ 656 len -= ETH_FCS_LEN - sz; 657 658 if (unlikely(dev->features & NETIF_F_RXFCS)) { 659 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 660 *buf = val; 661 } 662 663 if (sz < 0) { 664 err = sz; 665 break; 666 } 667 668 if (ocelot->ptp) { 669 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 670 671 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 672 if ((tod_in_ns & 0xffffffff) < info.timestamp) 673 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 674 info.timestamp; 675 else 676 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 677 info.timestamp; 678 679 shhwtstamps = skb_hwtstamps(skb); 680 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 681 shhwtstamps->hwtstamp = full_ts_in_ns; 682 } 683 684 /* Everything we see on an interface that is in the HW bridge 685 * has already been forwarded. 686 */ 687 if (ocelot->bridge_mask & BIT(info.port)) 688 skb->offload_fwd_mark = 1; 689 690 skb->protocol = eth_type_trans(skb, dev); 691 if (!skb_defer_rx_timestamp(skb)) 692 netif_rx(skb); 693 dev->stats.rx_bytes += len; 694 dev->stats.rx_packets++; 695 } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); 696 697 if (err) 698 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 699 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 700 701 return IRQ_HANDLED; 702 } 703 704 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 705 { 706 struct ocelot *ocelot = arg; 707 708 ocelot_get_txtstamp(ocelot); 709 710 return IRQ_HANDLED; 711 } 712 713 static const struct of_device_id mscc_ocelot_match[] = { 714 { .compatible = "mscc,vsc7514-switch" }, 715 { } 716 }; 717 MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 718 719 static int ocelot_reset(struct ocelot *ocelot) 720 { 721 int retries = 100; 722 u32 val; 723 724 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 725 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 726 727 do { 728 msleep(1); 729 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 730 &val); 731 } while (val && --retries); 732 733 if (!retries) 734 return -ETIMEDOUT; 735 736 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 737 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 738 739 return 0; 740 } 741 742 /* Watermark encode 743 * Bit 8: Unit; 0:1, 1:16 744 * Bit 7-0: Value to be multiplied with unit 745 */ 746 static u16 ocelot_wm_enc(u16 value) 747 { 748 if (value >= BIT(8)) 749 return BIT(8) | (value / 16); 750 751 return value; 752 } 753 754 static const struct ocelot_ops ocelot_ops = { 755 .reset = ocelot_reset, 756 .wm_enc = ocelot_wm_enc, 757 }; 758 759 static const struct vcap_field vsc7514_vcap_is2_keys[] = { 760 /* Common: 46 bits */ 761 [VCAP_IS2_TYPE] = { 0, 4}, 762 [VCAP_IS2_HK_FIRST] = { 4, 1}, 763 [VCAP_IS2_HK_PAG] = { 5, 8}, 764 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 765 [VCAP_IS2_HK_RSV2] = { 25, 1}, 766 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 767 [VCAP_IS2_HK_L2_MC] = { 27, 1}, 768 [VCAP_IS2_HK_L2_BC] = { 28, 1}, 769 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 770 [VCAP_IS2_HK_VID] = { 30, 12}, 771 [VCAP_IS2_HK_DEI] = { 42, 1}, 772 [VCAP_IS2_HK_PCP] = { 43, 3}, 773 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 774 [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 775 [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 776 /* MAC_ETYPE (TYPE=000) */ 777 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 778 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 779 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 780 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 781 /* MAC_LLC (TYPE=001) */ 782 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 783 /* MAC_SNAP (TYPE=010) */ 784 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 785 /* MAC_ARP (TYPE=011) */ 786 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 787 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 788 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 789 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 790 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 791 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 792 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 793 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 794 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 795 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 796 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 797 /* IP4_TCP_UDP / IP4_OTHER common */ 798 [VCAP_IS2_HK_IP4] = { 46, 1}, 799 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 800 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 801 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 802 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 803 [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 804 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 805 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 806 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 807 /* IP4_TCP_UDP (TYPE=100) */ 808 [VCAP_IS2_HK_TCP] = {124, 1}, 809 [VCAP_IS2_HK_L4_SPORT] = {125, 16}, 810 [VCAP_IS2_HK_L4_DPORT] = {141, 16}, 811 [VCAP_IS2_HK_L4_RNG] = {157, 8}, 812 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 813 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 814 [VCAP_IS2_HK_L4_URG] = {167, 1}, 815 [VCAP_IS2_HK_L4_ACK] = {168, 1}, 816 [VCAP_IS2_HK_L4_PSH] = {169, 1}, 817 [VCAP_IS2_HK_L4_RST] = {170, 1}, 818 [VCAP_IS2_HK_L4_SYN] = {171, 1}, 819 [VCAP_IS2_HK_L4_FIN] = {172, 1}, 820 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 821 [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 822 /* IP4_OTHER (TYPE=101) */ 823 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 824 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 825 /* IP6_STD (TYPE=110) */ 826 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 827 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 828 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 829 /* OAM (TYPE=111) */ 830 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 831 [VCAP_IS2_HK_OAM_VER] = {149, 5}, 832 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 833 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 834 [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 835 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 836 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 837 }; 838 839 static const struct vcap_field vsc7514_vcap_is2_actions[] = { 840 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 841 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 842 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 843 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 844 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 845 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 846 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 847 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 848 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 849 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 850 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 851 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 852 [VCAP_IS2_ACT_RSV] = { 41, 2}, 853 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 854 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 855 }; 856 857 static const struct vcap_props vsc7514_vcap_props[] = { 858 [VCAP_IS2] = { 859 .tg_width = 2, 860 .sw_count = 4, 861 .entry_count = VSC7514_VCAP_IS2_CNT, 862 .entry_width = VSC7514_VCAP_IS2_ENTRY_WIDTH, 863 .action_count = VSC7514_VCAP_IS2_CNT + 864 VSC7514_VCAP_PORT_CNT + 2, 865 .action_width = 99, 866 .action_type_width = 1, 867 .action_table = { 868 [IS2_ACTION_TYPE_NORMAL] = { 869 .width = 49, 870 .count = 2 871 }, 872 [IS2_ACTION_TYPE_SMAC_SIP] = { 873 .width = 6, 874 .count = 4 875 }, 876 }, 877 .counter_words = 4, 878 .counter_width = 32, 879 }, 880 }; 881 882 static struct ptp_clock_info ocelot_ptp_clock_info = { 883 .owner = THIS_MODULE, 884 .name = "ocelot ptp", 885 .max_adj = 0x7fffffff, 886 .n_alarm = 0, 887 .n_ext_ts = 0, 888 .n_per_out = OCELOT_PTP_PINS_NUM, 889 .n_pins = OCELOT_PTP_PINS_NUM, 890 .pps = 0, 891 .gettime64 = ocelot_ptp_gettime64, 892 .settime64 = ocelot_ptp_settime64, 893 .adjtime = ocelot_ptp_adjtime, 894 .adjfine = ocelot_ptp_adjfine, 895 .verify = ocelot_ptp_verify, 896 .enable = ocelot_ptp_enable, 897 }; 898 899 static int mscc_ocelot_probe(struct platform_device *pdev) 900 { 901 struct device_node *np = pdev->dev.of_node; 902 struct device_node *ports, *portnp; 903 int err, irq_xtr, irq_ptp_rdy; 904 struct ocelot *ocelot; 905 struct regmap *hsio; 906 unsigned int i; 907 908 struct { 909 enum ocelot_target id; 910 char *name; 911 u8 optional:1; 912 } io_target[] = { 913 { SYS, "sys" }, 914 { REW, "rew" }, 915 { QSYS, "qsys" }, 916 { ANA, "ana" }, 917 { QS, "qs" }, 918 { S2, "s2" }, 919 { PTP, "ptp", 1 }, 920 }; 921 922 if (!np && !pdev->dev.platform_data) 923 return -ENODEV; 924 925 ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL); 926 if (!ocelot) 927 return -ENOMEM; 928 929 platform_set_drvdata(pdev, ocelot); 930 ocelot->dev = &pdev->dev; 931 932 for (i = 0; i < ARRAY_SIZE(io_target); i++) { 933 struct regmap *target; 934 struct resource *res; 935 936 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 937 io_target[i].name); 938 939 target = ocelot_regmap_init(ocelot, res); 940 if (IS_ERR(target)) { 941 if (io_target[i].optional) { 942 ocelot->targets[io_target[i].id] = NULL; 943 continue; 944 } 945 return PTR_ERR(target); 946 } 947 948 ocelot->targets[io_target[i].id] = target; 949 } 950 951 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 952 if (IS_ERR(hsio)) { 953 dev_err(&pdev->dev, "missing hsio syscon\n"); 954 return PTR_ERR(hsio); 955 } 956 957 ocelot->targets[HSIO] = hsio; 958 959 err = ocelot_chip_init(ocelot, &ocelot_ops); 960 if (err) 961 return err; 962 963 irq_xtr = platform_get_irq_byname(pdev, "xtr"); 964 if (irq_xtr < 0) 965 return -ENODEV; 966 967 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 968 ocelot_xtr_irq_handler, IRQF_ONESHOT, 969 "frame extraction", ocelot); 970 if (err) 971 return err; 972 973 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 974 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 975 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 976 ocelot_ptp_rdy_irq_handler, 977 IRQF_ONESHOT, "ptp ready", 978 ocelot); 979 if (err) 980 return err; 981 982 /* Both the PTP interrupt and the PTP bank are available */ 983 ocelot->ptp = 1; 984 } 985 986 ports = of_get_child_by_name(np, "ethernet-ports"); 987 if (!ports) { 988 dev_err(&pdev->dev, "no ethernet-ports child node found\n"); 989 return -ENODEV; 990 } 991 992 ocelot->num_phys_ports = of_get_child_count(ports); 993 994 ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports, 995 sizeof(struct ocelot_port *), GFP_KERNEL); 996 997 ocelot->vcap_is2_keys = vsc7514_vcap_is2_keys; 998 ocelot->vcap_is2_actions = vsc7514_vcap_is2_actions; 999 ocelot->vcap = vsc7514_vcap_props; 1000 1001 ocelot_init(ocelot); 1002 if (ocelot->ptp) { 1003 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1004 if (err) { 1005 dev_err(ocelot->dev, 1006 "Timestamp initialization failed\n"); 1007 ocelot->ptp = 0; 1008 } 1009 } 1010 1011 /* No NPI port */ 1012 ocelot_configure_cpu(ocelot, -1, OCELOT_TAG_PREFIX_NONE, 1013 OCELOT_TAG_PREFIX_NONE); 1014 1015 for_each_available_child_of_node(ports, portnp) { 1016 struct ocelot_port_private *priv; 1017 struct ocelot_port *ocelot_port; 1018 struct device_node *phy_node; 1019 phy_interface_t phy_mode; 1020 struct phy_device *phy; 1021 struct regmap *target; 1022 struct resource *res; 1023 struct phy *serdes; 1024 char res_name[8]; 1025 u32 port; 1026 1027 if (of_property_read_u32(portnp, "reg", &port)) 1028 continue; 1029 1030 snprintf(res_name, sizeof(res_name), "port%d", port); 1031 1032 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1033 res_name); 1034 target = ocelot_regmap_init(ocelot, res); 1035 if (IS_ERR(target)) 1036 continue; 1037 1038 phy_node = of_parse_phandle(portnp, "phy-handle", 0); 1039 if (!phy_node) 1040 continue; 1041 1042 phy = of_phy_find_device(phy_node); 1043 of_node_put(phy_node); 1044 if (!phy) 1045 continue; 1046 1047 err = ocelot_probe_port(ocelot, port, target, phy); 1048 if (err) { 1049 of_node_put(portnp); 1050 goto out_put_ports; 1051 } 1052 1053 ocelot_port = ocelot->ports[port]; 1054 priv = container_of(ocelot_port, struct ocelot_port_private, 1055 port); 1056 1057 of_get_phy_mode(portnp, &phy_mode); 1058 1059 ocelot_port->phy_mode = phy_mode; 1060 1061 switch (ocelot_port->phy_mode) { 1062 case PHY_INTERFACE_MODE_NA: 1063 continue; 1064 case PHY_INTERFACE_MODE_SGMII: 1065 break; 1066 case PHY_INTERFACE_MODE_QSGMII: 1067 /* Ensure clock signals and speed is set on all 1068 * QSGMII links 1069 */ 1070 ocelot_port_writel(ocelot_port, 1071 DEV_CLOCK_CFG_LINK_SPEED 1072 (OCELOT_SPEED_1000), 1073 DEV_CLOCK_CFG); 1074 break; 1075 default: 1076 dev_err(ocelot->dev, 1077 "invalid phy mode for port%d, (Q)SGMII only\n", 1078 port); 1079 of_node_put(portnp); 1080 err = -EINVAL; 1081 goto out_put_ports; 1082 } 1083 1084 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); 1085 if (IS_ERR(serdes)) { 1086 err = PTR_ERR(serdes); 1087 if (err == -EPROBE_DEFER) 1088 dev_dbg(ocelot->dev, "deferring probe\n"); 1089 else 1090 dev_err(ocelot->dev, 1091 "missing SerDes phys for port%d\n", 1092 port); 1093 1094 of_node_put(portnp); 1095 goto out_put_ports; 1096 } 1097 1098 priv->serdes = serdes; 1099 } 1100 1101 register_netdevice_notifier(&ocelot_netdevice_nb); 1102 register_switchdev_notifier(&ocelot_switchdev_nb); 1103 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1104 1105 dev_info(&pdev->dev, "Ocelot switch probed\n"); 1106 1107 out_put_ports: 1108 of_node_put(ports); 1109 return err; 1110 } 1111 1112 static int mscc_ocelot_remove(struct platform_device *pdev) 1113 { 1114 struct ocelot *ocelot = platform_get_drvdata(pdev); 1115 1116 ocelot_deinit_timestamp(ocelot); 1117 ocelot_deinit(ocelot); 1118 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1119 unregister_switchdev_notifier(&ocelot_switchdev_nb); 1120 unregister_netdevice_notifier(&ocelot_netdevice_nb); 1121 1122 return 0; 1123 } 1124 1125 static struct platform_driver mscc_ocelot_driver = { 1126 .probe = mscc_ocelot_probe, 1127 .remove = mscc_ocelot_remove, 1128 .driver = { 1129 .name = "ocelot-switch", 1130 .of_match_table = mscc_ocelot_match, 1131 }, 1132 }; 1133 1134 module_platform_driver(mscc_ocelot_driver); 1135 1136 MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1137 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1138 MODULE_LICENSE("Dual MIT/GPL"); 1139