1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_net.h> 10 #include <linux/netdevice.h> 11 #include <linux/of_mdio.h> 12 #include <linux/of_platform.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/skbuff.h> 15 #include <net/switchdev.h> 16 17 #include <soc/mscc/ocelot_vcap.h> 18 #include <soc/mscc/ocelot_hsio.h> 19 #include "ocelot.h" 20 21 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) 22 #define VSC7514_VCAP_IS2_CNT 64 23 #define VSC7514_VCAP_IS2_ENTRY_WIDTH 376 24 #define VSC7514_VCAP_IS2_ACTION_WIDTH 99 25 #define VSC7514_VCAP_PORT_CNT 11 26 27 static const u32 ocelot_ana_regmap[] = { 28 REG(ANA_ADVLEARN, 0x009000), 29 REG(ANA_VLANMASK, 0x009004), 30 REG(ANA_PORT_B_DOMAIN, 0x009008), 31 REG(ANA_ANAGEFIL, 0x00900c), 32 REG(ANA_ANEVENTS, 0x009010), 33 REG(ANA_STORMLIMIT_BURST, 0x009014), 34 REG(ANA_STORMLIMIT_CFG, 0x009018), 35 REG(ANA_ISOLATED_PORTS, 0x009028), 36 REG(ANA_COMMUNITY_PORTS, 0x00902c), 37 REG(ANA_AUTOAGE, 0x009030), 38 REG(ANA_MACTOPTIONS, 0x009034), 39 REG(ANA_LEARNDISC, 0x009038), 40 REG(ANA_AGENCTRL, 0x00903c), 41 REG(ANA_MIRRORPORTS, 0x009040), 42 REG(ANA_EMIRRORPORTS, 0x009044), 43 REG(ANA_FLOODING, 0x009048), 44 REG(ANA_FLOODING_IPMC, 0x00904c), 45 REG(ANA_SFLOW_CFG, 0x009050), 46 REG(ANA_PORT_MODE, 0x009080), 47 REG(ANA_PGID_PGID, 0x008c00), 48 REG(ANA_TABLES_ANMOVED, 0x008b30), 49 REG(ANA_TABLES_MACHDATA, 0x008b34), 50 REG(ANA_TABLES_MACLDATA, 0x008b38), 51 REG(ANA_TABLES_MACACCESS, 0x008b3c), 52 REG(ANA_TABLES_MACTINDX, 0x008b40), 53 REG(ANA_TABLES_VLANACCESS, 0x008b44), 54 REG(ANA_TABLES_VLANTIDX, 0x008b48), 55 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 56 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 57 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 58 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 59 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 60 REG(ANA_MSTI_STATE, 0x008e00), 61 REG(ANA_PORT_VLAN_CFG, 0x007000), 62 REG(ANA_PORT_DROP_CFG, 0x007004), 63 REG(ANA_PORT_QOS_CFG, 0x007008), 64 REG(ANA_PORT_VCAP_CFG, 0x00700c), 65 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 66 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 67 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 68 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 69 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 70 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 71 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 72 REG(ANA_PORT_PORT_CFG, 0x007070), 73 REG(ANA_PORT_POL_CFG, 0x007074), 74 REG(ANA_PORT_PTP_CFG, 0x007078), 75 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 76 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 77 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 78 REG(ANA_PFC_PFC_CFG, 0x008800), 79 REG(ANA_PFC_PFC_TIMER, 0x008804), 80 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 81 REG(ANA_IPT_IPT, 0x008004), 82 REG(ANA_PPT_PPT, 0x008ac0), 83 REG(ANA_FID_MAP_FID_MAP, 0x000000), 84 REG(ANA_AGGR_CFG, 0x0090b4), 85 REG(ANA_CPUQ_CFG, 0x0090b8), 86 REG(ANA_CPUQ_CFG2, 0x0090bc), 87 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 88 REG(ANA_DSCP_CFG, 0x009100), 89 REG(ANA_DSCP_REWR_CFG, 0x009200), 90 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 91 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 92 REG(ANA_VRAP_CFG, 0x009280), 93 REG(ANA_VRAP_HDR_DATA, 0x009284), 94 REG(ANA_VRAP_HDR_MASK, 0x009288), 95 REG(ANA_DISCARD_CFG, 0x00928c), 96 REG(ANA_FID_CFG, 0x009290), 97 REG(ANA_POL_PIR_CFG, 0x004000), 98 REG(ANA_POL_CIR_CFG, 0x004004), 99 REG(ANA_POL_MODE_CFG, 0x004008), 100 REG(ANA_POL_PIR_STATE, 0x00400c), 101 REG(ANA_POL_CIR_STATE, 0x004010), 102 REG(ANA_POL_STATE, 0x004014), 103 REG(ANA_POL_FLOWC, 0x008b80), 104 REG(ANA_POL_HYST, 0x008bec), 105 REG(ANA_POL_MISC_CFG, 0x008bf0), 106 }; 107 108 static const u32 ocelot_qs_regmap[] = { 109 REG(QS_XTR_GRP_CFG, 0x000000), 110 REG(QS_XTR_RD, 0x000008), 111 REG(QS_XTR_FRM_PRUNING, 0x000010), 112 REG(QS_XTR_FLUSH, 0x000018), 113 REG(QS_XTR_DATA_PRESENT, 0x00001c), 114 REG(QS_XTR_CFG, 0x000020), 115 REG(QS_INJ_GRP_CFG, 0x000024), 116 REG(QS_INJ_WR, 0x00002c), 117 REG(QS_INJ_CTRL, 0x000034), 118 REG(QS_INJ_STATUS, 0x00003c), 119 REG(QS_INJ_ERR, 0x000040), 120 REG(QS_INH_DBG, 0x000048), 121 }; 122 123 static const u32 ocelot_qsys_regmap[] = { 124 REG(QSYS_PORT_MODE, 0x011200), 125 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 126 REG(QSYS_STAT_CNT_CFG, 0x011264), 127 REG(QSYS_EEE_CFG, 0x011268), 128 REG(QSYS_EEE_THRES, 0x011294), 129 REG(QSYS_IGR_NO_SHARING, 0x011298), 130 REG(QSYS_EGR_NO_SHARING, 0x01129c), 131 REG(QSYS_SW_STATUS, 0x0112a0), 132 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 133 REG(QSYS_PAD_CFG, 0x0112d4), 134 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 135 REG(QSYS_QMAP, 0x0112dc), 136 REG(QSYS_ISDX_SGRP, 0x011400), 137 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 138 REG(QSYS_TFRM_MISC, 0x011310), 139 REG(QSYS_TFRM_PORT_DLY, 0x011314), 140 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 141 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 142 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 143 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 144 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 145 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 146 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 147 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 148 REG(QSYS_RED_PROFILE, 0x011338), 149 REG(QSYS_RES_QOS_MODE, 0x011378), 150 REG(QSYS_RES_CFG, 0x012000), 151 REG(QSYS_RES_STAT, 0x012004), 152 REG(QSYS_EGR_DROP_MODE, 0x01137c), 153 REG(QSYS_EQ_CTRL, 0x011380), 154 REG(QSYS_EVENTS_CORE, 0x011384), 155 REG(QSYS_CIR_CFG, 0x000000), 156 REG(QSYS_EIR_CFG, 0x000004), 157 REG(QSYS_SE_CFG, 0x000008), 158 REG(QSYS_SE_DWRR_CFG, 0x00000c), 159 REG(QSYS_SE_CONNECT, 0x00003c), 160 REG(QSYS_SE_DLB_SENSE, 0x000040), 161 REG(QSYS_CIR_STATE, 0x000044), 162 REG(QSYS_EIR_STATE, 0x000048), 163 REG(QSYS_SE_STATE, 0x00004c), 164 REG(QSYS_HSCH_MISC_CFG, 0x011388), 165 }; 166 167 static const u32 ocelot_rew_regmap[] = { 168 REG(REW_PORT_VLAN_CFG, 0x000000), 169 REG(REW_TAG_CFG, 0x000004), 170 REG(REW_PORT_CFG, 0x000008), 171 REG(REW_DSCP_CFG, 0x00000c), 172 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 173 REG(REW_PTP_CFG, 0x000050), 174 REG(REW_PTP_DLY1_CFG, 0x000054), 175 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 176 REG(REW_DSCP_REMAP_CFG, 0x000790), 177 REG(REW_STAT_CFG, 0x000890), 178 REG(REW_PPT, 0x000680), 179 }; 180 181 static const u32 ocelot_sys_regmap[] = { 182 REG(SYS_COUNT_RX_OCTETS, 0x000000), 183 REG(SYS_COUNT_RX_UNICAST, 0x000004), 184 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 185 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 186 REG(SYS_COUNT_RX_SHORTS, 0x000010), 187 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 188 REG(SYS_COUNT_RX_JABBERS, 0x000018), 189 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 190 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 191 REG(SYS_COUNT_RX_64, 0x000024), 192 REG(SYS_COUNT_RX_65_127, 0x000028), 193 REG(SYS_COUNT_RX_128_255, 0x00002c), 194 REG(SYS_COUNT_RX_256_1023, 0x000030), 195 REG(SYS_COUNT_RX_1024_1526, 0x000034), 196 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 197 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 198 REG(SYS_COUNT_RX_CONTROL, 0x000040), 199 REG(SYS_COUNT_RX_LONGS, 0x000044), 200 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 201 REG(SYS_COUNT_TX_OCTETS, 0x000100), 202 REG(SYS_COUNT_TX_UNICAST, 0x000104), 203 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 204 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 205 REG(SYS_COUNT_TX_COLLISION, 0x000110), 206 REG(SYS_COUNT_TX_DROPS, 0x000114), 207 REG(SYS_COUNT_TX_PAUSE, 0x000118), 208 REG(SYS_COUNT_TX_64, 0x00011c), 209 REG(SYS_COUNT_TX_65_127, 0x000120), 210 REG(SYS_COUNT_TX_128_511, 0x000124), 211 REG(SYS_COUNT_TX_512_1023, 0x000128), 212 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 213 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 214 REG(SYS_COUNT_TX_AGING, 0x000170), 215 REG(SYS_RESET_CFG, 0x000508), 216 REG(SYS_CMID, 0x00050c), 217 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 218 REG(SYS_PORT_MODE, 0x000514), 219 REG(SYS_FRONT_PORT_MODE, 0x000548), 220 REG(SYS_FRM_AGING, 0x000574), 221 REG(SYS_STAT_CFG, 0x000578), 222 REG(SYS_SW_STATUS, 0x00057c), 223 REG(SYS_MISC_CFG, 0x0005ac), 224 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 225 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 226 REG(SYS_CM_ADDR, 0x000500), 227 REG(SYS_CM_DATA, 0x000504), 228 REG(SYS_PAUSE_CFG, 0x000608), 229 REG(SYS_PAUSE_TOT_CFG, 0x000638), 230 REG(SYS_ATOP, 0x00063c), 231 REG(SYS_ATOP_TOT_CFG, 0x00066c), 232 REG(SYS_MAC_FC_CFG, 0x000670), 233 REG(SYS_MMGT, 0x00069c), 234 REG(SYS_MMGT_FAST, 0x0006a0), 235 REG(SYS_EVENTS_DIF, 0x0006a4), 236 REG(SYS_EVENTS_CORE, 0x0006b4), 237 REG(SYS_CNT, 0x000000), 238 REG(SYS_PTP_STATUS, 0x0006b8), 239 REG(SYS_PTP_TXSTAMP, 0x0006bc), 240 REG(SYS_PTP_NXT, 0x0006c0), 241 REG(SYS_PTP_CFG, 0x0006c4), 242 }; 243 244 static const u32 ocelot_s2_regmap[] = { 245 REG(S2_CORE_UPDATE_CTRL, 0x000000), 246 REG(S2_CORE_MV_CFG, 0x000004), 247 REG(S2_CACHE_ENTRY_DAT, 0x000008), 248 REG(S2_CACHE_MASK_DAT, 0x000108), 249 REG(S2_CACHE_ACTION_DAT, 0x000208), 250 REG(S2_CACHE_CNT_DAT, 0x000308), 251 REG(S2_CACHE_TG_DAT, 0x000388), 252 }; 253 254 static const u32 ocelot_ptp_regmap[] = { 255 REG(PTP_PIN_CFG, 0x000000), 256 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 257 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 258 REG(PTP_PIN_TOD_NSEC, 0x00000c), 259 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 260 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 261 REG(PTP_CFG_MISC, 0x0000a0), 262 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 263 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 264 }; 265 266 static const u32 *ocelot_regmap[] = { 267 [ANA] = ocelot_ana_regmap, 268 [QS] = ocelot_qs_regmap, 269 [QSYS] = ocelot_qsys_regmap, 270 [REW] = ocelot_rew_regmap, 271 [SYS] = ocelot_sys_regmap, 272 [S2] = ocelot_s2_regmap, 273 [PTP] = ocelot_ptp_regmap, 274 }; 275 276 static const struct reg_field ocelot_regfields[] = { 277 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 278 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 279 [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 280 [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 281 [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 282 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 283 [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 284 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 285 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 286 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 287 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 288 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 289 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 290 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 291 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 292 [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 293 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 294 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 295 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 296 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 297 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 298 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 299 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 300 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 301 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 302 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 303 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 304 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 305 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 306 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 307 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 308 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 309 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 310 [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 311 [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 312 [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 313 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 314 [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 315 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 316 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 317 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 318 }; 319 320 static const struct ocelot_stat_layout ocelot_stats_layout[] = { 321 { .name = "rx_octets", .offset = 0x00, }, 322 { .name = "rx_unicast", .offset = 0x01, }, 323 { .name = "rx_multicast", .offset = 0x02, }, 324 { .name = "rx_broadcast", .offset = 0x03, }, 325 { .name = "rx_shorts", .offset = 0x04, }, 326 { .name = "rx_fragments", .offset = 0x05, }, 327 { .name = "rx_jabbers", .offset = 0x06, }, 328 { .name = "rx_crc_align_errs", .offset = 0x07, }, 329 { .name = "rx_sym_errs", .offset = 0x08, }, 330 { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 331 { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 332 { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 333 { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 334 { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 335 { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 336 { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 337 { .name = "rx_pause", .offset = 0x10, }, 338 { .name = "rx_control", .offset = 0x11, }, 339 { .name = "rx_longs", .offset = 0x12, }, 340 { .name = "rx_classified_drops", .offset = 0x13, }, 341 { .name = "rx_red_prio_0", .offset = 0x14, }, 342 { .name = "rx_red_prio_1", .offset = 0x15, }, 343 { .name = "rx_red_prio_2", .offset = 0x16, }, 344 { .name = "rx_red_prio_3", .offset = 0x17, }, 345 { .name = "rx_red_prio_4", .offset = 0x18, }, 346 { .name = "rx_red_prio_5", .offset = 0x19, }, 347 { .name = "rx_red_prio_6", .offset = 0x1A, }, 348 { .name = "rx_red_prio_7", .offset = 0x1B, }, 349 { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 350 { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 351 { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 352 { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 353 { .name = "rx_yellow_prio_4", .offset = 0x20, }, 354 { .name = "rx_yellow_prio_5", .offset = 0x21, }, 355 { .name = "rx_yellow_prio_6", .offset = 0x22, }, 356 { .name = "rx_yellow_prio_7", .offset = 0x23, }, 357 { .name = "rx_green_prio_0", .offset = 0x24, }, 358 { .name = "rx_green_prio_1", .offset = 0x25, }, 359 { .name = "rx_green_prio_2", .offset = 0x26, }, 360 { .name = "rx_green_prio_3", .offset = 0x27, }, 361 { .name = "rx_green_prio_4", .offset = 0x28, }, 362 { .name = "rx_green_prio_5", .offset = 0x29, }, 363 { .name = "rx_green_prio_6", .offset = 0x2A, }, 364 { .name = "rx_green_prio_7", .offset = 0x2B, }, 365 { .name = "tx_octets", .offset = 0x40, }, 366 { .name = "tx_unicast", .offset = 0x41, }, 367 { .name = "tx_multicast", .offset = 0x42, }, 368 { .name = "tx_broadcast", .offset = 0x43, }, 369 { .name = "tx_collision", .offset = 0x44, }, 370 { .name = "tx_drops", .offset = 0x45, }, 371 { .name = "tx_pause", .offset = 0x46, }, 372 { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 373 { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 374 { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 375 { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 376 { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 377 { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 378 { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 379 { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 380 { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 381 { .name = "tx_yellow_prio_2", .offset = 0x50, }, 382 { .name = "tx_yellow_prio_3", .offset = 0x51, }, 383 { .name = "tx_yellow_prio_4", .offset = 0x52, }, 384 { .name = "tx_yellow_prio_5", .offset = 0x53, }, 385 { .name = "tx_yellow_prio_6", .offset = 0x54, }, 386 { .name = "tx_yellow_prio_7", .offset = 0x55, }, 387 { .name = "tx_green_prio_0", .offset = 0x56, }, 388 { .name = "tx_green_prio_1", .offset = 0x57, }, 389 { .name = "tx_green_prio_2", .offset = 0x58, }, 390 { .name = "tx_green_prio_3", .offset = 0x59, }, 391 { .name = "tx_green_prio_4", .offset = 0x5A, }, 392 { .name = "tx_green_prio_5", .offset = 0x5B, }, 393 { .name = "tx_green_prio_6", .offset = 0x5C, }, 394 { .name = "tx_green_prio_7", .offset = 0x5D, }, 395 { .name = "tx_aged", .offset = 0x5E, }, 396 { .name = "drop_local", .offset = 0x80, }, 397 { .name = "drop_tail", .offset = 0x81, }, 398 { .name = "drop_yellow_prio_0", .offset = 0x82, }, 399 { .name = "drop_yellow_prio_1", .offset = 0x83, }, 400 { .name = "drop_yellow_prio_2", .offset = 0x84, }, 401 { .name = "drop_yellow_prio_3", .offset = 0x85, }, 402 { .name = "drop_yellow_prio_4", .offset = 0x86, }, 403 { .name = "drop_yellow_prio_5", .offset = 0x87, }, 404 { .name = "drop_yellow_prio_6", .offset = 0x88, }, 405 { .name = "drop_yellow_prio_7", .offset = 0x89, }, 406 { .name = "drop_green_prio_0", .offset = 0x8A, }, 407 { .name = "drop_green_prio_1", .offset = 0x8B, }, 408 { .name = "drop_green_prio_2", .offset = 0x8C, }, 409 { .name = "drop_green_prio_3", .offset = 0x8D, }, 410 { .name = "drop_green_prio_4", .offset = 0x8E, }, 411 { .name = "drop_green_prio_5", .offset = 0x8F, }, 412 { .name = "drop_green_prio_6", .offset = 0x90, }, 413 { .name = "drop_green_prio_7", .offset = 0x91, }, 414 }; 415 416 static void ocelot_pll5_init(struct ocelot *ocelot) 417 { 418 /* Configure PLL5. This will need a proper CCF driver 419 * The values are coming from the VTSS API for Ocelot 420 */ 421 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 422 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 423 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 424 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 425 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 426 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 427 HSIO_PLL5G_CFG0_ENA_BIAS | 428 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 429 HSIO_PLL5G_CFG0_ENA_CP1 | 430 HSIO_PLL5G_CFG0_SELCPI(2) | 431 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 432 HSIO_PLL5G_CFG0_SELBGV820(4) | 433 HSIO_PLL5G_CFG0_DIV4 | 434 HSIO_PLL5G_CFG0_ENA_CLKTREE | 435 HSIO_PLL5G_CFG0_ENA_LANE); 436 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 437 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 438 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 439 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 440 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 441 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 442 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 443 } 444 445 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 446 { 447 int ret; 448 449 ocelot->map = ocelot_regmap; 450 ocelot->stats_layout = ocelot_stats_layout; 451 ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 452 ocelot->shared_queue_sz = 224 * 1024; 453 ocelot->num_mact_rows = 1024; 454 ocelot->ops = ops; 455 456 ret = ocelot_regfields_init(ocelot, ocelot_regfields); 457 if (ret) 458 return ret; 459 460 ocelot_pll5_init(ocelot); 461 462 eth_random_addr(ocelot->base_mac); 463 ocelot->base_mac[5] &= 0xf0; 464 465 return 0; 466 } 467 468 static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info) 469 { 470 u8 llen, wlen; 471 u64 ifh[2]; 472 473 ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]); 474 ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]); 475 476 wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7, 8); 477 llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15, 6); 478 479 info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80; 480 481 info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32); 482 483 info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4); 484 485 info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16, 1); 486 info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0, 12); 487 488 return 0; 489 } 490 491 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 492 u32 *rval) 493 { 494 u32 val; 495 u32 bytes_valid; 496 497 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 498 if (val == XTR_NOT_READY) { 499 if (ifh) 500 return -EIO; 501 502 do { 503 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 504 } while (val == XTR_NOT_READY); 505 } 506 507 switch (val) { 508 case XTR_ABORT: 509 return -EIO; 510 case XTR_EOF_0: 511 case XTR_EOF_1: 512 case XTR_EOF_2: 513 case XTR_EOF_3: 514 case XTR_PRUNED: 515 bytes_valid = XTR_VALID_BYTES(val); 516 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 517 if (val == XTR_ESCAPE) 518 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 519 else 520 *rval = val; 521 522 return bytes_valid; 523 case XTR_ESCAPE: 524 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 525 526 return 4; 527 default: 528 *rval = val; 529 530 return 4; 531 } 532 } 533 534 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 535 { 536 struct ocelot *ocelot = arg; 537 int i = 0, grp = 0; 538 int err = 0; 539 540 if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) 541 return IRQ_NONE; 542 543 do { 544 struct skb_shared_hwtstamps *shhwtstamps; 545 struct ocelot_port_private *priv; 546 struct ocelot_port *ocelot_port; 547 u64 tod_in_ns, full_ts_in_ns; 548 struct frame_info info = {}; 549 struct net_device *dev; 550 u32 ifh[4], val, *buf; 551 struct timespec64 ts; 552 int sz, len, buf_len; 553 struct sk_buff *skb; 554 555 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 556 err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]); 557 if (err != 4) 558 break; 559 } 560 561 if (err != 4) 562 break; 563 564 /* At this point the IFH was read correctly, so it is safe to 565 * presume that there is no error. The err needs to be reset 566 * otherwise a frame could come in CPU queue between the while 567 * condition and the check for error later on. And in that case 568 * the new frame is just removed and not processed. 569 */ 570 err = 0; 571 572 ocelot_parse_ifh(ifh, &info); 573 574 ocelot_port = ocelot->ports[info.port]; 575 priv = container_of(ocelot_port, struct ocelot_port_private, 576 port); 577 dev = priv->dev; 578 579 skb = netdev_alloc_skb(dev, info.len); 580 581 if (unlikely(!skb)) { 582 netdev_err(dev, "Unable to allocate sk_buff\n"); 583 err = -ENOMEM; 584 break; 585 } 586 buf_len = info.len - ETH_FCS_LEN; 587 buf = (u32 *)skb_put(skb, buf_len); 588 589 len = 0; 590 do { 591 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 592 *buf++ = val; 593 len += sz; 594 } while (len < buf_len); 595 596 /* Read the FCS */ 597 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 598 /* Update the statistics if part of the FCS was read before */ 599 len -= ETH_FCS_LEN - sz; 600 601 if (unlikely(dev->features & NETIF_F_RXFCS)) { 602 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 603 *buf = val; 604 } 605 606 if (sz < 0) { 607 err = sz; 608 break; 609 } 610 611 if (ocelot->ptp) { 612 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 613 614 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 615 if ((tod_in_ns & 0xffffffff) < info.timestamp) 616 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 617 info.timestamp; 618 else 619 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 620 info.timestamp; 621 622 shhwtstamps = skb_hwtstamps(skb); 623 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 624 shhwtstamps->hwtstamp = full_ts_in_ns; 625 } 626 627 /* Everything we see on an interface that is in the HW bridge 628 * has already been forwarded. 629 */ 630 if (ocelot->bridge_mask & BIT(info.port)) 631 skb->offload_fwd_mark = 1; 632 633 skb->protocol = eth_type_trans(skb, dev); 634 if (!skb_defer_rx_timestamp(skb)) 635 netif_rx(skb); 636 dev->stats.rx_bytes += len; 637 dev->stats.rx_packets++; 638 } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); 639 640 if (err) 641 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 642 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 643 644 return IRQ_HANDLED; 645 } 646 647 static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 648 { 649 struct ocelot *ocelot = arg; 650 651 ocelot_get_txtstamp(ocelot); 652 653 return IRQ_HANDLED; 654 } 655 656 static const struct of_device_id mscc_ocelot_match[] = { 657 { .compatible = "mscc,vsc7514-switch" }, 658 { } 659 }; 660 MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 661 662 static int ocelot_reset(struct ocelot *ocelot) 663 { 664 int retries = 100; 665 u32 val; 666 667 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 668 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 669 670 do { 671 msleep(1); 672 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 673 &val); 674 } while (val && --retries); 675 676 if (!retries) 677 return -ETIMEDOUT; 678 679 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 680 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 681 682 return 0; 683 } 684 685 static const struct ocelot_ops ocelot_ops = { 686 .reset = ocelot_reset, 687 }; 688 689 static const struct vcap_field vsc7514_vcap_is2_keys[] = { 690 /* Common: 46 bits */ 691 [VCAP_IS2_TYPE] = { 0, 4}, 692 [VCAP_IS2_HK_FIRST] = { 4, 1}, 693 [VCAP_IS2_HK_PAG] = { 5, 8}, 694 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 695 [VCAP_IS2_HK_RSV2] = { 25, 1}, 696 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 697 [VCAP_IS2_HK_L2_MC] = { 27, 1}, 698 [VCAP_IS2_HK_L2_BC] = { 28, 1}, 699 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 700 [VCAP_IS2_HK_VID] = { 30, 12}, 701 [VCAP_IS2_HK_DEI] = { 42, 1}, 702 [VCAP_IS2_HK_PCP] = { 43, 3}, 703 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 704 [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 705 [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 706 /* MAC_ETYPE (TYPE=000) */ 707 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 708 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 709 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 710 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 711 /* MAC_LLC (TYPE=001) */ 712 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 713 /* MAC_SNAP (TYPE=010) */ 714 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 715 /* MAC_ARP (TYPE=011) */ 716 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 717 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 718 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 719 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 720 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 721 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 722 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 723 [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 724 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 725 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 726 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 727 /* IP4_TCP_UDP / IP4_OTHER common */ 728 [VCAP_IS2_HK_IP4] = { 46, 1}, 729 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 730 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 731 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 732 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 733 [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 734 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 735 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 736 [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 737 /* IP4_TCP_UDP (TYPE=100) */ 738 [VCAP_IS2_HK_TCP] = {124, 1}, 739 [VCAP_IS2_HK_L4_SPORT] = {125, 16}, 740 [VCAP_IS2_HK_L4_DPORT] = {141, 16}, 741 [VCAP_IS2_HK_L4_RNG] = {157, 8}, 742 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 743 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 744 [VCAP_IS2_HK_L4_URG] = {167, 1}, 745 [VCAP_IS2_HK_L4_ACK] = {168, 1}, 746 [VCAP_IS2_HK_L4_PSH] = {169, 1}, 747 [VCAP_IS2_HK_L4_RST] = {170, 1}, 748 [VCAP_IS2_HK_L4_SYN] = {171, 1}, 749 [VCAP_IS2_HK_L4_FIN] = {172, 1}, 750 [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 751 [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 752 /* IP4_OTHER (TYPE=101) */ 753 [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 754 [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 755 /* IP6_STD (TYPE=110) */ 756 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 757 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 758 [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 759 /* OAM (TYPE=111) */ 760 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 761 [VCAP_IS2_HK_OAM_VER] = {149, 5}, 762 [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 763 [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 764 [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 765 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 766 [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 767 }; 768 769 static const struct vcap_field vsc7514_vcap_is2_actions[] = { 770 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 771 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 772 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 773 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 774 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 775 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 776 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 777 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 778 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 779 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 780 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 781 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 782 [VCAP_IS2_ACT_RSV] = { 41, 2}, 783 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 784 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 785 }; 786 787 static const struct vcap_props vsc7514_vcap_props[] = { 788 [VCAP_IS2] = { 789 .tg_width = 2, 790 .sw_count = 4, 791 .entry_count = VSC7514_VCAP_IS2_CNT, 792 .entry_width = VSC7514_VCAP_IS2_ENTRY_WIDTH, 793 .action_count = VSC7514_VCAP_IS2_CNT + 794 VSC7514_VCAP_PORT_CNT + 2, 795 .action_width = 99, 796 .action_type_width = 1, 797 .action_table = { 798 [IS2_ACTION_TYPE_NORMAL] = { 799 .width = 49, 800 .count = 2 801 }, 802 [IS2_ACTION_TYPE_SMAC_SIP] = { 803 .width = 6, 804 .count = 4 805 }, 806 }, 807 .counter_words = 4, 808 .counter_width = 32, 809 }, 810 }; 811 812 static struct ptp_clock_info ocelot_ptp_clock_info = { 813 .owner = THIS_MODULE, 814 .name = "ocelot ptp", 815 .max_adj = 0x7fffffff, 816 .n_alarm = 0, 817 .n_ext_ts = 0, 818 .n_per_out = OCELOT_PTP_PINS_NUM, 819 .n_pins = OCELOT_PTP_PINS_NUM, 820 .pps = 0, 821 .gettime64 = ocelot_ptp_gettime64, 822 .settime64 = ocelot_ptp_settime64, 823 .adjtime = ocelot_ptp_adjtime, 824 .adjfine = ocelot_ptp_adjfine, 825 .verify = ocelot_ptp_verify, 826 .enable = ocelot_ptp_enable, 827 }; 828 829 static int mscc_ocelot_probe(struct platform_device *pdev) 830 { 831 struct device_node *np = pdev->dev.of_node; 832 struct device_node *ports, *portnp; 833 int err, irq_xtr, irq_ptp_rdy; 834 struct ocelot *ocelot; 835 struct regmap *hsio; 836 unsigned int i; 837 838 struct { 839 enum ocelot_target id; 840 char *name; 841 u8 optional:1; 842 } io_target[] = { 843 { SYS, "sys" }, 844 { REW, "rew" }, 845 { QSYS, "qsys" }, 846 { ANA, "ana" }, 847 { QS, "qs" }, 848 { S2, "s2" }, 849 { PTP, "ptp", 1 }, 850 }; 851 852 if (!np && !pdev->dev.platform_data) 853 return -ENODEV; 854 855 ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL); 856 if (!ocelot) 857 return -ENOMEM; 858 859 platform_set_drvdata(pdev, ocelot); 860 ocelot->dev = &pdev->dev; 861 862 for (i = 0; i < ARRAY_SIZE(io_target); i++) { 863 struct regmap *target; 864 struct resource *res; 865 866 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 867 io_target[i].name); 868 869 target = ocelot_regmap_init(ocelot, res); 870 if (IS_ERR(target)) { 871 if (io_target[i].optional) { 872 ocelot->targets[io_target[i].id] = NULL; 873 continue; 874 } 875 return PTR_ERR(target); 876 } 877 878 ocelot->targets[io_target[i].id] = target; 879 } 880 881 hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 882 if (IS_ERR(hsio)) { 883 dev_err(&pdev->dev, "missing hsio syscon\n"); 884 return PTR_ERR(hsio); 885 } 886 887 ocelot->targets[HSIO] = hsio; 888 889 err = ocelot_chip_init(ocelot, &ocelot_ops); 890 if (err) 891 return err; 892 893 irq_xtr = platform_get_irq_byname(pdev, "xtr"); 894 if (irq_xtr < 0) 895 return -ENODEV; 896 897 err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 898 ocelot_xtr_irq_handler, IRQF_ONESHOT, 899 "frame extraction", ocelot); 900 if (err) 901 return err; 902 903 irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 904 if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 905 err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 906 ocelot_ptp_rdy_irq_handler, 907 IRQF_ONESHOT, "ptp ready", 908 ocelot); 909 if (err) 910 return err; 911 912 /* Both the PTP interrupt and the PTP bank are available */ 913 ocelot->ptp = 1; 914 } 915 916 ports = of_get_child_by_name(np, "ethernet-ports"); 917 if (!ports) { 918 dev_err(&pdev->dev, "no ethernet-ports child node found\n"); 919 return -ENODEV; 920 } 921 922 ocelot->num_phys_ports = of_get_child_count(ports); 923 924 ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports, 925 sizeof(struct ocelot_port *), GFP_KERNEL); 926 927 ocelot->vcap_is2_keys = vsc7514_vcap_is2_keys; 928 ocelot->vcap_is2_actions = vsc7514_vcap_is2_actions; 929 ocelot->vcap = vsc7514_vcap_props; 930 931 ocelot_init(ocelot); 932 if (ocelot->ptp) { 933 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 934 if (err) { 935 dev_err(ocelot->dev, 936 "Timestamp initialization failed\n"); 937 ocelot->ptp = 0; 938 } 939 } 940 941 /* No NPI port */ 942 ocelot_configure_cpu(ocelot, -1, OCELOT_TAG_PREFIX_NONE, 943 OCELOT_TAG_PREFIX_NONE); 944 945 for_each_available_child_of_node(ports, portnp) { 946 struct ocelot_port_private *priv; 947 struct ocelot_port *ocelot_port; 948 struct device_node *phy_node; 949 phy_interface_t phy_mode; 950 struct phy_device *phy; 951 struct resource *res; 952 struct phy *serdes; 953 void __iomem *regs; 954 char res_name[8]; 955 u32 port; 956 957 if (of_property_read_u32(portnp, "reg", &port)) 958 continue; 959 960 snprintf(res_name, sizeof(res_name), "port%d", port); 961 962 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 963 res_name); 964 regs = devm_ioremap_resource(&pdev->dev, res); 965 if (IS_ERR(regs)) 966 continue; 967 968 phy_node = of_parse_phandle(portnp, "phy-handle", 0); 969 if (!phy_node) 970 continue; 971 972 phy = of_phy_find_device(phy_node); 973 of_node_put(phy_node); 974 if (!phy) 975 continue; 976 977 err = ocelot_probe_port(ocelot, port, regs, phy); 978 if (err) { 979 of_node_put(portnp); 980 goto out_put_ports; 981 } 982 983 ocelot_port = ocelot->ports[port]; 984 priv = container_of(ocelot_port, struct ocelot_port_private, 985 port); 986 987 of_get_phy_mode(portnp, &phy_mode); 988 989 ocelot_port->phy_mode = phy_mode; 990 991 switch (ocelot_port->phy_mode) { 992 case PHY_INTERFACE_MODE_NA: 993 continue; 994 case PHY_INTERFACE_MODE_SGMII: 995 break; 996 case PHY_INTERFACE_MODE_QSGMII: 997 /* Ensure clock signals and speed is set on all 998 * QSGMII links 999 */ 1000 ocelot_port_writel(ocelot_port, 1001 DEV_CLOCK_CFG_LINK_SPEED 1002 (OCELOT_SPEED_1000), 1003 DEV_CLOCK_CFG); 1004 break; 1005 default: 1006 dev_err(ocelot->dev, 1007 "invalid phy mode for port%d, (Q)SGMII only\n", 1008 port); 1009 of_node_put(portnp); 1010 err = -EINVAL; 1011 goto out_put_ports; 1012 } 1013 1014 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); 1015 if (IS_ERR(serdes)) { 1016 err = PTR_ERR(serdes); 1017 if (err == -EPROBE_DEFER) 1018 dev_dbg(ocelot->dev, "deferring probe\n"); 1019 else 1020 dev_err(ocelot->dev, 1021 "missing SerDes phys for port%d\n", 1022 port); 1023 1024 of_node_put(portnp); 1025 goto out_put_ports; 1026 } 1027 1028 priv->serdes = serdes; 1029 } 1030 1031 register_netdevice_notifier(&ocelot_netdevice_nb); 1032 register_switchdev_notifier(&ocelot_switchdev_nb); 1033 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1034 1035 dev_info(&pdev->dev, "Ocelot switch probed\n"); 1036 1037 out_put_ports: 1038 of_node_put(ports); 1039 return err; 1040 } 1041 1042 static int mscc_ocelot_remove(struct platform_device *pdev) 1043 { 1044 struct ocelot *ocelot = platform_get_drvdata(pdev); 1045 1046 ocelot_deinit_timestamp(ocelot); 1047 ocelot_deinit(ocelot); 1048 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1049 unregister_switchdev_notifier(&ocelot_switchdev_nb); 1050 unregister_netdevice_notifier(&ocelot_netdevice_nb); 1051 1052 return 0; 1053 } 1054 1055 static struct platform_driver mscc_ocelot_driver = { 1056 .probe = mscc_ocelot_probe, 1057 .remove = mscc_ocelot_remove, 1058 .driver = { 1059 .name = "ocelot-switch", 1060 .of_match_table = mscc_ocelot_match, 1061 }, 1062 }; 1063 1064 module_platform_driver(mscc_ocelot_driver); 1065 1066 MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1067 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1068 MODULE_LICENSE("Dual MIT/GPL"); 1069