1589aa6e7SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2589aa6e7SVladimir Oltean /* 3589aa6e7SVladimir Oltean * Microsemi Ocelot Switch driver 4589aa6e7SVladimir Oltean * 5589aa6e7SVladimir Oltean * Copyright (c) 2017 Microsemi Corporation 6589aa6e7SVladimir Oltean */ 7589aa6e7SVladimir Oltean #include <linux/interrupt.h> 8589aa6e7SVladimir Oltean #include <linux/module.h> 9589aa6e7SVladimir Oltean #include <linux/of_net.h> 10589aa6e7SVladimir Oltean #include <linux/netdevice.h> 11589aa6e7SVladimir Oltean #include <linux/of_mdio.h> 12589aa6e7SVladimir Oltean #include <linux/of_platform.h> 13589aa6e7SVladimir Oltean #include <linux/mfd/syscon.h> 14589aa6e7SVladimir Oltean #include <linux/skbuff.h> 15589aa6e7SVladimir Oltean #include <net/switchdev.h> 16589aa6e7SVladimir Oltean 17589aa6e7SVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 18d9feb904SVladimir Oltean #include <soc/mscc/ocelot_hsio.h> 19589aa6e7SVladimir Oltean #include "ocelot.h" 20589aa6e7SVladimir Oltean 21589aa6e7SVladimir Oltean #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) 22589aa6e7SVladimir Oltean 23d9feb904SVladimir Oltean static const u32 ocelot_ana_regmap[] = { 24d9feb904SVladimir Oltean REG(ANA_ADVLEARN, 0x009000), 25d9feb904SVladimir Oltean REG(ANA_VLANMASK, 0x009004), 26d9feb904SVladimir Oltean REG(ANA_PORT_B_DOMAIN, 0x009008), 27d9feb904SVladimir Oltean REG(ANA_ANAGEFIL, 0x00900c), 28d9feb904SVladimir Oltean REG(ANA_ANEVENTS, 0x009010), 29d9feb904SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x009014), 30d9feb904SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x009018), 31d9feb904SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x009028), 32d9feb904SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x00902c), 33d9feb904SVladimir Oltean REG(ANA_AUTOAGE, 0x009030), 34d9feb904SVladimir Oltean REG(ANA_MACTOPTIONS, 0x009034), 35d9feb904SVladimir Oltean REG(ANA_LEARNDISC, 0x009038), 36d9feb904SVladimir Oltean REG(ANA_AGENCTRL, 0x00903c), 37d9feb904SVladimir Oltean REG(ANA_MIRRORPORTS, 0x009040), 38d9feb904SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x009044), 39d9feb904SVladimir Oltean REG(ANA_FLOODING, 0x009048), 40d9feb904SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x00904c), 41d9feb904SVladimir Oltean REG(ANA_SFLOW_CFG, 0x009050), 42d9feb904SVladimir Oltean REG(ANA_PORT_MODE, 0x009080), 43d9feb904SVladimir Oltean REG(ANA_PGID_PGID, 0x008c00), 44d9feb904SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x008b30), 45d9feb904SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x008b34), 46d9feb904SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x008b38), 47d9feb904SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x008b3c), 48d9feb904SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x008b40), 49d9feb904SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x008b44), 50d9feb904SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x008b48), 51d9feb904SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 52d9feb904SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x008b50), 53d9feb904SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x008b00), 54d9feb904SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 55d9feb904SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 56d9feb904SVladimir Oltean REG(ANA_MSTI_STATE, 0x008e00), 57d9feb904SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007000), 58d9feb904SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007004), 59d9feb904SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007008), 60d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00700c), 61d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 62d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 63d9feb904SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 64d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 65d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 66d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 67d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 68d9feb904SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007070), 69d9feb904SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007074), 70d9feb904SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007078), 71d9feb904SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 72d9feb904SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 73d9feb904SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 74d9feb904SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 75d9feb904SVladimir Oltean REG(ANA_PFC_PFC_TIMER, 0x008804), 76d9feb904SVladimir Oltean REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 77d9feb904SVladimir Oltean REG(ANA_IPT_IPT, 0x008004), 78d9feb904SVladimir Oltean REG(ANA_PPT_PPT, 0x008ac0), 79d9feb904SVladimir Oltean REG(ANA_FID_MAP_FID_MAP, 0x000000), 80d9feb904SVladimir Oltean REG(ANA_AGGR_CFG, 0x0090b4), 81d9feb904SVladimir Oltean REG(ANA_CPUQ_CFG, 0x0090b8), 82d9feb904SVladimir Oltean REG(ANA_CPUQ_CFG2, 0x0090bc), 83d9feb904SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x0090c0), 84d9feb904SVladimir Oltean REG(ANA_DSCP_CFG, 0x009100), 85d9feb904SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x009200), 86d9feb904SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 87d9feb904SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 88d9feb904SVladimir Oltean REG(ANA_VRAP_CFG, 0x009280), 89d9feb904SVladimir Oltean REG(ANA_VRAP_HDR_DATA, 0x009284), 90d9feb904SVladimir Oltean REG(ANA_VRAP_HDR_MASK, 0x009288), 91d9feb904SVladimir Oltean REG(ANA_DISCARD_CFG, 0x00928c), 92d9feb904SVladimir Oltean REG(ANA_FID_CFG, 0x009290), 93d9feb904SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 94d9feb904SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 95d9feb904SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 96d9feb904SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 97d9feb904SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 98d9feb904SVladimir Oltean REG(ANA_POL_STATE, 0x004014), 99d9feb904SVladimir Oltean REG(ANA_POL_FLOWC, 0x008b80), 100d9feb904SVladimir Oltean REG(ANA_POL_HYST, 0x008bec), 101d9feb904SVladimir Oltean REG(ANA_POL_MISC_CFG, 0x008bf0), 102d9feb904SVladimir Oltean }; 103d9feb904SVladimir Oltean 104d9feb904SVladimir Oltean static const u32 ocelot_qs_regmap[] = { 105d9feb904SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 106d9feb904SVladimir Oltean REG(QS_XTR_RD, 0x000008), 107d9feb904SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 108d9feb904SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 109d9feb904SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 110d9feb904SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 111d9feb904SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 112d9feb904SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 113d9feb904SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 114d9feb904SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 115d9feb904SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 116d9feb904SVladimir Oltean REG(QS_INH_DBG, 0x000048), 117d9feb904SVladimir Oltean }; 118d9feb904SVladimir Oltean 119d9feb904SVladimir Oltean static const u32 ocelot_qsys_regmap[] = { 120d9feb904SVladimir Oltean REG(QSYS_PORT_MODE, 0x011200), 121d9feb904SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x011234), 122d9feb904SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x011264), 123d9feb904SVladimir Oltean REG(QSYS_EEE_CFG, 0x011268), 124d9feb904SVladimir Oltean REG(QSYS_EEE_THRES, 0x011294), 125d9feb904SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x011298), 126d9feb904SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x01129c), 127d9feb904SVladimir Oltean REG(QSYS_SW_STATUS, 0x0112a0), 128d9feb904SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x0112d0), 129d9feb904SVladimir Oltean REG(QSYS_PAD_CFG, 0x0112d4), 130d9feb904SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 131d9feb904SVladimir Oltean REG(QSYS_QMAP, 0x0112dc), 132d9feb904SVladimir Oltean REG(QSYS_ISDX_SGRP, 0x011400), 133d9feb904SVladimir Oltean REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 134d9feb904SVladimir Oltean REG(QSYS_TFRM_MISC, 0x011310), 135d9feb904SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x011314), 136d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 137d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 138d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 139d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 140d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 141d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 142d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 143d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 144d9feb904SVladimir Oltean REG(QSYS_RED_PROFILE, 0x011338), 145d9feb904SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x011378), 146d9feb904SVladimir Oltean REG(QSYS_RES_CFG, 0x012000), 147d9feb904SVladimir Oltean REG(QSYS_RES_STAT, 0x012004), 148d9feb904SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x01137c), 149d9feb904SVladimir Oltean REG(QSYS_EQ_CTRL, 0x011380), 150d9feb904SVladimir Oltean REG(QSYS_EVENTS_CORE, 0x011384), 151d9feb904SVladimir Oltean REG(QSYS_CIR_CFG, 0x000000), 152d9feb904SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 153d9feb904SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 154d9feb904SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 155d9feb904SVladimir Oltean REG(QSYS_SE_CONNECT, 0x00003c), 156d9feb904SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 157d9feb904SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 158d9feb904SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 159d9feb904SVladimir Oltean REG(QSYS_SE_STATE, 0x00004c), 160d9feb904SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x011388), 161d9feb904SVladimir Oltean }; 162d9feb904SVladimir Oltean 163d9feb904SVladimir Oltean static const u32 ocelot_rew_regmap[] = { 164d9feb904SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 165d9feb904SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 166d9feb904SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 167d9feb904SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 168d9feb904SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 169d9feb904SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 170d9feb904SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 171d9feb904SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 172d9feb904SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000790), 173d9feb904SVladimir Oltean REG(REW_STAT_CFG, 0x000890), 174d9feb904SVladimir Oltean REG(REW_PPT, 0x000680), 175d9feb904SVladimir Oltean }; 176d9feb904SVladimir Oltean 177d9feb904SVladimir Oltean static const u32 ocelot_sys_regmap[] = { 178d9feb904SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 179d9feb904SVladimir Oltean REG(SYS_COUNT_RX_UNICAST, 0x000004), 180d9feb904SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 181d9feb904SVladimir Oltean REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 182d9feb904SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 183d9feb904SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 184d9feb904SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 185d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 186d9feb904SVladimir Oltean REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 187d9feb904SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 188d9feb904SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 189d9feb904SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 190d9feb904SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 191d9feb904SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 192d9feb904SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 193d9feb904SVladimir Oltean REG(SYS_COUNT_RX_PAUSE, 0x00003c), 194d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CONTROL, 0x000040), 195d9feb904SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 196d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 197d9feb904SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000100), 198d9feb904SVladimir Oltean REG(SYS_COUNT_TX_UNICAST, 0x000104), 199d9feb904SVladimir Oltean REG(SYS_COUNT_TX_MULTICAST, 0x000108), 200d9feb904SVladimir Oltean REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 201d9feb904SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000110), 202d9feb904SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000114), 203d9feb904SVladimir Oltean REG(SYS_COUNT_TX_PAUSE, 0x000118), 204d9feb904SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00011c), 205d9feb904SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000120), 206d9feb904SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000124), 207d9feb904SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000128), 208d9feb904SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00012c), 209d9feb904SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000130), 210d9feb904SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000170), 211d9feb904SVladimir Oltean REG(SYS_RESET_CFG, 0x000508), 212d9feb904SVladimir Oltean REG(SYS_CMID, 0x00050c), 213d9feb904SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000510), 214d9feb904SVladimir Oltean REG(SYS_PORT_MODE, 0x000514), 215d9feb904SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000548), 216d9feb904SVladimir Oltean REG(SYS_FRM_AGING, 0x000574), 217d9feb904SVladimir Oltean REG(SYS_STAT_CFG, 0x000578), 218d9feb904SVladimir Oltean REG(SYS_SW_STATUS, 0x00057c), 219d9feb904SVladimir Oltean REG(SYS_MISC_CFG, 0x0005ac), 220d9feb904SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 221d9feb904SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 222d9feb904SVladimir Oltean REG(SYS_CM_ADDR, 0x000500), 223d9feb904SVladimir Oltean REG(SYS_CM_DATA, 0x000504), 224d9feb904SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000608), 225d9feb904SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000638), 226d9feb904SVladimir Oltean REG(SYS_ATOP, 0x00063c), 227d9feb904SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x00066c), 228d9feb904SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000670), 229d9feb904SVladimir Oltean REG(SYS_MMGT, 0x00069c), 230d9feb904SVladimir Oltean REG(SYS_MMGT_FAST, 0x0006a0), 231d9feb904SVladimir Oltean REG(SYS_EVENTS_DIF, 0x0006a4), 232d9feb904SVladimir Oltean REG(SYS_EVENTS_CORE, 0x0006b4), 233d9feb904SVladimir Oltean REG(SYS_CNT, 0x000000), 234d9feb904SVladimir Oltean REG(SYS_PTP_STATUS, 0x0006b8), 235d9feb904SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x0006bc), 236d9feb904SVladimir Oltean REG(SYS_PTP_NXT, 0x0006c0), 237d9feb904SVladimir Oltean REG(SYS_PTP_CFG, 0x0006c4), 238d9feb904SVladimir Oltean }; 239d9feb904SVladimir Oltean 240c1c3993eSVladimir Oltean static const u32 ocelot_vcap_regmap[] = { 241c1c3993eSVladimir Oltean /* VCAP_CORE_CFG */ 242c1c3993eSVladimir Oltean REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 243c1c3993eSVladimir Oltean REG(VCAP_CORE_MV_CFG, 0x000004), 244c1c3993eSVladimir Oltean /* VCAP_CORE_CACHE */ 245c1c3993eSVladimir Oltean REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 246c1c3993eSVladimir Oltean REG(VCAP_CACHE_MASK_DAT, 0x000108), 247c1c3993eSVladimir Oltean REG(VCAP_CACHE_ACTION_DAT, 0x000208), 248c1c3993eSVladimir Oltean REG(VCAP_CACHE_CNT_DAT, 0x000308), 249c1c3993eSVladimir Oltean REG(VCAP_CACHE_TG_DAT, 0x000388), 25020968054SVladimir Oltean /* VCAP_CONST */ 25120968054SVladimir Oltean REG(VCAP_CONST_VCAP_VER, 0x000398), 25220968054SVladimir Oltean REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 25320968054SVladimir Oltean REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 25420968054SVladimir Oltean REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 25520968054SVladimir Oltean REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 25620968054SVladimir Oltean REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 25720968054SVladimir Oltean REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 25820968054SVladimir Oltean REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 25920968054SVladimir Oltean REG(VCAP_CONST_CORE_CNT, 0x0003b8), 26020968054SVladimir Oltean REG(VCAP_CONST_IF_CNT, 0x0003bc), 261d9feb904SVladimir Oltean }; 262d9feb904SVladimir Oltean 263d9feb904SVladimir Oltean static const u32 ocelot_ptp_regmap[] = { 264d9feb904SVladimir Oltean REG(PTP_PIN_CFG, 0x000000), 265d9feb904SVladimir Oltean REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 266d9feb904SVladimir Oltean REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 267d9feb904SVladimir Oltean REG(PTP_PIN_TOD_NSEC, 0x00000c), 268d9feb904SVladimir Oltean REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 269d9feb904SVladimir Oltean REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 270d9feb904SVladimir Oltean REG(PTP_CFG_MISC, 0x0000a0), 271d9feb904SVladimir Oltean REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 272d9feb904SVladimir Oltean REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 273d9feb904SVladimir Oltean }; 274d9feb904SVladimir Oltean 27591c724cfSVladimir Oltean static const u32 ocelot_dev_gmii_regmap[] = { 27691c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 27791c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 27891c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 27991c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 28091c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 28191c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 28291c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 28391c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 28491c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 28591c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 28691c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 28791c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 28891c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 28991c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 29091c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 29191c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 29291c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 29391c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 29491c724cfSVladimir Oltean REG(PCS1G_CFG, 0x48), 29591c724cfSVladimir Oltean REG(PCS1G_MODE_CFG, 0x4c), 29691c724cfSVladimir Oltean REG(PCS1G_SD_CFG, 0x50), 29791c724cfSVladimir Oltean REG(PCS1G_ANEG_CFG, 0x54), 29891c724cfSVladimir Oltean REG(PCS1G_ANEG_NP_CFG, 0x58), 29991c724cfSVladimir Oltean REG(PCS1G_LB_CFG, 0x5c), 30091c724cfSVladimir Oltean REG(PCS1G_DBG_CFG, 0x60), 30191c724cfSVladimir Oltean REG(PCS1G_CDET_CFG, 0x64), 30291c724cfSVladimir Oltean REG(PCS1G_ANEG_STATUS, 0x68), 30391c724cfSVladimir Oltean REG(PCS1G_ANEG_NP_STATUS, 0x6c), 30491c724cfSVladimir Oltean REG(PCS1G_LINK_STATUS, 0x70), 30591c724cfSVladimir Oltean REG(PCS1G_LINK_DOWN_CNT, 0x74), 30691c724cfSVladimir Oltean REG(PCS1G_STICKY, 0x78), 30791c724cfSVladimir Oltean REG(PCS1G_DEBUG_STATUS, 0x7c), 30891c724cfSVladimir Oltean REG(PCS1G_LPI_CFG, 0x80), 30991c724cfSVladimir Oltean REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 31091c724cfSVladimir Oltean REG(PCS1G_LPI_STATUS, 0x88), 31191c724cfSVladimir Oltean REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 31291c724cfSVladimir Oltean REG(PCS1G_TSTPAT_STATUS, 0x90), 31391c724cfSVladimir Oltean REG(DEV_PCS_FX100_CFG, 0x94), 31491c724cfSVladimir Oltean REG(DEV_PCS_FX100_STATUS, 0x98), 31591c724cfSVladimir Oltean }; 31691c724cfSVladimir Oltean 31791c724cfSVladimir Oltean static const u32 *ocelot_regmap[TARGET_MAX] = { 318d9feb904SVladimir Oltean [ANA] = ocelot_ana_regmap, 319d9feb904SVladimir Oltean [QS] = ocelot_qs_regmap, 320d9feb904SVladimir Oltean [QSYS] = ocelot_qsys_regmap, 321d9feb904SVladimir Oltean [REW] = ocelot_rew_regmap, 322d9feb904SVladimir Oltean [SYS] = ocelot_sys_regmap, 323de997e54SVladimir Oltean [S0] = ocelot_vcap_regmap, 324de997e54SVladimir Oltean [S1] = ocelot_vcap_regmap, 325c1c3993eSVladimir Oltean [S2] = ocelot_vcap_regmap, 326d9feb904SVladimir Oltean [PTP] = ocelot_ptp_regmap, 32791c724cfSVladimir Oltean [DEV_GMII] = ocelot_dev_gmii_regmap, 328d9feb904SVladimir Oltean }; 329d9feb904SVladimir Oltean 3302789658fSMaxim Kochetkov static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 331d9feb904SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 332d9feb904SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 333d9feb904SVladimir Oltean [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 334d9feb904SVladimir Oltean [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 335d9feb904SVladimir Oltean [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 336d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 337d9feb904SVladimir Oltean [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 338d9feb904SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 339d9feb904SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 340d9feb904SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 341d9feb904SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 342d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 343d9feb904SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 344d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 345d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 346d9feb904SVladimir Oltean [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 347d9feb904SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 348d9feb904SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 349d9feb904SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 350d9feb904SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 351d9feb904SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 352d9feb904SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 353d9feb904SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 354d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 355d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 356d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 357d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 358d9feb904SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 359d9feb904SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 360d9feb904SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 361d9feb904SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 362d9feb904SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 363d9feb904SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 364d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 365d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 366d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 367d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 368d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 369d9feb904SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 370d9feb904SVladimir Oltean [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 371d9feb904SVladimir Oltean [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 3728bb849d6SVladimir Oltean /* Replicated per number of ports (12), register size 4 per port */ 3738bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 3748bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 3758bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 3768bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 3778bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 3788bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 3798bb849d6SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 3808bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 3818bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 3828bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 3838bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 3848bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 3858bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 386d9feb904SVladimir Oltean }; 387d9feb904SVladimir Oltean 388d9feb904SVladimir Oltean static const struct ocelot_stat_layout ocelot_stats_layout[] = { 389d9feb904SVladimir Oltean { .name = "rx_octets", .offset = 0x00, }, 390d9feb904SVladimir Oltean { .name = "rx_unicast", .offset = 0x01, }, 391d9feb904SVladimir Oltean { .name = "rx_multicast", .offset = 0x02, }, 392d9feb904SVladimir Oltean { .name = "rx_broadcast", .offset = 0x03, }, 393d9feb904SVladimir Oltean { .name = "rx_shorts", .offset = 0x04, }, 394d9feb904SVladimir Oltean { .name = "rx_fragments", .offset = 0x05, }, 395d9feb904SVladimir Oltean { .name = "rx_jabbers", .offset = 0x06, }, 396d9feb904SVladimir Oltean { .name = "rx_crc_align_errs", .offset = 0x07, }, 397d9feb904SVladimir Oltean { .name = "rx_sym_errs", .offset = 0x08, }, 398d9feb904SVladimir Oltean { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 399d9feb904SVladimir Oltean { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 400d9feb904SVladimir Oltean { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 401d9feb904SVladimir Oltean { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 402d9feb904SVladimir Oltean { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 403d9feb904SVladimir Oltean { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 404d9feb904SVladimir Oltean { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 405d9feb904SVladimir Oltean { .name = "rx_pause", .offset = 0x10, }, 406d9feb904SVladimir Oltean { .name = "rx_control", .offset = 0x11, }, 407d9feb904SVladimir Oltean { .name = "rx_longs", .offset = 0x12, }, 408d9feb904SVladimir Oltean { .name = "rx_classified_drops", .offset = 0x13, }, 409d9feb904SVladimir Oltean { .name = "rx_red_prio_0", .offset = 0x14, }, 410d9feb904SVladimir Oltean { .name = "rx_red_prio_1", .offset = 0x15, }, 411d9feb904SVladimir Oltean { .name = "rx_red_prio_2", .offset = 0x16, }, 412d9feb904SVladimir Oltean { .name = "rx_red_prio_3", .offset = 0x17, }, 413d9feb904SVladimir Oltean { .name = "rx_red_prio_4", .offset = 0x18, }, 414d9feb904SVladimir Oltean { .name = "rx_red_prio_5", .offset = 0x19, }, 415d9feb904SVladimir Oltean { .name = "rx_red_prio_6", .offset = 0x1A, }, 416d9feb904SVladimir Oltean { .name = "rx_red_prio_7", .offset = 0x1B, }, 417d9feb904SVladimir Oltean { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 418d9feb904SVladimir Oltean { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 419d9feb904SVladimir Oltean { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 420d9feb904SVladimir Oltean { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 421d9feb904SVladimir Oltean { .name = "rx_yellow_prio_4", .offset = 0x20, }, 422d9feb904SVladimir Oltean { .name = "rx_yellow_prio_5", .offset = 0x21, }, 423d9feb904SVladimir Oltean { .name = "rx_yellow_prio_6", .offset = 0x22, }, 424d9feb904SVladimir Oltean { .name = "rx_yellow_prio_7", .offset = 0x23, }, 425d9feb904SVladimir Oltean { .name = "rx_green_prio_0", .offset = 0x24, }, 426d9feb904SVladimir Oltean { .name = "rx_green_prio_1", .offset = 0x25, }, 427d9feb904SVladimir Oltean { .name = "rx_green_prio_2", .offset = 0x26, }, 428d9feb904SVladimir Oltean { .name = "rx_green_prio_3", .offset = 0x27, }, 429d9feb904SVladimir Oltean { .name = "rx_green_prio_4", .offset = 0x28, }, 430d9feb904SVladimir Oltean { .name = "rx_green_prio_5", .offset = 0x29, }, 431d9feb904SVladimir Oltean { .name = "rx_green_prio_6", .offset = 0x2A, }, 432d9feb904SVladimir Oltean { .name = "rx_green_prio_7", .offset = 0x2B, }, 433d9feb904SVladimir Oltean { .name = "tx_octets", .offset = 0x40, }, 434d9feb904SVladimir Oltean { .name = "tx_unicast", .offset = 0x41, }, 435d9feb904SVladimir Oltean { .name = "tx_multicast", .offset = 0x42, }, 436d9feb904SVladimir Oltean { .name = "tx_broadcast", .offset = 0x43, }, 437d9feb904SVladimir Oltean { .name = "tx_collision", .offset = 0x44, }, 438d9feb904SVladimir Oltean { .name = "tx_drops", .offset = 0x45, }, 439d9feb904SVladimir Oltean { .name = "tx_pause", .offset = 0x46, }, 440d9feb904SVladimir Oltean { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 441d9feb904SVladimir Oltean { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 442d9feb904SVladimir Oltean { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 443d9feb904SVladimir Oltean { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 444d9feb904SVladimir Oltean { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 445d9feb904SVladimir Oltean { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 446d9feb904SVladimir Oltean { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 447d9feb904SVladimir Oltean { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 448d9feb904SVladimir Oltean { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 449d9feb904SVladimir Oltean { .name = "tx_yellow_prio_2", .offset = 0x50, }, 450d9feb904SVladimir Oltean { .name = "tx_yellow_prio_3", .offset = 0x51, }, 451d9feb904SVladimir Oltean { .name = "tx_yellow_prio_4", .offset = 0x52, }, 452d9feb904SVladimir Oltean { .name = "tx_yellow_prio_5", .offset = 0x53, }, 453d9feb904SVladimir Oltean { .name = "tx_yellow_prio_6", .offset = 0x54, }, 454d9feb904SVladimir Oltean { .name = "tx_yellow_prio_7", .offset = 0x55, }, 455d9feb904SVladimir Oltean { .name = "tx_green_prio_0", .offset = 0x56, }, 456d9feb904SVladimir Oltean { .name = "tx_green_prio_1", .offset = 0x57, }, 457d9feb904SVladimir Oltean { .name = "tx_green_prio_2", .offset = 0x58, }, 458d9feb904SVladimir Oltean { .name = "tx_green_prio_3", .offset = 0x59, }, 459d9feb904SVladimir Oltean { .name = "tx_green_prio_4", .offset = 0x5A, }, 460d9feb904SVladimir Oltean { .name = "tx_green_prio_5", .offset = 0x5B, }, 461d9feb904SVladimir Oltean { .name = "tx_green_prio_6", .offset = 0x5C, }, 462d9feb904SVladimir Oltean { .name = "tx_green_prio_7", .offset = 0x5D, }, 463d9feb904SVladimir Oltean { .name = "tx_aged", .offset = 0x5E, }, 464d9feb904SVladimir Oltean { .name = "drop_local", .offset = 0x80, }, 465d9feb904SVladimir Oltean { .name = "drop_tail", .offset = 0x81, }, 466d9feb904SVladimir Oltean { .name = "drop_yellow_prio_0", .offset = 0x82, }, 467d9feb904SVladimir Oltean { .name = "drop_yellow_prio_1", .offset = 0x83, }, 468d9feb904SVladimir Oltean { .name = "drop_yellow_prio_2", .offset = 0x84, }, 469d9feb904SVladimir Oltean { .name = "drop_yellow_prio_3", .offset = 0x85, }, 470d9feb904SVladimir Oltean { .name = "drop_yellow_prio_4", .offset = 0x86, }, 471d9feb904SVladimir Oltean { .name = "drop_yellow_prio_5", .offset = 0x87, }, 472d9feb904SVladimir Oltean { .name = "drop_yellow_prio_6", .offset = 0x88, }, 473d9feb904SVladimir Oltean { .name = "drop_yellow_prio_7", .offset = 0x89, }, 474d9feb904SVladimir Oltean { .name = "drop_green_prio_0", .offset = 0x8A, }, 475d9feb904SVladimir Oltean { .name = "drop_green_prio_1", .offset = 0x8B, }, 476d9feb904SVladimir Oltean { .name = "drop_green_prio_2", .offset = 0x8C, }, 477d9feb904SVladimir Oltean { .name = "drop_green_prio_3", .offset = 0x8D, }, 478d9feb904SVladimir Oltean { .name = "drop_green_prio_4", .offset = 0x8E, }, 479d9feb904SVladimir Oltean { .name = "drop_green_prio_5", .offset = 0x8F, }, 480d9feb904SVladimir Oltean { .name = "drop_green_prio_6", .offset = 0x90, }, 481d9feb904SVladimir Oltean { .name = "drop_green_prio_7", .offset = 0x91, }, 482d9feb904SVladimir Oltean }; 483d9feb904SVladimir Oltean 484d9feb904SVladimir Oltean static void ocelot_pll5_init(struct ocelot *ocelot) 485d9feb904SVladimir Oltean { 486d9feb904SVladimir Oltean /* Configure PLL5. This will need a proper CCF driver 487d9feb904SVladimir Oltean * The values are coming from the VTSS API for Ocelot 488d9feb904SVladimir Oltean */ 489d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 490d9feb904SVladimir Oltean HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 491d9feb904SVladimir Oltean HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 492d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 493d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 494d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 495d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_BIAS | 496d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_VCO_BUF | 497d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_CP1 | 498d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_SELCPI(2) | 499d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 500d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_SELBGV820(4) | 501d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_DIV4 | 502d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_CLKTREE | 503d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_LANE); 504d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 505d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 506d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 507d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 508d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_ENA_AMPCTRL | 509d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 510d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 511d9feb904SVladimir Oltean } 512d9feb904SVladimir Oltean 513d9feb904SVladimir Oltean static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 514d9feb904SVladimir Oltean { 515d9feb904SVladimir Oltean int ret; 516d9feb904SVladimir Oltean 517d9feb904SVladimir Oltean ocelot->map = ocelot_regmap; 518d9feb904SVladimir Oltean ocelot->stats_layout = ocelot_stats_layout; 519d9feb904SVladimir Oltean ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 520d9feb904SVladimir Oltean ocelot->shared_queue_sz = 224 * 1024; 521d9feb904SVladimir Oltean ocelot->num_mact_rows = 1024; 522d9feb904SVladimir Oltean ocelot->ops = ops; 523d9feb904SVladimir Oltean 524d9feb904SVladimir Oltean ret = ocelot_regfields_init(ocelot, ocelot_regfields); 525d9feb904SVladimir Oltean if (ret) 526d9feb904SVladimir Oltean return ret; 527d9feb904SVladimir Oltean 528d9feb904SVladimir Oltean ocelot_pll5_init(ocelot); 529d9feb904SVladimir Oltean 530d9feb904SVladimir Oltean eth_random_addr(ocelot->base_mac); 531d9feb904SVladimir Oltean ocelot->base_mac[5] &= 0xf0; 532d9feb904SVladimir Oltean 533d9feb904SVladimir Oltean return 0; 534d9feb904SVladimir Oltean } 535d9feb904SVladimir Oltean 536589aa6e7SVladimir Oltean static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info) 537589aa6e7SVladimir Oltean { 538589aa6e7SVladimir Oltean u8 llen, wlen; 539589aa6e7SVladimir Oltean u64 ifh[2]; 540589aa6e7SVladimir Oltean 541589aa6e7SVladimir Oltean ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]); 542589aa6e7SVladimir Oltean ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]); 543589aa6e7SVladimir Oltean 544589aa6e7SVladimir Oltean wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7, 8); 545589aa6e7SVladimir Oltean llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15, 6); 546589aa6e7SVladimir Oltean 547589aa6e7SVladimir Oltean info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80; 548589aa6e7SVladimir Oltean 549589aa6e7SVladimir Oltean info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32); 550589aa6e7SVladimir Oltean 551589aa6e7SVladimir Oltean info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4); 552589aa6e7SVladimir Oltean 553589aa6e7SVladimir Oltean info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16, 1); 554589aa6e7SVladimir Oltean info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0, 12); 555589aa6e7SVladimir Oltean 556589aa6e7SVladimir Oltean return 0; 557589aa6e7SVladimir Oltean } 558589aa6e7SVladimir Oltean 559589aa6e7SVladimir Oltean static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 560589aa6e7SVladimir Oltean u32 *rval) 561589aa6e7SVladimir Oltean { 562589aa6e7SVladimir Oltean u32 val; 563589aa6e7SVladimir Oltean u32 bytes_valid; 564589aa6e7SVladimir Oltean 565589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 566589aa6e7SVladimir Oltean if (val == XTR_NOT_READY) { 567589aa6e7SVladimir Oltean if (ifh) 568589aa6e7SVladimir Oltean return -EIO; 569589aa6e7SVladimir Oltean 570589aa6e7SVladimir Oltean do { 571589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 572589aa6e7SVladimir Oltean } while (val == XTR_NOT_READY); 573589aa6e7SVladimir Oltean } 574589aa6e7SVladimir Oltean 575589aa6e7SVladimir Oltean switch (val) { 576589aa6e7SVladimir Oltean case XTR_ABORT: 577589aa6e7SVladimir Oltean return -EIO; 578589aa6e7SVladimir Oltean case XTR_EOF_0: 579589aa6e7SVladimir Oltean case XTR_EOF_1: 580589aa6e7SVladimir Oltean case XTR_EOF_2: 581589aa6e7SVladimir Oltean case XTR_EOF_3: 582589aa6e7SVladimir Oltean case XTR_PRUNED: 583589aa6e7SVladimir Oltean bytes_valid = XTR_VALID_BYTES(val); 584589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 585589aa6e7SVladimir Oltean if (val == XTR_ESCAPE) 586589aa6e7SVladimir Oltean *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 587589aa6e7SVladimir Oltean else 588589aa6e7SVladimir Oltean *rval = val; 589589aa6e7SVladimir Oltean 590589aa6e7SVladimir Oltean return bytes_valid; 591589aa6e7SVladimir Oltean case XTR_ESCAPE: 592589aa6e7SVladimir Oltean *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 593589aa6e7SVladimir Oltean 594589aa6e7SVladimir Oltean return 4; 595589aa6e7SVladimir Oltean default: 596589aa6e7SVladimir Oltean *rval = val; 597589aa6e7SVladimir Oltean 598589aa6e7SVladimir Oltean return 4; 599589aa6e7SVladimir Oltean } 600589aa6e7SVladimir Oltean } 601589aa6e7SVladimir Oltean 602589aa6e7SVladimir Oltean static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 603589aa6e7SVladimir Oltean { 604589aa6e7SVladimir Oltean struct ocelot *ocelot = arg; 605589aa6e7SVladimir Oltean int i = 0, grp = 0; 606589aa6e7SVladimir Oltean int err = 0; 607589aa6e7SVladimir Oltean 608589aa6e7SVladimir Oltean if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) 609589aa6e7SVladimir Oltean return IRQ_NONE; 610589aa6e7SVladimir Oltean 611589aa6e7SVladimir Oltean do { 612589aa6e7SVladimir Oltean struct skb_shared_hwtstamps *shhwtstamps; 613589aa6e7SVladimir Oltean struct ocelot_port_private *priv; 614589aa6e7SVladimir Oltean struct ocelot_port *ocelot_port; 615589aa6e7SVladimir Oltean u64 tod_in_ns, full_ts_in_ns; 616589aa6e7SVladimir Oltean struct frame_info info = {}; 617589aa6e7SVladimir Oltean struct net_device *dev; 618589aa6e7SVladimir Oltean u32 ifh[4], val, *buf; 619589aa6e7SVladimir Oltean struct timespec64 ts; 620589aa6e7SVladimir Oltean int sz, len, buf_len; 621589aa6e7SVladimir Oltean struct sk_buff *skb; 622589aa6e7SVladimir Oltean 623589aa6e7SVladimir Oltean for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 624589aa6e7SVladimir Oltean err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]); 625589aa6e7SVladimir Oltean if (err != 4) 626589aa6e7SVladimir Oltean break; 627589aa6e7SVladimir Oltean } 628589aa6e7SVladimir Oltean 629589aa6e7SVladimir Oltean if (err != 4) 630589aa6e7SVladimir Oltean break; 631589aa6e7SVladimir Oltean 632589aa6e7SVladimir Oltean /* At this point the IFH was read correctly, so it is safe to 633589aa6e7SVladimir Oltean * presume that there is no error. The err needs to be reset 634589aa6e7SVladimir Oltean * otherwise a frame could come in CPU queue between the while 635589aa6e7SVladimir Oltean * condition and the check for error later on. And in that case 636589aa6e7SVladimir Oltean * the new frame is just removed and not processed. 637589aa6e7SVladimir Oltean */ 638589aa6e7SVladimir Oltean err = 0; 639589aa6e7SVladimir Oltean 640589aa6e7SVladimir Oltean ocelot_parse_ifh(ifh, &info); 641589aa6e7SVladimir Oltean 642589aa6e7SVladimir Oltean ocelot_port = ocelot->ports[info.port]; 643589aa6e7SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 644589aa6e7SVladimir Oltean port); 645589aa6e7SVladimir Oltean dev = priv->dev; 646589aa6e7SVladimir Oltean 647589aa6e7SVladimir Oltean skb = netdev_alloc_skb(dev, info.len); 648589aa6e7SVladimir Oltean 649589aa6e7SVladimir Oltean if (unlikely(!skb)) { 650589aa6e7SVladimir Oltean netdev_err(dev, "Unable to allocate sk_buff\n"); 651589aa6e7SVladimir Oltean err = -ENOMEM; 652589aa6e7SVladimir Oltean break; 653589aa6e7SVladimir Oltean } 654589aa6e7SVladimir Oltean buf_len = info.len - ETH_FCS_LEN; 655589aa6e7SVladimir Oltean buf = (u32 *)skb_put(skb, buf_len); 656589aa6e7SVladimir Oltean 657589aa6e7SVladimir Oltean len = 0; 658589aa6e7SVladimir Oltean do { 659589aa6e7SVladimir Oltean sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 660589aa6e7SVladimir Oltean *buf++ = val; 661589aa6e7SVladimir Oltean len += sz; 662589aa6e7SVladimir Oltean } while (len < buf_len); 663589aa6e7SVladimir Oltean 664589aa6e7SVladimir Oltean /* Read the FCS */ 665589aa6e7SVladimir Oltean sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 666589aa6e7SVladimir Oltean /* Update the statistics if part of the FCS was read before */ 667589aa6e7SVladimir Oltean len -= ETH_FCS_LEN - sz; 668589aa6e7SVladimir Oltean 669589aa6e7SVladimir Oltean if (unlikely(dev->features & NETIF_F_RXFCS)) { 670589aa6e7SVladimir Oltean buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 671589aa6e7SVladimir Oltean *buf = val; 672589aa6e7SVladimir Oltean } 673589aa6e7SVladimir Oltean 674589aa6e7SVladimir Oltean if (sz < 0) { 675589aa6e7SVladimir Oltean err = sz; 676589aa6e7SVladimir Oltean break; 677589aa6e7SVladimir Oltean } 678589aa6e7SVladimir Oltean 679589aa6e7SVladimir Oltean if (ocelot->ptp) { 680589aa6e7SVladimir Oltean ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 681589aa6e7SVladimir Oltean 682589aa6e7SVladimir Oltean tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 683589aa6e7SVladimir Oltean if ((tod_in_ns & 0xffffffff) < info.timestamp) 684589aa6e7SVladimir Oltean full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 685589aa6e7SVladimir Oltean info.timestamp; 686589aa6e7SVladimir Oltean else 687589aa6e7SVladimir Oltean full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 688589aa6e7SVladimir Oltean info.timestamp; 689589aa6e7SVladimir Oltean 690589aa6e7SVladimir Oltean shhwtstamps = skb_hwtstamps(skb); 691589aa6e7SVladimir Oltean memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 692589aa6e7SVladimir Oltean shhwtstamps->hwtstamp = full_ts_in_ns; 693589aa6e7SVladimir Oltean } 694589aa6e7SVladimir Oltean 695589aa6e7SVladimir Oltean /* Everything we see on an interface that is in the HW bridge 696589aa6e7SVladimir Oltean * has already been forwarded. 697589aa6e7SVladimir Oltean */ 698589aa6e7SVladimir Oltean if (ocelot->bridge_mask & BIT(info.port)) 699589aa6e7SVladimir Oltean skb->offload_fwd_mark = 1; 700589aa6e7SVladimir Oltean 701589aa6e7SVladimir Oltean skb->protocol = eth_type_trans(skb, dev); 702589aa6e7SVladimir Oltean if (!skb_defer_rx_timestamp(skb)) 703589aa6e7SVladimir Oltean netif_rx(skb); 704589aa6e7SVladimir Oltean dev->stats.rx_bytes += len; 705589aa6e7SVladimir Oltean dev->stats.rx_packets++; 706589aa6e7SVladimir Oltean } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); 707589aa6e7SVladimir Oltean 708589aa6e7SVladimir Oltean if (err) 709589aa6e7SVladimir Oltean while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 710589aa6e7SVladimir Oltean ocelot_read_rix(ocelot, QS_XTR_RD, grp); 711589aa6e7SVladimir Oltean 712589aa6e7SVladimir Oltean return IRQ_HANDLED; 713589aa6e7SVladimir Oltean } 714589aa6e7SVladimir Oltean 715589aa6e7SVladimir Oltean static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 716589aa6e7SVladimir Oltean { 717589aa6e7SVladimir Oltean struct ocelot *ocelot = arg; 718589aa6e7SVladimir Oltean 719589aa6e7SVladimir Oltean ocelot_get_txtstamp(ocelot); 720589aa6e7SVladimir Oltean 721589aa6e7SVladimir Oltean return IRQ_HANDLED; 722589aa6e7SVladimir Oltean } 723589aa6e7SVladimir Oltean 724589aa6e7SVladimir Oltean static const struct of_device_id mscc_ocelot_match[] = { 725589aa6e7SVladimir Oltean { .compatible = "mscc,vsc7514-switch" }, 726589aa6e7SVladimir Oltean { } 727589aa6e7SVladimir Oltean }; 728589aa6e7SVladimir Oltean MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 729589aa6e7SVladimir Oltean 730589aa6e7SVladimir Oltean static int ocelot_reset(struct ocelot *ocelot) 731589aa6e7SVladimir Oltean { 732589aa6e7SVladimir Oltean int retries = 100; 733589aa6e7SVladimir Oltean u32 val; 734589aa6e7SVladimir Oltean 735589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 736589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 737589aa6e7SVladimir Oltean 738589aa6e7SVladimir Oltean do { 739589aa6e7SVladimir Oltean msleep(1); 740589aa6e7SVladimir Oltean regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 741589aa6e7SVladimir Oltean &val); 742589aa6e7SVladimir Oltean } while (val && --retries); 743589aa6e7SVladimir Oltean 744589aa6e7SVladimir Oltean if (!retries) 745589aa6e7SVladimir Oltean return -ETIMEDOUT; 746589aa6e7SVladimir Oltean 747589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 748589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 749589aa6e7SVladimir Oltean 750589aa6e7SVladimir Oltean return 0; 751589aa6e7SVladimir Oltean } 752589aa6e7SVladimir Oltean 753aa92d836SMaxim Kochetkov /* Watermark encode 754aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 755aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 756aa92d836SMaxim Kochetkov */ 757aa92d836SMaxim Kochetkov static u16 ocelot_wm_enc(u16 value) 758aa92d836SMaxim Kochetkov { 75901326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8)); 76001326493SVladimir Oltean 761aa92d836SMaxim Kochetkov if (value >= BIT(8)) 762aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 763aa92d836SMaxim Kochetkov 764aa92d836SMaxim Kochetkov return value; 765aa92d836SMaxim Kochetkov } 766aa92d836SMaxim Kochetkov 767589aa6e7SVladimir Oltean static const struct ocelot_ops ocelot_ops = { 768589aa6e7SVladimir Oltean .reset = ocelot_reset, 769aa92d836SMaxim Kochetkov .wm_enc = ocelot_wm_enc, 770319e4dd1SVladimir Oltean .port_to_netdev = ocelot_port_to_netdev, 771319e4dd1SVladimir Oltean .netdev_to_port = ocelot_netdev_to_port, 772589aa6e7SVladimir Oltean }; 773589aa6e7SVladimir Oltean 774e3aea296SVladimir Oltean static const struct vcap_field vsc7514_vcap_es0_keys[] = { 775e3aea296SVladimir Oltean [VCAP_ES0_EGR_PORT] = { 0, 4}, 776e3aea296SVladimir Oltean [VCAP_ES0_IGR_PORT] = { 4, 4}, 777e3aea296SVladimir Oltean [VCAP_ES0_RSV] = { 8, 2}, 778e3aea296SVladimir Oltean [VCAP_ES0_L2_MC] = { 10, 1}, 779e3aea296SVladimir Oltean [VCAP_ES0_L2_BC] = { 11, 1}, 780e3aea296SVladimir Oltean [VCAP_ES0_VID] = { 12, 12}, 781e3aea296SVladimir Oltean [VCAP_ES0_DP] = { 24, 1}, 782e3aea296SVladimir Oltean [VCAP_ES0_PCP] = { 25, 3}, 783e3aea296SVladimir Oltean }; 784e3aea296SVladimir Oltean 785e3aea296SVladimir Oltean static const struct vcap_field vsc7514_vcap_es0_actions[] = { 786e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 787e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 788e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 789e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 790e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 791e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 792e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 793e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 794e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 795e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 796e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 797e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 798e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 799e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 800e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 801e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 802e3aea296SVladimir Oltean [VCAP_ES0_ACT_RSV] = { 49, 24}, 803e3aea296SVladimir Oltean [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 804e3aea296SVladimir Oltean }; 805e3aea296SVladimir Oltean 806a61e365dSVladimir Oltean static const struct vcap_field vsc7514_vcap_is1_keys[] = { 807a61e365dSVladimir Oltean [VCAP_IS1_HK_TYPE] = { 0, 1}, 808a61e365dSVladimir Oltean [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 809a61e365dSVladimir Oltean [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12}, 810a61e365dSVladimir Oltean [VCAP_IS1_HK_RSV] = { 15, 9}, 811a61e365dSVladimir Oltean [VCAP_IS1_HK_OAM_Y1731] = { 24, 1}, 812a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_MC] = { 25, 1}, 813a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_BC] = { 26, 1}, 814a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_MC] = { 27, 1}, 815a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1}, 816a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1}, 817a61e365dSVladimir Oltean [VCAP_IS1_HK_TPID] = { 30, 1}, 818a61e365dSVladimir Oltean [VCAP_IS1_HK_VID] = { 31, 12}, 819a61e365dSVladimir Oltean [VCAP_IS1_HK_DEI] = { 43, 1}, 820a61e365dSVladimir Oltean [VCAP_IS1_HK_PCP] = { 44, 3}, 821a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */ 822a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_SMAC] = { 47, 48}, 823a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1}, 824a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE] = { 96, 16}, 825a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_SNAP] = {112, 1}, 826a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4] = {113, 1}, 827a61e365dSVladimir Oltean /* Layer-3 Information */ 828a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAGMENT] = {114, 1}, 829a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {115, 1}, 830a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_OPTIONS] = {116, 1}, 831a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_DSCP] = {117, 6}, 832a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_IP4_SIP] = {123, 32}, 833a61e365dSVladimir Oltean /* Layer-4 Information */ 834a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP_UDP] = {155, 1}, 835a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP] = {156, 1}, 836a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_SPORT] = {157, 16}, 837a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_RNG] = {173, 8}, 838a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 839a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1}, 840a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12}, 841a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1}, 842a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3}, 843a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP4] = { 64, 1}, 844a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1}, 845a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1}, 846a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1}, 847a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6}, 848a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32}, 849a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {106, 32}, 850a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_PROTO] = {138, 8}, 851a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP_UDP] = {146, 1}, 852a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP] = {147, 1}, 853a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L4_RNG] = {148, 8}, 854a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {156, 32}, 855a61e365dSVladimir Oltean }; 856a61e365dSVladimir Oltean 857a61e365dSVladimir Oltean static const struct vcap_field vsc7514_vcap_is1_actions[] = { 858a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 859a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 860a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 861a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 862a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 863a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 864a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 865a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 866a61e365dSVladimir Oltean [VCAP_IS1_ACT_RSV] = { 29, 9}, 867a61e365dSVladimir Oltean /* The fields below are incorrectly shifted by 2 in the manual */ 868a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 869a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 870a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 871a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 872a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 873a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 874a61e365dSVladimir Oltean [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 875a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 876a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 877a61e365dSVladimir Oltean [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 878a61e365dSVladimir Oltean [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 879a61e365dSVladimir Oltean }; 880a61e365dSVladimir Oltean 881589aa6e7SVladimir Oltean static const struct vcap_field vsc7514_vcap_is2_keys[] = { 882589aa6e7SVladimir Oltean /* Common: 46 bits */ 883589aa6e7SVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 884589aa6e7SVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 885589aa6e7SVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 886589aa6e7SVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 887589aa6e7SVladimir Oltean [VCAP_IS2_HK_RSV2] = { 25, 1}, 888589aa6e7SVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 889589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 27, 1}, 890589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 28, 1}, 891589aa6e7SVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 892589aa6e7SVladimir Oltean [VCAP_IS2_HK_VID] = { 30, 12}, 893589aa6e7SVladimir Oltean [VCAP_IS2_HK_DEI] = { 42, 1}, 894589aa6e7SVladimir Oltean [VCAP_IS2_HK_PCP] = { 43, 3}, 895589aa6e7SVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 896589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 897589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 898589aa6e7SVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 899589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 900589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 901589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 902589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 903589aa6e7SVladimir Oltean /* MAC_LLC (TYPE=001) */ 904589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 905589aa6e7SVladimir Oltean /* MAC_SNAP (TYPE=010) */ 906589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 907589aa6e7SVladimir Oltean /* MAC_ARP (TYPE=011) */ 908589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 909589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 910589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 911589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 912589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 913589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 914589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 915589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 916589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 917589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 918589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 919589aa6e7SVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 920589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4] = { 46, 1}, 921589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 922589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 923589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 924589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 925589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 926589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 927589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 928589aa6e7SVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 929589aa6e7SVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 930589aa6e7SVladimir Oltean [VCAP_IS2_HK_TCP] = {124, 1}, 9318194d8faSVladimir Oltean [VCAP_IS2_HK_L4_DPORT] = {125, 16}, 9328194d8faSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {141, 16}, 933589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {157, 8}, 934589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 935589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 9368194d8faSVladimir Oltean [VCAP_IS2_HK_L4_FIN] = {167, 1}, 9378194d8faSVladimir Oltean [VCAP_IS2_HK_L4_SYN] = {168, 1}, 9388194d8faSVladimir Oltean [VCAP_IS2_HK_L4_RST] = {169, 1}, 9398194d8faSVladimir Oltean [VCAP_IS2_HK_L4_PSH] = {170, 1}, 9408194d8faSVladimir Oltean [VCAP_IS2_HK_L4_ACK] = {171, 1}, 9418194d8faSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {172, 1}, 942589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 943589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 944589aa6e7SVladimir Oltean /* IP4_OTHER (TYPE=101) */ 945589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 946589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 947589aa6e7SVladimir Oltean /* IP6_STD (TYPE=110) */ 948589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 949589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 950589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 951589aa6e7SVladimir Oltean /* OAM (TYPE=111) */ 952589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 953589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {149, 5}, 954589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 955589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 956589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 957589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 958589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 959589aa6e7SVladimir Oltean }; 960589aa6e7SVladimir Oltean 961589aa6e7SVladimir Oltean static const struct vcap_field vsc7514_vcap_is2_actions[] = { 962589aa6e7SVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 963589aa6e7SVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 964589aa6e7SVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 965589aa6e7SVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 966589aa6e7SVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 967589aa6e7SVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 968589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 969589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 970589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 971589aa6e7SVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 972589aa6e7SVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 973589aa6e7SVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 974589aa6e7SVladimir Oltean [VCAP_IS2_ACT_RSV] = { 41, 2}, 975589aa6e7SVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 976589aa6e7SVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 977589aa6e7SVladimir Oltean }; 978589aa6e7SVladimir Oltean 97920968054SVladimir Oltean static struct vcap_props vsc7514_vcap_props[] = { 980e3aea296SVladimir Oltean [VCAP_ES0] = { 981e3aea296SVladimir Oltean .action_type_width = 0, 982e3aea296SVladimir Oltean .action_table = { 983e3aea296SVladimir Oltean [ES0_ACTION_TYPE_NORMAL] = { 984e3aea296SVladimir Oltean .width = 73, /* HIT_STICKY not included */ 985e3aea296SVladimir Oltean .count = 1, 986e3aea296SVladimir Oltean }, 987e3aea296SVladimir Oltean }, 988e3aea296SVladimir Oltean .target = S0, 989e3aea296SVladimir Oltean .keys = vsc7514_vcap_es0_keys, 990e3aea296SVladimir Oltean .actions = vsc7514_vcap_es0_actions, 991e3aea296SVladimir Oltean }, 992a61e365dSVladimir Oltean [VCAP_IS1] = { 993a61e365dSVladimir Oltean .action_type_width = 0, 994a61e365dSVladimir Oltean .action_table = { 995a61e365dSVladimir Oltean [IS1_ACTION_TYPE_NORMAL] = { 996a61e365dSVladimir Oltean .width = 78, /* HIT_STICKY not included */ 997a61e365dSVladimir Oltean .count = 4, 998a61e365dSVladimir Oltean }, 999a61e365dSVladimir Oltean }, 1000a61e365dSVladimir Oltean .target = S1, 1001a61e365dSVladimir Oltean .keys = vsc7514_vcap_is1_keys, 1002a61e365dSVladimir Oltean .actions = vsc7514_vcap_is1_actions, 1003a61e365dSVladimir Oltean }, 1004589aa6e7SVladimir Oltean [VCAP_IS2] = { 1005589aa6e7SVladimir Oltean .action_type_width = 1, 1006589aa6e7SVladimir Oltean .action_table = { 1007589aa6e7SVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 1008589aa6e7SVladimir Oltean .width = 49, 1009589aa6e7SVladimir Oltean .count = 2 1010589aa6e7SVladimir Oltean }, 1011589aa6e7SVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 1012589aa6e7SVladimir Oltean .width = 6, 1013589aa6e7SVladimir Oltean .count = 4 1014589aa6e7SVladimir Oltean }, 1015589aa6e7SVladimir Oltean }, 1016c1c3993eSVladimir Oltean .target = S2, 1017c1c3993eSVladimir Oltean .keys = vsc7514_vcap_is2_keys, 1018c1c3993eSVladimir Oltean .actions = vsc7514_vcap_is2_actions, 1019589aa6e7SVladimir Oltean }, 1020589aa6e7SVladimir Oltean }; 1021589aa6e7SVladimir Oltean 1022589aa6e7SVladimir Oltean static struct ptp_clock_info ocelot_ptp_clock_info = { 1023589aa6e7SVladimir Oltean .owner = THIS_MODULE, 1024589aa6e7SVladimir Oltean .name = "ocelot ptp", 1025589aa6e7SVladimir Oltean .max_adj = 0x7fffffff, 1026589aa6e7SVladimir Oltean .n_alarm = 0, 1027589aa6e7SVladimir Oltean .n_ext_ts = 0, 1028589aa6e7SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM, 1029589aa6e7SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM, 1030589aa6e7SVladimir Oltean .pps = 0, 1031589aa6e7SVladimir Oltean .gettime64 = ocelot_ptp_gettime64, 1032589aa6e7SVladimir Oltean .settime64 = ocelot_ptp_settime64, 1033589aa6e7SVladimir Oltean .adjtime = ocelot_ptp_adjtime, 1034589aa6e7SVladimir Oltean .adjfine = ocelot_ptp_adjfine, 1035589aa6e7SVladimir Oltean .verify = ocelot_ptp_verify, 1036589aa6e7SVladimir Oltean .enable = ocelot_ptp_enable, 1037589aa6e7SVladimir Oltean }; 1038589aa6e7SVladimir Oltean 103922cdb493SVladimir Oltean static void mscc_ocelot_release_ports(struct ocelot *ocelot) 104022cdb493SVladimir Oltean { 104122cdb493SVladimir Oltean int port; 104222cdb493SVladimir Oltean 104322cdb493SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 104422cdb493SVladimir Oltean struct ocelot_port_private *priv; 104522cdb493SVladimir Oltean struct ocelot_port *ocelot_port; 104622cdb493SVladimir Oltean 104722cdb493SVladimir Oltean ocelot_port = ocelot->ports[port]; 104822cdb493SVladimir Oltean if (!ocelot_port) 104922cdb493SVladimir Oltean continue; 105022cdb493SVladimir Oltean 1051e5fb512dSVladimir Oltean ocelot_deinit_port(ocelot, port); 1052e5fb512dSVladimir Oltean 105322cdb493SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 105422cdb493SVladimir Oltean port); 105522cdb493SVladimir Oltean 105622cdb493SVladimir Oltean unregister_netdev(priv->dev); 105722cdb493SVladimir Oltean free_netdev(priv->dev); 105822cdb493SVladimir Oltean } 105922cdb493SVladimir Oltean } 106022cdb493SVladimir Oltean 10617c411799SVladimir Oltean static int mscc_ocelot_init_ports(struct platform_device *pdev, 10627c411799SVladimir Oltean struct device_node *ports) 10637c411799SVladimir Oltean { 10647c411799SVladimir Oltean struct ocelot *ocelot = platform_get_drvdata(pdev); 10657c411799SVladimir Oltean struct device_node *portnp; 10667c411799SVladimir Oltean int err; 10677c411799SVladimir Oltean 10687c411799SVladimir Oltean ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 10697c411799SVladimir Oltean sizeof(struct ocelot_port *), GFP_KERNEL); 10707c411799SVladimir Oltean if (!ocelot->ports) 10717c411799SVladimir Oltean return -ENOMEM; 10727c411799SVladimir Oltean 10737c411799SVladimir Oltean for_each_available_child_of_node(ports, portnp) { 10747c411799SVladimir Oltean struct ocelot_port_private *priv; 10757c411799SVladimir Oltean struct ocelot_port *ocelot_port; 10767c411799SVladimir Oltean struct device_node *phy_node; 10777c411799SVladimir Oltean phy_interface_t phy_mode; 10787c411799SVladimir Oltean struct phy_device *phy; 10797c411799SVladimir Oltean struct regmap *target; 10807c411799SVladimir Oltean struct resource *res; 10817c411799SVladimir Oltean struct phy *serdes; 10827c411799SVladimir Oltean char res_name[8]; 10837c411799SVladimir Oltean u32 port; 10847c411799SVladimir Oltean 10857c411799SVladimir Oltean if (of_property_read_u32(portnp, "reg", &port)) 10867c411799SVladimir Oltean continue; 10877c411799SVladimir Oltean 10887c411799SVladimir Oltean snprintf(res_name, sizeof(res_name), "port%d", port); 10897c411799SVladimir Oltean 10907c411799SVladimir Oltean res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 10917c411799SVladimir Oltean res_name); 10927c411799SVladimir Oltean target = ocelot_regmap_init(ocelot, res); 10937c411799SVladimir Oltean if (IS_ERR(target)) 10947c411799SVladimir Oltean continue; 10957c411799SVladimir Oltean 10967c411799SVladimir Oltean phy_node = of_parse_phandle(portnp, "phy-handle", 0); 10977c411799SVladimir Oltean if (!phy_node) 10987c411799SVladimir Oltean continue; 10997c411799SVladimir Oltean 11007c411799SVladimir Oltean phy = of_phy_find_device(phy_node); 11017c411799SVladimir Oltean of_node_put(phy_node); 11027c411799SVladimir Oltean if (!phy) 11037c411799SVladimir Oltean continue; 11047c411799SVladimir Oltean 11057c411799SVladimir Oltean err = ocelot_probe_port(ocelot, port, target, phy); 11067c411799SVladimir Oltean if (err) { 11077c411799SVladimir Oltean of_node_put(portnp); 11087c411799SVladimir Oltean return err; 11097c411799SVladimir Oltean } 11107c411799SVladimir Oltean 11117c411799SVladimir Oltean ocelot_port = ocelot->ports[port]; 11127c411799SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 11137c411799SVladimir Oltean port); 11147c411799SVladimir Oltean 11157c411799SVladimir Oltean of_get_phy_mode(portnp, &phy_mode); 11167c411799SVladimir Oltean 11177c411799SVladimir Oltean ocelot_port->phy_mode = phy_mode; 11187c411799SVladimir Oltean 11197c411799SVladimir Oltean switch (ocelot_port->phy_mode) { 11207c411799SVladimir Oltean case PHY_INTERFACE_MODE_NA: 11217c411799SVladimir Oltean continue; 11227c411799SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 11237c411799SVladimir Oltean break; 11247c411799SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 11257c411799SVladimir Oltean /* Ensure clock signals and speed is set on all 11267c411799SVladimir Oltean * QSGMII links 11277c411799SVladimir Oltean */ 11287c411799SVladimir Oltean ocelot_port_writel(ocelot_port, 11297c411799SVladimir Oltean DEV_CLOCK_CFG_LINK_SPEED 11307c411799SVladimir Oltean (OCELOT_SPEED_1000), 11317c411799SVladimir Oltean DEV_CLOCK_CFG); 11327c411799SVladimir Oltean break; 11337c411799SVladimir Oltean default: 11347c411799SVladimir Oltean dev_err(ocelot->dev, 11357c411799SVladimir Oltean "invalid phy mode for port%d, (Q)SGMII only\n", 11367c411799SVladimir Oltean port); 11377c411799SVladimir Oltean of_node_put(portnp); 11387c411799SVladimir Oltean return -EINVAL; 11397c411799SVladimir Oltean } 11407c411799SVladimir Oltean 11417c411799SVladimir Oltean serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); 11427c411799SVladimir Oltean if (IS_ERR(serdes)) { 11437c411799SVladimir Oltean err = PTR_ERR(serdes); 11447c411799SVladimir Oltean if (err == -EPROBE_DEFER) 11457c411799SVladimir Oltean dev_dbg(ocelot->dev, "deferring probe\n"); 11467c411799SVladimir Oltean else 11477c411799SVladimir Oltean dev_err(ocelot->dev, 11487c411799SVladimir Oltean "missing SerDes phys for port%d\n", 11497c411799SVladimir Oltean port); 11507c411799SVladimir Oltean 11517c411799SVladimir Oltean of_node_put(portnp); 11527c411799SVladimir Oltean return err; 11537c411799SVladimir Oltean } 11547c411799SVladimir Oltean 11557c411799SVladimir Oltean priv->serdes = serdes; 11567c411799SVladimir Oltean } 11577c411799SVladimir Oltean 11587c411799SVladimir Oltean return 0; 11597c411799SVladimir Oltean } 11607c411799SVladimir Oltean 1161589aa6e7SVladimir Oltean static int mscc_ocelot_probe(struct platform_device *pdev) 1162589aa6e7SVladimir Oltean { 1163589aa6e7SVladimir Oltean struct device_node *np = pdev->dev.of_node; 1164589aa6e7SVladimir Oltean int err, irq_xtr, irq_ptp_rdy; 11657c411799SVladimir Oltean struct device_node *ports; 1166589aa6e7SVladimir Oltean struct ocelot *ocelot; 1167589aa6e7SVladimir Oltean struct regmap *hsio; 1168589aa6e7SVladimir Oltean unsigned int i; 1169589aa6e7SVladimir Oltean 1170589aa6e7SVladimir Oltean struct { 1171589aa6e7SVladimir Oltean enum ocelot_target id; 1172589aa6e7SVladimir Oltean char *name; 1173589aa6e7SVladimir Oltean u8 optional:1; 1174589aa6e7SVladimir Oltean } io_target[] = { 1175589aa6e7SVladimir Oltean { SYS, "sys" }, 1176589aa6e7SVladimir Oltean { REW, "rew" }, 1177589aa6e7SVladimir Oltean { QSYS, "qsys" }, 1178589aa6e7SVladimir Oltean { ANA, "ana" }, 1179589aa6e7SVladimir Oltean { QS, "qs" }, 1180e3aea296SVladimir Oltean { S0, "s0" }, 1181a61e365dSVladimir Oltean { S1, "s1" }, 1182589aa6e7SVladimir Oltean { S2, "s2" }, 1183589aa6e7SVladimir Oltean { PTP, "ptp", 1 }, 1184589aa6e7SVladimir Oltean }; 1185589aa6e7SVladimir Oltean 1186589aa6e7SVladimir Oltean if (!np && !pdev->dev.platform_data) 1187589aa6e7SVladimir Oltean return -ENODEV; 1188589aa6e7SVladimir Oltean 1189589aa6e7SVladimir Oltean ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL); 1190589aa6e7SVladimir Oltean if (!ocelot) 1191589aa6e7SVladimir Oltean return -ENOMEM; 1192589aa6e7SVladimir Oltean 1193589aa6e7SVladimir Oltean platform_set_drvdata(pdev, ocelot); 1194589aa6e7SVladimir Oltean ocelot->dev = &pdev->dev; 1195589aa6e7SVladimir Oltean 1196589aa6e7SVladimir Oltean for (i = 0; i < ARRAY_SIZE(io_target); i++) { 1197589aa6e7SVladimir Oltean struct regmap *target; 1198589aa6e7SVladimir Oltean struct resource *res; 1199589aa6e7SVladimir Oltean 1200589aa6e7SVladimir Oltean res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1201589aa6e7SVladimir Oltean io_target[i].name); 1202589aa6e7SVladimir Oltean 1203589aa6e7SVladimir Oltean target = ocelot_regmap_init(ocelot, res); 1204589aa6e7SVladimir Oltean if (IS_ERR(target)) { 1205589aa6e7SVladimir Oltean if (io_target[i].optional) { 1206589aa6e7SVladimir Oltean ocelot->targets[io_target[i].id] = NULL; 1207589aa6e7SVladimir Oltean continue; 1208589aa6e7SVladimir Oltean } 1209589aa6e7SVladimir Oltean return PTR_ERR(target); 1210589aa6e7SVladimir Oltean } 1211589aa6e7SVladimir Oltean 1212589aa6e7SVladimir Oltean ocelot->targets[io_target[i].id] = target; 1213589aa6e7SVladimir Oltean } 1214589aa6e7SVladimir Oltean 1215589aa6e7SVladimir Oltean hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 1216589aa6e7SVladimir Oltean if (IS_ERR(hsio)) { 1217589aa6e7SVladimir Oltean dev_err(&pdev->dev, "missing hsio syscon\n"); 1218589aa6e7SVladimir Oltean return PTR_ERR(hsio); 1219589aa6e7SVladimir Oltean } 1220589aa6e7SVladimir Oltean 1221589aa6e7SVladimir Oltean ocelot->targets[HSIO] = hsio; 1222589aa6e7SVladimir Oltean 1223589aa6e7SVladimir Oltean err = ocelot_chip_init(ocelot, &ocelot_ops); 1224589aa6e7SVladimir Oltean if (err) 1225589aa6e7SVladimir Oltean return err; 1226589aa6e7SVladimir Oltean 1227589aa6e7SVladimir Oltean irq_xtr = platform_get_irq_byname(pdev, "xtr"); 1228589aa6e7SVladimir Oltean if (irq_xtr < 0) 1229589aa6e7SVladimir Oltean return -ENODEV; 1230589aa6e7SVladimir Oltean 1231589aa6e7SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 1232589aa6e7SVladimir Oltean ocelot_xtr_irq_handler, IRQF_ONESHOT, 1233589aa6e7SVladimir Oltean "frame extraction", ocelot); 1234589aa6e7SVladimir Oltean if (err) 1235589aa6e7SVladimir Oltean return err; 1236589aa6e7SVladimir Oltean 1237589aa6e7SVladimir Oltean irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 1238589aa6e7SVladimir Oltean if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 1239589aa6e7SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 1240589aa6e7SVladimir Oltean ocelot_ptp_rdy_irq_handler, 1241589aa6e7SVladimir Oltean IRQF_ONESHOT, "ptp ready", 1242589aa6e7SVladimir Oltean ocelot); 1243589aa6e7SVladimir Oltean if (err) 1244589aa6e7SVladimir Oltean return err; 1245589aa6e7SVladimir Oltean 1246589aa6e7SVladimir Oltean /* Both the PTP interrupt and the PTP bank are available */ 1247589aa6e7SVladimir Oltean ocelot->ptp = 1; 1248589aa6e7SVladimir Oltean } 1249589aa6e7SVladimir Oltean 1250589aa6e7SVladimir Oltean ports = of_get_child_by_name(np, "ethernet-ports"); 1251589aa6e7SVladimir Oltean if (!ports) { 12527c411799SVladimir Oltean dev_err(ocelot->dev, "no ethernet-ports child node found\n"); 1253589aa6e7SVladimir Oltean return -ENODEV; 1254589aa6e7SVladimir Oltean } 1255589aa6e7SVladimir Oltean 1256589aa6e7SVladimir Oltean ocelot->num_phys_ports = of_get_child_count(ports); 1257edd2410bSVladimir Oltean ocelot->num_flooding_pgids = 1; 1258589aa6e7SVladimir Oltean 1259589aa6e7SVladimir Oltean ocelot->vcap = vsc7514_vcap_props; 12602d44b097SVladimir Oltean ocelot->inj_prefix = OCELOT_TAG_PREFIX_NONE; 12612d44b097SVladimir Oltean ocelot->xtr_prefix = OCELOT_TAG_PREFIX_NONE; 12622d44b097SVladimir Oltean ocelot->npi = -1; 1263589aa6e7SVladimir Oltean 1264d1cc0e93SVladimir Oltean err = ocelot_init(ocelot); 1265d1cc0e93SVladimir Oltean if (err) 1266d1cc0e93SVladimir Oltean goto out_put_ports; 1267d1cc0e93SVladimir Oltean 12687c411799SVladimir Oltean err = mscc_ocelot_init_ports(pdev, ports); 12697c411799SVladimir Oltean if (err) 1270*f87675b8SChristophe JAILLET goto out_ocelot_deinit; 12717c411799SVladimir Oltean 1272589aa6e7SVladimir Oltean if (ocelot->ptp) { 1273589aa6e7SVladimir Oltean err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1274589aa6e7SVladimir Oltean if (err) { 1275589aa6e7SVladimir Oltean dev_err(ocelot->dev, 1276589aa6e7SVladimir Oltean "Timestamp initialization failed\n"); 1277589aa6e7SVladimir Oltean ocelot->ptp = 0; 1278589aa6e7SVladimir Oltean } 1279589aa6e7SVladimir Oltean } 1280589aa6e7SVladimir Oltean 1281589aa6e7SVladimir Oltean register_netdevice_notifier(&ocelot_netdevice_nb); 1282589aa6e7SVladimir Oltean register_switchdev_notifier(&ocelot_switchdev_nb); 1283589aa6e7SVladimir Oltean register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1284589aa6e7SVladimir Oltean 1285*f87675b8SChristophe JAILLET of_node_put(ports); 1286*f87675b8SChristophe JAILLET 1287589aa6e7SVladimir Oltean dev_info(&pdev->dev, "Ocelot switch probed\n"); 1288589aa6e7SVladimir Oltean 1289*f87675b8SChristophe JAILLET return 0; 1290*f87675b8SChristophe JAILLET 1291*f87675b8SChristophe JAILLET out_ocelot_deinit: 1292*f87675b8SChristophe JAILLET ocelot_deinit(ocelot); 1293589aa6e7SVladimir Oltean out_put_ports: 1294589aa6e7SVladimir Oltean of_node_put(ports); 1295589aa6e7SVladimir Oltean return err; 1296589aa6e7SVladimir Oltean } 1297589aa6e7SVladimir Oltean 1298589aa6e7SVladimir Oltean static int mscc_ocelot_remove(struct platform_device *pdev) 1299589aa6e7SVladimir Oltean { 1300589aa6e7SVladimir Oltean struct ocelot *ocelot = platform_get_drvdata(pdev); 1301589aa6e7SVladimir Oltean 1302589aa6e7SVladimir Oltean ocelot_deinit_timestamp(ocelot); 130322cdb493SVladimir Oltean mscc_ocelot_release_ports(ocelot); 1304589aa6e7SVladimir Oltean ocelot_deinit(ocelot); 1305589aa6e7SVladimir Oltean unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1306589aa6e7SVladimir Oltean unregister_switchdev_notifier(&ocelot_switchdev_nb); 1307589aa6e7SVladimir Oltean unregister_netdevice_notifier(&ocelot_netdevice_nb); 1308589aa6e7SVladimir Oltean 1309589aa6e7SVladimir Oltean return 0; 1310589aa6e7SVladimir Oltean } 1311589aa6e7SVladimir Oltean 1312589aa6e7SVladimir Oltean static struct platform_driver mscc_ocelot_driver = { 1313589aa6e7SVladimir Oltean .probe = mscc_ocelot_probe, 1314589aa6e7SVladimir Oltean .remove = mscc_ocelot_remove, 1315589aa6e7SVladimir Oltean .driver = { 1316589aa6e7SVladimir Oltean .name = "ocelot-switch", 1317589aa6e7SVladimir Oltean .of_match_table = mscc_ocelot_match, 1318589aa6e7SVladimir Oltean }, 1319589aa6e7SVladimir Oltean }; 1320589aa6e7SVladimir Oltean 1321589aa6e7SVladimir Oltean module_platform_driver(mscc_ocelot_driver); 1322589aa6e7SVladimir Oltean 1323589aa6e7SVladimir Oltean MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1324589aa6e7SVladimir Oltean MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1325589aa6e7SVladimir Oltean MODULE_LICENSE("Dual MIT/GPL"); 1326