1589aa6e7SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2589aa6e7SVladimir Oltean /* 3589aa6e7SVladimir Oltean * Microsemi Ocelot Switch driver 4589aa6e7SVladimir Oltean * 5589aa6e7SVladimir Oltean * Copyright (c) 2017 Microsemi Corporation 6589aa6e7SVladimir Oltean */ 7589aa6e7SVladimir Oltean #include <linux/interrupt.h> 8589aa6e7SVladimir Oltean #include <linux/module.h> 9589aa6e7SVladimir Oltean #include <linux/of_net.h> 10589aa6e7SVladimir Oltean #include <linux/netdevice.h> 11589aa6e7SVladimir Oltean #include <linux/of_mdio.h> 12589aa6e7SVladimir Oltean #include <linux/of_platform.h> 13589aa6e7SVladimir Oltean #include <linux/mfd/syscon.h> 14589aa6e7SVladimir Oltean #include <linux/skbuff.h> 15589aa6e7SVladimir Oltean #include <net/switchdev.h> 16589aa6e7SVladimir Oltean 17589aa6e7SVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 18d9feb904SVladimir Oltean #include <soc/mscc/ocelot_hsio.h> 19589aa6e7SVladimir Oltean #include "ocelot.h" 20589aa6e7SVladimir Oltean 21589aa6e7SVladimir Oltean #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0)) 22589aa6e7SVladimir Oltean #define VSC7514_VCAP_IS2_CNT 64 23589aa6e7SVladimir Oltean #define VSC7514_VCAP_IS2_ENTRY_WIDTH 376 24589aa6e7SVladimir Oltean #define VSC7514_VCAP_IS2_ACTION_WIDTH 99 25589aa6e7SVladimir Oltean #define VSC7514_VCAP_PORT_CNT 11 26589aa6e7SVladimir Oltean 27d9feb904SVladimir Oltean static const u32 ocelot_ana_regmap[] = { 28d9feb904SVladimir Oltean REG(ANA_ADVLEARN, 0x009000), 29d9feb904SVladimir Oltean REG(ANA_VLANMASK, 0x009004), 30d9feb904SVladimir Oltean REG(ANA_PORT_B_DOMAIN, 0x009008), 31d9feb904SVladimir Oltean REG(ANA_ANAGEFIL, 0x00900c), 32d9feb904SVladimir Oltean REG(ANA_ANEVENTS, 0x009010), 33d9feb904SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x009014), 34d9feb904SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x009018), 35d9feb904SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x009028), 36d9feb904SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x00902c), 37d9feb904SVladimir Oltean REG(ANA_AUTOAGE, 0x009030), 38d9feb904SVladimir Oltean REG(ANA_MACTOPTIONS, 0x009034), 39d9feb904SVladimir Oltean REG(ANA_LEARNDISC, 0x009038), 40d9feb904SVladimir Oltean REG(ANA_AGENCTRL, 0x00903c), 41d9feb904SVladimir Oltean REG(ANA_MIRRORPORTS, 0x009040), 42d9feb904SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x009044), 43d9feb904SVladimir Oltean REG(ANA_FLOODING, 0x009048), 44d9feb904SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x00904c), 45d9feb904SVladimir Oltean REG(ANA_SFLOW_CFG, 0x009050), 46d9feb904SVladimir Oltean REG(ANA_PORT_MODE, 0x009080), 47d9feb904SVladimir Oltean REG(ANA_PGID_PGID, 0x008c00), 48d9feb904SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x008b30), 49d9feb904SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x008b34), 50d9feb904SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x008b38), 51d9feb904SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x008b3c), 52d9feb904SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x008b40), 53d9feb904SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x008b44), 54d9feb904SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x008b48), 55d9feb904SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 56d9feb904SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x008b50), 57d9feb904SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x008b00), 58d9feb904SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 59d9feb904SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 60d9feb904SVladimir Oltean REG(ANA_MSTI_STATE, 0x008e00), 61d9feb904SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007000), 62d9feb904SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007004), 63d9feb904SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007008), 64d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00700c), 65d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 66d9feb904SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 67d9feb904SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 68d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 69d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 70d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 71d9feb904SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 72d9feb904SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007070), 73d9feb904SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007074), 74d9feb904SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007078), 75d9feb904SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 76d9feb904SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 77d9feb904SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 78d9feb904SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 79d9feb904SVladimir Oltean REG(ANA_PFC_PFC_TIMER, 0x008804), 80d9feb904SVladimir Oltean REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 81d9feb904SVladimir Oltean REG(ANA_IPT_IPT, 0x008004), 82d9feb904SVladimir Oltean REG(ANA_PPT_PPT, 0x008ac0), 83d9feb904SVladimir Oltean REG(ANA_FID_MAP_FID_MAP, 0x000000), 84d9feb904SVladimir Oltean REG(ANA_AGGR_CFG, 0x0090b4), 85d9feb904SVladimir Oltean REG(ANA_CPUQ_CFG, 0x0090b8), 86d9feb904SVladimir Oltean REG(ANA_CPUQ_CFG2, 0x0090bc), 87d9feb904SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x0090c0), 88d9feb904SVladimir Oltean REG(ANA_DSCP_CFG, 0x009100), 89d9feb904SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x009200), 90d9feb904SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 91d9feb904SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 92d9feb904SVladimir Oltean REG(ANA_VRAP_CFG, 0x009280), 93d9feb904SVladimir Oltean REG(ANA_VRAP_HDR_DATA, 0x009284), 94d9feb904SVladimir Oltean REG(ANA_VRAP_HDR_MASK, 0x009288), 95d9feb904SVladimir Oltean REG(ANA_DISCARD_CFG, 0x00928c), 96d9feb904SVladimir Oltean REG(ANA_FID_CFG, 0x009290), 97d9feb904SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 98d9feb904SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 99d9feb904SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 100d9feb904SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 101d9feb904SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 102d9feb904SVladimir Oltean REG(ANA_POL_STATE, 0x004014), 103d9feb904SVladimir Oltean REG(ANA_POL_FLOWC, 0x008b80), 104d9feb904SVladimir Oltean REG(ANA_POL_HYST, 0x008bec), 105d9feb904SVladimir Oltean REG(ANA_POL_MISC_CFG, 0x008bf0), 106d9feb904SVladimir Oltean }; 107d9feb904SVladimir Oltean 108d9feb904SVladimir Oltean static const u32 ocelot_qs_regmap[] = { 109d9feb904SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 110d9feb904SVladimir Oltean REG(QS_XTR_RD, 0x000008), 111d9feb904SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 112d9feb904SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 113d9feb904SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 114d9feb904SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 115d9feb904SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 116d9feb904SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 117d9feb904SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 118d9feb904SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 119d9feb904SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 120d9feb904SVladimir Oltean REG(QS_INH_DBG, 0x000048), 121d9feb904SVladimir Oltean }; 122d9feb904SVladimir Oltean 123d9feb904SVladimir Oltean static const u32 ocelot_qsys_regmap[] = { 124d9feb904SVladimir Oltean REG(QSYS_PORT_MODE, 0x011200), 125d9feb904SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x011234), 126d9feb904SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x011264), 127d9feb904SVladimir Oltean REG(QSYS_EEE_CFG, 0x011268), 128d9feb904SVladimir Oltean REG(QSYS_EEE_THRES, 0x011294), 129d9feb904SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x011298), 130d9feb904SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x01129c), 131d9feb904SVladimir Oltean REG(QSYS_SW_STATUS, 0x0112a0), 132d9feb904SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x0112d0), 133d9feb904SVladimir Oltean REG(QSYS_PAD_CFG, 0x0112d4), 134d9feb904SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 135d9feb904SVladimir Oltean REG(QSYS_QMAP, 0x0112dc), 136d9feb904SVladimir Oltean REG(QSYS_ISDX_SGRP, 0x011400), 137d9feb904SVladimir Oltean REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 138d9feb904SVladimir Oltean REG(QSYS_TFRM_MISC, 0x011310), 139d9feb904SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x011314), 140d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 141d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 142d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 143d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 144d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 145d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 146d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 147d9feb904SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 148d9feb904SVladimir Oltean REG(QSYS_RED_PROFILE, 0x011338), 149d9feb904SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x011378), 150d9feb904SVladimir Oltean REG(QSYS_RES_CFG, 0x012000), 151d9feb904SVladimir Oltean REG(QSYS_RES_STAT, 0x012004), 152d9feb904SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x01137c), 153d9feb904SVladimir Oltean REG(QSYS_EQ_CTRL, 0x011380), 154d9feb904SVladimir Oltean REG(QSYS_EVENTS_CORE, 0x011384), 155d9feb904SVladimir Oltean REG(QSYS_CIR_CFG, 0x000000), 156d9feb904SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 157d9feb904SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 158d9feb904SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 159d9feb904SVladimir Oltean REG(QSYS_SE_CONNECT, 0x00003c), 160d9feb904SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 161d9feb904SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 162d9feb904SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 163d9feb904SVladimir Oltean REG(QSYS_SE_STATE, 0x00004c), 164d9feb904SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x011388), 165d9feb904SVladimir Oltean }; 166d9feb904SVladimir Oltean 167d9feb904SVladimir Oltean static const u32 ocelot_rew_regmap[] = { 168d9feb904SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 169d9feb904SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 170d9feb904SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 171d9feb904SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 172d9feb904SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 173d9feb904SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 174d9feb904SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 175d9feb904SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 176d9feb904SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000790), 177d9feb904SVladimir Oltean REG(REW_STAT_CFG, 0x000890), 178d9feb904SVladimir Oltean REG(REW_PPT, 0x000680), 179d9feb904SVladimir Oltean }; 180d9feb904SVladimir Oltean 181d9feb904SVladimir Oltean static const u32 ocelot_sys_regmap[] = { 182d9feb904SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 183d9feb904SVladimir Oltean REG(SYS_COUNT_RX_UNICAST, 0x000004), 184d9feb904SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 185d9feb904SVladimir Oltean REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 186d9feb904SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 187d9feb904SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 188d9feb904SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 189d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 190d9feb904SVladimir Oltean REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 191d9feb904SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 192d9feb904SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 193d9feb904SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 194d9feb904SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 195d9feb904SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 196d9feb904SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 197d9feb904SVladimir Oltean REG(SYS_COUNT_RX_PAUSE, 0x00003c), 198d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CONTROL, 0x000040), 199d9feb904SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 200d9feb904SVladimir Oltean REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 201d9feb904SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000100), 202d9feb904SVladimir Oltean REG(SYS_COUNT_TX_UNICAST, 0x000104), 203d9feb904SVladimir Oltean REG(SYS_COUNT_TX_MULTICAST, 0x000108), 204d9feb904SVladimir Oltean REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 205d9feb904SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000110), 206d9feb904SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000114), 207d9feb904SVladimir Oltean REG(SYS_COUNT_TX_PAUSE, 0x000118), 208d9feb904SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00011c), 209d9feb904SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000120), 210d9feb904SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000124), 211d9feb904SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000128), 212d9feb904SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00012c), 213d9feb904SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000130), 214d9feb904SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000170), 215d9feb904SVladimir Oltean REG(SYS_RESET_CFG, 0x000508), 216d9feb904SVladimir Oltean REG(SYS_CMID, 0x00050c), 217d9feb904SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000510), 218d9feb904SVladimir Oltean REG(SYS_PORT_MODE, 0x000514), 219d9feb904SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000548), 220d9feb904SVladimir Oltean REG(SYS_FRM_AGING, 0x000574), 221d9feb904SVladimir Oltean REG(SYS_STAT_CFG, 0x000578), 222d9feb904SVladimir Oltean REG(SYS_SW_STATUS, 0x00057c), 223d9feb904SVladimir Oltean REG(SYS_MISC_CFG, 0x0005ac), 224d9feb904SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 225d9feb904SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 226d9feb904SVladimir Oltean REG(SYS_CM_ADDR, 0x000500), 227d9feb904SVladimir Oltean REG(SYS_CM_DATA, 0x000504), 228d9feb904SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000608), 229d9feb904SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000638), 230d9feb904SVladimir Oltean REG(SYS_ATOP, 0x00063c), 231d9feb904SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x00066c), 232d9feb904SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000670), 233d9feb904SVladimir Oltean REG(SYS_MMGT, 0x00069c), 234d9feb904SVladimir Oltean REG(SYS_MMGT_FAST, 0x0006a0), 235d9feb904SVladimir Oltean REG(SYS_EVENTS_DIF, 0x0006a4), 236d9feb904SVladimir Oltean REG(SYS_EVENTS_CORE, 0x0006b4), 237d9feb904SVladimir Oltean REG(SYS_CNT, 0x000000), 238d9feb904SVladimir Oltean REG(SYS_PTP_STATUS, 0x0006b8), 239d9feb904SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x0006bc), 240d9feb904SVladimir Oltean REG(SYS_PTP_NXT, 0x0006c0), 241d9feb904SVladimir Oltean REG(SYS_PTP_CFG, 0x0006c4), 242d9feb904SVladimir Oltean }; 243d9feb904SVladimir Oltean 244d9feb904SVladimir Oltean static const u32 ocelot_s2_regmap[] = { 245d9feb904SVladimir Oltean REG(S2_CORE_UPDATE_CTRL, 0x000000), 246d9feb904SVladimir Oltean REG(S2_CORE_MV_CFG, 0x000004), 247d9feb904SVladimir Oltean REG(S2_CACHE_ENTRY_DAT, 0x000008), 248d9feb904SVladimir Oltean REG(S2_CACHE_MASK_DAT, 0x000108), 249d9feb904SVladimir Oltean REG(S2_CACHE_ACTION_DAT, 0x000208), 250d9feb904SVladimir Oltean REG(S2_CACHE_CNT_DAT, 0x000308), 251d9feb904SVladimir Oltean REG(S2_CACHE_TG_DAT, 0x000388), 252d9feb904SVladimir Oltean }; 253d9feb904SVladimir Oltean 254d9feb904SVladimir Oltean static const u32 ocelot_ptp_regmap[] = { 255d9feb904SVladimir Oltean REG(PTP_PIN_CFG, 0x000000), 256d9feb904SVladimir Oltean REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 257d9feb904SVladimir Oltean REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 258d9feb904SVladimir Oltean REG(PTP_PIN_TOD_NSEC, 0x00000c), 259d9feb904SVladimir Oltean REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 260d9feb904SVladimir Oltean REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 261d9feb904SVladimir Oltean REG(PTP_CFG_MISC, 0x0000a0), 262d9feb904SVladimir Oltean REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 263d9feb904SVladimir Oltean REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 264d9feb904SVladimir Oltean }; 265d9feb904SVladimir Oltean 26691c724cfSVladimir Oltean static const u32 ocelot_dev_gmii_regmap[] = { 26791c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 26891c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 26991c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 27091c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 27191c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 27291c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 27391c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 27491c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 27591c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 27691c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 27791c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 27891c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 27991c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 28091c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 28191c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 28291c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 28391c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 28491c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 28591c724cfSVladimir Oltean REG(PCS1G_CFG, 0x48), 28691c724cfSVladimir Oltean REG(PCS1G_MODE_CFG, 0x4c), 28791c724cfSVladimir Oltean REG(PCS1G_SD_CFG, 0x50), 28891c724cfSVladimir Oltean REG(PCS1G_ANEG_CFG, 0x54), 28991c724cfSVladimir Oltean REG(PCS1G_ANEG_NP_CFG, 0x58), 29091c724cfSVladimir Oltean REG(PCS1G_LB_CFG, 0x5c), 29191c724cfSVladimir Oltean REG(PCS1G_DBG_CFG, 0x60), 29291c724cfSVladimir Oltean REG(PCS1G_CDET_CFG, 0x64), 29391c724cfSVladimir Oltean REG(PCS1G_ANEG_STATUS, 0x68), 29491c724cfSVladimir Oltean REG(PCS1G_ANEG_NP_STATUS, 0x6c), 29591c724cfSVladimir Oltean REG(PCS1G_LINK_STATUS, 0x70), 29691c724cfSVladimir Oltean REG(PCS1G_LINK_DOWN_CNT, 0x74), 29791c724cfSVladimir Oltean REG(PCS1G_STICKY, 0x78), 29891c724cfSVladimir Oltean REG(PCS1G_DEBUG_STATUS, 0x7c), 29991c724cfSVladimir Oltean REG(PCS1G_LPI_CFG, 0x80), 30091c724cfSVladimir Oltean REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 30191c724cfSVladimir Oltean REG(PCS1G_LPI_STATUS, 0x88), 30291c724cfSVladimir Oltean REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 30391c724cfSVladimir Oltean REG(PCS1G_TSTPAT_STATUS, 0x90), 30491c724cfSVladimir Oltean REG(DEV_PCS_FX100_CFG, 0x94), 30591c724cfSVladimir Oltean REG(DEV_PCS_FX100_STATUS, 0x98), 30691c724cfSVladimir Oltean }; 30791c724cfSVladimir Oltean 30891c724cfSVladimir Oltean static const u32 *ocelot_regmap[TARGET_MAX] = { 309d9feb904SVladimir Oltean [ANA] = ocelot_ana_regmap, 310d9feb904SVladimir Oltean [QS] = ocelot_qs_regmap, 311d9feb904SVladimir Oltean [QSYS] = ocelot_qsys_regmap, 312d9feb904SVladimir Oltean [REW] = ocelot_rew_regmap, 313d9feb904SVladimir Oltean [SYS] = ocelot_sys_regmap, 314d9feb904SVladimir Oltean [S2] = ocelot_s2_regmap, 315d9feb904SVladimir Oltean [PTP] = ocelot_ptp_regmap, 31691c724cfSVladimir Oltean [DEV_GMII] = ocelot_dev_gmii_regmap, 317d9feb904SVladimir Oltean }; 318d9feb904SVladimir Oltean 3192789658fSMaxim Kochetkov static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { 320d9feb904SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), 321d9feb904SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), 322d9feb904SVladimir Oltean [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), 323d9feb904SVladimir Oltean [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), 324d9feb904SVladimir Oltean [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), 325d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 326d9feb904SVladimir Oltean [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), 327d9feb904SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 328d9feb904SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 329d9feb904SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 330d9feb904SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 331d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 332d9feb904SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 333d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 334d9feb904SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 335d9feb904SVladimir Oltean [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), 336d9feb904SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 337d9feb904SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 338d9feb904SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 339d9feb904SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 340d9feb904SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 341d9feb904SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 342d9feb904SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 343d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 344d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 345d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 346d9feb904SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 347d9feb904SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 348d9feb904SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 349d9feb904SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 350d9feb904SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), 351d9feb904SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), 352d9feb904SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), 353d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), 354d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), 355d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), 356d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), 357d9feb904SVladimir Oltean [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), 358d9feb904SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), 359d9feb904SVladimir Oltean [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), 360d9feb904SVladimir Oltean [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), 3618bb849d6SVladimir Oltean /* Replicated per number of ports (12), register size 4 per port */ 3628bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), 3638bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), 3648bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), 3658bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), 3668bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), 3678bb849d6SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), 3688bb849d6SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), 3698bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), 3708bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), 3718bb849d6SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), 3728bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), 3738bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), 3748bb849d6SVladimir Oltean [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), 375d9feb904SVladimir Oltean }; 376d9feb904SVladimir Oltean 377d9feb904SVladimir Oltean static const struct ocelot_stat_layout ocelot_stats_layout[] = { 378d9feb904SVladimir Oltean { .name = "rx_octets", .offset = 0x00, }, 379d9feb904SVladimir Oltean { .name = "rx_unicast", .offset = 0x01, }, 380d9feb904SVladimir Oltean { .name = "rx_multicast", .offset = 0x02, }, 381d9feb904SVladimir Oltean { .name = "rx_broadcast", .offset = 0x03, }, 382d9feb904SVladimir Oltean { .name = "rx_shorts", .offset = 0x04, }, 383d9feb904SVladimir Oltean { .name = "rx_fragments", .offset = 0x05, }, 384d9feb904SVladimir Oltean { .name = "rx_jabbers", .offset = 0x06, }, 385d9feb904SVladimir Oltean { .name = "rx_crc_align_errs", .offset = 0x07, }, 386d9feb904SVladimir Oltean { .name = "rx_sym_errs", .offset = 0x08, }, 387d9feb904SVladimir Oltean { .name = "rx_frames_below_65_octets", .offset = 0x09, }, 388d9feb904SVladimir Oltean { .name = "rx_frames_65_to_127_octets", .offset = 0x0A, }, 389d9feb904SVladimir Oltean { .name = "rx_frames_128_to_255_octets", .offset = 0x0B, }, 390d9feb904SVladimir Oltean { .name = "rx_frames_256_to_511_octets", .offset = 0x0C, }, 391d9feb904SVladimir Oltean { .name = "rx_frames_512_to_1023_octets", .offset = 0x0D, }, 392d9feb904SVladimir Oltean { .name = "rx_frames_1024_to_1526_octets", .offset = 0x0E, }, 393d9feb904SVladimir Oltean { .name = "rx_frames_over_1526_octets", .offset = 0x0F, }, 394d9feb904SVladimir Oltean { .name = "rx_pause", .offset = 0x10, }, 395d9feb904SVladimir Oltean { .name = "rx_control", .offset = 0x11, }, 396d9feb904SVladimir Oltean { .name = "rx_longs", .offset = 0x12, }, 397d9feb904SVladimir Oltean { .name = "rx_classified_drops", .offset = 0x13, }, 398d9feb904SVladimir Oltean { .name = "rx_red_prio_0", .offset = 0x14, }, 399d9feb904SVladimir Oltean { .name = "rx_red_prio_1", .offset = 0x15, }, 400d9feb904SVladimir Oltean { .name = "rx_red_prio_2", .offset = 0x16, }, 401d9feb904SVladimir Oltean { .name = "rx_red_prio_3", .offset = 0x17, }, 402d9feb904SVladimir Oltean { .name = "rx_red_prio_4", .offset = 0x18, }, 403d9feb904SVladimir Oltean { .name = "rx_red_prio_5", .offset = 0x19, }, 404d9feb904SVladimir Oltean { .name = "rx_red_prio_6", .offset = 0x1A, }, 405d9feb904SVladimir Oltean { .name = "rx_red_prio_7", .offset = 0x1B, }, 406d9feb904SVladimir Oltean { .name = "rx_yellow_prio_0", .offset = 0x1C, }, 407d9feb904SVladimir Oltean { .name = "rx_yellow_prio_1", .offset = 0x1D, }, 408d9feb904SVladimir Oltean { .name = "rx_yellow_prio_2", .offset = 0x1E, }, 409d9feb904SVladimir Oltean { .name = "rx_yellow_prio_3", .offset = 0x1F, }, 410d9feb904SVladimir Oltean { .name = "rx_yellow_prio_4", .offset = 0x20, }, 411d9feb904SVladimir Oltean { .name = "rx_yellow_prio_5", .offset = 0x21, }, 412d9feb904SVladimir Oltean { .name = "rx_yellow_prio_6", .offset = 0x22, }, 413d9feb904SVladimir Oltean { .name = "rx_yellow_prio_7", .offset = 0x23, }, 414d9feb904SVladimir Oltean { .name = "rx_green_prio_0", .offset = 0x24, }, 415d9feb904SVladimir Oltean { .name = "rx_green_prio_1", .offset = 0x25, }, 416d9feb904SVladimir Oltean { .name = "rx_green_prio_2", .offset = 0x26, }, 417d9feb904SVladimir Oltean { .name = "rx_green_prio_3", .offset = 0x27, }, 418d9feb904SVladimir Oltean { .name = "rx_green_prio_4", .offset = 0x28, }, 419d9feb904SVladimir Oltean { .name = "rx_green_prio_5", .offset = 0x29, }, 420d9feb904SVladimir Oltean { .name = "rx_green_prio_6", .offset = 0x2A, }, 421d9feb904SVladimir Oltean { .name = "rx_green_prio_7", .offset = 0x2B, }, 422d9feb904SVladimir Oltean { .name = "tx_octets", .offset = 0x40, }, 423d9feb904SVladimir Oltean { .name = "tx_unicast", .offset = 0x41, }, 424d9feb904SVladimir Oltean { .name = "tx_multicast", .offset = 0x42, }, 425d9feb904SVladimir Oltean { .name = "tx_broadcast", .offset = 0x43, }, 426d9feb904SVladimir Oltean { .name = "tx_collision", .offset = 0x44, }, 427d9feb904SVladimir Oltean { .name = "tx_drops", .offset = 0x45, }, 428d9feb904SVladimir Oltean { .name = "tx_pause", .offset = 0x46, }, 429d9feb904SVladimir Oltean { .name = "tx_frames_below_65_octets", .offset = 0x47, }, 430d9feb904SVladimir Oltean { .name = "tx_frames_65_to_127_octets", .offset = 0x48, }, 431d9feb904SVladimir Oltean { .name = "tx_frames_128_255_octets", .offset = 0x49, }, 432d9feb904SVladimir Oltean { .name = "tx_frames_256_511_octets", .offset = 0x4A, }, 433d9feb904SVladimir Oltean { .name = "tx_frames_512_1023_octets", .offset = 0x4B, }, 434d9feb904SVladimir Oltean { .name = "tx_frames_1024_1526_octets", .offset = 0x4C, }, 435d9feb904SVladimir Oltean { .name = "tx_frames_over_1526_octets", .offset = 0x4D, }, 436d9feb904SVladimir Oltean { .name = "tx_yellow_prio_0", .offset = 0x4E, }, 437d9feb904SVladimir Oltean { .name = "tx_yellow_prio_1", .offset = 0x4F, }, 438d9feb904SVladimir Oltean { .name = "tx_yellow_prio_2", .offset = 0x50, }, 439d9feb904SVladimir Oltean { .name = "tx_yellow_prio_3", .offset = 0x51, }, 440d9feb904SVladimir Oltean { .name = "tx_yellow_prio_4", .offset = 0x52, }, 441d9feb904SVladimir Oltean { .name = "tx_yellow_prio_5", .offset = 0x53, }, 442d9feb904SVladimir Oltean { .name = "tx_yellow_prio_6", .offset = 0x54, }, 443d9feb904SVladimir Oltean { .name = "tx_yellow_prio_7", .offset = 0x55, }, 444d9feb904SVladimir Oltean { .name = "tx_green_prio_0", .offset = 0x56, }, 445d9feb904SVladimir Oltean { .name = "tx_green_prio_1", .offset = 0x57, }, 446d9feb904SVladimir Oltean { .name = "tx_green_prio_2", .offset = 0x58, }, 447d9feb904SVladimir Oltean { .name = "tx_green_prio_3", .offset = 0x59, }, 448d9feb904SVladimir Oltean { .name = "tx_green_prio_4", .offset = 0x5A, }, 449d9feb904SVladimir Oltean { .name = "tx_green_prio_5", .offset = 0x5B, }, 450d9feb904SVladimir Oltean { .name = "tx_green_prio_6", .offset = 0x5C, }, 451d9feb904SVladimir Oltean { .name = "tx_green_prio_7", .offset = 0x5D, }, 452d9feb904SVladimir Oltean { .name = "tx_aged", .offset = 0x5E, }, 453d9feb904SVladimir Oltean { .name = "drop_local", .offset = 0x80, }, 454d9feb904SVladimir Oltean { .name = "drop_tail", .offset = 0x81, }, 455d9feb904SVladimir Oltean { .name = "drop_yellow_prio_0", .offset = 0x82, }, 456d9feb904SVladimir Oltean { .name = "drop_yellow_prio_1", .offset = 0x83, }, 457d9feb904SVladimir Oltean { .name = "drop_yellow_prio_2", .offset = 0x84, }, 458d9feb904SVladimir Oltean { .name = "drop_yellow_prio_3", .offset = 0x85, }, 459d9feb904SVladimir Oltean { .name = "drop_yellow_prio_4", .offset = 0x86, }, 460d9feb904SVladimir Oltean { .name = "drop_yellow_prio_5", .offset = 0x87, }, 461d9feb904SVladimir Oltean { .name = "drop_yellow_prio_6", .offset = 0x88, }, 462d9feb904SVladimir Oltean { .name = "drop_yellow_prio_7", .offset = 0x89, }, 463d9feb904SVladimir Oltean { .name = "drop_green_prio_0", .offset = 0x8A, }, 464d9feb904SVladimir Oltean { .name = "drop_green_prio_1", .offset = 0x8B, }, 465d9feb904SVladimir Oltean { .name = "drop_green_prio_2", .offset = 0x8C, }, 466d9feb904SVladimir Oltean { .name = "drop_green_prio_3", .offset = 0x8D, }, 467d9feb904SVladimir Oltean { .name = "drop_green_prio_4", .offset = 0x8E, }, 468d9feb904SVladimir Oltean { .name = "drop_green_prio_5", .offset = 0x8F, }, 469d9feb904SVladimir Oltean { .name = "drop_green_prio_6", .offset = 0x90, }, 470d9feb904SVladimir Oltean { .name = "drop_green_prio_7", .offset = 0x91, }, 471d9feb904SVladimir Oltean }; 472d9feb904SVladimir Oltean 473d9feb904SVladimir Oltean static void ocelot_pll5_init(struct ocelot *ocelot) 474d9feb904SVladimir Oltean { 475d9feb904SVladimir Oltean /* Configure PLL5. This will need a proper CCF driver 476d9feb904SVladimir Oltean * The values are coming from the VTSS API for Ocelot 477d9feb904SVladimir Oltean */ 478d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 479d9feb904SVladimir Oltean HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 480d9feb904SVladimir Oltean HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 481d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 482d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 483d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 484d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_BIAS | 485d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_VCO_BUF | 486d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_CP1 | 487d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_SELCPI(2) | 488d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 489d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_SELBGV820(4) | 490d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_DIV4 | 491d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_CLKTREE | 492d9feb904SVladimir Oltean HSIO_PLL5G_CFG0_ENA_LANE); 493d9feb904SVladimir Oltean regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 494d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 495d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 496d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 497d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_ENA_AMPCTRL | 498d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 499d9feb904SVladimir Oltean HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 500d9feb904SVladimir Oltean } 501d9feb904SVladimir Oltean 502d9feb904SVladimir Oltean static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) 503d9feb904SVladimir Oltean { 504d9feb904SVladimir Oltean int ret; 505d9feb904SVladimir Oltean 506d9feb904SVladimir Oltean ocelot->map = ocelot_regmap; 507d9feb904SVladimir Oltean ocelot->stats_layout = ocelot_stats_layout; 508d9feb904SVladimir Oltean ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout); 509d9feb904SVladimir Oltean ocelot->shared_queue_sz = 224 * 1024; 510d9feb904SVladimir Oltean ocelot->num_mact_rows = 1024; 511d9feb904SVladimir Oltean ocelot->ops = ops; 512d9feb904SVladimir Oltean 513d9feb904SVladimir Oltean ret = ocelot_regfields_init(ocelot, ocelot_regfields); 514d9feb904SVladimir Oltean if (ret) 515d9feb904SVladimir Oltean return ret; 516d9feb904SVladimir Oltean 517d9feb904SVladimir Oltean ocelot_pll5_init(ocelot); 518d9feb904SVladimir Oltean 519d9feb904SVladimir Oltean eth_random_addr(ocelot->base_mac); 520d9feb904SVladimir Oltean ocelot->base_mac[5] &= 0xf0; 521d9feb904SVladimir Oltean 522d9feb904SVladimir Oltean return 0; 523d9feb904SVladimir Oltean } 524d9feb904SVladimir Oltean 525589aa6e7SVladimir Oltean static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info) 526589aa6e7SVladimir Oltean { 527589aa6e7SVladimir Oltean u8 llen, wlen; 528589aa6e7SVladimir Oltean u64 ifh[2]; 529589aa6e7SVladimir Oltean 530589aa6e7SVladimir Oltean ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]); 531589aa6e7SVladimir Oltean ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]); 532589aa6e7SVladimir Oltean 533589aa6e7SVladimir Oltean wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7, 8); 534589aa6e7SVladimir Oltean llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15, 6); 535589aa6e7SVladimir Oltean 536589aa6e7SVladimir Oltean info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80; 537589aa6e7SVladimir Oltean 538589aa6e7SVladimir Oltean info->timestamp = IFH_EXTRACT_BITFIELD64(ifh[0], 21, 32); 539589aa6e7SVladimir Oltean 540589aa6e7SVladimir Oltean info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4); 541589aa6e7SVladimir Oltean 542589aa6e7SVladimir Oltean info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16, 1); 543589aa6e7SVladimir Oltean info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0, 12); 544589aa6e7SVladimir Oltean 545589aa6e7SVladimir Oltean return 0; 546589aa6e7SVladimir Oltean } 547589aa6e7SVladimir Oltean 548589aa6e7SVladimir Oltean static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 549589aa6e7SVladimir Oltean u32 *rval) 550589aa6e7SVladimir Oltean { 551589aa6e7SVladimir Oltean u32 val; 552589aa6e7SVladimir Oltean u32 bytes_valid; 553589aa6e7SVladimir Oltean 554589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 555589aa6e7SVladimir Oltean if (val == XTR_NOT_READY) { 556589aa6e7SVladimir Oltean if (ifh) 557589aa6e7SVladimir Oltean return -EIO; 558589aa6e7SVladimir Oltean 559589aa6e7SVladimir Oltean do { 560589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 561589aa6e7SVladimir Oltean } while (val == XTR_NOT_READY); 562589aa6e7SVladimir Oltean } 563589aa6e7SVladimir Oltean 564589aa6e7SVladimir Oltean switch (val) { 565589aa6e7SVladimir Oltean case XTR_ABORT: 566589aa6e7SVladimir Oltean return -EIO; 567589aa6e7SVladimir Oltean case XTR_EOF_0: 568589aa6e7SVladimir Oltean case XTR_EOF_1: 569589aa6e7SVladimir Oltean case XTR_EOF_2: 570589aa6e7SVladimir Oltean case XTR_EOF_3: 571589aa6e7SVladimir Oltean case XTR_PRUNED: 572589aa6e7SVladimir Oltean bytes_valid = XTR_VALID_BYTES(val); 573589aa6e7SVladimir Oltean val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 574589aa6e7SVladimir Oltean if (val == XTR_ESCAPE) 575589aa6e7SVladimir Oltean *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 576589aa6e7SVladimir Oltean else 577589aa6e7SVladimir Oltean *rval = val; 578589aa6e7SVladimir Oltean 579589aa6e7SVladimir Oltean return bytes_valid; 580589aa6e7SVladimir Oltean case XTR_ESCAPE: 581589aa6e7SVladimir Oltean *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 582589aa6e7SVladimir Oltean 583589aa6e7SVladimir Oltean return 4; 584589aa6e7SVladimir Oltean default: 585589aa6e7SVladimir Oltean *rval = val; 586589aa6e7SVladimir Oltean 587589aa6e7SVladimir Oltean return 4; 588589aa6e7SVladimir Oltean } 589589aa6e7SVladimir Oltean } 590589aa6e7SVladimir Oltean 591589aa6e7SVladimir Oltean static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg) 592589aa6e7SVladimir Oltean { 593589aa6e7SVladimir Oltean struct ocelot *ocelot = arg; 594589aa6e7SVladimir Oltean int i = 0, grp = 0; 595589aa6e7SVladimir Oltean int err = 0; 596589aa6e7SVladimir Oltean 597589aa6e7SVladimir Oltean if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))) 598589aa6e7SVladimir Oltean return IRQ_NONE; 599589aa6e7SVladimir Oltean 600589aa6e7SVladimir Oltean do { 601589aa6e7SVladimir Oltean struct skb_shared_hwtstamps *shhwtstamps; 602589aa6e7SVladimir Oltean struct ocelot_port_private *priv; 603589aa6e7SVladimir Oltean struct ocelot_port *ocelot_port; 604589aa6e7SVladimir Oltean u64 tod_in_ns, full_ts_in_ns; 605589aa6e7SVladimir Oltean struct frame_info info = {}; 606589aa6e7SVladimir Oltean struct net_device *dev; 607589aa6e7SVladimir Oltean u32 ifh[4], val, *buf; 608589aa6e7SVladimir Oltean struct timespec64 ts; 609589aa6e7SVladimir Oltean int sz, len, buf_len; 610589aa6e7SVladimir Oltean struct sk_buff *skb; 611589aa6e7SVladimir Oltean 612589aa6e7SVladimir Oltean for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 613589aa6e7SVladimir Oltean err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]); 614589aa6e7SVladimir Oltean if (err != 4) 615589aa6e7SVladimir Oltean break; 616589aa6e7SVladimir Oltean } 617589aa6e7SVladimir Oltean 618589aa6e7SVladimir Oltean if (err != 4) 619589aa6e7SVladimir Oltean break; 620589aa6e7SVladimir Oltean 621589aa6e7SVladimir Oltean /* At this point the IFH was read correctly, so it is safe to 622589aa6e7SVladimir Oltean * presume that there is no error. The err needs to be reset 623589aa6e7SVladimir Oltean * otherwise a frame could come in CPU queue between the while 624589aa6e7SVladimir Oltean * condition and the check for error later on. And in that case 625589aa6e7SVladimir Oltean * the new frame is just removed and not processed. 626589aa6e7SVladimir Oltean */ 627589aa6e7SVladimir Oltean err = 0; 628589aa6e7SVladimir Oltean 629589aa6e7SVladimir Oltean ocelot_parse_ifh(ifh, &info); 630589aa6e7SVladimir Oltean 631589aa6e7SVladimir Oltean ocelot_port = ocelot->ports[info.port]; 632589aa6e7SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 633589aa6e7SVladimir Oltean port); 634589aa6e7SVladimir Oltean dev = priv->dev; 635589aa6e7SVladimir Oltean 636589aa6e7SVladimir Oltean skb = netdev_alloc_skb(dev, info.len); 637589aa6e7SVladimir Oltean 638589aa6e7SVladimir Oltean if (unlikely(!skb)) { 639589aa6e7SVladimir Oltean netdev_err(dev, "Unable to allocate sk_buff\n"); 640589aa6e7SVladimir Oltean err = -ENOMEM; 641589aa6e7SVladimir Oltean break; 642589aa6e7SVladimir Oltean } 643589aa6e7SVladimir Oltean buf_len = info.len - ETH_FCS_LEN; 644589aa6e7SVladimir Oltean buf = (u32 *)skb_put(skb, buf_len); 645589aa6e7SVladimir Oltean 646589aa6e7SVladimir Oltean len = 0; 647589aa6e7SVladimir Oltean do { 648589aa6e7SVladimir Oltean sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 649589aa6e7SVladimir Oltean *buf++ = val; 650589aa6e7SVladimir Oltean len += sz; 651589aa6e7SVladimir Oltean } while (len < buf_len); 652589aa6e7SVladimir Oltean 653589aa6e7SVladimir Oltean /* Read the FCS */ 654589aa6e7SVladimir Oltean sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 655589aa6e7SVladimir Oltean /* Update the statistics if part of the FCS was read before */ 656589aa6e7SVladimir Oltean len -= ETH_FCS_LEN - sz; 657589aa6e7SVladimir Oltean 658589aa6e7SVladimir Oltean if (unlikely(dev->features & NETIF_F_RXFCS)) { 659589aa6e7SVladimir Oltean buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 660589aa6e7SVladimir Oltean *buf = val; 661589aa6e7SVladimir Oltean } 662589aa6e7SVladimir Oltean 663589aa6e7SVladimir Oltean if (sz < 0) { 664589aa6e7SVladimir Oltean err = sz; 665589aa6e7SVladimir Oltean break; 666589aa6e7SVladimir Oltean } 667589aa6e7SVladimir Oltean 668589aa6e7SVladimir Oltean if (ocelot->ptp) { 669589aa6e7SVladimir Oltean ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 670589aa6e7SVladimir Oltean 671589aa6e7SVladimir Oltean tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 672589aa6e7SVladimir Oltean if ((tod_in_ns & 0xffffffff) < info.timestamp) 673589aa6e7SVladimir Oltean full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 674589aa6e7SVladimir Oltean info.timestamp; 675589aa6e7SVladimir Oltean else 676589aa6e7SVladimir Oltean full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 677589aa6e7SVladimir Oltean info.timestamp; 678589aa6e7SVladimir Oltean 679589aa6e7SVladimir Oltean shhwtstamps = skb_hwtstamps(skb); 680589aa6e7SVladimir Oltean memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 681589aa6e7SVladimir Oltean shhwtstamps->hwtstamp = full_ts_in_ns; 682589aa6e7SVladimir Oltean } 683589aa6e7SVladimir Oltean 684589aa6e7SVladimir Oltean /* Everything we see on an interface that is in the HW bridge 685589aa6e7SVladimir Oltean * has already been forwarded. 686589aa6e7SVladimir Oltean */ 687589aa6e7SVladimir Oltean if (ocelot->bridge_mask & BIT(info.port)) 688589aa6e7SVladimir Oltean skb->offload_fwd_mark = 1; 689589aa6e7SVladimir Oltean 690589aa6e7SVladimir Oltean skb->protocol = eth_type_trans(skb, dev); 691589aa6e7SVladimir Oltean if (!skb_defer_rx_timestamp(skb)) 692589aa6e7SVladimir Oltean netif_rx(skb); 693589aa6e7SVladimir Oltean dev->stats.rx_bytes += len; 694589aa6e7SVladimir Oltean dev->stats.rx_packets++; 695589aa6e7SVladimir Oltean } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)); 696589aa6e7SVladimir Oltean 697589aa6e7SVladimir Oltean if (err) 698589aa6e7SVladimir Oltean while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 699589aa6e7SVladimir Oltean ocelot_read_rix(ocelot, QS_XTR_RD, grp); 700589aa6e7SVladimir Oltean 701589aa6e7SVladimir Oltean return IRQ_HANDLED; 702589aa6e7SVladimir Oltean } 703589aa6e7SVladimir Oltean 704589aa6e7SVladimir Oltean static irqreturn_t ocelot_ptp_rdy_irq_handler(int irq, void *arg) 705589aa6e7SVladimir Oltean { 706589aa6e7SVladimir Oltean struct ocelot *ocelot = arg; 707589aa6e7SVladimir Oltean 708589aa6e7SVladimir Oltean ocelot_get_txtstamp(ocelot); 709589aa6e7SVladimir Oltean 710589aa6e7SVladimir Oltean return IRQ_HANDLED; 711589aa6e7SVladimir Oltean } 712589aa6e7SVladimir Oltean 713589aa6e7SVladimir Oltean static const struct of_device_id mscc_ocelot_match[] = { 714589aa6e7SVladimir Oltean { .compatible = "mscc,vsc7514-switch" }, 715589aa6e7SVladimir Oltean { } 716589aa6e7SVladimir Oltean }; 717589aa6e7SVladimir Oltean MODULE_DEVICE_TABLE(of, mscc_ocelot_match); 718589aa6e7SVladimir Oltean 719589aa6e7SVladimir Oltean static int ocelot_reset(struct ocelot *ocelot) 720589aa6e7SVladimir Oltean { 721589aa6e7SVladimir Oltean int retries = 100; 722589aa6e7SVladimir Oltean u32 val; 723589aa6e7SVladimir Oltean 724589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 725589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 726589aa6e7SVladimir Oltean 727589aa6e7SVladimir Oltean do { 728589aa6e7SVladimir Oltean msleep(1); 729589aa6e7SVladimir Oltean regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 730589aa6e7SVladimir Oltean &val); 731589aa6e7SVladimir Oltean } while (val && --retries); 732589aa6e7SVladimir Oltean 733589aa6e7SVladimir Oltean if (!retries) 734589aa6e7SVladimir Oltean return -ETIMEDOUT; 735589aa6e7SVladimir Oltean 736589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 737589aa6e7SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 738589aa6e7SVladimir Oltean 739589aa6e7SVladimir Oltean return 0; 740589aa6e7SVladimir Oltean } 741589aa6e7SVladimir Oltean 742aa92d836SMaxim Kochetkov /* Watermark encode 743aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 744aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 745aa92d836SMaxim Kochetkov */ 746aa92d836SMaxim Kochetkov static u16 ocelot_wm_enc(u16 value) 747aa92d836SMaxim Kochetkov { 748*01326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8)); 749*01326493SVladimir Oltean 750aa92d836SMaxim Kochetkov if (value >= BIT(8)) 751aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 752aa92d836SMaxim Kochetkov 753aa92d836SMaxim Kochetkov return value; 754aa92d836SMaxim Kochetkov } 755aa92d836SMaxim Kochetkov 756589aa6e7SVladimir Oltean static const struct ocelot_ops ocelot_ops = { 757589aa6e7SVladimir Oltean .reset = ocelot_reset, 758aa92d836SMaxim Kochetkov .wm_enc = ocelot_wm_enc, 759589aa6e7SVladimir Oltean }; 760589aa6e7SVladimir Oltean 761589aa6e7SVladimir Oltean static const struct vcap_field vsc7514_vcap_is2_keys[] = { 762589aa6e7SVladimir Oltean /* Common: 46 bits */ 763589aa6e7SVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 764589aa6e7SVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 765589aa6e7SVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 766589aa6e7SVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12}, 767589aa6e7SVladimir Oltean [VCAP_IS2_HK_RSV2] = { 25, 1}, 768589aa6e7SVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 26, 1}, 769589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 27, 1}, 770589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 28, 1}, 771589aa6e7SVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1}, 772589aa6e7SVladimir Oltean [VCAP_IS2_HK_VID] = { 30, 12}, 773589aa6e7SVladimir Oltean [VCAP_IS2_HK_DEI] = { 42, 1}, 774589aa6e7SVladimir Oltean [VCAP_IS2_HK_PCP] = { 43, 3}, 775589aa6e7SVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 776589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 46, 48}, 777589aa6e7SVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 94, 48}, 778589aa6e7SVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 779589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {142, 16}, 780589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {158, 16}, 781589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {174, 8}, 782589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {182, 3}, 783589aa6e7SVladimir Oltean /* MAC_LLC (TYPE=001) */ 784589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {142, 40}, 785589aa6e7SVladimir Oltean /* MAC_SNAP (TYPE=010) */ 786589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {142, 40}, 787589aa6e7SVladimir Oltean /* MAC_ARP (TYPE=011) */ 788589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48}, 789589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1}, 790589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1}, 791589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1}, 792589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1}, 793589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1}, 794589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1}, 795589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = {100, 2}, 796589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {102, 32}, 797589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {134, 32}, 798589aa6e7SVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {166, 1}, 799589aa6e7SVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 800589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4] = { 46, 1}, 801589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1}, 802589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1}, 803589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1}, 804589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1}, 805589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 51, 8}, 806589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32}, 807589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32}, 808589aa6e7SVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {123, 1}, 809589aa6e7SVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 810589aa6e7SVladimir Oltean [VCAP_IS2_HK_TCP] = {124, 1}, 8118194d8faSVladimir Oltean [VCAP_IS2_HK_L4_DPORT] = {125, 16}, 8128194d8faSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {141, 16}, 813589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {157, 8}, 814589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {165, 1}, 815589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {166, 1}, 8168194d8faSVladimir Oltean [VCAP_IS2_HK_L4_FIN] = {167, 1}, 8178194d8faSVladimir Oltean [VCAP_IS2_HK_L4_SYN] = {168, 1}, 8188194d8faSVladimir Oltean [VCAP_IS2_HK_L4_RST] = {169, 1}, 8198194d8faSVladimir Oltean [VCAP_IS2_HK_L4_PSH] = {170, 1}, 8208194d8faSVladimir Oltean [VCAP_IS2_HK_L4_ACK] = {171, 1}, 8218194d8faSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {172, 1}, 822589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {173, 8}, 823589aa6e7SVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {181, 4}, 824589aa6e7SVladimir Oltean /* IP4_OTHER (TYPE=101) */ 825589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {124, 8}, 826589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {132, 56}, 827589aa6e7SVladimir Oltean /* IP6_STD (TYPE=110) */ 828589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1}, 829589aa6e7SVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128}, 830589aa6e7SVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {175, 8}, 831589aa6e7SVladimir Oltean /* OAM (TYPE=111) */ 832589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {142, 7}, 833589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {149, 5}, 834589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {154, 8}, 835589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {162, 8}, 836589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {170, 16}, 837589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {186, 1}, 838589aa6e7SVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {187, 1}, 839589aa6e7SVladimir Oltean }; 840589aa6e7SVladimir Oltean 841589aa6e7SVladimir Oltean static const struct vcap_field vsc7514_vcap_is2_actions[] = { 842589aa6e7SVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 843589aa6e7SVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 844589aa6e7SVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 845589aa6e7SVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 846589aa6e7SVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 847589aa6e7SVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 848589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 849589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 850589aa6e7SVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 851589aa6e7SVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 852589aa6e7SVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 853589aa6e7SVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 854589aa6e7SVladimir Oltean [VCAP_IS2_ACT_RSV] = { 41, 2}, 855589aa6e7SVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 856589aa6e7SVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 857589aa6e7SVladimir Oltean }; 858589aa6e7SVladimir Oltean 859589aa6e7SVladimir Oltean static const struct vcap_props vsc7514_vcap_props[] = { 860589aa6e7SVladimir Oltean [VCAP_IS2] = { 861589aa6e7SVladimir Oltean .tg_width = 2, 862589aa6e7SVladimir Oltean .sw_count = 4, 863589aa6e7SVladimir Oltean .entry_count = VSC7514_VCAP_IS2_CNT, 864589aa6e7SVladimir Oltean .entry_width = VSC7514_VCAP_IS2_ENTRY_WIDTH, 865589aa6e7SVladimir Oltean .action_count = VSC7514_VCAP_IS2_CNT + 866589aa6e7SVladimir Oltean VSC7514_VCAP_PORT_CNT + 2, 867589aa6e7SVladimir Oltean .action_width = 99, 868589aa6e7SVladimir Oltean .action_type_width = 1, 869589aa6e7SVladimir Oltean .action_table = { 870589aa6e7SVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 871589aa6e7SVladimir Oltean .width = 49, 872589aa6e7SVladimir Oltean .count = 2 873589aa6e7SVladimir Oltean }, 874589aa6e7SVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 875589aa6e7SVladimir Oltean .width = 6, 876589aa6e7SVladimir Oltean .count = 4 877589aa6e7SVladimir Oltean }, 878589aa6e7SVladimir Oltean }, 879589aa6e7SVladimir Oltean .counter_words = 4, 880589aa6e7SVladimir Oltean .counter_width = 32, 881589aa6e7SVladimir Oltean }, 882589aa6e7SVladimir Oltean }; 883589aa6e7SVladimir Oltean 884589aa6e7SVladimir Oltean static struct ptp_clock_info ocelot_ptp_clock_info = { 885589aa6e7SVladimir Oltean .owner = THIS_MODULE, 886589aa6e7SVladimir Oltean .name = "ocelot ptp", 887589aa6e7SVladimir Oltean .max_adj = 0x7fffffff, 888589aa6e7SVladimir Oltean .n_alarm = 0, 889589aa6e7SVladimir Oltean .n_ext_ts = 0, 890589aa6e7SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM, 891589aa6e7SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM, 892589aa6e7SVladimir Oltean .pps = 0, 893589aa6e7SVladimir Oltean .gettime64 = ocelot_ptp_gettime64, 894589aa6e7SVladimir Oltean .settime64 = ocelot_ptp_settime64, 895589aa6e7SVladimir Oltean .adjtime = ocelot_ptp_adjtime, 896589aa6e7SVladimir Oltean .adjfine = ocelot_ptp_adjfine, 897589aa6e7SVladimir Oltean .verify = ocelot_ptp_verify, 898589aa6e7SVladimir Oltean .enable = ocelot_ptp_enable, 899589aa6e7SVladimir Oltean }; 900589aa6e7SVladimir Oltean 90122cdb493SVladimir Oltean static void mscc_ocelot_release_ports(struct ocelot *ocelot) 90222cdb493SVladimir Oltean { 90322cdb493SVladimir Oltean int port; 90422cdb493SVladimir Oltean 90522cdb493SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 90622cdb493SVladimir Oltean struct ocelot_port_private *priv; 90722cdb493SVladimir Oltean struct ocelot_port *ocelot_port; 90822cdb493SVladimir Oltean 90922cdb493SVladimir Oltean ocelot_port = ocelot->ports[port]; 91022cdb493SVladimir Oltean if (!ocelot_port) 91122cdb493SVladimir Oltean continue; 91222cdb493SVladimir Oltean 913e5fb512dSVladimir Oltean ocelot_deinit_port(ocelot, port); 914e5fb512dSVladimir Oltean 91522cdb493SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 91622cdb493SVladimir Oltean port); 91722cdb493SVladimir Oltean 91822cdb493SVladimir Oltean unregister_netdev(priv->dev); 91922cdb493SVladimir Oltean free_netdev(priv->dev); 92022cdb493SVladimir Oltean } 92122cdb493SVladimir Oltean } 92222cdb493SVladimir Oltean 9237c411799SVladimir Oltean static int mscc_ocelot_init_ports(struct platform_device *pdev, 9247c411799SVladimir Oltean struct device_node *ports) 9257c411799SVladimir Oltean { 9267c411799SVladimir Oltean struct ocelot *ocelot = platform_get_drvdata(pdev); 9277c411799SVladimir Oltean struct device_node *portnp; 9287c411799SVladimir Oltean int err; 9297c411799SVladimir Oltean 9307c411799SVladimir Oltean ocelot->ports = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 9317c411799SVladimir Oltean sizeof(struct ocelot_port *), GFP_KERNEL); 9327c411799SVladimir Oltean if (!ocelot->ports) 9337c411799SVladimir Oltean return -ENOMEM; 9347c411799SVladimir Oltean 9357c411799SVladimir Oltean /* No NPI port */ 9367c411799SVladimir Oltean ocelot_configure_cpu(ocelot, -1, OCELOT_TAG_PREFIX_NONE, 9377c411799SVladimir Oltean OCELOT_TAG_PREFIX_NONE); 9387c411799SVladimir Oltean 9397c411799SVladimir Oltean for_each_available_child_of_node(ports, portnp) { 9407c411799SVladimir Oltean struct ocelot_port_private *priv; 9417c411799SVladimir Oltean struct ocelot_port *ocelot_port; 9427c411799SVladimir Oltean struct device_node *phy_node; 9437c411799SVladimir Oltean phy_interface_t phy_mode; 9447c411799SVladimir Oltean struct phy_device *phy; 9457c411799SVladimir Oltean struct regmap *target; 9467c411799SVladimir Oltean struct resource *res; 9477c411799SVladimir Oltean struct phy *serdes; 9487c411799SVladimir Oltean char res_name[8]; 9497c411799SVladimir Oltean u32 port; 9507c411799SVladimir Oltean 9517c411799SVladimir Oltean if (of_property_read_u32(portnp, "reg", &port)) 9527c411799SVladimir Oltean continue; 9537c411799SVladimir Oltean 9547c411799SVladimir Oltean snprintf(res_name, sizeof(res_name), "port%d", port); 9557c411799SVladimir Oltean 9567c411799SVladimir Oltean res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 9577c411799SVladimir Oltean res_name); 9587c411799SVladimir Oltean target = ocelot_regmap_init(ocelot, res); 9597c411799SVladimir Oltean if (IS_ERR(target)) 9607c411799SVladimir Oltean continue; 9617c411799SVladimir Oltean 9627c411799SVladimir Oltean phy_node = of_parse_phandle(portnp, "phy-handle", 0); 9637c411799SVladimir Oltean if (!phy_node) 9647c411799SVladimir Oltean continue; 9657c411799SVladimir Oltean 9667c411799SVladimir Oltean phy = of_phy_find_device(phy_node); 9677c411799SVladimir Oltean of_node_put(phy_node); 9687c411799SVladimir Oltean if (!phy) 9697c411799SVladimir Oltean continue; 9707c411799SVladimir Oltean 9717c411799SVladimir Oltean err = ocelot_probe_port(ocelot, port, target, phy); 9727c411799SVladimir Oltean if (err) { 9737c411799SVladimir Oltean of_node_put(portnp); 9747c411799SVladimir Oltean return err; 9757c411799SVladimir Oltean } 9767c411799SVladimir Oltean 9777c411799SVladimir Oltean ocelot_port = ocelot->ports[port]; 9787c411799SVladimir Oltean priv = container_of(ocelot_port, struct ocelot_port_private, 9797c411799SVladimir Oltean port); 9807c411799SVladimir Oltean 9817c411799SVladimir Oltean of_get_phy_mode(portnp, &phy_mode); 9827c411799SVladimir Oltean 9837c411799SVladimir Oltean ocelot_port->phy_mode = phy_mode; 9847c411799SVladimir Oltean 9857c411799SVladimir Oltean switch (ocelot_port->phy_mode) { 9867c411799SVladimir Oltean case PHY_INTERFACE_MODE_NA: 9877c411799SVladimir Oltean continue; 9887c411799SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 9897c411799SVladimir Oltean break; 9907c411799SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 9917c411799SVladimir Oltean /* Ensure clock signals and speed is set on all 9927c411799SVladimir Oltean * QSGMII links 9937c411799SVladimir Oltean */ 9947c411799SVladimir Oltean ocelot_port_writel(ocelot_port, 9957c411799SVladimir Oltean DEV_CLOCK_CFG_LINK_SPEED 9967c411799SVladimir Oltean (OCELOT_SPEED_1000), 9977c411799SVladimir Oltean DEV_CLOCK_CFG); 9987c411799SVladimir Oltean break; 9997c411799SVladimir Oltean default: 10007c411799SVladimir Oltean dev_err(ocelot->dev, 10017c411799SVladimir Oltean "invalid phy mode for port%d, (Q)SGMII only\n", 10027c411799SVladimir Oltean port); 10037c411799SVladimir Oltean of_node_put(portnp); 10047c411799SVladimir Oltean return -EINVAL; 10057c411799SVladimir Oltean } 10067c411799SVladimir Oltean 10077c411799SVladimir Oltean serdes = devm_of_phy_get(ocelot->dev, portnp, NULL); 10087c411799SVladimir Oltean if (IS_ERR(serdes)) { 10097c411799SVladimir Oltean err = PTR_ERR(serdes); 10107c411799SVladimir Oltean if (err == -EPROBE_DEFER) 10117c411799SVladimir Oltean dev_dbg(ocelot->dev, "deferring probe\n"); 10127c411799SVladimir Oltean else 10137c411799SVladimir Oltean dev_err(ocelot->dev, 10147c411799SVladimir Oltean "missing SerDes phys for port%d\n", 10157c411799SVladimir Oltean port); 10167c411799SVladimir Oltean 10177c411799SVladimir Oltean of_node_put(portnp); 10187c411799SVladimir Oltean return err; 10197c411799SVladimir Oltean } 10207c411799SVladimir Oltean 10217c411799SVladimir Oltean priv->serdes = serdes; 10227c411799SVladimir Oltean } 10237c411799SVladimir Oltean 10247c411799SVladimir Oltean return 0; 10257c411799SVladimir Oltean } 10267c411799SVladimir Oltean 1027589aa6e7SVladimir Oltean static int mscc_ocelot_probe(struct platform_device *pdev) 1028589aa6e7SVladimir Oltean { 1029589aa6e7SVladimir Oltean struct device_node *np = pdev->dev.of_node; 1030589aa6e7SVladimir Oltean int err, irq_xtr, irq_ptp_rdy; 10317c411799SVladimir Oltean struct device_node *ports; 1032589aa6e7SVladimir Oltean struct ocelot *ocelot; 1033589aa6e7SVladimir Oltean struct regmap *hsio; 1034589aa6e7SVladimir Oltean unsigned int i; 1035589aa6e7SVladimir Oltean 1036589aa6e7SVladimir Oltean struct { 1037589aa6e7SVladimir Oltean enum ocelot_target id; 1038589aa6e7SVladimir Oltean char *name; 1039589aa6e7SVladimir Oltean u8 optional:1; 1040589aa6e7SVladimir Oltean } io_target[] = { 1041589aa6e7SVladimir Oltean { SYS, "sys" }, 1042589aa6e7SVladimir Oltean { REW, "rew" }, 1043589aa6e7SVladimir Oltean { QSYS, "qsys" }, 1044589aa6e7SVladimir Oltean { ANA, "ana" }, 1045589aa6e7SVladimir Oltean { QS, "qs" }, 1046589aa6e7SVladimir Oltean { S2, "s2" }, 1047589aa6e7SVladimir Oltean { PTP, "ptp", 1 }, 1048589aa6e7SVladimir Oltean }; 1049589aa6e7SVladimir Oltean 1050589aa6e7SVladimir Oltean if (!np && !pdev->dev.platform_data) 1051589aa6e7SVladimir Oltean return -ENODEV; 1052589aa6e7SVladimir Oltean 1053589aa6e7SVladimir Oltean ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL); 1054589aa6e7SVladimir Oltean if (!ocelot) 1055589aa6e7SVladimir Oltean return -ENOMEM; 1056589aa6e7SVladimir Oltean 1057589aa6e7SVladimir Oltean platform_set_drvdata(pdev, ocelot); 1058589aa6e7SVladimir Oltean ocelot->dev = &pdev->dev; 1059589aa6e7SVladimir Oltean 1060589aa6e7SVladimir Oltean for (i = 0; i < ARRAY_SIZE(io_target); i++) { 1061589aa6e7SVladimir Oltean struct regmap *target; 1062589aa6e7SVladimir Oltean struct resource *res; 1063589aa6e7SVladimir Oltean 1064589aa6e7SVladimir Oltean res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1065589aa6e7SVladimir Oltean io_target[i].name); 1066589aa6e7SVladimir Oltean 1067589aa6e7SVladimir Oltean target = ocelot_regmap_init(ocelot, res); 1068589aa6e7SVladimir Oltean if (IS_ERR(target)) { 1069589aa6e7SVladimir Oltean if (io_target[i].optional) { 1070589aa6e7SVladimir Oltean ocelot->targets[io_target[i].id] = NULL; 1071589aa6e7SVladimir Oltean continue; 1072589aa6e7SVladimir Oltean } 1073589aa6e7SVladimir Oltean return PTR_ERR(target); 1074589aa6e7SVladimir Oltean } 1075589aa6e7SVladimir Oltean 1076589aa6e7SVladimir Oltean ocelot->targets[io_target[i].id] = target; 1077589aa6e7SVladimir Oltean } 1078589aa6e7SVladimir Oltean 1079589aa6e7SVladimir Oltean hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio"); 1080589aa6e7SVladimir Oltean if (IS_ERR(hsio)) { 1081589aa6e7SVladimir Oltean dev_err(&pdev->dev, "missing hsio syscon\n"); 1082589aa6e7SVladimir Oltean return PTR_ERR(hsio); 1083589aa6e7SVladimir Oltean } 1084589aa6e7SVladimir Oltean 1085589aa6e7SVladimir Oltean ocelot->targets[HSIO] = hsio; 1086589aa6e7SVladimir Oltean 1087589aa6e7SVladimir Oltean err = ocelot_chip_init(ocelot, &ocelot_ops); 1088589aa6e7SVladimir Oltean if (err) 1089589aa6e7SVladimir Oltean return err; 1090589aa6e7SVladimir Oltean 1091589aa6e7SVladimir Oltean irq_xtr = platform_get_irq_byname(pdev, "xtr"); 1092589aa6e7SVladimir Oltean if (irq_xtr < 0) 1093589aa6e7SVladimir Oltean return -ENODEV; 1094589aa6e7SVladimir Oltean 1095589aa6e7SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, irq_xtr, NULL, 1096589aa6e7SVladimir Oltean ocelot_xtr_irq_handler, IRQF_ONESHOT, 1097589aa6e7SVladimir Oltean "frame extraction", ocelot); 1098589aa6e7SVladimir Oltean if (err) 1099589aa6e7SVladimir Oltean return err; 1100589aa6e7SVladimir Oltean 1101589aa6e7SVladimir Oltean irq_ptp_rdy = platform_get_irq_byname(pdev, "ptp_rdy"); 1102589aa6e7SVladimir Oltean if (irq_ptp_rdy > 0 && ocelot->targets[PTP]) { 1103589aa6e7SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, irq_ptp_rdy, NULL, 1104589aa6e7SVladimir Oltean ocelot_ptp_rdy_irq_handler, 1105589aa6e7SVladimir Oltean IRQF_ONESHOT, "ptp ready", 1106589aa6e7SVladimir Oltean ocelot); 1107589aa6e7SVladimir Oltean if (err) 1108589aa6e7SVladimir Oltean return err; 1109589aa6e7SVladimir Oltean 1110589aa6e7SVladimir Oltean /* Both the PTP interrupt and the PTP bank are available */ 1111589aa6e7SVladimir Oltean ocelot->ptp = 1; 1112589aa6e7SVladimir Oltean } 1113589aa6e7SVladimir Oltean 1114589aa6e7SVladimir Oltean ports = of_get_child_by_name(np, "ethernet-ports"); 1115589aa6e7SVladimir Oltean if (!ports) { 11167c411799SVladimir Oltean dev_err(ocelot->dev, "no ethernet-ports child node found\n"); 1117589aa6e7SVladimir Oltean return -ENODEV; 1118589aa6e7SVladimir Oltean } 1119589aa6e7SVladimir Oltean 1120589aa6e7SVladimir Oltean ocelot->num_phys_ports = of_get_child_count(ports); 1121589aa6e7SVladimir Oltean 1122589aa6e7SVladimir Oltean ocelot->vcap_is2_keys = vsc7514_vcap_is2_keys; 1123589aa6e7SVladimir Oltean ocelot->vcap_is2_actions = vsc7514_vcap_is2_actions; 1124589aa6e7SVladimir Oltean ocelot->vcap = vsc7514_vcap_props; 1125589aa6e7SVladimir Oltean 1126d1cc0e93SVladimir Oltean err = ocelot_init(ocelot); 1127d1cc0e93SVladimir Oltean if (err) 1128d1cc0e93SVladimir Oltean goto out_put_ports; 1129d1cc0e93SVladimir Oltean 11307c411799SVladimir Oltean err = mscc_ocelot_init_ports(pdev, ports); 11317c411799SVladimir Oltean if (err) 11327c411799SVladimir Oltean goto out_put_ports; 11337c411799SVladimir Oltean 1134589aa6e7SVladimir Oltean if (ocelot->ptp) { 1135589aa6e7SVladimir Oltean err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 1136589aa6e7SVladimir Oltean if (err) { 1137589aa6e7SVladimir Oltean dev_err(ocelot->dev, 1138589aa6e7SVladimir Oltean "Timestamp initialization failed\n"); 1139589aa6e7SVladimir Oltean ocelot->ptp = 0; 1140589aa6e7SVladimir Oltean } 1141589aa6e7SVladimir Oltean } 1142589aa6e7SVladimir Oltean 1143589aa6e7SVladimir Oltean register_netdevice_notifier(&ocelot_netdevice_nb); 1144589aa6e7SVladimir Oltean register_switchdev_notifier(&ocelot_switchdev_nb); 1145589aa6e7SVladimir Oltean register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1146589aa6e7SVladimir Oltean 1147589aa6e7SVladimir Oltean dev_info(&pdev->dev, "Ocelot switch probed\n"); 1148589aa6e7SVladimir Oltean 1149589aa6e7SVladimir Oltean out_put_ports: 1150589aa6e7SVladimir Oltean of_node_put(ports); 1151589aa6e7SVladimir Oltean return err; 1152589aa6e7SVladimir Oltean } 1153589aa6e7SVladimir Oltean 1154589aa6e7SVladimir Oltean static int mscc_ocelot_remove(struct platform_device *pdev) 1155589aa6e7SVladimir Oltean { 1156589aa6e7SVladimir Oltean struct ocelot *ocelot = platform_get_drvdata(pdev); 1157589aa6e7SVladimir Oltean 1158589aa6e7SVladimir Oltean ocelot_deinit_timestamp(ocelot); 115922cdb493SVladimir Oltean mscc_ocelot_release_ports(ocelot); 1160589aa6e7SVladimir Oltean ocelot_deinit(ocelot); 1161589aa6e7SVladimir Oltean unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb); 1162589aa6e7SVladimir Oltean unregister_switchdev_notifier(&ocelot_switchdev_nb); 1163589aa6e7SVladimir Oltean unregister_netdevice_notifier(&ocelot_netdevice_nb); 1164589aa6e7SVladimir Oltean 1165589aa6e7SVladimir Oltean return 0; 1166589aa6e7SVladimir Oltean } 1167589aa6e7SVladimir Oltean 1168589aa6e7SVladimir Oltean static struct platform_driver mscc_ocelot_driver = { 1169589aa6e7SVladimir Oltean .probe = mscc_ocelot_probe, 1170589aa6e7SVladimir Oltean .remove = mscc_ocelot_remove, 1171589aa6e7SVladimir Oltean .driver = { 1172589aa6e7SVladimir Oltean .name = "ocelot-switch", 1173589aa6e7SVladimir Oltean .of_match_table = mscc_ocelot_match, 1174589aa6e7SVladimir Oltean }, 1175589aa6e7SVladimir Oltean }; 1176589aa6e7SVladimir Oltean 1177589aa6e7SVladimir Oltean module_platform_driver(mscc_ocelot_driver); 1178589aa6e7SVladimir Oltean 1179589aa6e7SVladimir Oltean MODULE_DESCRIPTION("Microsemi Ocelot switch driver"); 1180589aa6e7SVladimir Oltean MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); 1181589aa6e7SVladimir Oltean MODULE_LICENSE("Dual MIT/GPL"); 1182