1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
2  * Microsemi Ocelot Switch driver
3  * Copyright (c) 2019 Microsemi Corporation
4  */
5 
6 #ifndef _OCELOT_VCAP_H_
7 #define _OCELOT_VCAP_H_
8 
9 /* =================================================================
10  *  VCAP Common
11  * =================================================================
12  */
13 
14 /* VCAP Type-Group values */
15 #define VCAP_TG_NONE 0 /* Entry is invalid */
16 #define VCAP_TG_FULL 1 /* Full entry */
17 #define VCAP_TG_HALF 2 /* Half entry */
18 #define VCAP_TG_QUARTER 3 /* Quarter entry */
19 
20 /* =================================================================
21  *  VCAP IS2
22  * =================================================================
23  */
24 
25 #define VCAP_IS2_CNT 64
26 #define VCAP_IS2_ENTRY_WIDTH 376
27 #define VCAP_IS2_ACTION_WIDTH 99
28 #define VCAP_PORT_CNT 11
29 
30 /* IS2 half key types */
31 #define IS2_TYPE_ETYPE 0
32 #define IS2_TYPE_LLC 1
33 #define IS2_TYPE_SNAP 2
34 #define IS2_TYPE_ARP 3
35 #define IS2_TYPE_IP_UDP_TCP 4
36 #define IS2_TYPE_IP_OTHER 5
37 #define IS2_TYPE_IPV6 6
38 #define IS2_TYPE_OAM 7
39 #define IS2_TYPE_SMAC_SIP6 8
40 #define IS2_TYPE_ANY 100 /* Pseudo type */
41 
42 /* IS2 half key type mask for matching any IP */
43 #define IS2_TYPE_MASK_IP_ANY 0xe
44 
45 /* IS2 action types */
46 #define IS2_ACTION_TYPE_NORMAL 0
47 #define IS2_ACTION_TYPE_SMAC_SIP 1
48 
49 /* IS2 MASK_MODE values */
50 #define IS2_ACT_MASK_MODE_NONE 0
51 #define IS2_ACT_MASK_MODE_FILTER 1
52 #define IS2_ACT_MASK_MODE_POLICY 2
53 #define IS2_ACT_MASK_MODE_REDIR 3
54 
55 /* IS2 REW_OP values */
56 #define IS2_ACT_REW_OP_NONE 0
57 #define IS2_ACT_REW_OP_PTP_ONE 2
58 #define IS2_ACT_REW_OP_PTP_TWO 3
59 #define IS2_ACT_REW_OP_SPECIAL 8
60 #define IS2_ACT_REW_OP_PTP_ORG 9
61 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
62 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
63 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
64 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
65 
66 #define VCAP_PORT_WIDTH 4
67 
68 /* IS2 quarter key - SMAC_SIP4 */
69 #define IS2_QKO_IGR_PORT 0
70 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
71 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
72 #define IS2_QKL_L2_SMAC 48
73 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
74 #define IS2_QKL_L3_IP4_SIP 32
75 
76 /* IS2 half key - common */
77 #define IS2_HKO_TYPE 0
78 #define IS2_HKL_TYPE 4
79 #define IS2_HKO_FIRST (IS2_HKO_TYPE + IS2_HKL_TYPE)
80 #define IS2_HKL_FIRST 1
81 #define IS2_HKO_PAG (IS2_HKO_FIRST + IS2_HKL_FIRST)
82 #define IS2_HKL_PAG 8
83 #define IS2_HKO_IGR_PORT_MASK (IS2_HKO_PAG + IS2_HKL_PAG)
84 #define IS2_HKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
85 #define IS2_HKO_SERVICE_FRM (IS2_HKO_IGR_PORT_MASK + IS2_HKL_IGR_PORT_MASK)
86 #define IS2_HKL_SERVICE_FRM 1
87 #define IS2_HKO_HOST_MATCH (IS2_HKO_SERVICE_FRM + IS2_HKL_SERVICE_FRM)
88 #define IS2_HKL_HOST_MATCH 1
89 #define IS2_HKO_L2_MC (IS2_HKO_HOST_MATCH + IS2_HKL_HOST_MATCH)
90 #define IS2_HKL_L2_MC 1
91 #define IS2_HKO_L2_BC (IS2_HKO_L2_MC + IS2_HKL_L2_MC)
92 #define IS2_HKL_L2_BC 1
93 #define IS2_HKO_VLAN_TAGGED (IS2_HKO_L2_BC + IS2_HKL_L2_BC)
94 #define IS2_HKL_VLAN_TAGGED 1
95 #define IS2_HKO_VID (IS2_HKO_VLAN_TAGGED + IS2_HKL_VLAN_TAGGED)
96 #define IS2_HKL_VID 12
97 #define IS2_HKO_DEI (IS2_HKO_VID + IS2_HKL_VID)
98 #define IS2_HKL_DEI 1
99 #define IS2_HKO_PCP (IS2_HKO_DEI + IS2_HKL_DEI)
100 #define IS2_HKL_PCP 3
101 
102 /* IS2 half key - MAC_ETYPE/MAC_LLC/MAC_SNAP/OAM common */
103 #define IS2_HKO_L2_DMAC (IS2_HKO_PCP + IS2_HKL_PCP)
104 #define IS2_HKL_L2_DMAC 48
105 #define IS2_HKO_L2_SMAC (IS2_HKO_L2_DMAC + IS2_HKL_L2_DMAC)
106 #define IS2_HKL_L2_SMAC 48
107 
108 /* IS2 half key - MAC_ETYPE */
109 #define IS2_HKO_MAC_ETYPE_ETYPE (IS2_HKO_L2_SMAC + IS2_HKL_L2_SMAC)
110 #define IS2_HKL_MAC_ETYPE_ETYPE 16
111 #define IS2_HKO_MAC_ETYPE_L2_PAYLOAD                                           \
112 	(IS2_HKO_MAC_ETYPE_ETYPE + IS2_HKL_MAC_ETYPE_ETYPE)
113 #define IS2_HKL_MAC_ETYPE_L2_PAYLOAD 27
114 
115 /* IS2 half key - MAC_LLC */
116 #define IS2_HKO_MAC_LLC_L2_LLC IS2_HKO_MAC_ETYPE_ETYPE
117 #define IS2_HKL_MAC_LLC_L2_LLC 40
118 
119 /* IS2 half key - MAC_SNAP */
120 #define IS2_HKO_MAC_SNAP_L2_SNAP IS2_HKO_MAC_ETYPE_ETYPE
121 #define IS2_HKL_MAC_SNAP_L2_SNAP 40
122 
123 /* IS2 half key - ARP */
124 #define IS2_HKO_MAC_ARP_L2_SMAC IS2_HKO_L2_DMAC
125 #define IS2_HKL_MAC_ARP_L2_SMAC 48
126 #define IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK                                      \
127 	(IS2_HKO_MAC_ARP_L2_SMAC + IS2_HKL_MAC_ARP_L2_SMAC)
128 #define IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK 1
129 #define IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK                                     \
130 	(IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK + IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK)
131 #define IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK 1
132 #define IS2_HKO_MAC_ARP_ARP_LEN_OK                                             \
133 	(IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK +                                  \
134 	 IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK)
135 #define IS2_HKL_MAC_ARP_ARP_LEN_OK 1
136 #define IS2_HKO_MAC_ARP_ARP_TGT_MATCH                                          \
137 	(IS2_HKO_MAC_ARP_ARP_LEN_OK + IS2_HKL_MAC_ARP_ARP_LEN_OK)
138 #define IS2_HKL_MAC_ARP_ARP_TGT_MATCH 1
139 #define IS2_HKO_MAC_ARP_ARP_SENDER_MATCH                                       \
140 	(IS2_HKO_MAC_ARP_ARP_TGT_MATCH + IS2_HKL_MAC_ARP_ARP_TGT_MATCH)
141 #define IS2_HKL_MAC_ARP_ARP_SENDER_MATCH 1
142 #define IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN                                     \
143 	(IS2_HKO_MAC_ARP_ARP_SENDER_MATCH + IS2_HKL_MAC_ARP_ARP_SENDER_MATCH)
144 #define IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN 1
145 #define IS2_HKO_MAC_ARP_ARP_OPCODE                                             \
146 	(IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN +                                  \
147 	 IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN)
148 #define IS2_HKL_MAC_ARP_ARP_OPCODE 2
149 #define IS2_HKO_MAC_ARP_L3_IP4_DIP                                             \
150 	(IS2_HKO_MAC_ARP_ARP_OPCODE + IS2_HKL_MAC_ARP_ARP_OPCODE)
151 #define IS2_HKL_MAC_ARP_L3_IP4_DIP 32
152 #define IS2_HKO_MAC_ARP_L3_IP4_SIP                                             \
153 	(IS2_HKO_MAC_ARP_L3_IP4_DIP + IS2_HKL_MAC_ARP_L3_IP4_DIP)
154 #define IS2_HKL_MAC_ARP_L3_IP4_SIP 32
155 #define IS2_HKO_MAC_ARP_DIP_EQ_SIP                                             \
156 	(IS2_HKO_MAC_ARP_L3_IP4_SIP + IS2_HKL_MAC_ARP_L3_IP4_SIP)
157 #define IS2_HKL_MAC_ARP_DIP_EQ_SIP 1
158 
159 /* IS2 half key - IP4_TCP_UDP/IP4_OTHER common */
160 #define IS2_HKO_IP4 IS2_HKO_L2_DMAC
161 #define IS2_HKL_IP4 1
162 #define IS2_HKO_L3_FRAGMENT (IS2_HKO_IP4 + IS2_HKL_IP4)
163 #define IS2_HKL_L3_FRAGMENT 1
164 #define IS2_HKO_L3_FRAG_OFS_GT0 (IS2_HKO_L3_FRAGMENT + IS2_HKL_L3_FRAGMENT)
165 #define IS2_HKL_L3_FRAG_OFS_GT0 1
166 #define IS2_HKO_L3_OPTIONS (IS2_HKO_L3_FRAG_OFS_GT0 + IS2_HKL_L3_FRAG_OFS_GT0)
167 #define IS2_HKL_L3_OPTIONS 1
168 #define IS2_HKO_L3_TTL_GT0 (IS2_HKO_L3_OPTIONS + IS2_HKL_L3_OPTIONS)
169 #define IS2_HKL_L3_TTL_GT0 1
170 #define IS2_HKO_L3_TOS (IS2_HKO_L3_TTL_GT0 + IS2_HKL_L3_TTL_GT0)
171 #define IS2_HKL_L3_TOS 8
172 #define IS2_HKO_L3_IP4_DIP (IS2_HKO_L3_TOS + IS2_HKL_L3_TOS)
173 #define IS2_HKL_L3_IP4_DIP 32
174 #define IS2_HKO_L3_IP4_SIP (IS2_HKO_L3_IP4_DIP + IS2_HKL_L3_IP4_DIP)
175 #define IS2_HKL_L3_IP4_SIP 32
176 #define IS2_HKO_DIP_EQ_SIP (IS2_HKO_L3_IP4_SIP + IS2_HKL_L3_IP4_SIP)
177 #define IS2_HKL_DIP_EQ_SIP 1
178 
179 /* IS2 half key - IP4_TCP_UDP */
180 #define IS2_HKO_IP4_TCP_UDP_TCP (IS2_HKO_DIP_EQ_SIP + IS2_HKL_DIP_EQ_SIP)
181 #define IS2_HKL_IP4_TCP_UDP_TCP 1
182 #define IS2_HKO_IP4_TCP_UDP_L4_DPORT                                           \
183 	(IS2_HKO_IP4_TCP_UDP_TCP + IS2_HKL_IP4_TCP_UDP_TCP)
184 #define IS2_HKL_IP4_TCP_UDP_L4_DPORT 16
185 #define IS2_HKO_IP4_TCP_UDP_L4_SPORT                                           \
186 	(IS2_HKO_IP4_TCP_UDP_L4_DPORT + IS2_HKL_IP4_TCP_UDP_L4_DPORT)
187 #define IS2_HKL_IP4_TCP_UDP_L4_SPORT 16
188 #define IS2_HKO_IP4_TCP_UDP_L4_RNG                                             \
189 	(IS2_HKO_IP4_TCP_UDP_L4_SPORT + IS2_HKL_IP4_TCP_UDP_L4_SPORT)
190 #define IS2_HKL_IP4_TCP_UDP_L4_RNG 8
191 #define IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT                                     \
192 	(IS2_HKO_IP4_TCP_UDP_L4_RNG + IS2_HKL_IP4_TCP_UDP_L4_RNG)
193 #define IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT 1
194 #define IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0                                       \
195 	(IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT +                                  \
196 	 IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT)
197 #define IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0 1
198 #define IS2_HKO_IP4_TCP_UDP_L4_FIN                                             \
199 	(IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0 + IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0)
200 #define IS2_HKL_IP4_TCP_UDP_L4_FIN 1
201 #define IS2_HKO_IP4_TCP_UDP_L4_SYN                                             \
202 	(IS2_HKO_IP4_TCP_UDP_L4_FIN + IS2_HKL_IP4_TCP_UDP_L4_FIN)
203 #define IS2_HKL_IP4_TCP_UDP_L4_SYN 1
204 #define IS2_HKO_IP4_TCP_UDP_L4_RST                                             \
205 	(IS2_HKO_IP4_TCP_UDP_L4_SYN + IS2_HKL_IP4_TCP_UDP_L4_SYN)
206 #define IS2_HKL_IP4_TCP_UDP_L4_RST 1
207 #define IS2_HKO_IP4_TCP_UDP_L4_PSH                                             \
208 	(IS2_HKO_IP4_TCP_UDP_L4_RST + IS2_HKL_IP4_TCP_UDP_L4_RST)
209 #define IS2_HKL_IP4_TCP_UDP_L4_PSH 1
210 #define IS2_HKO_IP4_TCP_UDP_L4_ACK                                             \
211 	(IS2_HKO_IP4_TCP_UDP_L4_PSH + IS2_HKL_IP4_TCP_UDP_L4_PSH)
212 #define IS2_HKL_IP4_TCP_UDP_L4_ACK 1
213 #define IS2_HKO_IP4_TCP_UDP_L4_URG                                             \
214 	(IS2_HKO_IP4_TCP_UDP_L4_ACK + IS2_HKL_IP4_TCP_UDP_L4_ACK)
215 #define IS2_HKL_IP4_TCP_UDP_L4_URG 1
216 #define IS2_HKO_IP4_TCP_UDP_L4_1588_DOM                                        \
217 	(IS2_HKO_IP4_TCP_UDP_L4_URG + IS2_HKL_IP4_TCP_UDP_L4_URG)
218 #define IS2_HKL_IP4_TCP_UDP_L4_1588_DOM 8
219 #define IS2_HKO_IP4_TCP_UDP_L4_1588_VER                                        \
220 	(IS2_HKO_IP4_TCP_UDP_L4_1588_DOM + IS2_HKL_IP4_TCP_UDP_L4_1588_DOM)
221 #define IS2_HKL_IP4_TCP_UDP_L4_1588_VER 4
222 
223 /* IS2 half key - IP4_OTHER */
224 #define IS2_HKO_IP4_OTHER_L3_PROTO IS2_HKO_IP4_TCP_UDP_TCP
225 #define IS2_HKL_IP4_OTHER_L3_PROTO 8
226 #define IS2_HKO_IP4_OTHER_L3_PAYLOAD                                           \
227 	(IS2_HKO_IP4_OTHER_L3_PROTO + IS2_HKL_IP4_OTHER_L3_PROTO)
228 #define IS2_HKL_IP4_OTHER_L3_PAYLOAD 56
229 
230 /* IS2 half key - IP6_STD */
231 #define IS2_HKO_IP6_STD_L3_TTL_GT0 IS2_HKO_L2_DMAC
232 #define IS2_HKL_IP6_STD_L3_TTL_GT0 1
233 #define IS2_HKO_IP6_STD_L3_IP6_SIP                                             \
234 	(IS2_HKO_IP6_STD_L3_TTL_GT0 + IS2_HKL_IP6_STD_L3_TTL_GT0)
235 #define IS2_HKL_IP6_STD_L3_IP6_SIP 128
236 #define IS2_HKO_IP6_STD_L3_PROTO                                               \
237 	(IS2_HKO_IP6_STD_L3_IP6_SIP + IS2_HKL_IP6_STD_L3_IP6_SIP)
238 #define IS2_HKL_IP6_STD_L3_PROTO 8
239 
240 /* IS2 half key - OAM */
241 #define IS2_HKO_OAM_OAM_MEL_FLAGS IS2_HKO_MAC_ETYPE_ETYPE
242 #define IS2_HKL_OAM_OAM_MEL_FLAGS 7
243 #define IS2_HKO_OAM_OAM_VER                                                    \
244 	(IS2_HKO_OAM_OAM_MEL_FLAGS + IS2_HKL_OAM_OAM_MEL_FLAGS)
245 #define IS2_HKL_OAM_OAM_VER 5
246 #define IS2_HKO_OAM_OAM_OPCODE (IS2_HKO_OAM_OAM_VER + IS2_HKL_OAM_OAM_VER)
247 #define IS2_HKL_OAM_OAM_OPCODE 8
248 #define IS2_HKO_OAM_OAM_FLAGS (IS2_HKO_OAM_OAM_OPCODE + IS2_HKL_OAM_OAM_OPCODE)
249 #define IS2_HKL_OAM_OAM_FLAGS 8
250 #define IS2_HKO_OAM_OAM_MEPID (IS2_HKO_OAM_OAM_FLAGS + IS2_HKL_OAM_OAM_FLAGS)
251 #define IS2_HKL_OAM_OAM_MEPID 16
252 #define IS2_HKO_OAM_OAM_CCM_CNTS_EQ0                                           \
253 	(IS2_HKO_OAM_OAM_MEPID + IS2_HKL_OAM_OAM_MEPID)
254 #define IS2_HKL_OAM_OAM_CCM_CNTS_EQ0 1
255 
256 /* IS2 half key - SMAC_SIP6 */
257 #define IS2_HKO_SMAC_SIP6_IGR_PORT IS2_HKL_TYPE
258 #define IS2_HKL_SMAC_SIP6_IGR_PORT VCAP_PORT_WIDTH
259 #define IS2_HKO_SMAC_SIP6_L2_SMAC                                              \
260 	(IS2_HKO_SMAC_SIP6_IGR_PORT + IS2_HKL_SMAC_SIP6_IGR_PORT)
261 #define IS2_HKL_SMAC_SIP6_L2_SMAC 48
262 #define IS2_HKO_SMAC_SIP6_L3_IP6_SIP                                           \
263 	(IS2_HKO_SMAC_SIP6_L2_SMAC + IS2_HKL_SMAC_SIP6_L2_SMAC)
264 #define IS2_HKL_SMAC_SIP6_L3_IP6_SIP 128
265 
266 /* IS2 full key - common */
267 #define IS2_FKO_TYPE 0
268 #define IS2_FKL_TYPE 2
269 #define IS2_FKO_FIRST (IS2_FKO_TYPE + IS2_FKL_TYPE)
270 #define IS2_FKL_FIRST 1
271 #define IS2_FKO_PAG (IS2_FKO_FIRST + IS2_FKL_FIRST)
272 #define IS2_FKL_PAG 8
273 #define IS2_FKO_IGR_PORT_MASK (IS2_FKO_PAG + IS2_FKL_PAG)
274 #define IS2_FKL_IGR_PORT_MASK (VCAP_PORT_CNT + 1)
275 #define IS2_FKO_SERVICE_FRM (IS2_FKO_IGR_PORT_MASK + IS2_FKL_IGR_PORT_MASK)
276 #define IS2_FKL_SERVICE_FRM 1
277 #define IS2_FKO_HOST_MATCH (IS2_FKO_SERVICE_FRM + IS2_FKL_SERVICE_FRM)
278 #define IS2_FKL_HOST_MATCH 1
279 #define IS2_FKO_L2_MC (IS2_FKO_HOST_MATCH + IS2_FKL_HOST_MATCH)
280 #define IS2_FKL_L2_MC 1
281 #define IS2_FKO_L2_BC (IS2_FKO_L2_MC + IS2_FKL_L2_MC)
282 #define IS2_FKL_L2_BC 1
283 #define IS2_FKO_VLAN_TAGGED (IS2_FKO_L2_BC + IS2_FKL_L2_BC)
284 #define IS2_FKL_VLAN_TAGGED 1
285 #define IS2_FKO_VID (IS2_FKO_VLAN_TAGGED + IS2_FKL_VLAN_TAGGED)
286 #define IS2_FKL_VID 12
287 #define IS2_FKO_DEI (IS2_FKO_VID + IS2_FKL_VID)
288 #define IS2_FKL_DEI 1
289 #define IS2_FKO_PCP (IS2_FKO_DEI + IS2_FKL_DEI)
290 #define IS2_FKL_PCP 3
291 
292 /* IS2 full key - IP6_TCP_UDP/IP6_OTHER common */
293 #define IS2_FKO_L3_TTL_GT0 (IS2_FKO_PCP + IS2_FKL_PCP)
294 #define IS2_FKL_L3_TTL_GT0 1
295 #define IS2_FKO_L3_TOS (IS2_FKO_L3_TTL_GT0 + IS2_FKL_L3_TTL_GT0)
296 #define IS2_FKL_L3_TOS 8
297 #define IS2_FKO_L3_IP6_DIP (IS2_FKO_L3_TOS + IS2_FKL_L3_TOS)
298 #define IS2_FKL_L3_IP6_DIP 128
299 #define IS2_FKO_L3_IP6_SIP (IS2_FKO_L3_IP6_DIP + IS2_FKL_L3_IP6_DIP)
300 #define IS2_FKL_L3_IP6_SIP 128
301 #define IS2_FKO_DIP_EQ_SIP (IS2_FKO_L3_IP6_SIP + IS2_FKL_L3_IP6_SIP)
302 #define IS2_FKL_DIP_EQ_SIP 1
303 
304 /* IS2 full key - IP6_TCP_UDP */
305 #define IS2_FKO_IP6_TCP_UDP_TCP (IS2_FKO_DIP_EQ_SIP + IS2_FKL_DIP_EQ_SIP)
306 #define IS2_FKL_IP6_TCP_UDP_TCP 1
307 #define IS2_FKO_IP6_TCP_UDP_L4_DPORT                                           \
308 	(IS2_FKO_IP6_TCP_UDP_TCP + IS2_FKL_IP6_TCP_UDP_TCP)
309 #define IS2_FKL_IP6_TCP_UDP_L4_DPORT 16
310 #define IS2_FKO_IP6_TCP_UDP_L4_SPORT                                           \
311 	(IS2_FKO_IP6_TCP_UDP_L4_DPORT + IS2_FKL_IP6_TCP_UDP_L4_DPORT)
312 #define IS2_FKL_IP6_TCP_UDP_L4_SPORT 16
313 #define IS2_FKO_IP6_TCP_UDP_L4_RNG                                             \
314 	(IS2_FKO_IP6_TCP_UDP_L4_SPORT + IS2_FKL_IP6_TCP_UDP_L4_SPORT)
315 #define IS2_FKL_IP6_TCP_UDP_L4_RNG 8
316 #define IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT                                     \
317 	(IS2_FKO_IP6_TCP_UDP_L4_RNG + IS2_FKL_IP6_TCP_UDP_L4_RNG)
318 #define IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT 1
319 #define IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0                                       \
320 	(IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT +                                  \
321 	 IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT)
322 #define IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0 1
323 #define IS2_FKO_IP6_TCP_UDP_L4_FIN                                             \
324 	(IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0 + IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0)
325 #define IS2_FKL_IP6_TCP_UDP_L4_FIN 1
326 #define IS2_FKO_IP6_TCP_UDP_L4_SYN                                             \
327 	(IS2_FKO_IP6_TCP_UDP_L4_FIN + IS2_FKL_IP6_TCP_UDP_L4_FIN)
328 #define IS2_FKL_IP6_TCP_UDP_L4_SYN 1
329 #define IS2_FKO_IP6_TCP_UDP_L4_RST                                             \
330 	(IS2_FKO_IP6_TCP_UDP_L4_SYN + IS2_FKL_IP6_TCP_UDP_L4_SYN)
331 #define IS2_FKL_IP6_TCP_UDP_L4_RST 1
332 #define IS2_FKO_IP6_TCP_UDP_L4_PSH                                             \
333 	(IS2_FKO_IP6_TCP_UDP_L4_RST + IS2_FKL_IP6_TCP_UDP_L4_RST)
334 #define IS2_FKL_IP6_TCP_UDP_L4_PSH 1
335 #define IS2_FKO_IP6_TCP_UDP_L4_ACK                                             \
336 	(IS2_FKO_IP6_TCP_UDP_L4_PSH + IS2_FKL_IP6_TCP_UDP_L4_PSH)
337 #define IS2_FKL_IP6_TCP_UDP_L4_ACK 1
338 #define IS2_FKO_IP6_TCP_UDP_L4_URG                                             \
339 	(IS2_FKO_IP6_TCP_UDP_L4_ACK + IS2_FKL_IP6_TCP_UDP_L4_ACK)
340 #define IS2_FKL_IP6_TCP_UDP_L4_URG 1
341 #define IS2_FKO_IP6_TCP_UDP_L4_1588_DOM                                        \
342 	(IS2_FKO_IP6_TCP_UDP_L4_URG + IS2_FKL_IP6_TCP_UDP_L4_URG)
343 #define IS2_FKL_IP6_TCP_UDP_L4_1588_DOM 8
344 #define IS2_FKO_IP6_TCP_UDP_L4_1588_VER                                        \
345 	(IS2_FKO_IP6_TCP_UDP_L4_1588_DOM + IS2_FKL_IP6_TCP_UDP_L4_1588_DOM)
346 #define IS2_FKL_IP6_TCP_UDP_L4_1588_VER 4
347 
348 /* IS2 full key - IP6_OTHER */
349 #define IS2_FKO_IP6_OTHER_L3_PROTO IS2_FKO_IP6_TCP_UDP_TCP
350 #define IS2_FKL_IP6_OTHER_L3_PROTO 8
351 #define IS2_FKO_IP6_OTHER_L3_PAYLOAD                                           \
352 	(IS2_FKO_IP6_OTHER_L3_PROTO + IS2_FKL_IP6_OTHER_L3_PROTO)
353 #define IS2_FKL_IP6_OTHER_L3_PAYLOAD 56
354 
355 /* IS2 full key - CUSTOM */
356 #define IS2_FKO_CUSTOM_CUSTOM_TYPE IS2_FKO_L3_TTL_GT0
357 #define IS2_FKL_CUSTOM_CUSTOM_TYPE 1
358 #define IS2_FKO_CUSTOM_CUSTOM                                                  \
359 	(IS2_FKO_CUSTOM_CUSTOM_TYPE + IS2_FKL_CUSTOM_CUSTOM_TYPE)
360 #define IS2_FKL_CUSTOM_CUSTOM 320
361 
362 /* IS2 action - BASE_TYPE */
363 #define IS2_AO_HIT_ME_ONCE 0
364 #define IS2_AL_HIT_ME_ONCE 1
365 #define IS2_AO_CPU_COPY_ENA (IS2_AO_HIT_ME_ONCE + IS2_AL_HIT_ME_ONCE)
366 #define IS2_AL_CPU_COPY_ENA 1
367 #define IS2_AO_CPU_QU_NUM (IS2_AO_CPU_COPY_ENA + IS2_AL_CPU_COPY_ENA)
368 #define IS2_AL_CPU_QU_NUM 3
369 #define IS2_AO_MASK_MODE (IS2_AO_CPU_QU_NUM + IS2_AL_CPU_QU_NUM)
370 #define IS2_AL_MASK_MODE 2
371 #define IS2_AO_MIRROR_ENA (IS2_AO_MASK_MODE + IS2_AL_MASK_MODE)
372 #define IS2_AL_MIRROR_ENA 1
373 #define IS2_AO_LRN_DIS (IS2_AO_MIRROR_ENA + IS2_AL_MIRROR_ENA)
374 #define IS2_AL_LRN_DIS 1
375 #define IS2_AO_POLICE_ENA (IS2_AO_LRN_DIS + IS2_AL_LRN_DIS)
376 #define IS2_AL_POLICE_ENA 1
377 #define IS2_AO_POLICE_IDX (IS2_AO_POLICE_ENA + IS2_AL_POLICE_ENA)
378 #define IS2_AL_POLICE_IDX 9
379 #define IS2_AO_POLICE_VCAP_ONLY (IS2_AO_POLICE_IDX + IS2_AL_POLICE_IDX)
380 #define IS2_AL_POLICE_VCAP_ONLY 1
381 #define IS2_AO_PORT_MASK (IS2_AO_POLICE_VCAP_ONLY + IS2_AL_POLICE_VCAP_ONLY)
382 #define IS2_AL_PORT_MASK VCAP_PORT_CNT
383 #define IS2_AO_REW_OP (IS2_AO_PORT_MASK + IS2_AL_PORT_MASK)
384 #define IS2_AL_REW_OP 9
385 #define IS2_AO_LM_CNT_DIS (IS2_AO_REW_OP + IS2_AL_REW_OP)
386 #define IS2_AL_LM_CNT_DIS 1
387 #define IS2_AO_ISDX_ENA                                                        \
388 	(IS2_AO_LM_CNT_DIS + IS2_AL_LM_CNT_DIS + 1) /* Reserved bit */
389 #define IS2_AL_ISDX_ENA 1
390 #define IS2_AO_ACL_ID (IS2_AO_ISDX_ENA + IS2_AL_ISDX_ENA)
391 #define IS2_AL_ACL_ID 6
392 
393 /* IS2 action - SMAC_SIP */
394 #define IS2_AO_SMAC_SIP_CPU_COPY_ENA 0
395 #define IS2_AL_SMAC_SIP_CPU_COPY_ENA 1
396 #define IS2_AO_SMAC_SIP_CPU_QU_NUM 1
397 #define IS2_AL_SMAC_SIP_CPU_QU_NUM 3
398 #define IS2_AO_SMAC_SIP_FWD_KILL_ENA 4
399 #define IS2_AL_SMAC_SIP_FWD_KILL_ENA 1
400 #define IS2_AO_SMAC_SIP_HOST_MATCH 5
401 #define IS2_AL_SMAC_SIP_HOST_MATCH 1
402 
403 #endif /* _OCELOT_VCAP_H_ */
404