1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 #include <linux/proc_fs.h> 8 9 #include <soc/mscc/ocelot_vcap.h> 10 #include "ocelot_police.h" 11 #include "ocelot_vcap.h" 12 13 #define ENTRY_WIDTH 32 14 15 enum vcap_sel { 16 VCAP_SEL_ENTRY = 0x1, 17 VCAP_SEL_ACTION = 0x2, 18 VCAP_SEL_COUNTER = 0x4, 19 VCAP_SEL_ALL = 0x7, 20 }; 21 22 enum vcap_cmd { 23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */ 24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */ 25 VCAP_CMD_MOVE_UP = 2, /* Move <count> up */ 26 VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */ 27 VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */ 28 }; 29 30 #define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */ 31 #define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */ 32 33 struct vcap_data { 34 u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */ 35 u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */ 36 u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */ 37 u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */ 38 u32 tg; /* TG_DAT */ 39 u32 type; /* Action type */ 40 u32 tg_sw; /* Current type-group */ 41 u32 cnt; /* Current counter */ 42 u32 key_offset; /* Current entry offset */ 43 u32 action_offset; /* Current action offset */ 44 u32 counter_offset; /* Current counter offset */ 45 u32 tg_value; /* Current type-group value */ 46 u32 tg_mask; /* Current type-group mask */ 47 }; 48 49 static u32 vcap_read_update_ctrl(struct ocelot *ocelot, 50 const struct vcap_props *vcap) 51 { 52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); 53 } 54 55 static void vcap_cmd(struct ocelot *ocelot, const struct vcap_props *vcap, 56 u16 ix, int cmd, int sel) 57 { 58 u32 value = (VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) | 59 VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) | 60 VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT); 61 62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) 63 return; 64 65 if (!(sel & VCAP_SEL_ENTRY)) 66 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS; 67 68 if (!(sel & VCAP_SEL_ACTION)) 69 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS; 70 71 if (!(sel & VCAP_SEL_COUNTER)) 72 value |= VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS; 73 74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); 75 76 read_poll_timeout(vcap_read_update_ctrl, value, 77 (value & VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0, 78 10, 100000, false, ocelot, vcap); 79 } 80 81 /* Convert from 0-based row to VCAP entry row and run command */ 82 static void vcap_row_cmd(struct ocelot *ocelot, const struct vcap_props *vcap, 83 u32 row, int cmd, int sel) 84 { 85 vcap_cmd(ocelot, vcap, vcap->entry_count - row - 1, cmd, sel); 86 } 87 88 static void vcap_entry2cache(struct ocelot *ocelot, 89 const struct vcap_props *vcap, 90 struct vcap_data *data) 91 { 92 u32 entry_words, i; 93 94 entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH); 95 96 for (i = 0; i < entry_words; i++) { 97 ocelot_target_write_rix(ocelot, vcap->target, data->entry[i], 98 VCAP_CACHE_ENTRY_DAT, i); 99 ocelot_target_write_rix(ocelot, vcap->target, ~data->mask[i], 100 VCAP_CACHE_MASK_DAT, i); 101 } 102 ocelot_target_write(ocelot, vcap->target, data->tg, VCAP_CACHE_TG_DAT); 103 } 104 105 static void vcap_cache2entry(struct ocelot *ocelot, 106 const struct vcap_props *vcap, 107 struct vcap_data *data) 108 { 109 u32 entry_words, i; 110 111 entry_words = DIV_ROUND_UP(vcap->entry_width, ENTRY_WIDTH); 112 113 for (i = 0; i < entry_words; i++) { 114 data->entry[i] = ocelot_target_read_rix(ocelot, vcap->target, 115 VCAP_CACHE_ENTRY_DAT, i); 116 // Invert mask 117 data->mask[i] = ~ocelot_target_read_rix(ocelot, vcap->target, 118 VCAP_CACHE_MASK_DAT, i); 119 } 120 data->tg = ocelot_target_read(ocelot, vcap->target, VCAP_CACHE_TG_DAT); 121 } 122 123 static void vcap_action2cache(struct ocelot *ocelot, 124 const struct vcap_props *vcap, 125 struct vcap_data *data) 126 { 127 u32 action_words, mask; 128 int i, width; 129 130 /* Encode action type */ 131 width = vcap->action_type_width; 132 if (width) { 133 mask = GENMASK(width, 0); 134 data->action[0] = ((data->action[0] & ~mask) | data->type); 135 } 136 137 action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH); 138 139 for (i = 0; i < action_words; i++) 140 ocelot_target_write_rix(ocelot, vcap->target, data->action[i], 141 VCAP_CACHE_ACTION_DAT, i); 142 143 for (i = 0; i < vcap->counter_words; i++) 144 ocelot_target_write_rix(ocelot, vcap->target, data->counter[i], 145 VCAP_CACHE_CNT_DAT, i); 146 } 147 148 static void vcap_cache2action(struct ocelot *ocelot, 149 const struct vcap_props *vcap, 150 struct vcap_data *data) 151 { 152 u32 action_words; 153 int i, width; 154 155 action_words = DIV_ROUND_UP(vcap->action_width, ENTRY_WIDTH); 156 157 for (i = 0; i < action_words; i++) 158 data->action[i] = ocelot_target_read_rix(ocelot, vcap->target, 159 VCAP_CACHE_ACTION_DAT, 160 i); 161 162 for (i = 0; i < vcap->counter_words; i++) 163 data->counter[i] = ocelot_target_read_rix(ocelot, vcap->target, 164 VCAP_CACHE_CNT_DAT, 165 i); 166 167 /* Extract action type */ 168 width = vcap->action_type_width; 169 data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0); 170 } 171 172 /* Calculate offsets for entry */ 173 static void vcap_data_offset_get(const struct vcap_props *vcap, 174 struct vcap_data *data, int ix) 175 { 176 int num_subwords_per_entry, num_subwords_per_action; 177 int i, col, offset, num_entries_per_row, base; 178 u32 width = vcap->tg_width; 179 180 switch (data->tg_sw) { 181 case VCAP_TG_FULL: 182 num_entries_per_row = 1; 183 break; 184 case VCAP_TG_HALF: 185 num_entries_per_row = 2; 186 break; 187 case VCAP_TG_QUARTER: 188 num_entries_per_row = 4; 189 break; 190 default: 191 return; 192 } 193 194 col = (ix % num_entries_per_row); 195 num_subwords_per_entry = (vcap->sw_count / num_entries_per_row); 196 base = (vcap->sw_count - col * num_subwords_per_entry - 197 num_subwords_per_entry); 198 data->tg_value = 0; 199 data->tg_mask = 0; 200 for (i = 0; i < num_subwords_per_entry; i++) { 201 offset = ((base + i) * width); 202 data->tg_value |= (data->tg_sw << offset); 203 data->tg_mask |= GENMASK(offset + width - 1, offset); 204 } 205 206 /* Calculate key/action/counter offsets */ 207 col = (num_entries_per_row - col - 1); 208 data->key_offset = (base * vcap->entry_width) / vcap->sw_count; 209 data->counter_offset = (num_subwords_per_entry * col * 210 vcap->counter_width); 211 i = data->type; 212 width = vcap->action_table[i].width; 213 num_subwords_per_action = vcap->action_table[i].count; 214 data->action_offset = ((num_subwords_per_action * col * width) / 215 num_entries_per_row); 216 data->action_offset += vcap->action_type_width; 217 } 218 219 static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value) 220 { 221 u32 i, v, m; 222 223 for (i = 0; i < len; i++, offset++) { 224 v = data[offset / ENTRY_WIDTH]; 225 m = (1 << (offset % ENTRY_WIDTH)); 226 if (value & (1 << i)) 227 v |= m; 228 else 229 v &= ~m; 230 data[offset / ENTRY_WIDTH] = v; 231 } 232 } 233 234 static u32 vcap_data_get(u32 *data, u32 offset, u32 len) 235 { 236 u32 i, v, m, value = 0; 237 238 for (i = 0; i < len; i++, offset++) { 239 v = data[offset / ENTRY_WIDTH]; 240 m = (1 << (offset % ENTRY_WIDTH)); 241 if (v & m) 242 value |= (1 << i); 243 } 244 return value; 245 } 246 247 static void vcap_key_field_set(struct vcap_data *data, u32 offset, u32 width, 248 u32 value, u32 mask) 249 { 250 vcap_data_set(data->entry, offset + data->key_offset, width, value); 251 vcap_data_set(data->mask, offset + data->key_offset, width, mask); 252 } 253 254 static void vcap_key_set(const struct vcap_props *vcap, struct vcap_data *data, 255 int field, u32 value, u32 mask) 256 { 257 u32 offset = vcap->keys[field].offset; 258 u32 length = vcap->keys[field].length; 259 260 vcap_key_field_set(data, offset, length, value, mask); 261 } 262 263 static void vcap_key_bytes_set(const struct vcap_props *vcap, 264 struct vcap_data *data, int field, 265 u8 *val, u8 *msk) 266 { 267 u32 offset = vcap->keys[field].offset; 268 u32 count = vcap->keys[field].length; 269 u32 i, j, n = 0, value = 0, mask = 0; 270 271 WARN_ON(count % 8); 272 273 /* Data wider than 32 bits are split up in chunks of maximum 32 bits. 274 * The 32 LSB of the data are written to the 32 MSB of the TCAM. 275 */ 276 offset += count; 277 count /= 8; 278 279 for (i = 0; i < count; i++) { 280 j = (count - i - 1); 281 value += (val[j] << n); 282 mask += (msk[j] << n); 283 n += 8; 284 if (n == ENTRY_WIDTH || (i + 1) == count) { 285 offset -= n; 286 vcap_key_field_set(data, offset, n, value, mask); 287 n = 0; 288 value = 0; 289 mask = 0; 290 } 291 } 292 } 293 294 static void vcap_key_l4_port_set(const struct vcap_props *vcap, 295 struct vcap_data *data, int field, 296 struct ocelot_vcap_udp_tcp *port) 297 { 298 u32 offset = vcap->keys[field].offset; 299 u32 length = vcap->keys[field].length; 300 301 WARN_ON(length != 16); 302 303 vcap_key_field_set(data, offset, length, port->value, port->mask); 304 } 305 306 static void vcap_key_bit_set(const struct vcap_props *vcap, 307 struct vcap_data *data, int field, 308 enum ocelot_vcap_bit val) 309 { 310 u32 value = (val == OCELOT_VCAP_BIT_1 ? 1 : 0); 311 u32 msk = (val == OCELOT_VCAP_BIT_ANY ? 0 : 1); 312 u32 offset = vcap->keys[field].offset; 313 u32 length = vcap->keys[field].length; 314 315 WARN_ON(length != 1); 316 317 vcap_key_field_set(data, offset, length, value, msk); 318 } 319 320 static void vcap_action_set(const struct vcap_props *vcap, 321 struct vcap_data *data, int field, u32 value) 322 { 323 int offset = vcap->actions[field].offset; 324 int length = vcap->actions[field].length; 325 326 vcap_data_set(data->action, offset + data->action_offset, length, 327 value); 328 } 329 330 static void is2_action_set(struct ocelot *ocelot, struct vcap_data *data, 331 struct ocelot_vcap_filter *filter) 332 { 333 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2]; 334 struct ocelot_vcap_action *a = &filter->action; 335 336 vcap_action_set(vcap, data, VCAP_IS2_ACT_MASK_MODE, a->mask_mode); 337 vcap_action_set(vcap, data, VCAP_IS2_ACT_PORT_MASK, a->port_mask); 338 vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_ENA, a->police_ena); 339 vcap_action_set(vcap, data, VCAP_IS2_ACT_POLICE_IDX, a->pol_ix); 340 vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_QU_NUM, a->cpu_qu_num); 341 vcap_action_set(vcap, data, VCAP_IS2_ACT_CPU_COPY_ENA, a->cpu_copy_ena); 342 } 343 344 static void is2_entry_set(struct ocelot *ocelot, int ix, 345 struct ocelot_vcap_filter *filter) 346 { 347 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS2]; 348 struct ocelot_vcap_key_vlan *tag = &filter->vlan; 349 u32 val, msk, type, type_mask = 0xf, i, count; 350 struct ocelot_vcap_u64 payload; 351 struct vcap_data data; 352 int row = (ix / 2); 353 354 memset(&payload, 0, sizeof(payload)); 355 memset(&data, 0, sizeof(data)); 356 357 /* Read row */ 358 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL); 359 vcap_cache2entry(ocelot, vcap, &data); 360 vcap_cache2action(ocelot, vcap, &data); 361 362 data.tg_sw = VCAP_TG_HALF; 363 vcap_data_offset_get(vcap, &data, ix); 364 data.tg = (data.tg & ~data.tg_mask); 365 if (filter->prio != 0) 366 data.tg |= data.tg_value; 367 368 data.type = IS2_ACTION_TYPE_NORMAL; 369 370 vcap_key_set(vcap, &data, VCAP_IS2_HK_PAG, filter->pag, 0xff); 371 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_FIRST, 372 (filter->lookup == 0) ? OCELOT_VCAP_BIT_1 : 373 OCELOT_VCAP_BIT_0); 374 vcap_key_set(vcap, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0, 375 ~filter->ingress_port_mask); 376 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_FIRST, OCELOT_VCAP_BIT_ANY); 377 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_HOST_MATCH, 378 OCELOT_VCAP_BIT_ANY); 379 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_MC, filter->dmac_mc); 380 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L2_BC, filter->dmac_bc); 381 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_VLAN_TAGGED, tag->tagged); 382 vcap_key_set(vcap, &data, VCAP_IS2_HK_VID, 383 tag->vid.value, tag->vid.mask); 384 vcap_key_set(vcap, &data, VCAP_IS2_HK_PCP, 385 tag->pcp.value[0], tag->pcp.mask[0]); 386 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DEI, tag->dei); 387 388 switch (filter->key_type) { 389 case OCELOT_VCAP_KEY_ETYPE: { 390 struct ocelot_vcap_key_etype *etype = &filter->key.etype; 391 392 type = IS2_TYPE_ETYPE; 393 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC, 394 etype->dmac.value, etype->dmac.mask); 395 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC, 396 etype->smac.value, etype->smac.mask); 397 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_ETYPE, 398 etype->etype.value, etype->etype.mask); 399 /* Clear unused bits */ 400 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 401 0, 0); 402 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 403 0, 0); 404 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 405 0, 0); 406 vcap_key_bytes_set(vcap, &data, 407 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 408 etype->data.value, etype->data.mask); 409 break; 410 } 411 case OCELOT_VCAP_KEY_LLC: { 412 struct ocelot_vcap_key_llc *llc = &filter->key.llc; 413 414 type = IS2_TYPE_LLC; 415 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC, 416 llc->dmac.value, llc->dmac.mask); 417 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC, 418 llc->smac.value, llc->smac.mask); 419 for (i = 0; i < 4; i++) { 420 payload.value[i] = llc->llc.value[i]; 421 payload.mask[i] = llc->llc.mask[i]; 422 } 423 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_LLC_L2_LLC, 424 payload.value, payload.mask); 425 break; 426 } 427 case OCELOT_VCAP_KEY_SNAP: { 428 struct ocelot_vcap_key_snap *snap = &filter->key.snap; 429 430 type = IS2_TYPE_SNAP; 431 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_DMAC, 432 snap->dmac.value, snap->dmac.mask); 433 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L2_SMAC, 434 snap->smac.value, snap->smac.mask); 435 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 436 filter->key.snap.snap.value, 437 filter->key.snap.snap.mask); 438 break; 439 } 440 case OCELOT_VCAP_KEY_ARP: { 441 struct ocelot_vcap_key_arp *arp = &filter->key.arp; 442 443 type = IS2_TYPE_ARP; 444 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_SMAC, 445 arp->smac.value, arp->smac.mask); 446 vcap_key_bit_set(vcap, &data, 447 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 448 arp->ethernet); 449 vcap_key_bit_set(vcap, &data, 450 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 451 arp->ip); 452 vcap_key_bit_set(vcap, &data, 453 VCAP_IS2_HK_MAC_ARP_LEN_OK, 454 arp->length); 455 vcap_key_bit_set(vcap, &data, 456 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 457 arp->dmac_match); 458 vcap_key_bit_set(vcap, &data, 459 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 460 arp->smac_match); 461 vcap_key_bit_set(vcap, &data, 462 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 463 arp->unknown); 464 465 /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */ 466 val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) | 467 (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0)); 468 msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) | 469 (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2)); 470 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_OPCODE, 471 val, msk); 472 vcap_key_bytes_set(vcap, &data, 473 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 474 arp->dip.value.addr, arp->dip.mask.addr); 475 vcap_key_bytes_set(vcap, &data, 476 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 477 arp->sip.value.addr, arp->sip.mask.addr); 478 vcap_key_set(vcap, &data, VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 479 0, 0); 480 break; 481 } 482 case OCELOT_VCAP_KEY_IPV4: 483 case OCELOT_VCAP_KEY_IPV6: { 484 enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp; 485 enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg; 486 enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh; 487 struct ocelot_vcap_key_ipv4 *ipv4 = NULL; 488 struct ocelot_vcap_key_ipv6 *ipv6 = NULL; 489 struct ocelot_vcap_udp_tcp *sport, *dport; 490 struct ocelot_vcap_ipv4 sip, dip; 491 struct ocelot_vcap_u8 proto, ds; 492 struct ocelot_vcap_u48 *ip_data; 493 494 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) { 495 ipv4 = &filter->key.ipv4; 496 ttl = ipv4->ttl; 497 fragment = ipv4->fragment; 498 options = ipv4->options; 499 proto = ipv4->proto; 500 ds = ipv4->ds; 501 ip_data = &ipv4->data; 502 sip = ipv4->sip; 503 dip = ipv4->dip; 504 sport = &ipv4->sport; 505 dport = &ipv4->dport; 506 tcp_fin = ipv4->tcp_fin; 507 tcp_syn = ipv4->tcp_syn; 508 tcp_rst = ipv4->tcp_rst; 509 tcp_psh = ipv4->tcp_psh; 510 tcp_ack = ipv4->tcp_ack; 511 tcp_urg = ipv4->tcp_urg; 512 sip_eq_dip = ipv4->sip_eq_dip; 513 sport_eq_dport = ipv4->sport_eq_dport; 514 seq_zero = ipv4->seq_zero; 515 } else { 516 ipv6 = &filter->key.ipv6; 517 ttl = ipv6->ttl; 518 fragment = OCELOT_VCAP_BIT_ANY; 519 options = OCELOT_VCAP_BIT_ANY; 520 proto = ipv6->proto; 521 ds = ipv6->ds; 522 ip_data = &ipv6->data; 523 for (i = 0; i < 8; i++) { 524 val = ipv6->sip.value[i + 8]; 525 msk = ipv6->sip.mask[i + 8]; 526 if (i < 4) { 527 dip.value.addr[i] = val; 528 dip.mask.addr[i] = msk; 529 } else { 530 sip.value.addr[i - 4] = val; 531 sip.mask.addr[i - 4] = msk; 532 } 533 } 534 sport = &ipv6->sport; 535 dport = &ipv6->dport; 536 tcp_fin = ipv6->tcp_fin; 537 tcp_syn = ipv6->tcp_syn; 538 tcp_rst = ipv6->tcp_rst; 539 tcp_psh = ipv6->tcp_psh; 540 tcp_ack = ipv6->tcp_ack; 541 tcp_urg = ipv6->tcp_urg; 542 sip_eq_dip = ipv6->sip_eq_dip; 543 sport_eq_dport = ipv6->sport_eq_dport; 544 seq_zero = ipv6->seq_zero; 545 } 546 547 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4, 548 ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 549 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_FRAGMENT, 550 fragment); 551 vcap_key_set(vcap, &data, VCAP_IS2_HK_L3_FRAG_OFS_GT0, 0, 0); 552 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L3_OPTIONS, 553 options); 554 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_IP4_L3_TTL_GT0, 555 ttl); 556 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_TOS, 557 ds.value, ds.mask); 558 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_DIP, 559 dip.value.addr, dip.mask.addr); 560 vcap_key_bytes_set(vcap, &data, VCAP_IS2_HK_L3_IP4_SIP, 561 sip.value.addr, sip.mask.addr); 562 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_DIP_EQ_SIP, 563 sip_eq_dip); 564 val = proto.value[0]; 565 msk = proto.mask[0]; 566 type = IS2_TYPE_IP_UDP_TCP; 567 if (msk == 0xff && (val == 6 || val == 17)) { 568 /* UDP/TCP protocol match */ 569 tcp = (val == 6 ? 570 OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 571 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_TCP, tcp); 572 vcap_key_l4_port_set(vcap, &data, 573 VCAP_IS2_HK_L4_DPORT, dport); 574 vcap_key_l4_port_set(vcap, &data, 575 VCAP_IS2_HK_L4_SPORT, sport); 576 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_RNG, 0, 0); 577 vcap_key_bit_set(vcap, &data, 578 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 579 sport_eq_dport); 580 vcap_key_bit_set(vcap, &data, 581 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 582 seq_zero); 583 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_FIN, 584 tcp_fin); 585 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_SYN, 586 tcp_syn); 587 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_RST, 588 tcp_rst); 589 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_PSH, 590 tcp_psh); 591 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_ACK, 592 tcp_ack); 593 vcap_key_bit_set(vcap, &data, VCAP_IS2_HK_L4_URG, 594 tcp_urg); 595 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_DOM, 596 0, 0); 597 vcap_key_set(vcap, &data, VCAP_IS2_HK_L4_1588_VER, 598 0, 0); 599 } else { 600 if (msk == 0) { 601 /* Any IP protocol match */ 602 type_mask = IS2_TYPE_MASK_IP_ANY; 603 } else { 604 /* Non-UDP/TCP protocol match */ 605 type = IS2_TYPE_IP_OTHER; 606 for (i = 0; i < 6; i++) { 607 payload.value[i] = ip_data->value[i]; 608 payload.mask[i] = ip_data->mask[i]; 609 } 610 } 611 vcap_key_bytes_set(vcap, &data, 612 VCAP_IS2_HK_IP4_L3_PROTO, 613 proto.value, proto.mask); 614 vcap_key_bytes_set(vcap, &data, 615 VCAP_IS2_HK_L3_PAYLOAD, 616 payload.value, payload.mask); 617 } 618 break; 619 } 620 case OCELOT_VCAP_KEY_ANY: 621 default: 622 type = 0; 623 type_mask = 0; 624 count = vcap->entry_width / 2; 625 /* Iterate over the non-common part of the key and 626 * clear entry data 627 */ 628 for (i = vcap->keys[VCAP_IS2_HK_L2_DMAC].offset; 629 i < count; i += ENTRY_WIDTH) { 630 vcap_key_field_set(&data, i, min(32u, count - i), 0, 0); 631 } 632 break; 633 } 634 635 vcap_key_set(vcap, &data, VCAP_IS2_TYPE, type, type_mask); 636 is2_action_set(ocelot, &data, filter); 637 vcap_data_set(data.counter, data.counter_offset, 638 vcap->counter_width, filter->stats.pkts); 639 640 /* Write row */ 641 vcap_entry2cache(ocelot, vcap, &data); 642 vcap_action2cache(ocelot, vcap, &data); 643 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL); 644 } 645 646 static void is1_action_set(struct ocelot *ocelot, struct vcap_data *data, 647 const struct ocelot_vcap_filter *filter) 648 { 649 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS1]; 650 const struct ocelot_vcap_action *a = &filter->action; 651 652 vcap_action_set(vcap, data, VCAP_IS1_ACT_VID_REPLACE_ENA, 653 a->vid_replace_ena); 654 vcap_action_set(vcap, data, VCAP_IS1_ACT_VID_ADD_VAL, a->vid); 655 vcap_action_set(vcap, data, VCAP_IS1_ACT_VLAN_POP_CNT_ENA, 656 a->vlan_pop_cnt_ena); 657 vcap_action_set(vcap, data, VCAP_IS1_ACT_VLAN_POP_CNT, 658 a->vlan_pop_cnt); 659 vcap_action_set(vcap, data, VCAP_IS1_ACT_PCP_DEI_ENA, a->pcp_dei_ena); 660 vcap_action_set(vcap, data, VCAP_IS1_ACT_PCP_VAL, a->pcp); 661 vcap_action_set(vcap, data, VCAP_IS1_ACT_DEI_VAL, a->dei); 662 vcap_action_set(vcap, data, VCAP_IS1_ACT_QOS_ENA, a->qos_ena); 663 vcap_action_set(vcap, data, VCAP_IS1_ACT_QOS_VAL, a->qos_val); 664 vcap_action_set(vcap, data, VCAP_IS1_ACT_PAG_OVERRIDE_MASK, 665 a->pag_override_mask); 666 vcap_action_set(vcap, data, VCAP_IS1_ACT_PAG_VAL, a->pag_val); 667 } 668 669 static void is1_entry_set(struct ocelot *ocelot, int ix, 670 struct ocelot_vcap_filter *filter) 671 { 672 const struct vcap_props *vcap = &ocelot->vcap[VCAP_IS1]; 673 struct ocelot_vcap_key_vlan *tag = &filter->vlan; 674 struct ocelot_vcap_u64 payload; 675 struct vcap_data data; 676 int row = ix / 2; 677 u32 type; 678 679 memset(&payload, 0, sizeof(payload)); 680 memset(&data, 0, sizeof(data)); 681 682 /* Read row */ 683 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL); 684 vcap_cache2entry(ocelot, vcap, &data); 685 vcap_cache2action(ocelot, vcap, &data); 686 687 data.tg_sw = VCAP_TG_HALF; 688 data.type = IS1_ACTION_TYPE_NORMAL; 689 vcap_data_offset_get(vcap, &data, ix); 690 data.tg = (data.tg & ~data.tg_mask); 691 if (filter->prio != 0) 692 data.tg |= data.tg_value; 693 694 vcap_key_set(vcap, &data, VCAP_IS1_HK_LOOKUP, filter->lookup, 0x3); 695 vcap_key_set(vcap, &data, VCAP_IS1_HK_IGR_PORT_MASK, 0, 696 ~filter->ingress_port_mask); 697 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_L2_MC, filter->dmac_mc); 698 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_L2_BC, filter->dmac_bc); 699 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_VLAN_TAGGED, tag->tagged); 700 vcap_key_set(vcap, &data, VCAP_IS1_HK_VID, 701 tag->vid.value, tag->vid.mask); 702 vcap_key_set(vcap, &data, VCAP_IS1_HK_PCP, 703 tag->pcp.value[0], tag->pcp.mask[0]); 704 type = IS1_TYPE_S1_NORMAL; 705 706 switch (filter->key_type) { 707 case OCELOT_VCAP_KEY_ETYPE: { 708 struct ocelot_vcap_key_etype *etype = &filter->key.etype; 709 710 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_L2_SMAC, 711 etype->smac.value, etype->smac.mask); 712 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_ETYPE, 713 etype->etype.value, etype->etype.mask); 714 break; 715 } 716 case OCELOT_VCAP_KEY_IPV4: { 717 struct ocelot_vcap_key_ipv4 *ipv4 = &filter->key.ipv4; 718 struct ocelot_vcap_udp_tcp *sport = &ipv4->sport; 719 struct ocelot_vcap_udp_tcp *dport = &ipv4->dport; 720 enum ocelot_vcap_bit tcp_udp = OCELOT_VCAP_BIT_0; 721 struct ocelot_vcap_u8 proto = ipv4->proto; 722 struct ocelot_vcap_ipv4 sip = ipv4->sip; 723 u32 val, msk; 724 725 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_IP_SNAP, 726 OCELOT_VCAP_BIT_1); 727 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_IP4, 728 OCELOT_VCAP_BIT_1); 729 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_ETYPE_LEN, 730 OCELOT_VCAP_BIT_1); 731 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_L3_IP4_SIP, 732 sip.value.addr, sip.mask.addr); 733 734 val = proto.value[0]; 735 msk = proto.mask[0]; 736 737 if ((val == NEXTHDR_TCP || val == NEXTHDR_UDP) && msk == 0xff) 738 tcp_udp = OCELOT_VCAP_BIT_1; 739 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TCP_UDP, tcp_udp); 740 741 if (tcp_udp) { 742 enum ocelot_vcap_bit tcp = OCELOT_VCAP_BIT_0; 743 744 if (val == NEXTHDR_TCP) 745 tcp = OCELOT_VCAP_BIT_1; 746 747 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TCP, tcp); 748 vcap_key_l4_port_set(vcap, &data, VCAP_IS1_HK_L4_SPORT, 749 sport); 750 /* Overloaded field */ 751 vcap_key_l4_port_set(vcap, &data, VCAP_IS1_HK_ETYPE, 752 dport); 753 } else { 754 /* IPv4 "other" frame */ 755 struct ocelot_vcap_u16 etype = {0}; 756 757 /* Overloaded field */ 758 etype.value[0] = proto.value[0]; 759 etype.mask[0] = proto.mask[0]; 760 761 vcap_key_bytes_set(vcap, &data, VCAP_IS1_HK_ETYPE, 762 etype.value, etype.mask); 763 } 764 } 765 default: 766 break; 767 } 768 vcap_key_bit_set(vcap, &data, VCAP_IS1_HK_TYPE, 769 type ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 770 771 is1_action_set(ocelot, &data, filter); 772 vcap_data_set(data.counter, data.counter_offset, 773 vcap->counter_width, filter->stats.pkts); 774 775 /* Write row */ 776 vcap_entry2cache(ocelot, vcap, &data); 777 vcap_action2cache(ocelot, vcap, &data); 778 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL); 779 } 780 781 static void es0_action_set(struct ocelot *ocelot, struct vcap_data *data, 782 const struct ocelot_vcap_filter *filter) 783 { 784 const struct vcap_props *vcap = &ocelot->vcap[VCAP_ES0]; 785 const struct ocelot_vcap_action *a = &filter->action; 786 787 vcap_action_set(vcap, data, VCAP_ES0_ACT_PUSH_OUTER_TAG, 788 a->push_outer_tag); 789 vcap_action_set(vcap, data, VCAP_ES0_ACT_PUSH_INNER_TAG, 790 a->push_inner_tag); 791 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_TPID_SEL, 792 a->tag_a_tpid_sel); 793 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_VID_SEL, 794 a->tag_a_vid_sel); 795 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_A_PCP_SEL, 796 a->tag_a_pcp_sel); 797 vcap_action_set(vcap, data, VCAP_ES0_ACT_VID_A_VAL, a->vid_a_val); 798 vcap_action_set(vcap, data, VCAP_ES0_ACT_PCP_A_VAL, a->pcp_a_val); 799 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_TPID_SEL, 800 a->tag_b_tpid_sel); 801 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_VID_SEL, 802 a->tag_b_vid_sel); 803 vcap_action_set(vcap, data, VCAP_ES0_ACT_TAG_B_PCP_SEL, 804 a->tag_b_pcp_sel); 805 vcap_action_set(vcap, data, VCAP_ES0_ACT_VID_B_VAL, a->vid_b_val); 806 vcap_action_set(vcap, data, VCAP_ES0_ACT_PCP_B_VAL, a->pcp_b_val); 807 } 808 809 static void es0_entry_set(struct ocelot *ocelot, int ix, 810 struct ocelot_vcap_filter *filter) 811 { 812 const struct vcap_props *vcap = &ocelot->vcap[VCAP_ES0]; 813 struct ocelot_vcap_key_vlan *tag = &filter->vlan; 814 struct ocelot_vcap_u64 payload; 815 struct vcap_data data; 816 int row = ix; 817 818 memset(&payload, 0, sizeof(payload)); 819 memset(&data, 0, sizeof(data)); 820 821 /* Read row */ 822 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_ALL); 823 vcap_cache2entry(ocelot, vcap, &data); 824 vcap_cache2action(ocelot, vcap, &data); 825 826 data.tg_sw = VCAP_TG_FULL; 827 data.type = ES0_ACTION_TYPE_NORMAL; 828 vcap_data_offset_get(vcap, &data, ix); 829 data.tg = (data.tg & ~data.tg_mask); 830 if (filter->prio != 0) 831 data.tg |= data.tg_value; 832 833 vcap_key_set(vcap, &data, VCAP_ES0_IGR_PORT, filter->ingress_port.value, 834 filter->ingress_port.mask); 835 vcap_key_set(vcap, &data, VCAP_ES0_EGR_PORT, filter->egress_port.value, 836 filter->egress_port.mask); 837 vcap_key_bit_set(vcap, &data, VCAP_ES0_L2_MC, filter->dmac_mc); 838 vcap_key_bit_set(vcap, &data, VCAP_ES0_L2_BC, filter->dmac_bc); 839 vcap_key_set(vcap, &data, VCAP_ES0_VID, 840 tag->vid.value, tag->vid.mask); 841 vcap_key_set(vcap, &data, VCAP_ES0_PCP, 842 tag->pcp.value[0], tag->pcp.mask[0]); 843 844 es0_action_set(ocelot, &data, filter); 845 vcap_data_set(data.counter, data.counter_offset, 846 vcap->counter_width, filter->stats.pkts); 847 848 /* Write row */ 849 vcap_entry2cache(ocelot, vcap, &data); 850 vcap_action2cache(ocelot, vcap, &data); 851 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_WRITE, VCAP_SEL_ALL); 852 } 853 854 static void vcap_entry_get(struct ocelot *ocelot, int ix, 855 struct ocelot_vcap_filter *filter) 856 { 857 const struct vcap_props *vcap = &ocelot->vcap[filter->block_id]; 858 struct vcap_data data; 859 int row, count; 860 u32 cnt; 861 862 if (filter->block_id == VCAP_ES0) 863 data.tg_sw = VCAP_TG_FULL; 864 else 865 data.tg_sw = VCAP_TG_HALF; 866 867 count = (1 << (data.tg_sw - 1)); 868 row = (ix / count); 869 vcap_row_cmd(ocelot, vcap, row, VCAP_CMD_READ, VCAP_SEL_COUNTER); 870 vcap_cache2action(ocelot, vcap, &data); 871 vcap_data_offset_get(vcap, &data, ix); 872 cnt = vcap_data_get(data.counter, data.counter_offset, 873 vcap->counter_width); 874 875 filter->stats.pkts = cnt; 876 } 877 878 static void vcap_entry_set(struct ocelot *ocelot, int ix, 879 struct ocelot_vcap_filter *filter) 880 { 881 if (filter->block_id == VCAP_IS1) 882 return is1_entry_set(ocelot, ix, filter); 883 if (filter->block_id == VCAP_IS2) 884 return is2_entry_set(ocelot, ix, filter); 885 if (filter->block_id == VCAP_ES0) 886 return es0_entry_set(ocelot, ix, filter); 887 } 888 889 static int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 890 struct ocelot_policer *pol) 891 { 892 struct qos_policer_conf pp = { 0 }; 893 894 if (!pol) 895 return -EINVAL; 896 897 pp.mode = MSCC_QOS_RATE_MODE_DATA; 898 pp.pir = pol->rate; 899 pp.pbs = pol->burst; 900 901 return qos_policer_conf_set(ocelot, 0, pol_ix, &pp); 902 } 903 904 static void ocelot_vcap_policer_del(struct ocelot *ocelot, 905 struct ocelot_vcap_block *block, 906 u32 pol_ix) 907 { 908 struct ocelot_vcap_filter *filter; 909 struct qos_policer_conf pp = {0}; 910 int index = -1; 911 912 if (pol_ix < block->pol_lpr) 913 return; 914 915 list_for_each_entry(filter, &block->rules, list) { 916 index++; 917 if (filter->block_id == VCAP_IS2 && 918 filter->action.police_ena && 919 filter->action.pol_ix < pol_ix) { 920 filter->action.pol_ix += 1; 921 ocelot_vcap_policer_add(ocelot, filter->action.pol_ix, 922 &filter->action.pol); 923 is2_entry_set(ocelot, index, filter); 924 } 925 } 926 927 pp.mode = MSCC_QOS_RATE_MODE_DISABLED; 928 qos_policer_conf_set(ocelot, 0, pol_ix, &pp); 929 930 block->pol_lpr++; 931 } 932 933 static void ocelot_vcap_filter_add_to_block(struct ocelot *ocelot, 934 struct ocelot_vcap_block *block, 935 struct ocelot_vcap_filter *filter) 936 { 937 struct ocelot_vcap_filter *tmp; 938 struct list_head *pos, *n; 939 940 if (filter->block_id == VCAP_IS2 && filter->action.police_ena) { 941 block->pol_lpr--; 942 filter->action.pol_ix = block->pol_lpr; 943 ocelot_vcap_policer_add(ocelot, filter->action.pol_ix, 944 &filter->action.pol); 945 } 946 947 block->count++; 948 949 if (list_empty(&block->rules)) { 950 list_add(&filter->list, &block->rules); 951 return; 952 } 953 954 list_for_each_safe(pos, n, &block->rules) { 955 tmp = list_entry(pos, struct ocelot_vcap_filter, list); 956 if (filter->prio < tmp->prio) 957 break; 958 } 959 list_add(&filter->list, pos->prev); 960 } 961 962 static bool ocelot_vcap_filter_equal(const struct ocelot_vcap_filter *a, 963 const struct ocelot_vcap_filter *b) 964 { 965 return !memcmp(&a->id, &b->id, sizeof(struct ocelot_vcap_id)); 966 } 967 968 static int ocelot_vcap_block_get_filter_index(struct ocelot_vcap_block *block, 969 struct ocelot_vcap_filter *filter) 970 { 971 struct ocelot_vcap_filter *tmp; 972 int index = 0; 973 974 list_for_each_entry(tmp, &block->rules, list) { 975 if (ocelot_vcap_filter_equal(filter, tmp)) 976 return index; 977 index++; 978 } 979 980 return -ENOENT; 981 } 982 983 static struct ocelot_vcap_filter* 984 ocelot_vcap_block_find_filter_by_index(struct ocelot_vcap_block *block, 985 int index) 986 { 987 struct ocelot_vcap_filter *tmp; 988 int i = 0; 989 990 list_for_each_entry(tmp, &block->rules, list) { 991 if (i == index) 992 return tmp; 993 ++i; 994 } 995 996 return NULL; 997 } 998 999 struct ocelot_vcap_filter * 1000 ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, int cookie, 1001 bool tc_offload) 1002 { 1003 struct ocelot_vcap_filter *filter; 1004 1005 list_for_each_entry(filter, &block->rules, list) 1006 if (filter->id.tc_offload == tc_offload && 1007 filter->id.cookie == cookie) 1008 return filter; 1009 1010 return NULL; 1011 } 1012 EXPORT_SYMBOL(ocelot_vcap_block_find_filter_by_id); 1013 1014 /* If @on=false, then SNAP, ARP, IP and OAM frames will not match on keys based 1015 * on destination and source MAC addresses, but only on higher-level protocol 1016 * information. The only frame types to match on keys containing MAC addresses 1017 * in this case are non-SNAP, non-ARP, non-IP and non-OAM frames. 1018 * 1019 * If @on=true, then the above frame types (SNAP, ARP, IP and OAM) will match 1020 * on MAC_ETYPE keys such as destination and source MAC on this ingress port. 1021 * However the setting has the side effect of making these frames not matching 1022 * on any _other_ keys than MAC_ETYPE ones. 1023 */ 1024 static void ocelot_match_all_as_mac_etype(struct ocelot *ocelot, int port, 1025 int lookup, bool on) 1026 { 1027 u32 val = 0; 1028 1029 if (on) 1030 val = ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(BIT(lookup)) | 1031 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(BIT(lookup)) | 1032 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(BIT(lookup)) | 1033 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(BIT(lookup)) | 1034 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(BIT(lookup)); 1035 1036 ocelot_rmw_gix(ocelot, val, 1037 ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(BIT(lookup)) | 1038 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(BIT(lookup)) | 1039 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(BIT(lookup)) | 1040 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(BIT(lookup)) | 1041 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(BIT(lookup)), 1042 ANA_PORT_VCAP_S2_CFG, port); 1043 } 1044 1045 static bool 1046 ocelot_vcap_is_problematic_mac_etype(struct ocelot_vcap_filter *filter) 1047 { 1048 u16 proto, mask; 1049 1050 if (filter->key_type != OCELOT_VCAP_KEY_ETYPE) 1051 return false; 1052 1053 proto = ntohs(*(__be16 *)filter->key.etype.etype.value); 1054 mask = ntohs(*(__be16 *)filter->key.etype.etype.mask); 1055 1056 /* ETH_P_ALL match, so all protocols below are included */ 1057 if (mask == 0) 1058 return true; 1059 if (proto == ETH_P_ARP) 1060 return true; 1061 if (proto == ETH_P_IP) 1062 return true; 1063 if (proto == ETH_P_IPV6) 1064 return true; 1065 1066 return false; 1067 } 1068 1069 static bool 1070 ocelot_vcap_is_problematic_non_mac_etype(struct ocelot_vcap_filter *filter) 1071 { 1072 if (filter->key_type == OCELOT_VCAP_KEY_SNAP) 1073 return true; 1074 if (filter->key_type == OCELOT_VCAP_KEY_ARP) 1075 return true; 1076 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) 1077 return true; 1078 if (filter->key_type == OCELOT_VCAP_KEY_IPV6) 1079 return true; 1080 return false; 1081 } 1082 1083 static bool 1084 ocelot_exclusive_mac_etype_filter_rules(struct ocelot *ocelot, 1085 struct ocelot_vcap_filter *filter) 1086 { 1087 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id]; 1088 struct ocelot_vcap_filter *tmp; 1089 unsigned long port; 1090 int i; 1091 1092 /* We only have the S2_IP_TCPUDP_DIS set of knobs for VCAP IS2 */ 1093 if (filter->block_id != VCAP_IS2) 1094 return true; 1095 1096 if (ocelot_vcap_is_problematic_mac_etype(filter)) { 1097 /* Search for any non-MAC_ETYPE rules on the port */ 1098 for (i = 0; i < block->count; i++) { 1099 tmp = ocelot_vcap_block_find_filter_by_index(block, i); 1100 if (tmp->ingress_port_mask & filter->ingress_port_mask && 1101 tmp->lookup == filter->lookup && 1102 ocelot_vcap_is_problematic_non_mac_etype(tmp)) 1103 return false; 1104 } 1105 1106 for_each_set_bit(port, &filter->ingress_port_mask, 1107 ocelot->num_phys_ports) 1108 ocelot_match_all_as_mac_etype(ocelot, port, 1109 filter->lookup, true); 1110 } else if (ocelot_vcap_is_problematic_non_mac_etype(filter)) { 1111 /* Search for any MAC_ETYPE rules on the port */ 1112 for (i = 0; i < block->count; i++) { 1113 tmp = ocelot_vcap_block_find_filter_by_index(block, i); 1114 if (tmp->ingress_port_mask & filter->ingress_port_mask && 1115 tmp->lookup == filter->lookup && 1116 ocelot_vcap_is_problematic_mac_etype(tmp)) 1117 return false; 1118 } 1119 1120 for_each_set_bit(port, &filter->ingress_port_mask, 1121 ocelot->num_phys_ports) 1122 ocelot_match_all_as_mac_etype(ocelot, port, 1123 filter->lookup, false); 1124 } 1125 1126 return true; 1127 } 1128 1129 int ocelot_vcap_filter_add(struct ocelot *ocelot, 1130 struct ocelot_vcap_filter *filter, 1131 struct netlink_ext_ack *extack) 1132 { 1133 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id]; 1134 int i, index; 1135 1136 if (!ocelot_exclusive_mac_etype_filter_rules(ocelot, filter)) { 1137 NL_SET_ERR_MSG_MOD(extack, 1138 "Cannot mix MAC_ETYPE with non-MAC_ETYPE rules, use the other IS2 lookup"); 1139 return -EBUSY; 1140 } 1141 1142 /* Add filter to the linked list */ 1143 ocelot_vcap_filter_add_to_block(ocelot, block, filter); 1144 1145 /* Get the index of the inserted filter */ 1146 index = ocelot_vcap_block_get_filter_index(block, filter); 1147 if (index < 0) 1148 return index; 1149 1150 /* Move down the rules to make place for the new filter */ 1151 for (i = block->count - 1; i > index; i--) { 1152 struct ocelot_vcap_filter *tmp; 1153 1154 tmp = ocelot_vcap_block_find_filter_by_index(block, i); 1155 vcap_entry_set(ocelot, i, tmp); 1156 } 1157 1158 /* Now insert the new filter */ 1159 vcap_entry_set(ocelot, index, filter); 1160 return 0; 1161 } 1162 EXPORT_SYMBOL(ocelot_vcap_filter_add); 1163 1164 static void ocelot_vcap_block_remove_filter(struct ocelot *ocelot, 1165 struct ocelot_vcap_block *block, 1166 struct ocelot_vcap_filter *filter) 1167 { 1168 struct ocelot_vcap_filter *tmp; 1169 struct list_head *pos, *q; 1170 1171 list_for_each_safe(pos, q, &block->rules) { 1172 tmp = list_entry(pos, struct ocelot_vcap_filter, list); 1173 if (ocelot_vcap_filter_equal(filter, tmp)) { 1174 if (tmp->block_id == VCAP_IS2 && 1175 tmp->action.police_ena) 1176 ocelot_vcap_policer_del(ocelot, block, 1177 tmp->action.pol_ix); 1178 1179 list_del(pos); 1180 kfree(tmp); 1181 } 1182 } 1183 1184 block->count--; 1185 } 1186 1187 int ocelot_vcap_filter_del(struct ocelot *ocelot, 1188 struct ocelot_vcap_filter *filter) 1189 { 1190 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id]; 1191 struct ocelot_vcap_filter del_filter; 1192 int i, index; 1193 1194 memset(&del_filter, 0, sizeof(del_filter)); 1195 1196 /* Gets index of the filter */ 1197 index = ocelot_vcap_block_get_filter_index(block, filter); 1198 if (index < 0) 1199 return index; 1200 1201 /* Delete filter */ 1202 ocelot_vcap_block_remove_filter(ocelot, block, filter); 1203 1204 /* Move up all the blocks over the deleted filter */ 1205 for (i = index; i < block->count; i++) { 1206 struct ocelot_vcap_filter *tmp; 1207 1208 tmp = ocelot_vcap_block_find_filter_by_index(block, i); 1209 vcap_entry_set(ocelot, i, tmp); 1210 } 1211 1212 /* Now delete the last filter, because it is duplicated */ 1213 vcap_entry_set(ocelot, block->count, &del_filter); 1214 1215 return 0; 1216 } 1217 EXPORT_SYMBOL(ocelot_vcap_filter_del); 1218 1219 int ocelot_vcap_filter_stats_update(struct ocelot *ocelot, 1220 struct ocelot_vcap_filter *filter) 1221 { 1222 struct ocelot_vcap_block *block = &ocelot->block[filter->block_id]; 1223 struct ocelot_vcap_filter tmp; 1224 int index; 1225 1226 index = ocelot_vcap_block_get_filter_index(block, filter); 1227 if (index < 0) 1228 return index; 1229 1230 vcap_entry_get(ocelot, index, filter); 1231 1232 /* After we get the result we need to clear the counters */ 1233 tmp = *filter; 1234 tmp.stats.pkts = 0; 1235 vcap_entry_set(ocelot, index, &tmp); 1236 1237 return 0; 1238 } 1239 1240 static void ocelot_vcap_init_one(struct ocelot *ocelot, 1241 const struct vcap_props *vcap) 1242 { 1243 struct vcap_data data; 1244 1245 memset(&data, 0, sizeof(data)); 1246 1247 vcap_entry2cache(ocelot, vcap, &data); 1248 ocelot_target_write(ocelot, vcap->target, vcap->entry_count, 1249 VCAP_CORE_MV_CFG); 1250 vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY); 1251 1252 vcap_action2cache(ocelot, vcap, &data); 1253 ocelot_target_write(ocelot, vcap->target, vcap->action_count, 1254 VCAP_CORE_MV_CFG); 1255 vcap_cmd(ocelot, vcap, 0, VCAP_CMD_INITIALIZE, 1256 VCAP_SEL_ACTION | VCAP_SEL_COUNTER); 1257 } 1258 1259 static void ocelot_vcap_detect_constants(struct ocelot *ocelot, 1260 struct vcap_props *vcap) 1261 { 1262 int counter_memory_width; 1263 int num_default_actions; 1264 int version; 1265 1266 version = ocelot_target_read(ocelot, vcap->target, 1267 VCAP_CONST_VCAP_VER); 1268 /* Only version 0 VCAP supported for now */ 1269 if (WARN_ON(version != 0)) 1270 return; 1271 1272 /* Width in bits of type-group field */ 1273 vcap->tg_width = ocelot_target_read(ocelot, vcap->target, 1274 VCAP_CONST_ENTRY_TG_WIDTH); 1275 /* Number of subwords per TCAM row */ 1276 vcap->sw_count = ocelot_target_read(ocelot, vcap->target, 1277 VCAP_CONST_ENTRY_SWCNT); 1278 /* Number of rows in TCAM. There can be this many full keys, or double 1279 * this number half keys, or 4 times this number quarter keys. 1280 */ 1281 vcap->entry_count = ocelot_target_read(ocelot, vcap->target, 1282 VCAP_CONST_ENTRY_CNT); 1283 /* Assuming there are 4 subwords per TCAM row, their layout in the 1284 * actual TCAM (not in the cache) would be: 1285 * 1286 * | SW 3 | TG 3 | SW 2 | TG 2 | SW 1 | TG 1 | SW 0 | TG 0 | 1287 * 1288 * (where SW=subword and TG=Type-Group). 1289 * 1290 * What VCAP_CONST_ENTRY_CNT is giving us is the width of one full TCAM 1291 * row. But when software accesses the TCAM through the cache 1292 * registers, the Type-Group values are written through another set of 1293 * registers VCAP_TG_DAT, and therefore, it appears as though the 4 1294 * subwords are contiguous in the cache memory. 1295 * Important mention: regardless of the number of key entries per row 1296 * (and therefore of key size: 1 full key or 2 half keys or 4 quarter 1297 * keys), software always has to configure 4 Type-Group values. For 1298 * example, in the case of 1 full key, the driver needs to set all 4 1299 * Type-Group to be full key. 1300 * 1301 * For this reason, we need to fix up the value that the hardware is 1302 * giving us. We don't actually care about the width of the entry in 1303 * the TCAM. What we care about is the width of the entry in the cache 1304 * registers, which is how we get to interact with it. And since the 1305 * VCAP_ENTRY_DAT cache registers access only the subwords and not the 1306 * Type-Groups, this means we need to subtract the width of the 1307 * Type-Groups when packing and unpacking key entry data in a TCAM row. 1308 */ 1309 vcap->entry_width = ocelot_target_read(ocelot, vcap->target, 1310 VCAP_CONST_ENTRY_WIDTH); 1311 vcap->entry_width -= vcap->tg_width * vcap->sw_count; 1312 num_default_actions = ocelot_target_read(ocelot, vcap->target, 1313 VCAP_CONST_ACTION_DEF_CNT); 1314 vcap->action_count = vcap->entry_count + num_default_actions; 1315 vcap->action_width = ocelot_target_read(ocelot, vcap->target, 1316 VCAP_CONST_ACTION_WIDTH); 1317 /* The width of the counter memory, this is the complete width of all 1318 * counter-fields associated with one full-word entry. There is one 1319 * counter per entry sub-word (see CAP_CORE::ENTRY_SWCNT for number of 1320 * subwords.) 1321 */ 1322 vcap->counter_words = vcap->sw_count; 1323 counter_memory_width = ocelot_target_read(ocelot, vcap->target, 1324 VCAP_CONST_CNT_WIDTH); 1325 vcap->counter_width = counter_memory_width / vcap->counter_words; 1326 } 1327 1328 int ocelot_vcap_init(struct ocelot *ocelot) 1329 { 1330 int i; 1331 1332 /* Create a policer that will drop the frames for the cpu. 1333 * This policer will be used as action in the acl rules to drop 1334 * frames. 1335 */ 1336 ocelot_write_gix(ocelot, 0x299, ANA_POL_MODE_CFG, 1337 OCELOT_POLICER_DISCARD); 1338 ocelot_write_gix(ocelot, 0x1, ANA_POL_PIR_CFG, 1339 OCELOT_POLICER_DISCARD); 1340 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_PIR_STATE, 1341 OCELOT_POLICER_DISCARD); 1342 ocelot_write_gix(ocelot, 0x0, ANA_POL_CIR_CFG, 1343 OCELOT_POLICER_DISCARD); 1344 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_CIR_STATE, 1345 OCELOT_POLICER_DISCARD); 1346 1347 for (i = 0; i < OCELOT_NUM_VCAP_BLOCKS; i++) { 1348 struct ocelot_vcap_block *block = &ocelot->block[i]; 1349 struct vcap_props *vcap = &ocelot->vcap[i]; 1350 1351 INIT_LIST_HEAD(&block->rules); 1352 block->pol_lpr = OCELOT_POLICER_DISCARD - 1; 1353 1354 ocelot_vcap_detect_constants(ocelot, vcap); 1355 ocelot_vcap_init_one(ocelot, vcap); 1356 } 1357 1358 INIT_LIST_HEAD(&ocelot->dummy_rules); 1359 1360 return 0; 1361 } 1362