1a556c76aSAlexandre Belloni /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a556c76aSAlexandre Belloni /* 3a556c76aSAlexandre Belloni * Microsemi Ocelot Switch driver 4a556c76aSAlexandre Belloni * 5a556c76aSAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 6a556c76aSAlexandre Belloni */ 7a556c76aSAlexandre Belloni 8a556c76aSAlexandre Belloni #ifndef _MSCC_OCELOT_REW_H_ 9a556c76aSAlexandre Belloni #define _MSCC_OCELOT_REW_H_ 10a556c76aSAlexandre Belloni 11a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_GSZ 0x80 12a556c76aSAlexandre Belloni 13a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16)) 14a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16) 15a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16) 16a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_DEI BIT(15) 17a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12)) 18a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12) 19a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12) 20a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0)) 21a556c76aSAlexandre Belloni #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0) 22a556c76aSAlexandre Belloni 23a556c76aSAlexandre Belloni #define REW_TAG_CFG_GSZ 0x80 24a556c76aSAlexandre Belloni 25a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7)) 26a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7) 27a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_CFG_X(x) (((x) & GENMASK(8, 7)) >> 7) 28a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_TPID_CFG(x) (((x) << 5) & GENMASK(6, 5)) 29a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_TPID_CFG_M GENMASK(6, 5) 30a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_TPID_CFG_X(x) (((x) & GENMASK(6, 5)) >> 5) 31a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_VID_CFG BIT(4) 32a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_PCP_CFG(x) (((x) << 2) & GENMASK(3, 2)) 33a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_PCP_CFG_M GENMASK(3, 2) 34a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_PCP_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2) 35a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_DEI_CFG(x) ((x) & GENMASK(1, 0)) 36a556c76aSAlexandre Belloni #define REW_TAG_CFG_TAG_DEI_CFG_M GENMASK(1, 0) 37a556c76aSAlexandre Belloni 38a556c76aSAlexandre Belloni #define REW_PORT_CFG_GSZ 0x80 39a556c76aSAlexandre Belloni 40a556c76aSAlexandre Belloni #define REW_PORT_CFG_ES0_EN BIT(5) 41a556c76aSAlexandre Belloni #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG(x) (((x) << 3) & GENMASK(4, 3)) 42a556c76aSAlexandre Belloni #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M GENMASK(4, 3) 43a556c76aSAlexandre Belloni #define REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X(x) (((x) & GENMASK(4, 3)) >> 3) 44a556c76aSAlexandre Belloni #define REW_PORT_CFG_FCS_UPDATE_CPU_ENA BIT(2) 45a556c76aSAlexandre Belloni #define REW_PORT_CFG_FLUSH_ENA BIT(1) 46a556c76aSAlexandre Belloni #define REW_PORT_CFG_AGE_DIS BIT(0) 47a556c76aSAlexandre Belloni 48a556c76aSAlexandre Belloni #define REW_DSCP_CFG_GSZ 0x80 49a556c76aSAlexandre Belloni 50a556c76aSAlexandre Belloni #define REW_PCP_DEI_QOS_MAP_CFG_GSZ 0x80 51a556c76aSAlexandre Belloni #define REW_PCP_DEI_QOS_MAP_CFG_RSZ 0x4 52a556c76aSAlexandre Belloni 53a556c76aSAlexandre Belloni #define REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL BIT(3) 54a556c76aSAlexandre Belloni #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL(x) ((x) & GENMASK(2, 0)) 55a556c76aSAlexandre Belloni #define REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M GENMASK(2, 0) 56a556c76aSAlexandre Belloni 57a556c76aSAlexandre Belloni #define REW_PTP_CFG_GSZ 0x80 58a556c76aSAlexandre Belloni 59a556c76aSAlexandre Belloni #define REW_PTP_CFG_PTP_BACKPLANE_MODE BIT(7) 60a556c76aSAlexandre Belloni #define REW_PTP_CFG_GP_CFG_UNUSED(x) (((x) << 3) & GENMASK(6, 3)) 61a556c76aSAlexandre Belloni #define REW_PTP_CFG_GP_CFG_UNUSED_M GENMASK(6, 3) 62a556c76aSAlexandre Belloni #define REW_PTP_CFG_GP_CFG_UNUSED_X(x) (((x) & GENMASK(6, 3)) >> 3) 63a556c76aSAlexandre Belloni #define REW_PTP_CFG_PTP_1STEP_DIS BIT(2) 64a556c76aSAlexandre Belloni #define REW_PTP_CFG_PTP_2STEP_DIS BIT(1) 65a556c76aSAlexandre Belloni #define REW_PTP_CFG_PTP_UDP_KEEP BIT(0) 66a556c76aSAlexandre Belloni 67a556c76aSAlexandre Belloni #define REW_PTP_DLY1_CFG_GSZ 0x80 68a556c76aSAlexandre Belloni 69a556c76aSAlexandre Belloni #define REW_RED_TAG_CFG_GSZ 0x80 70a556c76aSAlexandre Belloni 71a556c76aSAlexandre Belloni #define REW_RED_TAG_CFG_RED_TAG_CFG BIT(0) 72a556c76aSAlexandre Belloni 73a556c76aSAlexandre Belloni #define REW_DSCP_REMAP_DP1_CFG_RSZ 0x4 74a556c76aSAlexandre Belloni 75a556c76aSAlexandre Belloni #define REW_DSCP_REMAP_CFG_RSZ 0x4 76a556c76aSAlexandre Belloni 77a556c76aSAlexandre Belloni #define REW_REW_STICKY_ES0_TAGB_PUSH_FAILED BIT(0) 78a556c76aSAlexandre Belloni 79a556c76aSAlexandre Belloni #define REW_PPT_RSZ 0x4 80a556c76aSAlexandre Belloni 81a556c76aSAlexandre Belloni #endif 82