1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /*
3  * Microsemi Ocelot Switch driver
4  *
5  * Copyright (c) 2017 Microsemi Corporation
6  */
7 
8 #ifndef _MSCC_OCELOT_QS_H_
9 #define _MSCC_OCELOT_QS_H_
10 
11 /* TODO handle BE */
12 #define XTR_EOF_0          0x00000080U
13 #define XTR_EOF_1          0x01000080U
14 #define XTR_EOF_2          0x02000080U
15 #define XTR_EOF_3          0x03000080U
16 #define XTR_PRUNED         0x04000080U
17 #define XTR_ABORT          0x05000080U
18 #define XTR_ESCAPE         0x06000080U
19 #define XTR_NOT_READY      0x07000080U
20 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
21 
22 #define QS_XTR_GRP_CFG_RSZ                                0x4
23 
24 #define QS_XTR_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
25 #define QS_XTR_GRP_CFG_MODE_M                             GENMASK(3, 2)
26 #define QS_XTR_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
27 #define QS_XTR_GRP_CFG_STATUS_WORD_POS                    BIT(1)
28 #define QS_XTR_GRP_CFG_BYTE_SWAP                          BIT(0)
29 
30 #define QS_XTR_RD_RSZ                                     0x4
31 
32 #define QS_XTR_FRM_PRUNING_RSZ                            0x4
33 
34 #define QS_XTR_CFG_DP_WM(x)                               (((x) << 5) & GENMASK(7, 5))
35 #define QS_XTR_CFG_DP_WM_M                                GENMASK(7, 5)
36 #define QS_XTR_CFG_DP_WM_X(x)                             (((x) & GENMASK(7, 5)) >> 5)
37 #define QS_XTR_CFG_SCH_WM(x)                              (((x) << 2) & GENMASK(4, 2))
38 #define QS_XTR_CFG_SCH_WM_M                               GENMASK(4, 2)
39 #define QS_XTR_CFG_SCH_WM_X(x)                            (((x) & GENMASK(4, 2)) >> 2)
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x)                     ((x) & GENMASK(1, 0))
41 #define QS_XTR_CFG_OFLW_ERR_STICKY_M                      GENMASK(1, 0)
42 
43 #define QS_INJ_GRP_CFG_RSZ                                0x4
44 
45 #define QS_INJ_GRP_CFG_MODE(x)                            (((x) << 2) & GENMASK(3, 2))
46 #define QS_INJ_GRP_CFG_MODE_M                             GENMASK(3, 2)
47 #define QS_INJ_GRP_CFG_MODE_X(x)                          (((x) & GENMASK(3, 2)) >> 2)
48 #define QS_INJ_GRP_CFG_BYTE_SWAP                          BIT(0)
49 
50 #define QS_INJ_WR_RSZ                                     0x4
51 
52 #define QS_INJ_CTRL_RSZ                                   0x4
53 
54 #define QS_INJ_CTRL_GAP_SIZE(x)                           (((x) << 21) & GENMASK(24, 21))
55 #define QS_INJ_CTRL_GAP_SIZE_M                            GENMASK(24, 21)
56 #define QS_INJ_CTRL_GAP_SIZE_X(x)                         (((x) & GENMASK(24, 21)) >> 21)
57 #define QS_INJ_CTRL_ABORT                                 BIT(20)
58 #define QS_INJ_CTRL_EOF                                   BIT(19)
59 #define QS_INJ_CTRL_SOF                                   BIT(18)
60 #define QS_INJ_CTRL_VLD_BYTES(x)                          (((x) << 16) & GENMASK(17, 16))
61 #define QS_INJ_CTRL_VLD_BYTES_M                           GENMASK(17, 16)
62 #define QS_INJ_CTRL_VLD_BYTES_X(x)                        (((x) & GENMASK(17, 16)) >> 16)
63 
64 #define QS_INJ_STATUS_WMARK_REACHED(x)                    (((x) << 4) & GENMASK(5, 4))
65 #define QS_INJ_STATUS_WMARK_REACHED_M                     GENMASK(5, 4)
66 #define QS_INJ_STATUS_WMARK_REACHED_X(x)                  (((x) & GENMASK(5, 4)) >> 4)
67 #define QS_INJ_STATUS_FIFO_RDY(x)                         (((x) << 2) & GENMASK(3, 2))
68 #define QS_INJ_STATUS_FIFO_RDY_M                          GENMASK(3, 2)
69 #define QS_INJ_STATUS_FIFO_RDY_X(x)                       (((x) & GENMASK(3, 2)) >> 2)
70 #define QS_INJ_STATUS_INJ_IN_PROGRESS(x)                  ((x) & GENMASK(1, 0))
71 #define QS_INJ_STATUS_INJ_IN_PROGRESS_M                   GENMASK(1, 0)
72 
73 #define QS_INJ_ERR_RSZ                                    0x4
74 
75 #define QS_INJ_ERR_ABORT_ERR_STICKY                       BIT(1)
76 #define QS_INJ_ERR_WR_ERR_STICKY                          BIT(0)
77 
78 #endif
79