1a556c76aSAlexandre Belloni /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a556c76aSAlexandre Belloni /* 3a556c76aSAlexandre Belloni * Microsemi Ocelot Switch driver 4a556c76aSAlexandre Belloni * 5a556c76aSAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 6a556c76aSAlexandre Belloni */ 7a556c76aSAlexandre Belloni 8a556c76aSAlexandre Belloni #ifndef _MSCC_OCELOT_QS_H_ 9a556c76aSAlexandre Belloni #define _MSCC_OCELOT_QS_H_ 10a556c76aSAlexandre Belloni 11a556c76aSAlexandre Belloni /* TODO handle BE */ 12a556c76aSAlexandre Belloni #define XTR_EOF_0 0x00000080U 13a556c76aSAlexandre Belloni #define XTR_EOF_1 0x01000080U 14a556c76aSAlexandre Belloni #define XTR_EOF_2 0x02000080U 15a556c76aSAlexandre Belloni #define XTR_EOF_3 0x03000080U 16a556c76aSAlexandre Belloni #define XTR_PRUNED 0x04000080U 17a556c76aSAlexandre Belloni #define XTR_ABORT 0x05000080U 18a556c76aSAlexandre Belloni #define XTR_ESCAPE 0x06000080U 19a556c76aSAlexandre Belloni #define XTR_NOT_READY 0x07000080U 20a556c76aSAlexandre Belloni #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) 21a556c76aSAlexandre Belloni 22a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_RSZ 0x4 23a556c76aSAlexandre Belloni 24a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 25a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2) 26a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 27a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 28a556c76aSAlexandre Belloni #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 29a556c76aSAlexandre Belloni 30a556c76aSAlexandre Belloni #define QS_XTR_RD_RSZ 0x4 31a556c76aSAlexandre Belloni 32a556c76aSAlexandre Belloni #define QS_XTR_FRM_PRUNING_RSZ 0x4 33a556c76aSAlexandre Belloni 34a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) 35a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5) 36a556c76aSAlexandre Belloni #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) 37a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) 38a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2) 39a556c76aSAlexandre Belloni #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) 40a556c76aSAlexandre Belloni #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) 41a556c76aSAlexandre Belloni #define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0) 42a556c76aSAlexandre Belloni 43a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_RSZ 0x4 44a556c76aSAlexandre Belloni 45a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) 46a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2) 47a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) 48a556c76aSAlexandre Belloni #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 49a556c76aSAlexandre Belloni 50a556c76aSAlexandre Belloni #define QS_INJ_WR_RSZ 0x4 51a556c76aSAlexandre Belloni 52a556c76aSAlexandre Belloni #define QS_INJ_CTRL_RSZ 0x4 53a556c76aSAlexandre Belloni 54a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21)) 55a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21) 56a556c76aSAlexandre Belloni #define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21) 57a556c76aSAlexandre Belloni #define QS_INJ_CTRL_ABORT BIT(20) 58a556c76aSAlexandre Belloni #define QS_INJ_CTRL_EOF BIT(19) 59a556c76aSAlexandre Belloni #define QS_INJ_CTRL_SOF BIT(18) 60a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16)) 61a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16) 62a556c76aSAlexandre Belloni #define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16) 63a556c76aSAlexandre Belloni 64a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4)) 65a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4) 66a556c76aSAlexandre Belloni #define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4) 67a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2)) 68a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2) 69a556c76aSAlexandre Belloni #define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2) 70a556c76aSAlexandre Belloni #define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0)) 71a556c76aSAlexandre Belloni #define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0) 72a556c76aSAlexandre Belloni 73a556c76aSAlexandre Belloni #define QS_INJ_ERR_RSZ 0x4 74a556c76aSAlexandre Belloni 75a556c76aSAlexandre Belloni #define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1) 76a556c76aSAlexandre Belloni #define QS_INJ_ERR_WR_ERR_STICKY BIT(0) 77a556c76aSAlexandre Belloni 78a556c76aSAlexandre Belloni #endif 79