1*753a026cSClément Léger /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*753a026cSClément Léger /* 3*753a026cSClément Léger * Microsemi SoCs FDMA driver 4*753a026cSClément Léger * 5*753a026cSClément Léger * Copyright (c) 2021 Microchip 6*753a026cSClément Léger */ 7*753a026cSClément Léger #ifndef _MSCC_OCELOT_FDMA_H_ 8*753a026cSClément Léger #define _MSCC_OCELOT_FDMA_H_ 9*753a026cSClément Léger 10*753a026cSClément Léger #include "ocelot.h" 11*753a026cSClément Léger 12*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_BLOCKO(x) (((x) << 20) & GENMASK(31, 20)) 13*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_BLOCKO_M GENMASK(31, 20) 14*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_BLOCKO_X(x) (((x) & GENMASK(31, 20)) >> 20) 15*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_PD BIT(19) 16*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_ABORT BIT(18) 17*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_EOF BIT(17) 18*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_SOF BIT(16) 19*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_BLOCKL_M GENMASK(15, 0) 20*753a026cSClément Léger #define MSCC_FDMA_DCB_STAT_BLOCKL(x) ((x) & GENMASK(15, 0)) 21*753a026cSClément Léger 22*753a026cSClément Léger #define MSCC_FDMA_DCB_LLP(x) ((x) * 4 + 0x0) 23*753a026cSClément Léger #define MSCC_FDMA_DCB_LLP_PREV(x) ((x) * 4 + 0xA0) 24*753a026cSClément Léger #define MSCC_FDMA_CH_SAFE 0xcc 25*753a026cSClément Léger #define MSCC_FDMA_CH_ACTIVATE 0xd0 26*753a026cSClément Léger #define MSCC_FDMA_CH_DISABLE 0xd4 27*753a026cSClément Léger #define MSCC_FDMA_CH_FORCEDIS 0xd8 28*753a026cSClément Léger #define MSCC_FDMA_EVT_ERR 0x164 29*753a026cSClément Léger #define MSCC_FDMA_EVT_ERR_CODE 0x168 30*753a026cSClément Léger #define MSCC_FDMA_INTR_LLP 0x16c 31*753a026cSClément Léger #define MSCC_FDMA_INTR_LLP_ENA 0x170 32*753a026cSClément Léger #define MSCC_FDMA_INTR_FRM 0x174 33*753a026cSClément Léger #define MSCC_FDMA_INTR_FRM_ENA 0x178 34*753a026cSClément Léger #define MSCC_FDMA_INTR_ENA 0x184 35*753a026cSClément Léger #define MSCC_FDMA_INTR_IDENT 0x188 36*753a026cSClément Léger 37*753a026cSClément Léger #define MSCC_FDMA_INJ_CHAN 2 38*753a026cSClément Léger #define MSCC_FDMA_XTR_CHAN 0 39*753a026cSClément Léger 40*753a026cSClément Léger #define OCELOT_FDMA_WEIGHT 32 41*753a026cSClément Léger 42*753a026cSClément Léger #define OCELOT_FDMA_CH_SAFE_TIMEOUT_US 10 43*753a026cSClément Léger 44*753a026cSClément Léger #define OCELOT_FDMA_RX_RING_SIZE 512 45*753a026cSClément Léger #define OCELOT_FDMA_TX_RING_SIZE 128 46*753a026cSClément Léger 47*753a026cSClément Léger #define OCELOT_FDMA_RX_DCB_SIZE (OCELOT_FDMA_RX_RING_SIZE * \ 48*753a026cSClément Léger sizeof(struct ocelot_fdma_dcb)) 49*753a026cSClément Léger #define OCELOT_FDMA_TX_DCB_SIZE (OCELOT_FDMA_TX_RING_SIZE * \ 50*753a026cSClément Léger sizeof(struct ocelot_fdma_dcb)) 51*753a026cSClément Léger /* +4 allows for word alignment after allocation */ 52*753a026cSClément Léger #define OCELOT_DCBS_HW_ALLOC_SIZE (OCELOT_FDMA_RX_DCB_SIZE + \ 53*753a026cSClément Léger OCELOT_FDMA_TX_DCB_SIZE + \ 54*753a026cSClément Léger 4) 55*753a026cSClément Léger 56*753a026cSClément Léger #define OCELOT_FDMA_RX_SIZE (PAGE_SIZE / 2) 57*753a026cSClément Léger 58*753a026cSClément Léger #define OCELOT_FDMA_SKBFRAG_OVR (4 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 59*753a026cSClément Léger #define OCELOT_FDMA_RXB_SIZE ALIGN_DOWN(OCELOT_FDMA_RX_SIZE - OCELOT_FDMA_SKBFRAG_OVR, 4) 60*753a026cSClément Léger #define OCELOT_FDMA_SKBFRAG_SIZE (OCELOT_FDMA_RXB_SIZE + OCELOT_FDMA_SKBFRAG_OVR) 61*753a026cSClément Léger 62*753a026cSClément Léger DECLARE_STATIC_KEY_FALSE(ocelot_fdma_enabled); 63*753a026cSClément Léger 64*753a026cSClément Léger struct ocelot_fdma_dcb { 65*753a026cSClément Léger u32 llp; 66*753a026cSClément Léger u32 datap; 67*753a026cSClément Léger u32 datal; 68*753a026cSClément Léger u32 stat; 69*753a026cSClément Léger } __packed; 70*753a026cSClément Léger 71*753a026cSClément Léger /** 72*753a026cSClément Léger * struct ocelot_fdma_tx_buf - TX buffer structure 73*753a026cSClément Léger * @skb: SKB currently used in the corresponding DCB. 74*753a026cSClément Léger * @dma_addr: SKB DMA mapped address. 75*753a026cSClément Léger */ 76*753a026cSClément Léger struct ocelot_fdma_tx_buf { 77*753a026cSClément Léger struct sk_buff *skb; 78*753a026cSClément Léger DEFINE_DMA_UNMAP_ADDR(dma_addr); 79*753a026cSClément Léger }; 80*753a026cSClément Léger 81*753a026cSClément Léger /** 82*753a026cSClément Léger * struct ocelot_fdma_tx_ring - TX ring description of DCBs 83*753a026cSClément Léger * 84*753a026cSClément Léger * @dcbs: DCBs allocated for the ring 85*753a026cSClément Léger * @dcbs_dma: DMA base address of the DCBs 86*753a026cSClément Léger * @bufs: List of TX buffer associated to the DCBs 87*753a026cSClément Léger * @xmit_lock: lock for concurrent xmit access 88*753a026cSClément Léger * @next_to_clean: Next DCB to be cleaned in tx_cleanup 89*753a026cSClément Léger * @next_to_use: Next available DCB to send SKB 90*753a026cSClément Léger */ 91*753a026cSClément Léger struct ocelot_fdma_tx_ring { 92*753a026cSClément Léger struct ocelot_fdma_dcb *dcbs; 93*753a026cSClément Léger dma_addr_t dcbs_dma; 94*753a026cSClément Léger struct ocelot_fdma_tx_buf bufs[OCELOT_FDMA_TX_RING_SIZE]; 95*753a026cSClément Léger /* Protect concurrent xmit calls */ 96*753a026cSClément Léger spinlock_t xmit_lock; 97*753a026cSClément Léger u16 next_to_clean; 98*753a026cSClément Léger u16 next_to_use; 99*753a026cSClément Léger }; 100*753a026cSClément Léger 101*753a026cSClément Léger /** 102*753a026cSClément Léger * struct ocelot_fdma_rx_buf - RX buffer structure 103*753a026cSClément Léger * @page: Struct page used in this buffer 104*753a026cSClément Léger * @page_offset: Current page offset (either 0 or PAGE_SIZE/2) 105*753a026cSClément Léger * @dma_addr: DMA address of the page 106*753a026cSClément Léger */ 107*753a026cSClément Léger struct ocelot_fdma_rx_buf { 108*753a026cSClément Léger struct page *page; 109*753a026cSClément Léger u32 page_offset; 110*753a026cSClément Léger dma_addr_t dma_addr; 111*753a026cSClément Léger }; 112*753a026cSClément Léger 113*753a026cSClément Léger /** 114*753a026cSClément Léger * struct ocelot_fdma_rx_ring - TX ring description of DCBs 115*753a026cSClément Léger * 116*753a026cSClément Léger * @dcbs: DCBs allocated for the ring 117*753a026cSClément Léger * @dcbs_dma: DMA base address of the DCBs 118*753a026cSClément Léger * @bufs: List of RX buffer associated to the DCBs 119*753a026cSClément Léger * @skb: SKB currently received by the netdev 120*753a026cSClément Léger * @next_to_clean: Next DCB to be cleaned NAPI polling 121*753a026cSClément Léger * @next_to_use: Next available DCB to send SKB 122*753a026cSClément Léger * @next_to_alloc: Next buffer that needs to be allocated (page reuse or alloc) 123*753a026cSClément Léger */ 124*753a026cSClément Léger struct ocelot_fdma_rx_ring { 125*753a026cSClément Léger struct ocelot_fdma_dcb *dcbs; 126*753a026cSClément Léger dma_addr_t dcbs_dma; 127*753a026cSClément Léger struct ocelot_fdma_rx_buf bufs[OCELOT_FDMA_RX_RING_SIZE]; 128*753a026cSClément Léger struct sk_buff *skb; 129*753a026cSClément Léger u16 next_to_clean; 130*753a026cSClément Léger u16 next_to_use; 131*753a026cSClément Léger u16 next_to_alloc; 132*753a026cSClément Léger }; 133*753a026cSClément Léger 134*753a026cSClément Léger /** 135*753a026cSClément Léger * struct ocelot_fdma - FDMA context 136*753a026cSClément Léger * 137*753a026cSClément Léger * @irq: FDMA interrupt 138*753a026cSClément Léger * @ndev: Net device used to initialize NAPI 139*753a026cSClément Léger * @dcbs_base: Memory coherent DCBs 140*753a026cSClément Léger * @dcbs_dma_base: DMA base address of memory coherent DCBs 141*753a026cSClément Léger * @tx_ring: Injection ring 142*753a026cSClément Léger * @rx_ring: Extraction ring 143*753a026cSClément Léger * @napi: NAPI context 144*753a026cSClément Léger * @ocelot: Back-pointer to ocelot struct 145*753a026cSClément Léger */ 146*753a026cSClément Léger struct ocelot_fdma { 147*753a026cSClément Léger int irq; 148*753a026cSClément Léger struct net_device *ndev; 149*753a026cSClément Léger struct ocelot_fdma_dcb *dcbs_base; 150*753a026cSClément Léger dma_addr_t dcbs_dma_base; 151*753a026cSClément Léger struct ocelot_fdma_tx_ring tx_ring; 152*753a026cSClément Léger struct ocelot_fdma_rx_ring rx_ring; 153*753a026cSClément Léger struct napi_struct napi; 154*753a026cSClément Léger struct ocelot *ocelot; 155*753a026cSClément Léger }; 156*753a026cSClément Léger 157*753a026cSClément Léger void ocelot_fdma_init(struct platform_device *pdev, struct ocelot *ocelot); 158*753a026cSClément Léger void ocelot_fdma_start(struct ocelot *ocelot); 159*753a026cSClément Léger void ocelot_fdma_deinit(struct ocelot *ocelot); 160*753a026cSClément Léger int ocelot_fdma_inject_frame(struct ocelot *fdma, int port, u32 rew_op, 161*753a026cSClément Léger struct sk_buff *skb, struct net_device *dev); 162*753a026cSClément Léger void ocelot_fdma_netdev_init(struct ocelot *ocelot, struct net_device *dev); 163*753a026cSClément Léger void ocelot_fdma_netdev_deinit(struct ocelot *ocelot, 164*753a026cSClément Léger struct net_device *dev); 165*753a026cSClément Léger 166*753a026cSClément Léger #endif 167