1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 8 #ifndef _MSCC_OCELOT_H_ 9 #define _MSCC_OCELOT_H_ 10 11 #include <linux/bitops.h> 12 #include <linux/etherdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/phy.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 #include "ocelot_ana.h" 20 #include "ocelot_dev.h" 21 #include "ocelot_qsys.h" 22 #include "ocelot_rew.h" 23 #include "ocelot_sys.h" 24 #include "ocelot_qs.h" 25 #include "ocelot_tc.h" 26 27 #define PGID_AGGR 64 28 #define PGID_SRC 80 29 30 /* Reserved PGIDs */ 31 #define PGID_CPU (PGID_AGGR - 5) 32 #define PGID_UC (PGID_AGGR - 4) 33 #define PGID_MC (PGID_AGGR - 3) 34 #define PGID_MCIPV4 (PGID_AGGR - 2) 35 #define PGID_MCIPV6 (PGID_AGGR - 1) 36 37 #define OCELOT_BUFFER_CELL_SZ 60 38 39 #define OCELOT_STATS_CHECK_DELAY (2 * HZ) 40 41 #define IFH_LEN 4 42 43 struct frame_info { 44 u32 len; 45 u16 port; 46 u16 vid; 47 u8 cpuq; 48 u8 tag_type; 49 }; 50 51 #define IFH_INJ_BYPASS BIT(31) 52 #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 53 54 #define IFH_TAG_TYPE_C 0 55 #define IFH_TAG_TYPE_S 1 56 57 #define OCELOT_SPEED_2500 0 58 #define OCELOT_SPEED_1000 1 59 #define OCELOT_SPEED_100 2 60 #define OCELOT_SPEED_10 3 61 62 #define TARGET_OFFSET 24 63 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 64 #define REG(reg, offset) [reg & REG_MASK] = offset 65 66 enum ocelot_target { 67 ANA = 1, 68 QS, 69 QSYS, 70 REW, 71 SYS, 72 S2, 73 HSIO, 74 TARGET_MAX, 75 }; 76 77 enum ocelot_reg { 78 ANA_ADVLEARN = ANA << TARGET_OFFSET, 79 ANA_VLANMASK, 80 ANA_PORT_B_DOMAIN, 81 ANA_ANAGEFIL, 82 ANA_ANEVENTS, 83 ANA_STORMLIMIT_BURST, 84 ANA_STORMLIMIT_CFG, 85 ANA_ISOLATED_PORTS, 86 ANA_COMMUNITY_PORTS, 87 ANA_AUTOAGE, 88 ANA_MACTOPTIONS, 89 ANA_LEARNDISC, 90 ANA_AGENCTRL, 91 ANA_MIRRORPORTS, 92 ANA_EMIRRORPORTS, 93 ANA_FLOODING, 94 ANA_FLOODING_IPMC, 95 ANA_SFLOW_CFG, 96 ANA_PORT_MODE, 97 ANA_CUT_THRU_CFG, 98 ANA_PGID_PGID, 99 ANA_TABLES_ANMOVED, 100 ANA_TABLES_MACHDATA, 101 ANA_TABLES_MACLDATA, 102 ANA_TABLES_STREAMDATA, 103 ANA_TABLES_MACACCESS, 104 ANA_TABLES_MACTINDX, 105 ANA_TABLES_VLANACCESS, 106 ANA_TABLES_VLANTIDX, 107 ANA_TABLES_ISDXACCESS, 108 ANA_TABLES_ISDXTIDX, 109 ANA_TABLES_ENTRYLIM, 110 ANA_TABLES_PTP_ID_HIGH, 111 ANA_TABLES_PTP_ID_LOW, 112 ANA_TABLES_STREAMACCESS, 113 ANA_TABLES_STREAMTIDX, 114 ANA_TABLES_SEQ_HISTORY, 115 ANA_TABLES_SEQ_MASK, 116 ANA_TABLES_SFID_MASK, 117 ANA_TABLES_SFIDACCESS, 118 ANA_TABLES_SFIDTIDX, 119 ANA_MSTI_STATE, 120 ANA_OAM_UPM_LM_CNT, 121 ANA_SG_ACCESS_CTRL, 122 ANA_SG_CONFIG_REG_1, 123 ANA_SG_CONFIG_REG_2, 124 ANA_SG_CONFIG_REG_3, 125 ANA_SG_CONFIG_REG_4, 126 ANA_SG_CONFIG_REG_5, 127 ANA_SG_GCL_GS_CONFIG, 128 ANA_SG_GCL_TI_CONFIG, 129 ANA_SG_STATUS_REG_1, 130 ANA_SG_STATUS_REG_2, 131 ANA_SG_STATUS_REG_3, 132 ANA_PORT_VLAN_CFG, 133 ANA_PORT_DROP_CFG, 134 ANA_PORT_QOS_CFG, 135 ANA_PORT_VCAP_CFG, 136 ANA_PORT_VCAP_S1_KEY_CFG, 137 ANA_PORT_VCAP_S2_CFG, 138 ANA_PORT_PCP_DEI_MAP, 139 ANA_PORT_CPU_FWD_CFG, 140 ANA_PORT_CPU_FWD_BPDU_CFG, 141 ANA_PORT_CPU_FWD_GARP_CFG, 142 ANA_PORT_CPU_FWD_CCM_CFG, 143 ANA_PORT_PORT_CFG, 144 ANA_PORT_POL_CFG, 145 ANA_PORT_PTP_CFG, 146 ANA_PORT_PTP_DLY1_CFG, 147 ANA_PORT_PTP_DLY2_CFG, 148 ANA_PORT_SFID_CFG, 149 ANA_PFC_PFC_CFG, 150 ANA_PFC_PFC_TIMER, 151 ANA_IPT_OAM_MEP_CFG, 152 ANA_IPT_IPT, 153 ANA_PPT_PPT, 154 ANA_FID_MAP_FID_MAP, 155 ANA_AGGR_CFG, 156 ANA_CPUQ_CFG, 157 ANA_CPUQ_CFG2, 158 ANA_CPUQ_8021_CFG, 159 ANA_DSCP_CFG, 160 ANA_DSCP_REWR_CFG, 161 ANA_VCAP_RNG_TYPE_CFG, 162 ANA_VCAP_RNG_VAL_CFG, 163 ANA_VRAP_CFG, 164 ANA_VRAP_HDR_DATA, 165 ANA_VRAP_HDR_MASK, 166 ANA_DISCARD_CFG, 167 ANA_FID_CFG, 168 ANA_POL_PIR_CFG, 169 ANA_POL_CIR_CFG, 170 ANA_POL_MODE_CFG, 171 ANA_POL_PIR_STATE, 172 ANA_POL_CIR_STATE, 173 ANA_POL_STATE, 174 ANA_POL_FLOWC, 175 ANA_POL_HYST, 176 ANA_POL_MISC_CFG, 177 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 178 QS_XTR_RD, 179 QS_XTR_FRM_PRUNING, 180 QS_XTR_FLUSH, 181 QS_XTR_DATA_PRESENT, 182 QS_XTR_CFG, 183 QS_INJ_GRP_CFG, 184 QS_INJ_WR, 185 QS_INJ_CTRL, 186 QS_INJ_STATUS, 187 QS_INJ_ERR, 188 QS_INH_DBG, 189 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 190 QSYS_SWITCH_PORT_MODE, 191 QSYS_STAT_CNT_CFG, 192 QSYS_EEE_CFG, 193 QSYS_EEE_THRES, 194 QSYS_IGR_NO_SHARING, 195 QSYS_EGR_NO_SHARING, 196 QSYS_SW_STATUS, 197 QSYS_EXT_CPU_CFG, 198 QSYS_PAD_CFG, 199 QSYS_CPU_GROUP_MAP, 200 QSYS_QMAP, 201 QSYS_ISDX_SGRP, 202 QSYS_TIMED_FRAME_ENTRY, 203 QSYS_TFRM_MISC, 204 QSYS_TFRM_PORT_DLY, 205 QSYS_TFRM_TIMER_CFG_1, 206 QSYS_TFRM_TIMER_CFG_2, 207 QSYS_TFRM_TIMER_CFG_3, 208 QSYS_TFRM_TIMER_CFG_4, 209 QSYS_TFRM_TIMER_CFG_5, 210 QSYS_TFRM_TIMER_CFG_6, 211 QSYS_TFRM_TIMER_CFG_7, 212 QSYS_TFRM_TIMER_CFG_8, 213 QSYS_RED_PROFILE, 214 QSYS_RES_QOS_MODE, 215 QSYS_RES_CFG, 216 QSYS_RES_STAT, 217 QSYS_EGR_DROP_MODE, 218 QSYS_EQ_CTRL, 219 QSYS_EVENTS_CORE, 220 QSYS_QMAXSDU_CFG_0, 221 QSYS_QMAXSDU_CFG_1, 222 QSYS_QMAXSDU_CFG_2, 223 QSYS_QMAXSDU_CFG_3, 224 QSYS_QMAXSDU_CFG_4, 225 QSYS_QMAXSDU_CFG_5, 226 QSYS_QMAXSDU_CFG_6, 227 QSYS_QMAXSDU_CFG_7, 228 QSYS_PREEMPTION_CFG, 229 QSYS_CIR_CFG, 230 QSYS_EIR_CFG, 231 QSYS_SE_CFG, 232 QSYS_SE_DWRR_CFG, 233 QSYS_SE_CONNECT, 234 QSYS_SE_DLB_SENSE, 235 QSYS_CIR_STATE, 236 QSYS_EIR_STATE, 237 QSYS_SE_STATE, 238 QSYS_HSCH_MISC_CFG, 239 QSYS_TAG_CONFIG, 240 QSYS_TAS_PARAM_CFG_CTRL, 241 QSYS_PORT_MAX_SDU, 242 QSYS_PARAM_CFG_REG_1, 243 QSYS_PARAM_CFG_REG_2, 244 QSYS_PARAM_CFG_REG_3, 245 QSYS_PARAM_CFG_REG_4, 246 QSYS_PARAM_CFG_REG_5, 247 QSYS_GCL_CFG_REG_1, 248 QSYS_GCL_CFG_REG_2, 249 QSYS_PARAM_STATUS_REG_1, 250 QSYS_PARAM_STATUS_REG_2, 251 QSYS_PARAM_STATUS_REG_3, 252 QSYS_PARAM_STATUS_REG_4, 253 QSYS_PARAM_STATUS_REG_5, 254 QSYS_PARAM_STATUS_REG_6, 255 QSYS_PARAM_STATUS_REG_7, 256 QSYS_PARAM_STATUS_REG_8, 257 QSYS_PARAM_STATUS_REG_9, 258 QSYS_GCL_STATUS_REG_1, 259 QSYS_GCL_STATUS_REG_2, 260 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 261 REW_TAG_CFG, 262 REW_PORT_CFG, 263 REW_DSCP_CFG, 264 REW_PCP_DEI_QOS_MAP_CFG, 265 REW_PTP_CFG, 266 REW_PTP_DLY1_CFG, 267 REW_RED_TAG_CFG, 268 REW_DSCP_REMAP_DP1_CFG, 269 REW_DSCP_REMAP_CFG, 270 REW_STAT_CFG, 271 REW_REW_STICKY, 272 REW_PPT, 273 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 274 SYS_COUNT_RX_UNICAST, 275 SYS_COUNT_RX_MULTICAST, 276 SYS_COUNT_RX_BROADCAST, 277 SYS_COUNT_RX_SHORTS, 278 SYS_COUNT_RX_FRAGMENTS, 279 SYS_COUNT_RX_JABBERS, 280 SYS_COUNT_RX_CRC_ALIGN_ERRS, 281 SYS_COUNT_RX_SYM_ERRS, 282 SYS_COUNT_RX_64, 283 SYS_COUNT_RX_65_127, 284 SYS_COUNT_RX_128_255, 285 SYS_COUNT_RX_256_1023, 286 SYS_COUNT_RX_1024_1526, 287 SYS_COUNT_RX_1527_MAX, 288 SYS_COUNT_RX_PAUSE, 289 SYS_COUNT_RX_CONTROL, 290 SYS_COUNT_RX_LONGS, 291 SYS_COUNT_RX_CLASSIFIED_DROPS, 292 SYS_COUNT_TX_OCTETS, 293 SYS_COUNT_TX_UNICAST, 294 SYS_COUNT_TX_MULTICAST, 295 SYS_COUNT_TX_BROADCAST, 296 SYS_COUNT_TX_COLLISION, 297 SYS_COUNT_TX_DROPS, 298 SYS_COUNT_TX_PAUSE, 299 SYS_COUNT_TX_64, 300 SYS_COUNT_TX_65_127, 301 SYS_COUNT_TX_128_511, 302 SYS_COUNT_TX_512_1023, 303 SYS_COUNT_TX_1024_1526, 304 SYS_COUNT_TX_1527_MAX, 305 SYS_COUNT_TX_AGING, 306 SYS_RESET_CFG, 307 SYS_SR_ETYPE_CFG, 308 SYS_VLAN_ETYPE_CFG, 309 SYS_PORT_MODE, 310 SYS_FRONT_PORT_MODE, 311 SYS_FRM_AGING, 312 SYS_STAT_CFG, 313 SYS_SW_STATUS, 314 SYS_MISC_CFG, 315 SYS_REW_MAC_HIGH_CFG, 316 SYS_REW_MAC_LOW_CFG, 317 SYS_TIMESTAMP_OFFSET, 318 SYS_CMID, 319 SYS_PAUSE_CFG, 320 SYS_PAUSE_TOT_CFG, 321 SYS_ATOP, 322 SYS_ATOP_TOT_CFG, 323 SYS_MAC_FC_CFG, 324 SYS_MMGT, 325 SYS_MMGT_FAST, 326 SYS_EVENTS_DIF, 327 SYS_EVENTS_CORE, 328 SYS_CNT, 329 SYS_PTP_STATUS, 330 SYS_PTP_TXSTAMP, 331 SYS_PTP_NXT, 332 SYS_PTP_CFG, 333 SYS_RAM_INIT, 334 SYS_CM_ADDR, 335 SYS_CM_DATA_WR, 336 SYS_CM_DATA_RD, 337 SYS_CM_OP, 338 SYS_CM_DATA, 339 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 340 S2_CORE_MV_CFG, 341 S2_CACHE_ENTRY_DAT, 342 S2_CACHE_MASK_DAT, 343 S2_CACHE_ACTION_DAT, 344 S2_CACHE_CNT_DAT, 345 S2_CACHE_TG_DAT, 346 }; 347 348 enum ocelot_regfield { 349 ANA_ADVLEARN_VLAN_CHK, 350 ANA_ADVLEARN_LEARN_MIRROR, 351 ANA_ANEVENTS_FLOOD_DISCARD, 352 ANA_ANEVENTS_MSTI_DROP, 353 ANA_ANEVENTS_ACLKILL, 354 ANA_ANEVENTS_ACLUSED, 355 ANA_ANEVENTS_AUTOAGE, 356 ANA_ANEVENTS_VS2TTL1, 357 ANA_ANEVENTS_STORM_DROP, 358 ANA_ANEVENTS_LEARN_DROP, 359 ANA_ANEVENTS_AGED_ENTRY, 360 ANA_ANEVENTS_CPU_LEARN_FAILED, 361 ANA_ANEVENTS_AUTO_LEARN_FAILED, 362 ANA_ANEVENTS_LEARN_REMOVE, 363 ANA_ANEVENTS_AUTO_LEARNED, 364 ANA_ANEVENTS_AUTO_MOVED, 365 ANA_ANEVENTS_DROPPED, 366 ANA_ANEVENTS_CLASSIFIED_DROP, 367 ANA_ANEVENTS_CLASSIFIED_COPY, 368 ANA_ANEVENTS_VLAN_DISCARD, 369 ANA_ANEVENTS_FWD_DISCARD, 370 ANA_ANEVENTS_MULTICAST_FLOOD, 371 ANA_ANEVENTS_UNICAST_FLOOD, 372 ANA_ANEVENTS_DEST_KNOWN, 373 ANA_ANEVENTS_BUCKET3_MATCH, 374 ANA_ANEVENTS_BUCKET2_MATCH, 375 ANA_ANEVENTS_BUCKET1_MATCH, 376 ANA_ANEVENTS_BUCKET0_MATCH, 377 ANA_ANEVENTS_CPU_OPERATION, 378 ANA_ANEVENTS_DMAC_LOOKUP, 379 ANA_ANEVENTS_SMAC_LOOKUP, 380 ANA_ANEVENTS_SEQ_GEN_ERR_0, 381 ANA_ANEVENTS_SEQ_GEN_ERR_1, 382 ANA_TABLES_MACACCESS_B_DOM, 383 ANA_TABLES_MACTINDX_BUCKET, 384 ANA_TABLES_MACTINDX_M_INDEX, 385 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 386 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 387 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 388 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 389 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 390 SYS_RESET_CFG_CORE_ENA, 391 SYS_RESET_CFG_MEM_ENA, 392 SYS_RESET_CFG_MEM_INIT, 393 REGFIELD_MAX 394 }; 395 396 struct ocelot_multicast { 397 struct list_head list; 398 unsigned char addr[ETH_ALEN]; 399 u16 vid; 400 u16 ports; 401 }; 402 403 struct ocelot_port; 404 405 struct ocelot_stat_layout { 406 u32 offset; 407 char name[ETH_GSTRING_LEN]; 408 }; 409 410 struct ocelot { 411 struct device *dev; 412 413 struct regmap *targets[TARGET_MAX]; 414 struct regmap_field *regfields[REGFIELD_MAX]; 415 const u32 *const *map; 416 const struct ocelot_stat_layout *stats_layout; 417 unsigned int num_stats; 418 419 u8 base_mac[ETH_ALEN]; 420 421 struct net_device *hw_bridge_dev; 422 u16 bridge_mask; 423 u16 bridge_fwd_mask; 424 425 struct workqueue_struct *ocelot_owq; 426 427 int shared_queue_sz; 428 429 u8 num_phys_ports; 430 u8 num_cpu_ports; 431 struct ocelot_port **ports; 432 433 u32 *lags; 434 435 /* Keep track of the vlan port masks */ 436 u32 vlan_mask[VLAN_N_VID]; 437 438 struct list_head multicast; 439 440 /* Workqueue to check statistics for overflow with its lock */ 441 struct mutex stats_lock; 442 u64 *stats; 443 struct delayed_work stats_work; 444 struct workqueue_struct *stats_queue; 445 }; 446 447 struct ocelot_port { 448 struct net_device *dev; 449 struct ocelot *ocelot; 450 struct phy_device *phy; 451 void __iomem *regs; 452 u8 chip_port; 453 454 /* Ingress default VLAN (pvid) */ 455 u16 pvid; 456 457 /* Egress default VLAN (vid) */ 458 u16 vid; 459 460 u8 vlan_aware; 461 462 u64 *stats; 463 464 phy_interface_t phy_mode; 465 struct phy *serdes; 466 467 struct ocelot_port_tc tc; 468 }; 469 470 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 471 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 472 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 473 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 474 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 475 476 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 477 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 478 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 479 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 480 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 481 482 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask, 483 u32 offset); 484 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 485 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 486 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 487 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 488 489 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 490 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 491 492 int ocelot_regfields_init(struct ocelot *ocelot, 493 const struct reg_field *const regfields); 494 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot, 495 struct platform_device *pdev, 496 const char *name); 497 498 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 499 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 500 501 int ocelot_init(struct ocelot *ocelot); 502 void ocelot_deinit(struct ocelot *ocelot); 503 int ocelot_chip_init(struct ocelot *ocelot); 504 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 505 void __iomem *regs, 506 struct phy_device *phy); 507 508 extern struct notifier_block ocelot_netdevice_nb; 509 extern struct notifier_block ocelot_switchdev_nb; 510 extern struct notifier_block ocelot_switchdev_blocking_nb; 511 512 #endif 513