1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 8 #ifndef _MSCC_OCELOT_H_ 9 #define _MSCC_OCELOT_H_ 10 11 #include <linux/bitops.h> 12 #include <linux/etherdevice.h> 13 #include <linux/if_vlan.h> 14 #include <linux/phy.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 #include "ocelot_ana.h" 20 #include "ocelot_dev.h" 21 #include "ocelot_qsys.h" 22 #include "ocelot_rew.h" 23 #include "ocelot_sys.h" 24 #include "ocelot_qs.h" 25 26 #define PGID_AGGR 64 27 #define PGID_SRC 80 28 29 /* Reserved PGIDs */ 30 #define PGID_CPU (PGID_AGGR - 5) 31 #define PGID_UC (PGID_AGGR - 4) 32 #define PGID_MC (PGID_AGGR - 3) 33 #define PGID_MCIPV4 (PGID_AGGR - 2) 34 #define PGID_MCIPV6 (PGID_AGGR - 1) 35 36 #define OCELOT_BUFFER_CELL_SZ 60 37 38 #define OCELOT_STATS_CHECK_DELAY (2 * HZ) 39 40 #define IFH_LEN 4 41 42 struct frame_info { 43 u32 len; 44 u16 port; 45 u16 vid; 46 u8 cpuq; 47 u8 tag_type; 48 }; 49 50 #define IFH_INJ_BYPASS BIT(31) 51 #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 52 53 #define IFH_TAG_TYPE_C 0 54 #define IFH_TAG_TYPE_S 1 55 56 #define OCELOT_SPEED_2500 0 57 #define OCELOT_SPEED_1000 1 58 #define OCELOT_SPEED_100 2 59 #define OCELOT_SPEED_10 3 60 61 #define TARGET_OFFSET 24 62 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 63 #define REG(reg, offset) [reg & REG_MASK] = offset 64 65 enum ocelot_target { 66 ANA = 1, 67 QS, 68 QSYS, 69 REW, 70 SYS, 71 HSIO, 72 TARGET_MAX, 73 }; 74 75 enum ocelot_reg { 76 ANA_ADVLEARN = ANA << TARGET_OFFSET, 77 ANA_VLANMASK, 78 ANA_PORT_B_DOMAIN, 79 ANA_ANAGEFIL, 80 ANA_ANEVENTS, 81 ANA_STORMLIMIT_BURST, 82 ANA_STORMLIMIT_CFG, 83 ANA_ISOLATED_PORTS, 84 ANA_COMMUNITY_PORTS, 85 ANA_AUTOAGE, 86 ANA_MACTOPTIONS, 87 ANA_LEARNDISC, 88 ANA_AGENCTRL, 89 ANA_MIRRORPORTS, 90 ANA_EMIRRORPORTS, 91 ANA_FLOODING, 92 ANA_FLOODING_IPMC, 93 ANA_SFLOW_CFG, 94 ANA_PORT_MODE, 95 ANA_CUT_THRU_CFG, 96 ANA_PGID_PGID, 97 ANA_TABLES_ANMOVED, 98 ANA_TABLES_MACHDATA, 99 ANA_TABLES_MACLDATA, 100 ANA_TABLES_STREAMDATA, 101 ANA_TABLES_MACACCESS, 102 ANA_TABLES_MACTINDX, 103 ANA_TABLES_VLANACCESS, 104 ANA_TABLES_VLANTIDX, 105 ANA_TABLES_ISDXACCESS, 106 ANA_TABLES_ISDXTIDX, 107 ANA_TABLES_ENTRYLIM, 108 ANA_TABLES_PTP_ID_HIGH, 109 ANA_TABLES_PTP_ID_LOW, 110 ANA_TABLES_STREAMACCESS, 111 ANA_TABLES_STREAMTIDX, 112 ANA_TABLES_SEQ_HISTORY, 113 ANA_TABLES_SEQ_MASK, 114 ANA_TABLES_SFID_MASK, 115 ANA_TABLES_SFIDACCESS, 116 ANA_TABLES_SFIDTIDX, 117 ANA_MSTI_STATE, 118 ANA_OAM_UPM_LM_CNT, 119 ANA_SG_ACCESS_CTRL, 120 ANA_SG_CONFIG_REG_1, 121 ANA_SG_CONFIG_REG_2, 122 ANA_SG_CONFIG_REG_3, 123 ANA_SG_CONFIG_REG_4, 124 ANA_SG_CONFIG_REG_5, 125 ANA_SG_GCL_GS_CONFIG, 126 ANA_SG_GCL_TI_CONFIG, 127 ANA_SG_STATUS_REG_1, 128 ANA_SG_STATUS_REG_2, 129 ANA_SG_STATUS_REG_3, 130 ANA_PORT_VLAN_CFG, 131 ANA_PORT_DROP_CFG, 132 ANA_PORT_QOS_CFG, 133 ANA_PORT_VCAP_CFG, 134 ANA_PORT_VCAP_S1_KEY_CFG, 135 ANA_PORT_VCAP_S2_CFG, 136 ANA_PORT_PCP_DEI_MAP, 137 ANA_PORT_CPU_FWD_CFG, 138 ANA_PORT_CPU_FWD_BPDU_CFG, 139 ANA_PORT_CPU_FWD_GARP_CFG, 140 ANA_PORT_CPU_FWD_CCM_CFG, 141 ANA_PORT_PORT_CFG, 142 ANA_PORT_POL_CFG, 143 ANA_PORT_PTP_CFG, 144 ANA_PORT_PTP_DLY1_CFG, 145 ANA_PORT_PTP_DLY2_CFG, 146 ANA_PORT_SFID_CFG, 147 ANA_PFC_PFC_CFG, 148 ANA_PFC_PFC_TIMER, 149 ANA_IPT_OAM_MEP_CFG, 150 ANA_IPT_IPT, 151 ANA_PPT_PPT, 152 ANA_FID_MAP_FID_MAP, 153 ANA_AGGR_CFG, 154 ANA_CPUQ_CFG, 155 ANA_CPUQ_CFG2, 156 ANA_CPUQ_8021_CFG, 157 ANA_DSCP_CFG, 158 ANA_DSCP_REWR_CFG, 159 ANA_VCAP_RNG_TYPE_CFG, 160 ANA_VCAP_RNG_VAL_CFG, 161 ANA_VRAP_CFG, 162 ANA_VRAP_HDR_DATA, 163 ANA_VRAP_HDR_MASK, 164 ANA_DISCARD_CFG, 165 ANA_FID_CFG, 166 ANA_POL_PIR_CFG, 167 ANA_POL_CIR_CFG, 168 ANA_POL_MODE_CFG, 169 ANA_POL_PIR_STATE, 170 ANA_POL_CIR_STATE, 171 ANA_POL_STATE, 172 ANA_POL_FLOWC, 173 ANA_POL_HYST, 174 ANA_POL_MISC_CFG, 175 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 176 QS_XTR_RD, 177 QS_XTR_FRM_PRUNING, 178 QS_XTR_FLUSH, 179 QS_XTR_DATA_PRESENT, 180 QS_XTR_CFG, 181 QS_INJ_GRP_CFG, 182 QS_INJ_WR, 183 QS_INJ_CTRL, 184 QS_INJ_STATUS, 185 QS_INJ_ERR, 186 QS_INH_DBG, 187 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 188 QSYS_SWITCH_PORT_MODE, 189 QSYS_STAT_CNT_CFG, 190 QSYS_EEE_CFG, 191 QSYS_EEE_THRES, 192 QSYS_IGR_NO_SHARING, 193 QSYS_EGR_NO_SHARING, 194 QSYS_SW_STATUS, 195 QSYS_EXT_CPU_CFG, 196 QSYS_PAD_CFG, 197 QSYS_CPU_GROUP_MAP, 198 QSYS_QMAP, 199 QSYS_ISDX_SGRP, 200 QSYS_TIMED_FRAME_ENTRY, 201 QSYS_TFRM_MISC, 202 QSYS_TFRM_PORT_DLY, 203 QSYS_TFRM_TIMER_CFG_1, 204 QSYS_TFRM_TIMER_CFG_2, 205 QSYS_TFRM_TIMER_CFG_3, 206 QSYS_TFRM_TIMER_CFG_4, 207 QSYS_TFRM_TIMER_CFG_5, 208 QSYS_TFRM_TIMER_CFG_6, 209 QSYS_TFRM_TIMER_CFG_7, 210 QSYS_TFRM_TIMER_CFG_8, 211 QSYS_RED_PROFILE, 212 QSYS_RES_QOS_MODE, 213 QSYS_RES_CFG, 214 QSYS_RES_STAT, 215 QSYS_EGR_DROP_MODE, 216 QSYS_EQ_CTRL, 217 QSYS_EVENTS_CORE, 218 QSYS_QMAXSDU_CFG_0, 219 QSYS_QMAXSDU_CFG_1, 220 QSYS_QMAXSDU_CFG_2, 221 QSYS_QMAXSDU_CFG_3, 222 QSYS_QMAXSDU_CFG_4, 223 QSYS_QMAXSDU_CFG_5, 224 QSYS_QMAXSDU_CFG_6, 225 QSYS_QMAXSDU_CFG_7, 226 QSYS_PREEMPTION_CFG, 227 QSYS_CIR_CFG, 228 QSYS_EIR_CFG, 229 QSYS_SE_CFG, 230 QSYS_SE_DWRR_CFG, 231 QSYS_SE_CONNECT, 232 QSYS_SE_DLB_SENSE, 233 QSYS_CIR_STATE, 234 QSYS_EIR_STATE, 235 QSYS_SE_STATE, 236 QSYS_HSCH_MISC_CFG, 237 QSYS_TAG_CONFIG, 238 QSYS_TAS_PARAM_CFG_CTRL, 239 QSYS_PORT_MAX_SDU, 240 QSYS_PARAM_CFG_REG_1, 241 QSYS_PARAM_CFG_REG_2, 242 QSYS_PARAM_CFG_REG_3, 243 QSYS_PARAM_CFG_REG_4, 244 QSYS_PARAM_CFG_REG_5, 245 QSYS_GCL_CFG_REG_1, 246 QSYS_GCL_CFG_REG_2, 247 QSYS_PARAM_STATUS_REG_1, 248 QSYS_PARAM_STATUS_REG_2, 249 QSYS_PARAM_STATUS_REG_3, 250 QSYS_PARAM_STATUS_REG_4, 251 QSYS_PARAM_STATUS_REG_5, 252 QSYS_PARAM_STATUS_REG_6, 253 QSYS_PARAM_STATUS_REG_7, 254 QSYS_PARAM_STATUS_REG_8, 255 QSYS_PARAM_STATUS_REG_9, 256 QSYS_GCL_STATUS_REG_1, 257 QSYS_GCL_STATUS_REG_2, 258 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 259 REW_TAG_CFG, 260 REW_PORT_CFG, 261 REW_DSCP_CFG, 262 REW_PCP_DEI_QOS_MAP_CFG, 263 REW_PTP_CFG, 264 REW_PTP_DLY1_CFG, 265 REW_RED_TAG_CFG, 266 REW_DSCP_REMAP_DP1_CFG, 267 REW_DSCP_REMAP_CFG, 268 REW_STAT_CFG, 269 REW_REW_STICKY, 270 REW_PPT, 271 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 272 SYS_COUNT_RX_UNICAST, 273 SYS_COUNT_RX_MULTICAST, 274 SYS_COUNT_RX_BROADCAST, 275 SYS_COUNT_RX_SHORTS, 276 SYS_COUNT_RX_FRAGMENTS, 277 SYS_COUNT_RX_JABBERS, 278 SYS_COUNT_RX_CRC_ALIGN_ERRS, 279 SYS_COUNT_RX_SYM_ERRS, 280 SYS_COUNT_RX_64, 281 SYS_COUNT_RX_65_127, 282 SYS_COUNT_RX_128_255, 283 SYS_COUNT_RX_256_1023, 284 SYS_COUNT_RX_1024_1526, 285 SYS_COUNT_RX_1527_MAX, 286 SYS_COUNT_RX_PAUSE, 287 SYS_COUNT_RX_CONTROL, 288 SYS_COUNT_RX_LONGS, 289 SYS_COUNT_RX_CLASSIFIED_DROPS, 290 SYS_COUNT_TX_OCTETS, 291 SYS_COUNT_TX_UNICAST, 292 SYS_COUNT_TX_MULTICAST, 293 SYS_COUNT_TX_BROADCAST, 294 SYS_COUNT_TX_COLLISION, 295 SYS_COUNT_TX_DROPS, 296 SYS_COUNT_TX_PAUSE, 297 SYS_COUNT_TX_64, 298 SYS_COUNT_TX_65_127, 299 SYS_COUNT_TX_128_511, 300 SYS_COUNT_TX_512_1023, 301 SYS_COUNT_TX_1024_1526, 302 SYS_COUNT_TX_1527_MAX, 303 SYS_COUNT_TX_AGING, 304 SYS_RESET_CFG, 305 SYS_SR_ETYPE_CFG, 306 SYS_VLAN_ETYPE_CFG, 307 SYS_PORT_MODE, 308 SYS_FRONT_PORT_MODE, 309 SYS_FRM_AGING, 310 SYS_STAT_CFG, 311 SYS_SW_STATUS, 312 SYS_MISC_CFG, 313 SYS_REW_MAC_HIGH_CFG, 314 SYS_REW_MAC_LOW_CFG, 315 SYS_TIMESTAMP_OFFSET, 316 SYS_CMID, 317 SYS_PAUSE_CFG, 318 SYS_PAUSE_TOT_CFG, 319 SYS_ATOP, 320 SYS_ATOP_TOT_CFG, 321 SYS_MAC_FC_CFG, 322 SYS_MMGT, 323 SYS_MMGT_FAST, 324 SYS_EVENTS_DIF, 325 SYS_EVENTS_CORE, 326 SYS_CNT, 327 SYS_PTP_STATUS, 328 SYS_PTP_TXSTAMP, 329 SYS_PTP_NXT, 330 SYS_PTP_CFG, 331 SYS_RAM_INIT, 332 SYS_CM_ADDR, 333 SYS_CM_DATA_WR, 334 SYS_CM_DATA_RD, 335 SYS_CM_OP, 336 SYS_CM_DATA, 337 }; 338 339 enum ocelot_regfield { 340 ANA_ADVLEARN_VLAN_CHK, 341 ANA_ADVLEARN_LEARN_MIRROR, 342 ANA_ANEVENTS_FLOOD_DISCARD, 343 ANA_ANEVENTS_MSTI_DROP, 344 ANA_ANEVENTS_ACLKILL, 345 ANA_ANEVENTS_ACLUSED, 346 ANA_ANEVENTS_AUTOAGE, 347 ANA_ANEVENTS_VS2TTL1, 348 ANA_ANEVENTS_STORM_DROP, 349 ANA_ANEVENTS_LEARN_DROP, 350 ANA_ANEVENTS_AGED_ENTRY, 351 ANA_ANEVENTS_CPU_LEARN_FAILED, 352 ANA_ANEVENTS_AUTO_LEARN_FAILED, 353 ANA_ANEVENTS_LEARN_REMOVE, 354 ANA_ANEVENTS_AUTO_LEARNED, 355 ANA_ANEVENTS_AUTO_MOVED, 356 ANA_ANEVENTS_DROPPED, 357 ANA_ANEVENTS_CLASSIFIED_DROP, 358 ANA_ANEVENTS_CLASSIFIED_COPY, 359 ANA_ANEVENTS_VLAN_DISCARD, 360 ANA_ANEVENTS_FWD_DISCARD, 361 ANA_ANEVENTS_MULTICAST_FLOOD, 362 ANA_ANEVENTS_UNICAST_FLOOD, 363 ANA_ANEVENTS_DEST_KNOWN, 364 ANA_ANEVENTS_BUCKET3_MATCH, 365 ANA_ANEVENTS_BUCKET2_MATCH, 366 ANA_ANEVENTS_BUCKET1_MATCH, 367 ANA_ANEVENTS_BUCKET0_MATCH, 368 ANA_ANEVENTS_CPU_OPERATION, 369 ANA_ANEVENTS_DMAC_LOOKUP, 370 ANA_ANEVENTS_SMAC_LOOKUP, 371 ANA_ANEVENTS_SEQ_GEN_ERR_0, 372 ANA_ANEVENTS_SEQ_GEN_ERR_1, 373 ANA_TABLES_MACACCESS_B_DOM, 374 ANA_TABLES_MACTINDX_BUCKET, 375 ANA_TABLES_MACTINDX_M_INDEX, 376 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 377 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 378 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 379 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 380 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 381 SYS_RESET_CFG_CORE_ENA, 382 SYS_RESET_CFG_MEM_ENA, 383 SYS_RESET_CFG_MEM_INIT, 384 REGFIELD_MAX 385 }; 386 387 struct ocelot_multicast { 388 struct list_head list; 389 unsigned char addr[ETH_ALEN]; 390 u16 vid; 391 u16 ports; 392 }; 393 394 struct ocelot_port; 395 396 struct ocelot_stat_layout { 397 u32 offset; 398 char name[ETH_GSTRING_LEN]; 399 }; 400 401 struct ocelot { 402 struct device *dev; 403 404 struct regmap *targets[TARGET_MAX]; 405 struct regmap_field *regfields[REGFIELD_MAX]; 406 const u32 *const *map; 407 const struct ocelot_stat_layout *stats_layout; 408 unsigned int num_stats; 409 410 u8 base_mac[ETH_ALEN]; 411 412 struct net_device *hw_bridge_dev; 413 u16 bridge_mask; 414 u16 bridge_fwd_mask; 415 416 struct workqueue_struct *ocelot_owq; 417 418 int shared_queue_sz; 419 420 u8 num_phys_ports; 421 u8 num_cpu_ports; 422 struct ocelot_port **ports; 423 424 u32 *lags; 425 426 /* Keep track of the vlan port masks */ 427 u32 vlan_mask[VLAN_N_VID]; 428 429 struct list_head multicast; 430 431 /* Workqueue to check statistics for overflow with its lock */ 432 struct mutex stats_lock; 433 u64 *stats; 434 struct delayed_work stats_work; 435 struct workqueue_struct *stats_queue; 436 }; 437 438 struct ocelot_port { 439 struct net_device *dev; 440 struct ocelot *ocelot; 441 struct phy_device *phy; 442 void __iomem *regs; 443 u8 chip_port; 444 /* Keep a track of the mc addresses added to the mac table, so that they 445 * can be removed when needed. 446 */ 447 struct list_head mc; 448 449 /* Ingress default VLAN (pvid) */ 450 u16 pvid; 451 452 /* Egress default VLAN (vid) */ 453 u16 vid; 454 455 u8 vlan_aware; 456 457 u64 *stats; 458 459 phy_interface_t phy_mode; 460 struct phy *serdes; 461 }; 462 463 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 464 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 465 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 466 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 467 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 468 469 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 470 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 471 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 472 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 473 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 474 475 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask, 476 u32 offset); 477 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 478 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 479 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 480 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 481 482 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 483 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 484 485 int ocelot_regfields_init(struct ocelot *ocelot, 486 const struct reg_field *const regfields); 487 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot, 488 struct platform_device *pdev, 489 const char *name); 490 491 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 492 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 493 494 int ocelot_init(struct ocelot *ocelot); 495 void ocelot_deinit(struct ocelot *ocelot); 496 int ocelot_chip_init(struct ocelot *ocelot); 497 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 498 void __iomem *regs, 499 struct phy_device *phy); 500 501 extern struct notifier_block ocelot_netdevice_nb; 502 extern struct notifier_block ocelot_switchdev_nb; 503 extern struct notifier_block ocelot_switchdev_blocking_nb; 504 505 #endif 506