1a556c76aSAlexandre Belloni /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a556c76aSAlexandre Belloni /* 3a556c76aSAlexandre Belloni * Microsemi Ocelot Switch driver 4a556c76aSAlexandre Belloni * 5a556c76aSAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 6a556c76aSAlexandre Belloni */ 7a556c76aSAlexandre Belloni 8a556c76aSAlexandre Belloni #ifndef _MSCC_OCELOT_H_ 9a556c76aSAlexandre Belloni #define _MSCC_OCELOT_H_ 10a556c76aSAlexandre Belloni 11a556c76aSAlexandre Belloni #include <linux/bitops.h> 12a556c76aSAlexandre Belloni #include <linux/etherdevice.h> 13a556c76aSAlexandre Belloni #include <linux/if_vlan.h> 1471e32a20SQuentin Schulz #include <linux/phy.h> 1571e32a20SQuentin Schulz #include <linux/phy/phy.h> 16a556c76aSAlexandre Belloni #include <linux/platform_device.h> 17a556c76aSAlexandre Belloni #include <linux/regmap.h> 18a556c76aSAlexandre Belloni 19a556c76aSAlexandre Belloni #include "ocelot_ana.h" 20a556c76aSAlexandre Belloni #include "ocelot_dev.h" 21a556c76aSAlexandre Belloni #include "ocelot_qsys.h" 22a556c76aSAlexandre Belloni #include "ocelot_rew.h" 23a556c76aSAlexandre Belloni #include "ocelot_sys.h" 24a556c76aSAlexandre Belloni #include "ocelot_qs.h" 252c1d029aSJoergen Andreasen #include "ocelot_tc.h" 2645bce171SAntoine Tenart #include "ocelot_ptp.h" 27a556c76aSAlexandre Belloni 28a556c76aSAlexandre Belloni #define PGID_AGGR 64 29a556c76aSAlexandre Belloni #define PGID_SRC 80 30a556c76aSAlexandre Belloni 31a556c76aSAlexandre Belloni /* Reserved PGIDs */ 32a556c76aSAlexandre Belloni #define PGID_CPU (PGID_AGGR - 5) 33a556c76aSAlexandre Belloni #define PGID_UC (PGID_AGGR - 4) 34a556c76aSAlexandre Belloni #define PGID_MC (PGID_AGGR - 3) 35a556c76aSAlexandre Belloni #define PGID_MCIPV4 (PGID_AGGR - 2) 36a556c76aSAlexandre Belloni #define PGID_MCIPV6 (PGID_AGGR - 1) 37a556c76aSAlexandre Belloni 38a556c76aSAlexandre Belloni #define OCELOT_BUFFER_CELL_SZ 60 39a556c76aSAlexandre Belloni 40a556c76aSAlexandre Belloni #define OCELOT_STATS_CHECK_DELAY (2 * HZ) 41a556c76aSAlexandre Belloni 42a556c76aSAlexandre Belloni #define IFH_LEN 4 43a556c76aSAlexandre Belloni 44a556c76aSAlexandre Belloni struct frame_info { 45a556c76aSAlexandre Belloni u32 len; 46a556c76aSAlexandre Belloni u16 port; 47a556c76aSAlexandre Belloni u16 vid; 48a556c76aSAlexandre Belloni u8 cpuq; 49a556c76aSAlexandre Belloni u8 tag_type; 50a556c76aSAlexandre Belloni }; 51a556c76aSAlexandre Belloni 52a556c76aSAlexandre Belloni #define IFH_INJ_BYPASS BIT(31) 53a556c76aSAlexandre Belloni #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 54a556c76aSAlexandre Belloni 55a556c76aSAlexandre Belloni #define IFH_TAG_TYPE_C 0 56a556c76aSAlexandre Belloni #define IFH_TAG_TYPE_S 1 57a556c76aSAlexandre Belloni 58a556c76aSAlexandre Belloni #define OCELOT_SPEED_2500 0 59a556c76aSAlexandre Belloni #define OCELOT_SPEED_1000 1 60a556c76aSAlexandre Belloni #define OCELOT_SPEED_100 2 61a556c76aSAlexandre Belloni #define OCELOT_SPEED_10 3 62a556c76aSAlexandre Belloni 63a556c76aSAlexandre Belloni #define TARGET_OFFSET 24 64a556c76aSAlexandre Belloni #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 65a556c76aSAlexandre Belloni #define REG(reg, offset) [reg & REG_MASK] = offset 66a556c76aSAlexandre Belloni 67a556c76aSAlexandre Belloni enum ocelot_target { 68a556c76aSAlexandre Belloni ANA = 1, 69a556c76aSAlexandre Belloni QS, 70a556c76aSAlexandre Belloni QSYS, 71a556c76aSAlexandre Belloni REW, 72a556c76aSAlexandre Belloni SYS, 73b5962294SHoratiu Vultur S2, 74a556c76aSAlexandre Belloni HSIO, 7545bce171SAntoine Tenart PTP, 76a556c76aSAlexandre Belloni TARGET_MAX, 77a556c76aSAlexandre Belloni }; 78a556c76aSAlexandre Belloni 79a556c76aSAlexandre Belloni enum ocelot_reg { 80a556c76aSAlexandre Belloni ANA_ADVLEARN = ANA << TARGET_OFFSET, 81a556c76aSAlexandre Belloni ANA_VLANMASK, 82a556c76aSAlexandre Belloni ANA_PORT_B_DOMAIN, 83a556c76aSAlexandre Belloni ANA_ANAGEFIL, 84a556c76aSAlexandre Belloni ANA_ANEVENTS, 85a556c76aSAlexandre Belloni ANA_STORMLIMIT_BURST, 86a556c76aSAlexandre Belloni ANA_STORMLIMIT_CFG, 87a556c76aSAlexandre Belloni ANA_ISOLATED_PORTS, 88a556c76aSAlexandre Belloni ANA_COMMUNITY_PORTS, 89a556c76aSAlexandre Belloni ANA_AUTOAGE, 90a556c76aSAlexandre Belloni ANA_MACTOPTIONS, 91a556c76aSAlexandre Belloni ANA_LEARNDISC, 92a556c76aSAlexandre Belloni ANA_AGENCTRL, 93a556c76aSAlexandre Belloni ANA_MIRRORPORTS, 94a556c76aSAlexandre Belloni ANA_EMIRRORPORTS, 95a556c76aSAlexandre Belloni ANA_FLOODING, 96a556c76aSAlexandre Belloni ANA_FLOODING_IPMC, 97a556c76aSAlexandre Belloni ANA_SFLOW_CFG, 98a556c76aSAlexandre Belloni ANA_PORT_MODE, 99a556c76aSAlexandre Belloni ANA_CUT_THRU_CFG, 100a556c76aSAlexandre Belloni ANA_PGID_PGID, 101a556c76aSAlexandre Belloni ANA_TABLES_ANMOVED, 102a556c76aSAlexandre Belloni ANA_TABLES_MACHDATA, 103a556c76aSAlexandre Belloni ANA_TABLES_MACLDATA, 104a556c76aSAlexandre Belloni ANA_TABLES_STREAMDATA, 105a556c76aSAlexandre Belloni ANA_TABLES_MACACCESS, 106a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX, 107a556c76aSAlexandre Belloni ANA_TABLES_VLANACCESS, 108a556c76aSAlexandre Belloni ANA_TABLES_VLANTIDX, 109a556c76aSAlexandre Belloni ANA_TABLES_ISDXACCESS, 110a556c76aSAlexandre Belloni ANA_TABLES_ISDXTIDX, 111a556c76aSAlexandre Belloni ANA_TABLES_ENTRYLIM, 112a556c76aSAlexandre Belloni ANA_TABLES_PTP_ID_HIGH, 113a556c76aSAlexandre Belloni ANA_TABLES_PTP_ID_LOW, 114a556c76aSAlexandre Belloni ANA_TABLES_STREAMACCESS, 115a556c76aSAlexandre Belloni ANA_TABLES_STREAMTIDX, 116a556c76aSAlexandre Belloni ANA_TABLES_SEQ_HISTORY, 117a556c76aSAlexandre Belloni ANA_TABLES_SEQ_MASK, 118a556c76aSAlexandre Belloni ANA_TABLES_SFID_MASK, 119a556c76aSAlexandre Belloni ANA_TABLES_SFIDACCESS, 120a556c76aSAlexandre Belloni ANA_TABLES_SFIDTIDX, 121a556c76aSAlexandre Belloni ANA_MSTI_STATE, 122a556c76aSAlexandre Belloni ANA_OAM_UPM_LM_CNT, 123a556c76aSAlexandre Belloni ANA_SG_ACCESS_CTRL, 124a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_1, 125a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_2, 126a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_3, 127a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_4, 128a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_5, 129a556c76aSAlexandre Belloni ANA_SG_GCL_GS_CONFIG, 130a556c76aSAlexandre Belloni ANA_SG_GCL_TI_CONFIG, 131a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_1, 132a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_2, 133a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_3, 134a556c76aSAlexandre Belloni ANA_PORT_VLAN_CFG, 135a556c76aSAlexandre Belloni ANA_PORT_DROP_CFG, 136a556c76aSAlexandre Belloni ANA_PORT_QOS_CFG, 137a556c76aSAlexandre Belloni ANA_PORT_VCAP_CFG, 138a556c76aSAlexandre Belloni ANA_PORT_VCAP_S1_KEY_CFG, 139a556c76aSAlexandre Belloni ANA_PORT_VCAP_S2_CFG, 140a556c76aSAlexandre Belloni ANA_PORT_PCP_DEI_MAP, 141a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_CFG, 142a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_BPDU_CFG, 143a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_GARP_CFG, 144a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_CCM_CFG, 145a556c76aSAlexandre Belloni ANA_PORT_PORT_CFG, 146a556c76aSAlexandre Belloni ANA_PORT_POL_CFG, 147a556c76aSAlexandre Belloni ANA_PORT_PTP_CFG, 148a556c76aSAlexandre Belloni ANA_PORT_PTP_DLY1_CFG, 149a556c76aSAlexandre Belloni ANA_PORT_PTP_DLY2_CFG, 150a556c76aSAlexandre Belloni ANA_PORT_SFID_CFG, 151a556c76aSAlexandre Belloni ANA_PFC_PFC_CFG, 152a556c76aSAlexandre Belloni ANA_PFC_PFC_TIMER, 153a556c76aSAlexandre Belloni ANA_IPT_OAM_MEP_CFG, 154a556c76aSAlexandre Belloni ANA_IPT_IPT, 155a556c76aSAlexandre Belloni ANA_PPT_PPT, 156a556c76aSAlexandre Belloni ANA_FID_MAP_FID_MAP, 157a556c76aSAlexandre Belloni ANA_AGGR_CFG, 158a556c76aSAlexandre Belloni ANA_CPUQ_CFG, 159a556c76aSAlexandre Belloni ANA_CPUQ_CFG2, 160a556c76aSAlexandre Belloni ANA_CPUQ_8021_CFG, 161a556c76aSAlexandre Belloni ANA_DSCP_CFG, 162a556c76aSAlexandre Belloni ANA_DSCP_REWR_CFG, 163a556c76aSAlexandre Belloni ANA_VCAP_RNG_TYPE_CFG, 164a556c76aSAlexandre Belloni ANA_VCAP_RNG_VAL_CFG, 165a556c76aSAlexandre Belloni ANA_VRAP_CFG, 166a556c76aSAlexandre Belloni ANA_VRAP_HDR_DATA, 167a556c76aSAlexandre Belloni ANA_VRAP_HDR_MASK, 168a556c76aSAlexandre Belloni ANA_DISCARD_CFG, 169a556c76aSAlexandre Belloni ANA_FID_CFG, 170a556c76aSAlexandre Belloni ANA_POL_PIR_CFG, 171a556c76aSAlexandre Belloni ANA_POL_CIR_CFG, 172a556c76aSAlexandre Belloni ANA_POL_MODE_CFG, 173a556c76aSAlexandre Belloni ANA_POL_PIR_STATE, 174a556c76aSAlexandre Belloni ANA_POL_CIR_STATE, 175a556c76aSAlexandre Belloni ANA_POL_STATE, 176a556c76aSAlexandre Belloni ANA_POL_FLOWC, 177a556c76aSAlexandre Belloni ANA_POL_HYST, 178a556c76aSAlexandre Belloni ANA_POL_MISC_CFG, 179a556c76aSAlexandre Belloni QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 180a556c76aSAlexandre Belloni QS_XTR_RD, 181a556c76aSAlexandre Belloni QS_XTR_FRM_PRUNING, 182a556c76aSAlexandre Belloni QS_XTR_FLUSH, 183a556c76aSAlexandre Belloni QS_XTR_DATA_PRESENT, 184a556c76aSAlexandre Belloni QS_XTR_CFG, 185a556c76aSAlexandre Belloni QS_INJ_GRP_CFG, 186a556c76aSAlexandre Belloni QS_INJ_WR, 187a556c76aSAlexandre Belloni QS_INJ_CTRL, 188a556c76aSAlexandre Belloni QS_INJ_STATUS, 189a556c76aSAlexandre Belloni QS_INJ_ERR, 190a556c76aSAlexandre Belloni QS_INH_DBG, 191a556c76aSAlexandre Belloni QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 192a556c76aSAlexandre Belloni QSYS_SWITCH_PORT_MODE, 193a556c76aSAlexandre Belloni QSYS_STAT_CNT_CFG, 194a556c76aSAlexandre Belloni QSYS_EEE_CFG, 195a556c76aSAlexandre Belloni QSYS_EEE_THRES, 196a556c76aSAlexandre Belloni QSYS_IGR_NO_SHARING, 197a556c76aSAlexandre Belloni QSYS_EGR_NO_SHARING, 198a556c76aSAlexandre Belloni QSYS_SW_STATUS, 199a556c76aSAlexandre Belloni QSYS_EXT_CPU_CFG, 200a556c76aSAlexandre Belloni QSYS_PAD_CFG, 201a556c76aSAlexandre Belloni QSYS_CPU_GROUP_MAP, 202a556c76aSAlexandre Belloni QSYS_QMAP, 203a556c76aSAlexandre Belloni QSYS_ISDX_SGRP, 204a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY, 205a556c76aSAlexandre Belloni QSYS_TFRM_MISC, 206a556c76aSAlexandre Belloni QSYS_TFRM_PORT_DLY, 207a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_1, 208a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_2, 209a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_3, 210a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_4, 211a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_5, 212a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_6, 213a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_7, 214a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_8, 215a556c76aSAlexandre Belloni QSYS_RED_PROFILE, 216a556c76aSAlexandre Belloni QSYS_RES_QOS_MODE, 217a556c76aSAlexandre Belloni QSYS_RES_CFG, 218a556c76aSAlexandre Belloni QSYS_RES_STAT, 219a556c76aSAlexandre Belloni QSYS_EGR_DROP_MODE, 220a556c76aSAlexandre Belloni QSYS_EQ_CTRL, 221a556c76aSAlexandre Belloni QSYS_EVENTS_CORE, 222a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_0, 223a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_1, 224a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_2, 225a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_3, 226a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_4, 227a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_5, 228a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_6, 229a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_7, 230a556c76aSAlexandre Belloni QSYS_PREEMPTION_CFG, 231a556c76aSAlexandre Belloni QSYS_CIR_CFG, 232a556c76aSAlexandre Belloni QSYS_EIR_CFG, 233a556c76aSAlexandre Belloni QSYS_SE_CFG, 234a556c76aSAlexandre Belloni QSYS_SE_DWRR_CFG, 235a556c76aSAlexandre Belloni QSYS_SE_CONNECT, 236a556c76aSAlexandre Belloni QSYS_SE_DLB_SENSE, 237a556c76aSAlexandre Belloni QSYS_CIR_STATE, 238a556c76aSAlexandre Belloni QSYS_EIR_STATE, 239a556c76aSAlexandre Belloni QSYS_SE_STATE, 240a556c76aSAlexandre Belloni QSYS_HSCH_MISC_CFG, 241a556c76aSAlexandre Belloni QSYS_TAG_CONFIG, 242a556c76aSAlexandre Belloni QSYS_TAS_PARAM_CFG_CTRL, 243a556c76aSAlexandre Belloni QSYS_PORT_MAX_SDU, 244a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_1, 245a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_2, 246a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_3, 247a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_4, 248a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_5, 249a556c76aSAlexandre Belloni QSYS_GCL_CFG_REG_1, 250a556c76aSAlexandre Belloni QSYS_GCL_CFG_REG_2, 251a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_1, 252a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_2, 253a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_3, 254a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_4, 255a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_5, 256a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_6, 257a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_7, 258a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_8, 259a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_9, 260a556c76aSAlexandre Belloni QSYS_GCL_STATUS_REG_1, 261a556c76aSAlexandre Belloni QSYS_GCL_STATUS_REG_2, 262a556c76aSAlexandre Belloni REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 263a556c76aSAlexandre Belloni REW_TAG_CFG, 264a556c76aSAlexandre Belloni REW_PORT_CFG, 265a556c76aSAlexandre Belloni REW_DSCP_CFG, 266a556c76aSAlexandre Belloni REW_PCP_DEI_QOS_MAP_CFG, 267a556c76aSAlexandre Belloni REW_PTP_CFG, 268a556c76aSAlexandre Belloni REW_PTP_DLY1_CFG, 269a556c76aSAlexandre Belloni REW_RED_TAG_CFG, 270a556c76aSAlexandre Belloni REW_DSCP_REMAP_DP1_CFG, 271a556c76aSAlexandre Belloni REW_DSCP_REMAP_CFG, 272a556c76aSAlexandre Belloni REW_STAT_CFG, 273a556c76aSAlexandre Belloni REW_REW_STICKY, 274a556c76aSAlexandre Belloni REW_PPT, 275a556c76aSAlexandre Belloni SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 276a556c76aSAlexandre Belloni SYS_COUNT_RX_UNICAST, 277a556c76aSAlexandre Belloni SYS_COUNT_RX_MULTICAST, 278a556c76aSAlexandre Belloni SYS_COUNT_RX_BROADCAST, 279a556c76aSAlexandre Belloni SYS_COUNT_RX_SHORTS, 280a556c76aSAlexandre Belloni SYS_COUNT_RX_FRAGMENTS, 281a556c76aSAlexandre Belloni SYS_COUNT_RX_JABBERS, 282a556c76aSAlexandre Belloni SYS_COUNT_RX_CRC_ALIGN_ERRS, 283a556c76aSAlexandre Belloni SYS_COUNT_RX_SYM_ERRS, 284a556c76aSAlexandre Belloni SYS_COUNT_RX_64, 285a556c76aSAlexandre Belloni SYS_COUNT_RX_65_127, 286a556c76aSAlexandre Belloni SYS_COUNT_RX_128_255, 287a556c76aSAlexandre Belloni SYS_COUNT_RX_256_1023, 288a556c76aSAlexandre Belloni SYS_COUNT_RX_1024_1526, 289a556c76aSAlexandre Belloni SYS_COUNT_RX_1527_MAX, 290a556c76aSAlexandre Belloni SYS_COUNT_RX_PAUSE, 291a556c76aSAlexandre Belloni SYS_COUNT_RX_CONTROL, 292a556c76aSAlexandre Belloni SYS_COUNT_RX_LONGS, 293a556c76aSAlexandre Belloni SYS_COUNT_RX_CLASSIFIED_DROPS, 294a556c76aSAlexandre Belloni SYS_COUNT_TX_OCTETS, 295a556c76aSAlexandre Belloni SYS_COUNT_TX_UNICAST, 296a556c76aSAlexandre Belloni SYS_COUNT_TX_MULTICAST, 297a556c76aSAlexandre Belloni SYS_COUNT_TX_BROADCAST, 298a556c76aSAlexandre Belloni SYS_COUNT_TX_COLLISION, 299a556c76aSAlexandre Belloni SYS_COUNT_TX_DROPS, 300a556c76aSAlexandre Belloni SYS_COUNT_TX_PAUSE, 301a556c76aSAlexandre Belloni SYS_COUNT_TX_64, 302a556c76aSAlexandre Belloni SYS_COUNT_TX_65_127, 303a556c76aSAlexandre Belloni SYS_COUNT_TX_128_511, 304a556c76aSAlexandre Belloni SYS_COUNT_TX_512_1023, 305a556c76aSAlexandre Belloni SYS_COUNT_TX_1024_1526, 306a556c76aSAlexandre Belloni SYS_COUNT_TX_1527_MAX, 307a556c76aSAlexandre Belloni SYS_COUNT_TX_AGING, 308a556c76aSAlexandre Belloni SYS_RESET_CFG, 309a556c76aSAlexandre Belloni SYS_SR_ETYPE_CFG, 310a556c76aSAlexandre Belloni SYS_VLAN_ETYPE_CFG, 311a556c76aSAlexandre Belloni SYS_PORT_MODE, 312a556c76aSAlexandre Belloni SYS_FRONT_PORT_MODE, 313a556c76aSAlexandre Belloni SYS_FRM_AGING, 314a556c76aSAlexandre Belloni SYS_STAT_CFG, 315a556c76aSAlexandre Belloni SYS_SW_STATUS, 316a556c76aSAlexandre Belloni SYS_MISC_CFG, 317a556c76aSAlexandre Belloni SYS_REW_MAC_HIGH_CFG, 318a556c76aSAlexandre Belloni SYS_REW_MAC_LOW_CFG, 319a556c76aSAlexandre Belloni SYS_TIMESTAMP_OFFSET, 320a556c76aSAlexandre Belloni SYS_CMID, 321a556c76aSAlexandre Belloni SYS_PAUSE_CFG, 322a556c76aSAlexandre Belloni SYS_PAUSE_TOT_CFG, 323a556c76aSAlexandre Belloni SYS_ATOP, 324a556c76aSAlexandre Belloni SYS_ATOP_TOT_CFG, 325a556c76aSAlexandre Belloni SYS_MAC_FC_CFG, 326a556c76aSAlexandre Belloni SYS_MMGT, 327a556c76aSAlexandre Belloni SYS_MMGT_FAST, 328a556c76aSAlexandre Belloni SYS_EVENTS_DIF, 329a556c76aSAlexandre Belloni SYS_EVENTS_CORE, 330a556c76aSAlexandre Belloni SYS_CNT, 331a556c76aSAlexandre Belloni SYS_PTP_STATUS, 332a556c76aSAlexandre Belloni SYS_PTP_TXSTAMP, 333a556c76aSAlexandre Belloni SYS_PTP_NXT, 334a556c76aSAlexandre Belloni SYS_PTP_CFG, 335a556c76aSAlexandre Belloni SYS_RAM_INIT, 336a556c76aSAlexandre Belloni SYS_CM_ADDR, 337a556c76aSAlexandre Belloni SYS_CM_DATA_WR, 338a556c76aSAlexandre Belloni SYS_CM_DATA_RD, 339a556c76aSAlexandre Belloni SYS_CM_OP, 340a556c76aSAlexandre Belloni SYS_CM_DATA, 341b5962294SHoratiu Vultur S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 342b5962294SHoratiu Vultur S2_CORE_MV_CFG, 343b5962294SHoratiu Vultur S2_CACHE_ENTRY_DAT, 344b5962294SHoratiu Vultur S2_CACHE_MASK_DAT, 345b5962294SHoratiu Vultur S2_CACHE_ACTION_DAT, 346b5962294SHoratiu Vultur S2_CACHE_CNT_DAT, 347b5962294SHoratiu Vultur S2_CACHE_TG_DAT, 34845bce171SAntoine Tenart PTP_PIN_CFG = PTP << TARGET_OFFSET, 34945bce171SAntoine Tenart PTP_PIN_TOD_SEC_MSB, 35045bce171SAntoine Tenart PTP_PIN_TOD_SEC_LSB, 35145bce171SAntoine Tenart PTP_PIN_TOD_NSEC, 35245bce171SAntoine Tenart PTP_CFG_MISC, 35345bce171SAntoine Tenart PTP_CLK_CFG_ADJ_CFG, 35445bce171SAntoine Tenart PTP_CLK_CFG_ADJ_FREQ, 355a556c76aSAlexandre Belloni }; 356a556c76aSAlexandre Belloni 357a556c76aSAlexandre Belloni enum ocelot_regfield { 358a556c76aSAlexandre Belloni ANA_ADVLEARN_VLAN_CHK, 359a556c76aSAlexandre Belloni ANA_ADVLEARN_LEARN_MIRROR, 360a556c76aSAlexandre Belloni ANA_ANEVENTS_FLOOD_DISCARD, 361a556c76aSAlexandre Belloni ANA_ANEVENTS_MSTI_DROP, 362a556c76aSAlexandre Belloni ANA_ANEVENTS_ACLKILL, 363a556c76aSAlexandre Belloni ANA_ANEVENTS_ACLUSED, 364a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTOAGE, 365a556c76aSAlexandre Belloni ANA_ANEVENTS_VS2TTL1, 366a556c76aSAlexandre Belloni ANA_ANEVENTS_STORM_DROP, 367a556c76aSAlexandre Belloni ANA_ANEVENTS_LEARN_DROP, 368a556c76aSAlexandre Belloni ANA_ANEVENTS_AGED_ENTRY, 369a556c76aSAlexandre Belloni ANA_ANEVENTS_CPU_LEARN_FAILED, 370a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_LEARN_FAILED, 371a556c76aSAlexandre Belloni ANA_ANEVENTS_LEARN_REMOVE, 372a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_LEARNED, 373a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_MOVED, 374a556c76aSAlexandre Belloni ANA_ANEVENTS_DROPPED, 375a556c76aSAlexandre Belloni ANA_ANEVENTS_CLASSIFIED_DROP, 376a556c76aSAlexandre Belloni ANA_ANEVENTS_CLASSIFIED_COPY, 377a556c76aSAlexandre Belloni ANA_ANEVENTS_VLAN_DISCARD, 378a556c76aSAlexandre Belloni ANA_ANEVENTS_FWD_DISCARD, 379a556c76aSAlexandre Belloni ANA_ANEVENTS_MULTICAST_FLOOD, 380a556c76aSAlexandre Belloni ANA_ANEVENTS_UNICAST_FLOOD, 381a556c76aSAlexandre Belloni ANA_ANEVENTS_DEST_KNOWN, 382a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET3_MATCH, 383a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET2_MATCH, 384a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET1_MATCH, 385a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET0_MATCH, 386a556c76aSAlexandre Belloni ANA_ANEVENTS_CPU_OPERATION, 387a556c76aSAlexandre Belloni ANA_ANEVENTS_DMAC_LOOKUP, 388a556c76aSAlexandre Belloni ANA_ANEVENTS_SMAC_LOOKUP, 389a556c76aSAlexandre Belloni ANA_ANEVENTS_SEQ_GEN_ERR_0, 390a556c76aSAlexandre Belloni ANA_ANEVENTS_SEQ_GEN_ERR_1, 391a556c76aSAlexandre Belloni ANA_TABLES_MACACCESS_B_DOM, 392a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX_BUCKET, 393a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX_M_INDEX, 394a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 395a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 396a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 397a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 398a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 399a556c76aSAlexandre Belloni SYS_RESET_CFG_CORE_ENA, 400a556c76aSAlexandre Belloni SYS_RESET_CFG_MEM_ENA, 401a556c76aSAlexandre Belloni SYS_RESET_CFG_MEM_INIT, 402a556c76aSAlexandre Belloni REGFIELD_MAX 403a556c76aSAlexandre Belloni }; 404a556c76aSAlexandre Belloni 405a556c76aSAlexandre Belloni struct ocelot_multicast { 406a556c76aSAlexandre Belloni struct list_head list; 407a556c76aSAlexandre Belloni unsigned char addr[ETH_ALEN]; 408a556c76aSAlexandre Belloni u16 vid; 409a556c76aSAlexandre Belloni u16 ports; 410a556c76aSAlexandre Belloni }; 411a556c76aSAlexandre Belloni 412a556c76aSAlexandre Belloni struct ocelot_port; 413a556c76aSAlexandre Belloni 414a556c76aSAlexandre Belloni struct ocelot_stat_layout { 415a556c76aSAlexandre Belloni u32 offset; 416a556c76aSAlexandre Belloni char name[ETH_GSTRING_LEN]; 417a556c76aSAlexandre Belloni }; 418a556c76aSAlexandre Belloni 419a556c76aSAlexandre Belloni struct ocelot { 420a556c76aSAlexandre Belloni struct device *dev; 421a556c76aSAlexandre Belloni 422a556c76aSAlexandre Belloni struct regmap *targets[TARGET_MAX]; 423a556c76aSAlexandre Belloni struct regmap_field *regfields[REGFIELD_MAX]; 424a556c76aSAlexandre Belloni const u32 *const *map; 425a556c76aSAlexandre Belloni const struct ocelot_stat_layout *stats_layout; 426a556c76aSAlexandre Belloni unsigned int num_stats; 427a556c76aSAlexandre Belloni 428a556c76aSAlexandre Belloni u8 base_mac[ETH_ALEN]; 429a556c76aSAlexandre Belloni 430a556c76aSAlexandre Belloni struct net_device *hw_bridge_dev; 431a556c76aSAlexandre Belloni u16 bridge_mask; 432a556c76aSAlexandre Belloni u16 bridge_fwd_mask; 433a556c76aSAlexandre Belloni 434a556c76aSAlexandre Belloni struct workqueue_struct *ocelot_owq; 435a556c76aSAlexandre Belloni 436a556c76aSAlexandre Belloni int shared_queue_sz; 437a556c76aSAlexandre Belloni 438a556c76aSAlexandre Belloni u8 num_phys_ports; 439a556c76aSAlexandre Belloni u8 num_cpu_ports; 440a556c76aSAlexandre Belloni struct ocelot_port **ports; 441a556c76aSAlexandre Belloni 442dc96ee37SAlexandre Belloni u32 *lags; 443a556c76aSAlexandre Belloni 444a556c76aSAlexandre Belloni /* Keep track of the vlan port masks */ 445a556c76aSAlexandre Belloni u32 vlan_mask[VLAN_N_VID]; 446a556c76aSAlexandre Belloni 447a556c76aSAlexandre Belloni struct list_head multicast; 448a556c76aSAlexandre Belloni 449a556c76aSAlexandre Belloni /* Workqueue to check statistics for overflow with its lock */ 450a556c76aSAlexandre Belloni struct mutex stats_lock; 451a556c76aSAlexandre Belloni u64 *stats; 452a556c76aSAlexandre Belloni struct delayed_work stats_work; 453a556c76aSAlexandre Belloni struct workqueue_struct *stats_queue; 454a556c76aSAlexandre Belloni }; 455a556c76aSAlexandre Belloni 456a556c76aSAlexandre Belloni struct ocelot_port { 457a556c76aSAlexandre Belloni struct net_device *dev; 458a556c76aSAlexandre Belloni struct ocelot *ocelot; 459a556c76aSAlexandre Belloni struct phy_device *phy; 460a556c76aSAlexandre Belloni void __iomem *regs; 461a556c76aSAlexandre Belloni u8 chip_port; 462a556c76aSAlexandre Belloni 463a556c76aSAlexandre Belloni /* Ingress default VLAN (pvid) */ 464a556c76aSAlexandre Belloni u16 pvid; 465a556c76aSAlexandre Belloni 466a556c76aSAlexandre Belloni /* Egress default VLAN (vid) */ 467a556c76aSAlexandre Belloni u16 vid; 468a556c76aSAlexandre Belloni 469a556c76aSAlexandre Belloni u8 vlan_aware; 470a556c76aSAlexandre Belloni 471a556c76aSAlexandre Belloni u64 *stats; 47271e32a20SQuentin Schulz 47371e32a20SQuentin Schulz phy_interface_t phy_mode; 47471e32a20SQuentin Schulz struct phy *serdes; 4752c1d029aSJoergen Andreasen 4762c1d029aSJoergen Andreasen struct ocelot_port_tc tc; 477a556c76aSAlexandre Belloni }; 478a556c76aSAlexandre Belloni 479a556c76aSAlexandre Belloni u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 480a556c76aSAlexandre Belloni #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 481a556c76aSAlexandre Belloni #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 482a556c76aSAlexandre Belloni #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 483a556c76aSAlexandre Belloni #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 484a556c76aSAlexandre Belloni 485a556c76aSAlexandre Belloni void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 486a556c76aSAlexandre Belloni #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 487a556c76aSAlexandre Belloni #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 488a556c76aSAlexandre Belloni #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 489a556c76aSAlexandre Belloni #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 490a556c76aSAlexandre Belloni 491a556c76aSAlexandre Belloni void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask, 492a556c76aSAlexandre Belloni u32 offset); 493a556c76aSAlexandre Belloni #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 494a556c76aSAlexandre Belloni #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 495a556c76aSAlexandre Belloni #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 496a556c76aSAlexandre Belloni #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 497a556c76aSAlexandre Belloni 498a556c76aSAlexandre Belloni u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 499a556c76aSAlexandre Belloni void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 500a556c76aSAlexandre Belloni 501a556c76aSAlexandre Belloni int ocelot_regfields_init(struct ocelot *ocelot, 502a556c76aSAlexandre Belloni const struct reg_field *const regfields); 503a556c76aSAlexandre Belloni struct regmap *ocelot_io_platform_init(struct ocelot *ocelot, 504a556c76aSAlexandre Belloni struct platform_device *pdev, 505a556c76aSAlexandre Belloni const char *name); 506a556c76aSAlexandre Belloni 507a556c76aSAlexandre Belloni #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 508a556c76aSAlexandre Belloni #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 509a556c76aSAlexandre Belloni 510a556c76aSAlexandre Belloni int ocelot_init(struct ocelot *ocelot); 511a556c76aSAlexandre Belloni void ocelot_deinit(struct ocelot *ocelot); 512a556c76aSAlexandre Belloni int ocelot_chip_init(struct ocelot *ocelot); 513a556c76aSAlexandre Belloni int ocelot_probe_port(struct ocelot *ocelot, u8 port, 514a556c76aSAlexandre Belloni void __iomem *regs, 515a556c76aSAlexandre Belloni struct phy_device *phy); 516a556c76aSAlexandre Belloni 517a556c76aSAlexandre Belloni extern struct notifier_block ocelot_netdevice_nb; 51856da64bcSFlorian Fainelli extern struct notifier_block ocelot_switchdev_nb; 5190e332c85SPetr Machata extern struct notifier_block ocelot_switchdev_blocking_nb; 520a556c76aSAlexandre Belloni 521a556c76aSAlexandre Belloni #endif 522