1a556c76aSAlexandre Belloni /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2a556c76aSAlexandre Belloni /* 3a556c76aSAlexandre Belloni * Microsemi Ocelot Switch driver 4a556c76aSAlexandre Belloni * 5a556c76aSAlexandre Belloni * Copyright (c) 2017 Microsemi Corporation 6a556c76aSAlexandre Belloni */ 7a556c76aSAlexandre Belloni 8a556c76aSAlexandre Belloni #ifndef _MSCC_OCELOT_H_ 9a556c76aSAlexandre Belloni #define _MSCC_OCELOT_H_ 10a556c76aSAlexandre Belloni 11a556c76aSAlexandre Belloni #include <linux/bitops.h> 12a556c76aSAlexandre Belloni #include <linux/etherdevice.h> 13a556c76aSAlexandre Belloni #include <linux/if_vlan.h> 144e3b0468SAntoine Tenart #include <linux/net_tstamp.h> 1571e32a20SQuentin Schulz #include <linux/phy.h> 1671e32a20SQuentin Schulz #include <linux/phy/phy.h> 17a556c76aSAlexandre Belloni #include <linux/platform_device.h> 184e3b0468SAntoine Tenart #include <linux/ptp_clock_kernel.h> 19a556c76aSAlexandre Belloni #include <linux/regmap.h> 20a556c76aSAlexandre Belloni 21a556c76aSAlexandre Belloni #include "ocelot_ana.h" 22a556c76aSAlexandre Belloni #include "ocelot_dev.h" 23a556c76aSAlexandre Belloni #include "ocelot_qsys.h" 24a556c76aSAlexandre Belloni #include "ocelot_rew.h" 25a556c76aSAlexandre Belloni #include "ocelot_sys.h" 26a556c76aSAlexandre Belloni #include "ocelot_qs.h" 272c1d029aSJoergen Andreasen #include "ocelot_tc.h" 2845bce171SAntoine Tenart #include "ocelot_ptp.h" 29a556c76aSAlexandre Belloni 30a556c76aSAlexandre Belloni #define PGID_AGGR 64 31a556c76aSAlexandre Belloni #define PGID_SRC 80 32a556c76aSAlexandre Belloni 33a556c76aSAlexandre Belloni /* Reserved PGIDs */ 34a556c76aSAlexandre Belloni #define PGID_CPU (PGID_AGGR - 5) 35a556c76aSAlexandre Belloni #define PGID_UC (PGID_AGGR - 4) 36a556c76aSAlexandre Belloni #define PGID_MC (PGID_AGGR - 3) 37a556c76aSAlexandre Belloni #define PGID_MCIPV4 (PGID_AGGR - 2) 38a556c76aSAlexandre Belloni #define PGID_MCIPV6 (PGID_AGGR - 1) 39a556c76aSAlexandre Belloni 40a556c76aSAlexandre Belloni #define OCELOT_BUFFER_CELL_SZ 60 41a556c76aSAlexandre Belloni 42a556c76aSAlexandre Belloni #define OCELOT_STATS_CHECK_DELAY (2 * HZ) 43a556c76aSAlexandre Belloni 444e3b0468SAntoine Tenart #define OCELOT_PTP_QUEUE_SZ 128 454e3b0468SAntoine Tenart 46a556c76aSAlexandre Belloni #define IFH_LEN 4 47a556c76aSAlexandre Belloni 48a556c76aSAlexandre Belloni struct frame_info { 49a556c76aSAlexandre Belloni u32 len; 50a556c76aSAlexandre Belloni u16 port; 51a556c76aSAlexandre Belloni u16 vid; 52a556c76aSAlexandre Belloni u8 tag_type; 534e3b0468SAntoine Tenart u16 rew_op; 544e3b0468SAntoine Tenart u32 timestamp; /* rew_val */ 55a556c76aSAlexandre Belloni }; 56a556c76aSAlexandre Belloni 57a556c76aSAlexandre Belloni #define IFH_INJ_BYPASS BIT(31) 58a556c76aSAlexandre Belloni #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 59a556c76aSAlexandre Belloni 60a556c76aSAlexandre Belloni #define IFH_TAG_TYPE_C 0 61a556c76aSAlexandre Belloni #define IFH_TAG_TYPE_S 1 62a556c76aSAlexandre Belloni 634e3b0468SAntoine Tenart #define IFH_REW_OP_NOOP 0x0 644e3b0468SAntoine Tenart #define IFH_REW_OP_DSCP 0x1 654e3b0468SAntoine Tenart #define IFH_REW_OP_ONE_STEP_PTP 0x2 664e3b0468SAntoine Tenart #define IFH_REW_OP_TWO_STEP_PTP 0x3 674e3b0468SAntoine Tenart #define IFH_REW_OP_ORIGIN_PTP 0x5 684e3b0468SAntoine Tenart 69a556c76aSAlexandre Belloni #define OCELOT_SPEED_2500 0 70a556c76aSAlexandre Belloni #define OCELOT_SPEED_1000 1 71a556c76aSAlexandre Belloni #define OCELOT_SPEED_100 2 72a556c76aSAlexandre Belloni #define OCELOT_SPEED_10 3 73a556c76aSAlexandre Belloni 74a556c76aSAlexandre Belloni #define TARGET_OFFSET 24 75a556c76aSAlexandre Belloni #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 76a556c76aSAlexandre Belloni #define REG(reg, offset) [reg & REG_MASK] = offset 77a556c76aSAlexandre Belloni 78a556c76aSAlexandre Belloni enum ocelot_target { 79a556c76aSAlexandre Belloni ANA = 1, 80a556c76aSAlexandre Belloni QS, 81a556c76aSAlexandre Belloni QSYS, 82a556c76aSAlexandre Belloni REW, 83a556c76aSAlexandre Belloni SYS, 84b5962294SHoratiu Vultur S2, 85a556c76aSAlexandre Belloni HSIO, 8645bce171SAntoine Tenart PTP, 87a556c76aSAlexandre Belloni TARGET_MAX, 88a556c76aSAlexandre Belloni }; 89a556c76aSAlexandre Belloni 90a556c76aSAlexandre Belloni enum ocelot_reg { 91a556c76aSAlexandre Belloni ANA_ADVLEARN = ANA << TARGET_OFFSET, 92a556c76aSAlexandre Belloni ANA_VLANMASK, 93a556c76aSAlexandre Belloni ANA_PORT_B_DOMAIN, 94a556c76aSAlexandre Belloni ANA_ANAGEFIL, 95a556c76aSAlexandre Belloni ANA_ANEVENTS, 96a556c76aSAlexandre Belloni ANA_STORMLIMIT_BURST, 97a556c76aSAlexandre Belloni ANA_STORMLIMIT_CFG, 98a556c76aSAlexandre Belloni ANA_ISOLATED_PORTS, 99a556c76aSAlexandre Belloni ANA_COMMUNITY_PORTS, 100a556c76aSAlexandre Belloni ANA_AUTOAGE, 101a556c76aSAlexandre Belloni ANA_MACTOPTIONS, 102a556c76aSAlexandre Belloni ANA_LEARNDISC, 103a556c76aSAlexandre Belloni ANA_AGENCTRL, 104a556c76aSAlexandre Belloni ANA_MIRRORPORTS, 105a556c76aSAlexandre Belloni ANA_EMIRRORPORTS, 106a556c76aSAlexandre Belloni ANA_FLOODING, 107a556c76aSAlexandre Belloni ANA_FLOODING_IPMC, 108a556c76aSAlexandre Belloni ANA_SFLOW_CFG, 109a556c76aSAlexandre Belloni ANA_PORT_MODE, 110a556c76aSAlexandre Belloni ANA_CUT_THRU_CFG, 111a556c76aSAlexandre Belloni ANA_PGID_PGID, 112a556c76aSAlexandre Belloni ANA_TABLES_ANMOVED, 113a556c76aSAlexandre Belloni ANA_TABLES_MACHDATA, 114a556c76aSAlexandre Belloni ANA_TABLES_MACLDATA, 115a556c76aSAlexandre Belloni ANA_TABLES_STREAMDATA, 116a556c76aSAlexandre Belloni ANA_TABLES_MACACCESS, 117a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX, 118a556c76aSAlexandre Belloni ANA_TABLES_VLANACCESS, 119a556c76aSAlexandre Belloni ANA_TABLES_VLANTIDX, 120a556c76aSAlexandre Belloni ANA_TABLES_ISDXACCESS, 121a556c76aSAlexandre Belloni ANA_TABLES_ISDXTIDX, 122a556c76aSAlexandre Belloni ANA_TABLES_ENTRYLIM, 123a556c76aSAlexandre Belloni ANA_TABLES_PTP_ID_HIGH, 124a556c76aSAlexandre Belloni ANA_TABLES_PTP_ID_LOW, 125a556c76aSAlexandre Belloni ANA_TABLES_STREAMACCESS, 126a556c76aSAlexandre Belloni ANA_TABLES_STREAMTIDX, 127a556c76aSAlexandre Belloni ANA_TABLES_SEQ_HISTORY, 128a556c76aSAlexandre Belloni ANA_TABLES_SEQ_MASK, 129a556c76aSAlexandre Belloni ANA_TABLES_SFID_MASK, 130a556c76aSAlexandre Belloni ANA_TABLES_SFIDACCESS, 131a556c76aSAlexandre Belloni ANA_TABLES_SFIDTIDX, 132a556c76aSAlexandre Belloni ANA_MSTI_STATE, 133a556c76aSAlexandre Belloni ANA_OAM_UPM_LM_CNT, 134a556c76aSAlexandre Belloni ANA_SG_ACCESS_CTRL, 135a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_1, 136a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_2, 137a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_3, 138a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_4, 139a556c76aSAlexandre Belloni ANA_SG_CONFIG_REG_5, 140a556c76aSAlexandre Belloni ANA_SG_GCL_GS_CONFIG, 141a556c76aSAlexandre Belloni ANA_SG_GCL_TI_CONFIG, 142a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_1, 143a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_2, 144a556c76aSAlexandre Belloni ANA_SG_STATUS_REG_3, 145a556c76aSAlexandre Belloni ANA_PORT_VLAN_CFG, 146a556c76aSAlexandre Belloni ANA_PORT_DROP_CFG, 147a556c76aSAlexandre Belloni ANA_PORT_QOS_CFG, 148a556c76aSAlexandre Belloni ANA_PORT_VCAP_CFG, 149a556c76aSAlexandre Belloni ANA_PORT_VCAP_S1_KEY_CFG, 150a556c76aSAlexandre Belloni ANA_PORT_VCAP_S2_CFG, 151a556c76aSAlexandre Belloni ANA_PORT_PCP_DEI_MAP, 152a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_CFG, 153a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_BPDU_CFG, 154a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_GARP_CFG, 155a556c76aSAlexandre Belloni ANA_PORT_CPU_FWD_CCM_CFG, 156a556c76aSAlexandre Belloni ANA_PORT_PORT_CFG, 157a556c76aSAlexandre Belloni ANA_PORT_POL_CFG, 158a556c76aSAlexandre Belloni ANA_PORT_PTP_CFG, 159a556c76aSAlexandre Belloni ANA_PORT_PTP_DLY1_CFG, 160a556c76aSAlexandre Belloni ANA_PORT_PTP_DLY2_CFG, 161a556c76aSAlexandre Belloni ANA_PORT_SFID_CFG, 162a556c76aSAlexandre Belloni ANA_PFC_PFC_CFG, 163a556c76aSAlexandre Belloni ANA_PFC_PFC_TIMER, 164a556c76aSAlexandre Belloni ANA_IPT_OAM_MEP_CFG, 165a556c76aSAlexandre Belloni ANA_IPT_IPT, 166a556c76aSAlexandre Belloni ANA_PPT_PPT, 167a556c76aSAlexandre Belloni ANA_FID_MAP_FID_MAP, 168a556c76aSAlexandre Belloni ANA_AGGR_CFG, 169a556c76aSAlexandre Belloni ANA_CPUQ_CFG, 170a556c76aSAlexandre Belloni ANA_CPUQ_CFG2, 171a556c76aSAlexandre Belloni ANA_CPUQ_8021_CFG, 172a556c76aSAlexandre Belloni ANA_DSCP_CFG, 173a556c76aSAlexandre Belloni ANA_DSCP_REWR_CFG, 174a556c76aSAlexandre Belloni ANA_VCAP_RNG_TYPE_CFG, 175a556c76aSAlexandre Belloni ANA_VCAP_RNG_VAL_CFG, 176a556c76aSAlexandre Belloni ANA_VRAP_CFG, 177a556c76aSAlexandre Belloni ANA_VRAP_HDR_DATA, 178a556c76aSAlexandre Belloni ANA_VRAP_HDR_MASK, 179a556c76aSAlexandre Belloni ANA_DISCARD_CFG, 180a556c76aSAlexandre Belloni ANA_FID_CFG, 181a556c76aSAlexandre Belloni ANA_POL_PIR_CFG, 182a556c76aSAlexandre Belloni ANA_POL_CIR_CFG, 183a556c76aSAlexandre Belloni ANA_POL_MODE_CFG, 184a556c76aSAlexandre Belloni ANA_POL_PIR_STATE, 185a556c76aSAlexandre Belloni ANA_POL_CIR_STATE, 186a556c76aSAlexandre Belloni ANA_POL_STATE, 187a556c76aSAlexandre Belloni ANA_POL_FLOWC, 188a556c76aSAlexandre Belloni ANA_POL_HYST, 189a556c76aSAlexandre Belloni ANA_POL_MISC_CFG, 190a556c76aSAlexandre Belloni QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 191a556c76aSAlexandre Belloni QS_XTR_RD, 192a556c76aSAlexandre Belloni QS_XTR_FRM_PRUNING, 193a556c76aSAlexandre Belloni QS_XTR_FLUSH, 194a556c76aSAlexandre Belloni QS_XTR_DATA_PRESENT, 195a556c76aSAlexandre Belloni QS_XTR_CFG, 196a556c76aSAlexandre Belloni QS_INJ_GRP_CFG, 197a556c76aSAlexandre Belloni QS_INJ_WR, 198a556c76aSAlexandre Belloni QS_INJ_CTRL, 199a556c76aSAlexandre Belloni QS_INJ_STATUS, 200a556c76aSAlexandre Belloni QS_INJ_ERR, 201a556c76aSAlexandre Belloni QS_INH_DBG, 202a556c76aSAlexandre Belloni QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 203a556c76aSAlexandre Belloni QSYS_SWITCH_PORT_MODE, 204a556c76aSAlexandre Belloni QSYS_STAT_CNT_CFG, 205a556c76aSAlexandre Belloni QSYS_EEE_CFG, 206a556c76aSAlexandre Belloni QSYS_EEE_THRES, 207a556c76aSAlexandre Belloni QSYS_IGR_NO_SHARING, 208a556c76aSAlexandre Belloni QSYS_EGR_NO_SHARING, 209a556c76aSAlexandre Belloni QSYS_SW_STATUS, 210a556c76aSAlexandre Belloni QSYS_EXT_CPU_CFG, 211a556c76aSAlexandre Belloni QSYS_PAD_CFG, 212a556c76aSAlexandre Belloni QSYS_CPU_GROUP_MAP, 213a556c76aSAlexandre Belloni QSYS_QMAP, 214a556c76aSAlexandre Belloni QSYS_ISDX_SGRP, 215a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY, 216a556c76aSAlexandre Belloni QSYS_TFRM_MISC, 217a556c76aSAlexandre Belloni QSYS_TFRM_PORT_DLY, 218a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_1, 219a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_2, 220a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_3, 221a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_4, 222a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_5, 223a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_6, 224a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_7, 225a556c76aSAlexandre Belloni QSYS_TFRM_TIMER_CFG_8, 226a556c76aSAlexandre Belloni QSYS_RED_PROFILE, 227a556c76aSAlexandre Belloni QSYS_RES_QOS_MODE, 228a556c76aSAlexandre Belloni QSYS_RES_CFG, 229a556c76aSAlexandre Belloni QSYS_RES_STAT, 230a556c76aSAlexandre Belloni QSYS_EGR_DROP_MODE, 231a556c76aSAlexandre Belloni QSYS_EQ_CTRL, 232a556c76aSAlexandre Belloni QSYS_EVENTS_CORE, 233a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_0, 234a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_1, 235a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_2, 236a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_3, 237a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_4, 238a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_5, 239a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_6, 240a556c76aSAlexandre Belloni QSYS_QMAXSDU_CFG_7, 241a556c76aSAlexandre Belloni QSYS_PREEMPTION_CFG, 242a556c76aSAlexandre Belloni QSYS_CIR_CFG, 243a556c76aSAlexandre Belloni QSYS_EIR_CFG, 244a556c76aSAlexandre Belloni QSYS_SE_CFG, 245a556c76aSAlexandre Belloni QSYS_SE_DWRR_CFG, 246a556c76aSAlexandre Belloni QSYS_SE_CONNECT, 247a556c76aSAlexandre Belloni QSYS_SE_DLB_SENSE, 248a556c76aSAlexandre Belloni QSYS_CIR_STATE, 249a556c76aSAlexandre Belloni QSYS_EIR_STATE, 250a556c76aSAlexandre Belloni QSYS_SE_STATE, 251a556c76aSAlexandre Belloni QSYS_HSCH_MISC_CFG, 252a556c76aSAlexandre Belloni QSYS_TAG_CONFIG, 253a556c76aSAlexandre Belloni QSYS_TAS_PARAM_CFG_CTRL, 254a556c76aSAlexandre Belloni QSYS_PORT_MAX_SDU, 255a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_1, 256a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_2, 257a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_3, 258a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_4, 259a556c76aSAlexandre Belloni QSYS_PARAM_CFG_REG_5, 260a556c76aSAlexandre Belloni QSYS_GCL_CFG_REG_1, 261a556c76aSAlexandre Belloni QSYS_GCL_CFG_REG_2, 262a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_1, 263a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_2, 264a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_3, 265a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_4, 266a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_5, 267a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_6, 268a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_7, 269a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_8, 270a556c76aSAlexandre Belloni QSYS_PARAM_STATUS_REG_9, 271a556c76aSAlexandre Belloni QSYS_GCL_STATUS_REG_1, 272a556c76aSAlexandre Belloni QSYS_GCL_STATUS_REG_2, 273a556c76aSAlexandre Belloni REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 274a556c76aSAlexandre Belloni REW_TAG_CFG, 275a556c76aSAlexandre Belloni REW_PORT_CFG, 276a556c76aSAlexandre Belloni REW_DSCP_CFG, 277a556c76aSAlexandre Belloni REW_PCP_DEI_QOS_MAP_CFG, 278a556c76aSAlexandre Belloni REW_PTP_CFG, 279a556c76aSAlexandre Belloni REW_PTP_DLY1_CFG, 280a556c76aSAlexandre Belloni REW_RED_TAG_CFG, 281a556c76aSAlexandre Belloni REW_DSCP_REMAP_DP1_CFG, 282a556c76aSAlexandre Belloni REW_DSCP_REMAP_CFG, 283a556c76aSAlexandre Belloni REW_STAT_CFG, 284a556c76aSAlexandre Belloni REW_REW_STICKY, 285a556c76aSAlexandre Belloni REW_PPT, 286a556c76aSAlexandre Belloni SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 287a556c76aSAlexandre Belloni SYS_COUNT_RX_UNICAST, 288a556c76aSAlexandre Belloni SYS_COUNT_RX_MULTICAST, 289a556c76aSAlexandre Belloni SYS_COUNT_RX_BROADCAST, 290a556c76aSAlexandre Belloni SYS_COUNT_RX_SHORTS, 291a556c76aSAlexandre Belloni SYS_COUNT_RX_FRAGMENTS, 292a556c76aSAlexandre Belloni SYS_COUNT_RX_JABBERS, 293a556c76aSAlexandre Belloni SYS_COUNT_RX_CRC_ALIGN_ERRS, 294a556c76aSAlexandre Belloni SYS_COUNT_RX_SYM_ERRS, 295a556c76aSAlexandre Belloni SYS_COUNT_RX_64, 296a556c76aSAlexandre Belloni SYS_COUNT_RX_65_127, 297a556c76aSAlexandre Belloni SYS_COUNT_RX_128_255, 298a556c76aSAlexandre Belloni SYS_COUNT_RX_256_1023, 299a556c76aSAlexandre Belloni SYS_COUNT_RX_1024_1526, 300a556c76aSAlexandre Belloni SYS_COUNT_RX_1527_MAX, 301a556c76aSAlexandre Belloni SYS_COUNT_RX_PAUSE, 302a556c76aSAlexandre Belloni SYS_COUNT_RX_CONTROL, 303a556c76aSAlexandre Belloni SYS_COUNT_RX_LONGS, 304a556c76aSAlexandre Belloni SYS_COUNT_RX_CLASSIFIED_DROPS, 305a556c76aSAlexandre Belloni SYS_COUNT_TX_OCTETS, 306a556c76aSAlexandre Belloni SYS_COUNT_TX_UNICAST, 307a556c76aSAlexandre Belloni SYS_COUNT_TX_MULTICAST, 308a556c76aSAlexandre Belloni SYS_COUNT_TX_BROADCAST, 309a556c76aSAlexandre Belloni SYS_COUNT_TX_COLLISION, 310a556c76aSAlexandre Belloni SYS_COUNT_TX_DROPS, 311a556c76aSAlexandre Belloni SYS_COUNT_TX_PAUSE, 312a556c76aSAlexandre Belloni SYS_COUNT_TX_64, 313a556c76aSAlexandre Belloni SYS_COUNT_TX_65_127, 314a556c76aSAlexandre Belloni SYS_COUNT_TX_128_511, 315a556c76aSAlexandre Belloni SYS_COUNT_TX_512_1023, 316a556c76aSAlexandre Belloni SYS_COUNT_TX_1024_1526, 317a556c76aSAlexandre Belloni SYS_COUNT_TX_1527_MAX, 318a556c76aSAlexandre Belloni SYS_COUNT_TX_AGING, 319a556c76aSAlexandre Belloni SYS_RESET_CFG, 320a556c76aSAlexandre Belloni SYS_SR_ETYPE_CFG, 321a556c76aSAlexandre Belloni SYS_VLAN_ETYPE_CFG, 322a556c76aSAlexandre Belloni SYS_PORT_MODE, 323a556c76aSAlexandre Belloni SYS_FRONT_PORT_MODE, 324a556c76aSAlexandre Belloni SYS_FRM_AGING, 325a556c76aSAlexandre Belloni SYS_STAT_CFG, 326a556c76aSAlexandre Belloni SYS_SW_STATUS, 327a556c76aSAlexandre Belloni SYS_MISC_CFG, 328a556c76aSAlexandre Belloni SYS_REW_MAC_HIGH_CFG, 329a556c76aSAlexandre Belloni SYS_REW_MAC_LOW_CFG, 330a556c76aSAlexandre Belloni SYS_TIMESTAMP_OFFSET, 331a556c76aSAlexandre Belloni SYS_CMID, 332a556c76aSAlexandre Belloni SYS_PAUSE_CFG, 333a556c76aSAlexandre Belloni SYS_PAUSE_TOT_CFG, 334a556c76aSAlexandre Belloni SYS_ATOP, 335a556c76aSAlexandre Belloni SYS_ATOP_TOT_CFG, 336a556c76aSAlexandre Belloni SYS_MAC_FC_CFG, 337a556c76aSAlexandre Belloni SYS_MMGT, 338a556c76aSAlexandre Belloni SYS_MMGT_FAST, 339a556c76aSAlexandre Belloni SYS_EVENTS_DIF, 340a556c76aSAlexandre Belloni SYS_EVENTS_CORE, 341a556c76aSAlexandre Belloni SYS_CNT, 342a556c76aSAlexandre Belloni SYS_PTP_STATUS, 343a556c76aSAlexandre Belloni SYS_PTP_TXSTAMP, 344a556c76aSAlexandre Belloni SYS_PTP_NXT, 345a556c76aSAlexandre Belloni SYS_PTP_CFG, 346a556c76aSAlexandre Belloni SYS_RAM_INIT, 347a556c76aSAlexandre Belloni SYS_CM_ADDR, 348a556c76aSAlexandre Belloni SYS_CM_DATA_WR, 349a556c76aSAlexandre Belloni SYS_CM_DATA_RD, 350a556c76aSAlexandre Belloni SYS_CM_OP, 351a556c76aSAlexandre Belloni SYS_CM_DATA, 352b5962294SHoratiu Vultur S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 353b5962294SHoratiu Vultur S2_CORE_MV_CFG, 354b5962294SHoratiu Vultur S2_CACHE_ENTRY_DAT, 355b5962294SHoratiu Vultur S2_CACHE_MASK_DAT, 356b5962294SHoratiu Vultur S2_CACHE_ACTION_DAT, 357b5962294SHoratiu Vultur S2_CACHE_CNT_DAT, 358b5962294SHoratiu Vultur S2_CACHE_TG_DAT, 35945bce171SAntoine Tenart PTP_PIN_CFG = PTP << TARGET_OFFSET, 36045bce171SAntoine Tenart PTP_PIN_TOD_SEC_MSB, 36145bce171SAntoine Tenart PTP_PIN_TOD_SEC_LSB, 36245bce171SAntoine Tenart PTP_PIN_TOD_NSEC, 36345bce171SAntoine Tenart PTP_CFG_MISC, 36445bce171SAntoine Tenart PTP_CLK_CFG_ADJ_CFG, 36545bce171SAntoine Tenart PTP_CLK_CFG_ADJ_FREQ, 366a556c76aSAlexandre Belloni }; 367a556c76aSAlexandre Belloni 368a556c76aSAlexandre Belloni enum ocelot_regfield { 369a556c76aSAlexandre Belloni ANA_ADVLEARN_VLAN_CHK, 370a556c76aSAlexandre Belloni ANA_ADVLEARN_LEARN_MIRROR, 371a556c76aSAlexandre Belloni ANA_ANEVENTS_FLOOD_DISCARD, 372a556c76aSAlexandre Belloni ANA_ANEVENTS_MSTI_DROP, 373a556c76aSAlexandre Belloni ANA_ANEVENTS_ACLKILL, 374a556c76aSAlexandre Belloni ANA_ANEVENTS_ACLUSED, 375a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTOAGE, 376a556c76aSAlexandre Belloni ANA_ANEVENTS_VS2TTL1, 377a556c76aSAlexandre Belloni ANA_ANEVENTS_STORM_DROP, 378a556c76aSAlexandre Belloni ANA_ANEVENTS_LEARN_DROP, 379a556c76aSAlexandre Belloni ANA_ANEVENTS_AGED_ENTRY, 380a556c76aSAlexandre Belloni ANA_ANEVENTS_CPU_LEARN_FAILED, 381a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_LEARN_FAILED, 382a556c76aSAlexandre Belloni ANA_ANEVENTS_LEARN_REMOVE, 383a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_LEARNED, 384a556c76aSAlexandre Belloni ANA_ANEVENTS_AUTO_MOVED, 385a556c76aSAlexandre Belloni ANA_ANEVENTS_DROPPED, 386a556c76aSAlexandre Belloni ANA_ANEVENTS_CLASSIFIED_DROP, 387a556c76aSAlexandre Belloni ANA_ANEVENTS_CLASSIFIED_COPY, 388a556c76aSAlexandre Belloni ANA_ANEVENTS_VLAN_DISCARD, 389a556c76aSAlexandre Belloni ANA_ANEVENTS_FWD_DISCARD, 390a556c76aSAlexandre Belloni ANA_ANEVENTS_MULTICAST_FLOOD, 391a556c76aSAlexandre Belloni ANA_ANEVENTS_UNICAST_FLOOD, 392a556c76aSAlexandre Belloni ANA_ANEVENTS_DEST_KNOWN, 393a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET3_MATCH, 394a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET2_MATCH, 395a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET1_MATCH, 396a556c76aSAlexandre Belloni ANA_ANEVENTS_BUCKET0_MATCH, 397a556c76aSAlexandre Belloni ANA_ANEVENTS_CPU_OPERATION, 398a556c76aSAlexandre Belloni ANA_ANEVENTS_DMAC_LOOKUP, 399a556c76aSAlexandre Belloni ANA_ANEVENTS_SMAC_LOOKUP, 400a556c76aSAlexandre Belloni ANA_ANEVENTS_SEQ_GEN_ERR_0, 401a556c76aSAlexandre Belloni ANA_ANEVENTS_SEQ_GEN_ERR_1, 402a556c76aSAlexandre Belloni ANA_TABLES_MACACCESS_B_DOM, 403a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX_BUCKET, 404a556c76aSAlexandre Belloni ANA_TABLES_MACTINDX_M_INDEX, 405a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 406a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 407a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 408a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 409a556c76aSAlexandre Belloni QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 410a556c76aSAlexandre Belloni SYS_RESET_CFG_CORE_ENA, 411a556c76aSAlexandre Belloni SYS_RESET_CFG_MEM_ENA, 412a556c76aSAlexandre Belloni SYS_RESET_CFG_MEM_INIT, 413a556c76aSAlexandre Belloni REGFIELD_MAX 414a556c76aSAlexandre Belloni }; 415a556c76aSAlexandre Belloni 4164e3b0468SAntoine Tenart enum ocelot_clk_pins { 4174e3b0468SAntoine Tenart ALT_PPS_PIN = 1, 4184e3b0468SAntoine Tenart EXT_CLK_PIN, 4194e3b0468SAntoine Tenart ALT_LDST_PIN, 4204e3b0468SAntoine Tenart TOD_ACC_PIN 4214e3b0468SAntoine Tenart }; 4224e3b0468SAntoine Tenart 423a556c76aSAlexandre Belloni struct ocelot_multicast { 424a556c76aSAlexandre Belloni struct list_head list; 425a556c76aSAlexandre Belloni unsigned char addr[ETH_ALEN]; 426a556c76aSAlexandre Belloni u16 vid; 427a556c76aSAlexandre Belloni u16 ports; 428a556c76aSAlexandre Belloni }; 429a556c76aSAlexandre Belloni 43021468199SVladimir Oltean enum ocelot_tag_prefix { 43121468199SVladimir Oltean OCELOT_TAG_PREFIX_DISABLED = 0, 43221468199SVladimir Oltean OCELOT_TAG_PREFIX_NONE, 43321468199SVladimir Oltean OCELOT_TAG_PREFIX_SHORT, 43421468199SVladimir Oltean OCELOT_TAG_PREFIX_LONG, 43521468199SVladimir Oltean }; 43621468199SVladimir Oltean 437a556c76aSAlexandre Belloni struct ocelot_port; 438a556c76aSAlexandre Belloni 439a556c76aSAlexandre Belloni struct ocelot_stat_layout { 440a556c76aSAlexandre Belloni u32 offset; 441a556c76aSAlexandre Belloni char name[ETH_GSTRING_LEN]; 442a556c76aSAlexandre Belloni }; 443a556c76aSAlexandre Belloni 444a556c76aSAlexandre Belloni struct ocelot { 445a556c76aSAlexandre Belloni struct device *dev; 446a556c76aSAlexandre Belloni 447a556c76aSAlexandre Belloni struct regmap *targets[TARGET_MAX]; 448a556c76aSAlexandre Belloni struct regmap_field *regfields[REGFIELD_MAX]; 449a556c76aSAlexandre Belloni const u32 *const *map; 450a556c76aSAlexandre Belloni const struct ocelot_stat_layout *stats_layout; 451a556c76aSAlexandre Belloni unsigned int num_stats; 452a556c76aSAlexandre Belloni 453a556c76aSAlexandre Belloni u8 base_mac[ETH_ALEN]; 454a556c76aSAlexandre Belloni 455a556c76aSAlexandre Belloni struct net_device *hw_bridge_dev; 456a556c76aSAlexandre Belloni u16 bridge_mask; 457a556c76aSAlexandre Belloni u16 bridge_fwd_mask; 458a556c76aSAlexandre Belloni 459a556c76aSAlexandre Belloni struct workqueue_struct *ocelot_owq; 460a556c76aSAlexandre Belloni 461a556c76aSAlexandre Belloni int shared_queue_sz; 462a556c76aSAlexandre Belloni 463a556c76aSAlexandre Belloni u8 num_phys_ports; 464a556c76aSAlexandre Belloni u8 num_cpu_ports; 46521468199SVladimir Oltean u8 cpu; 466a556c76aSAlexandre Belloni struct ocelot_port **ports; 467a556c76aSAlexandre Belloni 468dc96ee37SAlexandre Belloni u32 *lags; 469a556c76aSAlexandre Belloni 470a556c76aSAlexandre Belloni /* Keep track of the vlan port masks */ 471a556c76aSAlexandre Belloni u32 vlan_mask[VLAN_N_VID]; 472a556c76aSAlexandre Belloni 473a556c76aSAlexandre Belloni struct list_head multicast; 474a556c76aSAlexandre Belloni 475a556c76aSAlexandre Belloni /* Workqueue to check statistics for overflow with its lock */ 476a556c76aSAlexandre Belloni struct mutex stats_lock; 477a556c76aSAlexandre Belloni u64 *stats; 478a556c76aSAlexandre Belloni struct delayed_work stats_work; 479a556c76aSAlexandre Belloni struct workqueue_struct *stats_queue; 4804e3b0468SAntoine Tenart 4814e3b0468SAntoine Tenart u8 ptp:1; 4824e3b0468SAntoine Tenart struct ptp_clock *ptp_clock; 4834e3b0468SAntoine Tenart struct ptp_clock_info ptp_info; 4844e3b0468SAntoine Tenart struct hwtstamp_config hwtstamp_config; 4854e3b0468SAntoine Tenart struct mutex ptp_lock; /* Protects the PTP interface state */ 4864e3b0468SAntoine Tenart spinlock_t ptp_clock_lock; /* Protects the PTP clock */ 487a556c76aSAlexandre Belloni }; 488a556c76aSAlexandre Belloni 489a556c76aSAlexandre Belloni struct ocelot_port { 490a556c76aSAlexandre Belloni struct ocelot *ocelot; 491004d44f6SVladimir Oltean 492a556c76aSAlexandre Belloni void __iomem *regs; 493a556c76aSAlexandre Belloni 494a556c76aSAlexandre Belloni /* Ingress default VLAN (pvid) */ 495a556c76aSAlexandre Belloni u16 pvid; 496a556c76aSAlexandre Belloni 497a556c76aSAlexandre Belloni /* Egress default VLAN (vid) */ 498a556c76aSAlexandre Belloni u16 vid; 499a556c76aSAlexandre Belloni 500004d44f6SVladimir Oltean u8 ptp_cmd; 501004d44f6SVladimir Oltean struct list_head skbs; 502004d44f6SVladimir Oltean u8 ts_id; 503004d44f6SVladimir Oltean }; 504a556c76aSAlexandre Belloni 505004d44f6SVladimir Oltean struct ocelot_port_private { 506004d44f6SVladimir Oltean struct ocelot_port port; 507004d44f6SVladimir Oltean struct net_device *dev; 508004d44f6SVladimir Oltean struct phy_device *phy; 509004d44f6SVladimir Oltean u8 chip_port; 510004d44f6SVladimir Oltean 511004d44f6SVladimir Oltean u8 vlan_aware; 51271e32a20SQuentin Schulz 51371e32a20SQuentin Schulz phy_interface_t phy_mode; 51471e32a20SQuentin Schulz struct phy *serdes; 5152c1d029aSJoergen Andreasen 5162c1d029aSJoergen Andreasen struct ocelot_port_tc tc; 5174e3b0468SAntoine Tenart }; 5184e3b0468SAntoine Tenart 5194e3b0468SAntoine Tenart struct ocelot_skb { 5204e3b0468SAntoine Tenart struct list_head head; 5214e3b0468SAntoine Tenart struct sk_buff *skb; 5224e3b0468SAntoine Tenart u8 id; 523a556c76aSAlexandre Belloni }; 524a556c76aSAlexandre Belloni 525a556c76aSAlexandre Belloni u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 526a556c76aSAlexandre Belloni #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 527a556c76aSAlexandre Belloni #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 528a556c76aSAlexandre Belloni #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 529a556c76aSAlexandre Belloni #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 530a556c76aSAlexandre Belloni 531a556c76aSAlexandre Belloni void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 532a556c76aSAlexandre Belloni #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 533a556c76aSAlexandre Belloni #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 534a556c76aSAlexandre Belloni #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 535a556c76aSAlexandre Belloni #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 536a556c76aSAlexandre Belloni 53717fdd763SVladimir Oltean void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 538a556c76aSAlexandre Belloni u32 offset); 539a556c76aSAlexandre Belloni #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 540a556c76aSAlexandre Belloni #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 541a556c76aSAlexandre Belloni #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 542a556c76aSAlexandre Belloni #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 543a556c76aSAlexandre Belloni 544a556c76aSAlexandre Belloni u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 545a556c76aSAlexandre Belloni void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 546a556c76aSAlexandre Belloni 547a556c76aSAlexandre Belloni int ocelot_regfields_init(struct ocelot *ocelot, 548a556c76aSAlexandre Belloni const struct reg_field *const regfields); 549a556c76aSAlexandre Belloni struct regmap *ocelot_io_platform_init(struct ocelot *ocelot, 550a556c76aSAlexandre Belloni struct platform_device *pdev, 551a556c76aSAlexandre Belloni const char *name); 552a556c76aSAlexandre Belloni 553a556c76aSAlexandre Belloni #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 554a556c76aSAlexandre Belloni #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 555a556c76aSAlexandre Belloni 556a556c76aSAlexandre Belloni int ocelot_init(struct ocelot *ocelot); 557a556c76aSAlexandre Belloni void ocelot_deinit(struct ocelot *ocelot); 558a556c76aSAlexandre Belloni int ocelot_chip_init(struct ocelot *ocelot); 559a556c76aSAlexandre Belloni int ocelot_probe_port(struct ocelot *ocelot, u8 port, 560a556c76aSAlexandre Belloni void __iomem *regs, 561a556c76aSAlexandre Belloni struct phy_device *phy); 562a556c76aSAlexandre Belloni 56321468199SVladimir Oltean void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu, 56421468199SVladimir Oltean enum ocelot_tag_prefix injection, 56521468199SVladimir Oltean enum ocelot_tag_prefix extraction); 56621468199SVladimir Oltean 567a556c76aSAlexandre Belloni extern struct notifier_block ocelot_netdevice_nb; 56856da64bcSFlorian Fainelli extern struct notifier_block ocelot_switchdev_nb; 5690e332c85SPetr Machata extern struct notifier_block ocelot_switchdev_blocking_nb; 570a556c76aSAlexandre Belloni 5714e3b0468SAntoine Tenart int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); 5724e3b0468SAntoine Tenart void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts); 5734e3b0468SAntoine Tenart 574a556c76aSAlexandre Belloni #endif 575