1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include "ocelot.h" 9 #include "ocelot_vcap.h" 10 11 #define TABLE_UPDATE_SLEEP_US 10 12 #define TABLE_UPDATE_TIMEOUT_US 100000 13 14 struct ocelot_mact_entry { 15 u8 mac[ETH_ALEN]; 16 u16 vid; 17 enum macaccess_entry_type type; 18 }; 19 20 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 21 { 22 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 23 } 24 25 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 26 { 27 u32 val; 28 29 return readx_poll_timeout(ocelot_mact_read_macaccess, 30 ocelot, val, 31 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 32 MACACCESS_CMD_IDLE, 33 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 34 } 35 36 static void ocelot_mact_select(struct ocelot *ocelot, 37 const unsigned char mac[ETH_ALEN], 38 unsigned int vid) 39 { 40 u32 macl = 0, mach = 0; 41 42 /* Set the MAC address to handle and the vlan associated in a format 43 * understood by the hardware. 44 */ 45 mach |= vid << 16; 46 mach |= mac[0] << 8; 47 mach |= mac[1] << 0; 48 macl |= mac[2] << 24; 49 macl |= mac[3] << 16; 50 macl |= mac[4] << 8; 51 macl |= mac[5] << 0; 52 53 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 54 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 55 56 } 57 58 int ocelot_mact_learn(struct ocelot *ocelot, int port, 59 const unsigned char mac[ETH_ALEN], 60 unsigned int vid, enum macaccess_entry_type type) 61 { 62 ocelot_mact_select(ocelot, mac, vid); 63 64 /* Issue a write command */ 65 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 69 ANA_TABLES_MACACCESS); 70 71 return ocelot_mact_wait_for_completion(ocelot); 72 } 73 EXPORT_SYMBOL(ocelot_mact_learn); 74 75 int ocelot_mact_forget(struct ocelot *ocelot, 76 const unsigned char mac[ETH_ALEN], unsigned int vid) 77 { 78 ocelot_mact_select(ocelot, mac, vid); 79 80 /* Issue a forget command */ 81 ocelot_write(ocelot, 82 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 83 ANA_TABLES_MACACCESS); 84 85 return ocelot_mact_wait_for_completion(ocelot); 86 } 87 EXPORT_SYMBOL(ocelot_mact_forget); 88 89 static void ocelot_mact_init(struct ocelot *ocelot) 90 { 91 /* Configure the learning mode entries attributes: 92 * - Do not copy the frame to the CPU extraction queues. 93 * - Use the vlan and mac_cpoy for dmac lookup. 94 */ 95 ocelot_rmw(ocelot, 0, 96 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 97 | ANA_AGENCTRL_LEARN_FWD_KILL 98 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 99 ANA_AGENCTRL); 100 101 /* Clear the MAC table */ 102 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 103 } 104 105 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 106 { 107 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 108 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 109 ANA_PORT_VCAP_S2_CFG, port); 110 } 111 112 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 113 { 114 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 115 } 116 117 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 118 { 119 u32 val; 120 121 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 122 ocelot, 123 val, 124 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 125 ANA_TABLES_VLANACCESS_CMD_IDLE, 126 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 127 } 128 129 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 130 { 131 /* Select the VID to configure */ 132 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 133 ANA_TABLES_VLANTIDX); 134 /* Set the vlan port members mask and issue a write command */ 135 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 136 ANA_TABLES_VLANACCESS_CMD_WRITE, 137 ANA_TABLES_VLANACCESS); 138 139 return ocelot_vlant_wait_for_completion(ocelot); 140 } 141 142 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 143 u16 vid) 144 { 145 struct ocelot_port *ocelot_port = ocelot->ports[port]; 146 u32 val = 0; 147 148 if (ocelot_port->vid != vid) { 149 /* Always permit deleting the native VLAN (vid = 0) */ 150 if (ocelot_port->vid && vid) { 151 dev_err(ocelot->dev, 152 "Port already has a native VLAN: %d\n", 153 ocelot_port->vid); 154 return -EBUSY; 155 } 156 ocelot_port->vid = vid; 157 } 158 159 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 160 REW_PORT_VLAN_CFG_PORT_VID_M, 161 REW_PORT_VLAN_CFG, port); 162 163 if (ocelot_port->vlan_aware && !ocelot_port->vid) 164 /* If port is vlan-aware and tagged, drop untagged and priority 165 * tagged frames. 166 */ 167 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 168 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 169 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 170 ocelot_rmw_gix(ocelot, val, 171 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 172 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 173 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 174 ANA_PORT_DROP_CFG, port); 175 176 if (ocelot_port->vlan_aware) { 177 if (ocelot_port->vid) 178 /* Tag all frames except when VID == DEFAULT_VLAN */ 179 val = REW_TAG_CFG_TAG_CFG(1); 180 else 181 /* Tag all frames */ 182 val = REW_TAG_CFG_TAG_CFG(3); 183 } else { 184 /* Port tagging disabled. */ 185 val = REW_TAG_CFG_TAG_CFG(0); 186 } 187 ocelot_rmw_gix(ocelot, val, 188 REW_TAG_CFG_TAG_CFG_M, 189 REW_TAG_CFG, port); 190 191 return 0; 192 } 193 194 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 195 bool vlan_aware) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val; 199 200 ocelot_port->vlan_aware = vlan_aware; 201 202 if (vlan_aware) 203 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 204 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 205 else 206 val = 0; 207 ocelot_rmw_gix(ocelot, val, 208 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 209 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 210 ANA_PORT_VLAN_CFG, port); 211 212 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 213 } 214 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 215 216 /* Default vlan to clasify for untagged frames (may be zero) */ 217 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 218 { 219 struct ocelot_port *ocelot_port = ocelot->ports[port]; 220 221 ocelot_rmw_gix(ocelot, 222 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 223 ANA_PORT_VLAN_CFG_VLAN_VID_M, 224 ANA_PORT_VLAN_CFG, port); 225 226 ocelot_port->pvid = pvid; 227 } 228 229 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 230 bool untagged) 231 { 232 int ret; 233 234 /* Make the port a member of the VLAN */ 235 ocelot->vlan_mask[vid] |= BIT(port); 236 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 237 if (ret) 238 return ret; 239 240 /* Default ingress vlan classification */ 241 if (pvid) 242 ocelot_port_set_pvid(ocelot, port, vid); 243 244 /* Untagged egress vlan clasification */ 245 if (untagged) { 246 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 247 if (ret) 248 return ret; 249 } 250 251 return 0; 252 } 253 EXPORT_SYMBOL(ocelot_vlan_add); 254 255 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 256 { 257 struct ocelot_port *ocelot_port = ocelot->ports[port]; 258 int ret; 259 260 /* Stop the port from being a member of the vlan */ 261 ocelot->vlan_mask[vid] &= ~BIT(port); 262 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 263 if (ret) 264 return ret; 265 266 /* Ingress */ 267 if (ocelot_port->pvid == vid) 268 ocelot_port_set_pvid(ocelot, port, 0); 269 270 /* Egress */ 271 if (ocelot_port->vid == vid) 272 ocelot_port_set_native_vlan(ocelot, port, 0); 273 274 return 0; 275 } 276 EXPORT_SYMBOL(ocelot_vlan_del); 277 278 static void ocelot_vlan_init(struct ocelot *ocelot) 279 { 280 u16 port, vid; 281 282 /* Clear VLAN table, by default all ports are members of all VLANs */ 283 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 284 ANA_TABLES_VLANACCESS); 285 ocelot_vlant_wait_for_completion(ocelot); 286 287 /* Configure the port VLAN memberships */ 288 for (vid = 1; vid < VLAN_N_VID; vid++) { 289 ocelot->vlan_mask[vid] = 0; 290 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 291 } 292 293 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 294 * traffic. It is added automatically if 8021q module is loaded, but 295 * we can't rely on it since module may be not loaded. 296 */ 297 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 298 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 299 300 /* Set vlan ingress filter mask to all ports but the CPU port by 301 * default. 302 */ 303 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 304 ANA_VLANMASK); 305 306 for (port = 0; port < ocelot->num_phys_ports; port++) { 307 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 308 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 309 } 310 } 311 312 void ocelot_adjust_link(struct ocelot *ocelot, int port, 313 struct phy_device *phydev) 314 { 315 struct ocelot_port *ocelot_port = ocelot->ports[port]; 316 int speed, mode = 0; 317 318 switch (phydev->speed) { 319 case SPEED_10: 320 speed = OCELOT_SPEED_10; 321 break; 322 case SPEED_100: 323 speed = OCELOT_SPEED_100; 324 break; 325 case SPEED_1000: 326 speed = OCELOT_SPEED_1000; 327 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 328 break; 329 case SPEED_2500: 330 speed = OCELOT_SPEED_2500; 331 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 332 break; 333 default: 334 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 335 port, phydev->speed); 336 return; 337 } 338 339 phy_print_status(phydev); 340 341 if (!phydev->link) 342 return; 343 344 /* Only full duplex supported for now */ 345 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 346 mode, DEV_MAC_MODE_CFG); 347 348 /* Disable HDX fast control */ 349 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 350 DEV_PORT_MISC); 351 352 /* SGMII only for now */ 353 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 354 PCS1G_MODE_CFG); 355 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 356 357 /* Enable PCS */ 358 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 359 360 /* No aneg on SGMII */ 361 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 362 363 /* No loopback */ 364 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 365 366 /* Enable MAC module */ 367 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 368 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 369 370 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 371 * reset */ 372 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 373 DEV_CLOCK_CFG); 374 375 /* No PFC */ 376 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 377 ANA_PFC_PFC_CFG, port); 378 379 /* Core: Enable port for frame transfer */ 380 ocelot_fields_write(ocelot, port, 381 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 382 383 /* Flow control */ 384 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 385 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 386 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 387 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 388 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 389 SYS_MAC_FC_CFG, port); 390 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 391 } 392 EXPORT_SYMBOL(ocelot_adjust_link); 393 394 void ocelot_port_enable(struct ocelot *ocelot, int port, 395 struct phy_device *phy) 396 { 397 /* Enable receiving frames on the port, and activate auto-learning of 398 * MAC addresses. 399 */ 400 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 401 ANA_PORT_PORT_CFG_RECV_ENA | 402 ANA_PORT_PORT_CFG_PORTID_VAL(port), 403 ANA_PORT_PORT_CFG, port); 404 } 405 EXPORT_SYMBOL(ocelot_port_enable); 406 407 void ocelot_port_disable(struct ocelot *ocelot, int port) 408 { 409 struct ocelot_port *ocelot_port = ocelot->ports[port]; 410 411 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 412 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 413 } 414 EXPORT_SYMBOL(ocelot_port_disable); 415 416 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 417 struct sk_buff *skb) 418 { 419 struct skb_shared_info *shinfo = skb_shinfo(skb); 420 struct ocelot *ocelot = ocelot_port->ocelot; 421 422 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 423 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 424 spin_lock(&ocelot_port->ts_id_lock); 425 426 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 427 /* Store timestamp ID in cb[0] of sk_buff */ 428 skb->cb[0] = ocelot_port->ts_id; 429 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 430 skb_queue_tail(&ocelot_port->tx_skbs, skb); 431 432 spin_unlock(&ocelot_port->ts_id_lock); 433 return 0; 434 } 435 return -ENODATA; 436 } 437 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 438 439 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 440 struct timespec64 *ts) 441 { 442 unsigned long flags; 443 u32 val; 444 445 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 446 447 /* Read current PTP time to get seconds */ 448 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 449 450 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 451 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 452 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 453 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 454 455 /* Read packet HW timestamp from FIFO */ 456 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 457 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 458 459 /* Sec has incremented since the ts was registered */ 460 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 461 ts->tv_sec--; 462 463 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 464 } 465 466 void ocelot_get_txtstamp(struct ocelot *ocelot) 467 { 468 int budget = OCELOT_PTP_QUEUE_SZ; 469 470 while (budget--) { 471 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 472 struct skb_shared_hwtstamps shhwtstamps; 473 struct ocelot_port *port; 474 struct timespec64 ts; 475 unsigned long flags; 476 u32 val, id, txport; 477 478 val = ocelot_read(ocelot, SYS_PTP_STATUS); 479 480 /* Check if a timestamp can be retrieved */ 481 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 482 break; 483 484 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 485 486 /* Retrieve the ts ID and Tx port */ 487 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 488 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 489 490 /* Retrieve its associated skb */ 491 port = ocelot->ports[txport]; 492 493 spin_lock_irqsave(&port->tx_skbs.lock, flags); 494 495 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 496 if (skb->cb[0] != id) 497 continue; 498 __skb_unlink(skb, &port->tx_skbs); 499 skb_match = skb; 500 break; 501 } 502 503 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 504 505 /* Get the h/w timestamp */ 506 ocelot_get_hwtimestamp(ocelot, &ts); 507 508 if (unlikely(!skb_match)) 509 continue; 510 511 /* Set the timestamp into the skb */ 512 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 513 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 514 skb_tstamp_tx(skb_match, &shhwtstamps); 515 516 dev_kfree_skb_any(skb_match); 517 518 /* Next ts */ 519 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 520 } 521 } 522 EXPORT_SYMBOL(ocelot_get_txtstamp); 523 524 int ocelot_fdb_add(struct ocelot *ocelot, int port, 525 const unsigned char *addr, u16 vid) 526 { 527 struct ocelot_port *ocelot_port = ocelot->ports[port]; 528 int pgid = port; 529 530 if (port == ocelot->npi) 531 pgid = PGID_CPU; 532 533 if (!vid) { 534 if (!ocelot_port->vlan_aware) 535 /* If the bridge is not VLAN aware and no VID was 536 * provided, set it to pvid to ensure the MAC entry 537 * matches incoming untagged packets 538 */ 539 vid = ocelot_port->pvid; 540 else 541 /* If the bridge is VLAN aware a VID must be provided as 542 * otherwise the learnt entry wouldn't match any frame. 543 */ 544 return -EINVAL; 545 } 546 547 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 548 } 549 EXPORT_SYMBOL(ocelot_fdb_add); 550 551 int ocelot_fdb_del(struct ocelot *ocelot, int port, 552 const unsigned char *addr, u16 vid) 553 { 554 return ocelot_mact_forget(ocelot, addr, vid); 555 } 556 EXPORT_SYMBOL(ocelot_fdb_del); 557 558 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 559 bool is_static, void *data) 560 { 561 struct ocelot_dump_ctx *dump = data; 562 u32 portid = NETLINK_CB(dump->cb->skb).portid; 563 u32 seq = dump->cb->nlh->nlmsg_seq; 564 struct nlmsghdr *nlh; 565 struct ndmsg *ndm; 566 567 if (dump->idx < dump->cb->args[2]) 568 goto skip; 569 570 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 571 sizeof(*ndm), NLM_F_MULTI); 572 if (!nlh) 573 return -EMSGSIZE; 574 575 ndm = nlmsg_data(nlh); 576 ndm->ndm_family = AF_BRIDGE; 577 ndm->ndm_pad1 = 0; 578 ndm->ndm_pad2 = 0; 579 ndm->ndm_flags = NTF_SELF; 580 ndm->ndm_type = 0; 581 ndm->ndm_ifindex = dump->dev->ifindex; 582 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 583 584 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 585 goto nla_put_failure; 586 587 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 588 goto nla_put_failure; 589 590 nlmsg_end(dump->skb, nlh); 591 592 skip: 593 dump->idx++; 594 return 0; 595 596 nla_put_failure: 597 nlmsg_cancel(dump->skb, nlh); 598 return -EMSGSIZE; 599 } 600 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 601 602 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 603 struct ocelot_mact_entry *entry) 604 { 605 u32 val, dst, macl, mach; 606 char mac[ETH_ALEN]; 607 608 /* Set row and column to read from */ 609 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 610 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 611 612 /* Issue a read command */ 613 ocelot_write(ocelot, 614 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 615 ANA_TABLES_MACACCESS); 616 617 if (ocelot_mact_wait_for_completion(ocelot)) 618 return -ETIMEDOUT; 619 620 /* Read the entry flags */ 621 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 622 if (!(val & ANA_TABLES_MACACCESS_VALID)) 623 return -EINVAL; 624 625 /* If the entry read has another port configured as its destination, 626 * do not report it. 627 */ 628 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 629 if (dst != port) 630 return -EINVAL; 631 632 /* Get the entry's MAC address and VLAN id */ 633 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 634 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 635 636 mac[0] = (mach >> 8) & 0xff; 637 mac[1] = (mach >> 0) & 0xff; 638 mac[2] = (macl >> 24) & 0xff; 639 mac[3] = (macl >> 16) & 0xff; 640 mac[4] = (macl >> 8) & 0xff; 641 mac[5] = (macl >> 0) & 0xff; 642 643 entry->vid = (mach >> 16) & 0xfff; 644 ether_addr_copy(entry->mac, mac); 645 646 return 0; 647 } 648 649 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 650 dsa_fdb_dump_cb_t *cb, void *data) 651 { 652 int i, j; 653 654 /* Loop through all the mac tables entries. */ 655 for (i = 0; i < ocelot->num_mact_rows; i++) { 656 for (j = 0; j < 4; j++) { 657 struct ocelot_mact_entry entry; 658 bool is_static; 659 int ret; 660 661 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 662 /* If the entry is invalid (wrong port, invalid...), 663 * skip it. 664 */ 665 if (ret == -EINVAL) 666 continue; 667 else if (ret) 668 return ret; 669 670 is_static = (entry.type == ENTRYTYPE_LOCKED); 671 672 ret = cb(entry.mac, entry.vid, is_static, data); 673 if (ret) 674 return ret; 675 } 676 } 677 678 return 0; 679 } 680 EXPORT_SYMBOL(ocelot_fdb_dump); 681 682 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 683 { 684 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 685 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 686 } 687 EXPORT_SYMBOL(ocelot_hwstamp_get); 688 689 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 690 { 691 struct ocelot_port *ocelot_port = ocelot->ports[port]; 692 struct hwtstamp_config cfg; 693 694 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 695 return -EFAULT; 696 697 /* reserved for future extensions */ 698 if (cfg.flags) 699 return -EINVAL; 700 701 /* Tx type sanity check */ 702 switch (cfg.tx_type) { 703 case HWTSTAMP_TX_ON: 704 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 705 break; 706 case HWTSTAMP_TX_ONESTEP_SYNC: 707 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 708 * need to update the origin time. 709 */ 710 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 711 break; 712 case HWTSTAMP_TX_OFF: 713 ocelot_port->ptp_cmd = 0; 714 break; 715 default: 716 return -ERANGE; 717 } 718 719 mutex_lock(&ocelot->ptp_lock); 720 721 switch (cfg.rx_filter) { 722 case HWTSTAMP_FILTER_NONE: 723 break; 724 case HWTSTAMP_FILTER_ALL: 725 case HWTSTAMP_FILTER_SOME: 726 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 727 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 728 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 729 case HWTSTAMP_FILTER_NTP_ALL: 730 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 731 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 732 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 733 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 734 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 735 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 736 case HWTSTAMP_FILTER_PTP_V2_EVENT: 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 739 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 740 break; 741 default: 742 mutex_unlock(&ocelot->ptp_lock); 743 return -ERANGE; 744 } 745 746 /* Commit back the result & save it */ 747 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 748 mutex_unlock(&ocelot->ptp_lock); 749 750 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 751 } 752 EXPORT_SYMBOL(ocelot_hwstamp_set); 753 754 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 755 { 756 int i; 757 758 if (sset != ETH_SS_STATS) 759 return; 760 761 for (i = 0; i < ocelot->num_stats; i++) 762 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 763 ETH_GSTRING_LEN); 764 } 765 EXPORT_SYMBOL(ocelot_get_strings); 766 767 static void ocelot_update_stats(struct ocelot *ocelot) 768 { 769 int i, j; 770 771 mutex_lock(&ocelot->stats_lock); 772 773 for (i = 0; i < ocelot->num_phys_ports; i++) { 774 /* Configure the port to read the stats from */ 775 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 776 777 for (j = 0; j < ocelot->num_stats; j++) { 778 u32 val; 779 unsigned int idx = i * ocelot->num_stats + j; 780 781 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 782 ocelot->stats_layout[j].offset); 783 784 if (val < (ocelot->stats[idx] & U32_MAX)) 785 ocelot->stats[idx] += (u64)1 << 32; 786 787 ocelot->stats[idx] = (ocelot->stats[idx] & 788 ~(u64)U32_MAX) + val; 789 } 790 } 791 792 mutex_unlock(&ocelot->stats_lock); 793 } 794 795 static void ocelot_check_stats_work(struct work_struct *work) 796 { 797 struct delayed_work *del_work = to_delayed_work(work); 798 struct ocelot *ocelot = container_of(del_work, struct ocelot, 799 stats_work); 800 801 ocelot_update_stats(ocelot); 802 803 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 804 OCELOT_STATS_CHECK_DELAY); 805 } 806 807 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 808 { 809 int i; 810 811 /* check and update now */ 812 ocelot_update_stats(ocelot); 813 814 /* Copy all counters */ 815 for (i = 0; i < ocelot->num_stats; i++) 816 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 817 } 818 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 819 820 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 821 { 822 if (sset != ETH_SS_STATS) 823 return -EOPNOTSUPP; 824 825 return ocelot->num_stats; 826 } 827 EXPORT_SYMBOL(ocelot_get_sset_count); 828 829 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 830 struct ethtool_ts_info *info) 831 { 832 info->phc_index = ocelot->ptp_clock ? 833 ptp_clock_index(ocelot->ptp_clock) : -1; 834 if (info->phc_index == -1) { 835 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 836 SOF_TIMESTAMPING_RX_SOFTWARE | 837 SOF_TIMESTAMPING_SOFTWARE; 838 return 0; 839 } 840 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 841 SOF_TIMESTAMPING_RX_SOFTWARE | 842 SOF_TIMESTAMPING_SOFTWARE | 843 SOF_TIMESTAMPING_TX_HARDWARE | 844 SOF_TIMESTAMPING_RX_HARDWARE | 845 SOF_TIMESTAMPING_RAW_HARDWARE; 846 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 847 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 848 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 849 850 return 0; 851 } 852 EXPORT_SYMBOL(ocelot_get_ts_info); 853 854 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 855 { 856 u32 port_cfg; 857 int p, i; 858 859 if (!(BIT(port) & ocelot->bridge_mask)) 860 return; 861 862 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 863 864 switch (state) { 865 case BR_STATE_FORWARDING: 866 ocelot->bridge_fwd_mask |= BIT(port); 867 fallthrough; 868 case BR_STATE_LEARNING: 869 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 870 break; 871 872 default: 873 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 874 ocelot->bridge_fwd_mask &= ~BIT(port); 875 break; 876 } 877 878 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 879 880 /* Apply FWD mask. The loop is needed to add/remove the current port as 881 * a source for the other ports. 882 */ 883 for (p = 0; p < ocelot->num_phys_ports; p++) { 884 if (ocelot->bridge_fwd_mask & BIT(p)) { 885 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 886 887 for (i = 0; i < ocelot->num_phys_ports; i++) { 888 unsigned long bond_mask = ocelot->lags[i]; 889 890 if (!bond_mask) 891 continue; 892 893 if (bond_mask & BIT(p)) { 894 mask &= ~bond_mask; 895 break; 896 } 897 } 898 899 ocelot_write_rix(ocelot, mask, 900 ANA_PGID_PGID, PGID_SRC + p); 901 } else { 902 ocelot_write_rix(ocelot, 0, 903 ANA_PGID_PGID, PGID_SRC + p); 904 } 905 } 906 } 907 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 908 909 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 910 { 911 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 912 913 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 914 * which is clearly not what our intention is. So avoid that. 915 */ 916 if (!age_period) 917 age_period = 1; 918 919 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 920 } 921 EXPORT_SYMBOL(ocelot_set_ageing_time); 922 923 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 924 const unsigned char *addr, 925 u16 vid) 926 { 927 struct ocelot_multicast *mc; 928 929 list_for_each_entry(mc, &ocelot->multicast, list) { 930 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 931 return mc; 932 } 933 934 return NULL; 935 } 936 937 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 938 { 939 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 940 return ENTRYTYPE_MACv4; 941 if (addr[0] == 0x33 && addr[1] == 0x33) 942 return ENTRYTYPE_MACv6; 943 return ENTRYTYPE_NORMAL; 944 } 945 946 static int ocelot_mdb_get_pgid(struct ocelot *ocelot, 947 enum macaccess_entry_type entry_type) 948 { 949 int pgid; 950 951 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 952 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 953 * destination mask table (PGID), the destination set is programmed as 954 * part of the entry MAC address.", and the DEST_IDX is set to 0. 955 */ 956 if (entry_type == ENTRYTYPE_MACv4 || 957 entry_type == ENTRYTYPE_MACv6) 958 return 0; 959 960 for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) { 961 struct ocelot_multicast *mc; 962 bool used = false; 963 964 list_for_each_entry(mc, &ocelot->multicast, list) { 965 if (mc->pgid == pgid) { 966 used = true; 967 break; 968 } 969 } 970 971 if (!used) 972 return pgid; 973 } 974 975 return -1; 976 } 977 978 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 979 struct ocelot_multicast *mc, 980 enum macaccess_entry_type entry_type) 981 { 982 memcpy(addr, mc->addr, ETH_ALEN); 983 984 if (entry_type == ENTRYTYPE_MACv4) { 985 addr[0] = 0; 986 addr[1] = mc->ports >> 8; 987 addr[2] = mc->ports & 0xff; 988 } else if (entry_type == ENTRYTYPE_MACv6) { 989 addr[0] = mc->ports >> 8; 990 addr[1] = mc->ports & 0xff; 991 } 992 } 993 994 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 995 const struct switchdev_obj_port_mdb *mdb) 996 { 997 struct ocelot_port *ocelot_port = ocelot->ports[port]; 998 enum macaccess_entry_type entry_type; 999 unsigned char addr[ETH_ALEN]; 1000 struct ocelot_multicast *mc; 1001 u16 vid = mdb->vid; 1002 bool new = false; 1003 1004 if (port == ocelot->npi) 1005 port = ocelot->num_phys_ports; 1006 1007 if (!vid) 1008 vid = ocelot_port->pvid; 1009 1010 entry_type = ocelot_classify_mdb(mdb->addr); 1011 1012 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1013 if (!mc) { 1014 int pgid = ocelot_mdb_get_pgid(ocelot, entry_type); 1015 1016 if (pgid < 0) { 1017 dev_err(ocelot->dev, 1018 "No more PGIDs available for mdb %pM vid %d\n", 1019 mdb->addr, vid); 1020 return -ENOSPC; 1021 } 1022 1023 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1024 if (!mc) 1025 return -ENOMEM; 1026 1027 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1028 mc->vid = vid; 1029 mc->pgid = pgid; 1030 1031 list_add_tail(&mc->list, &ocelot->multicast); 1032 new = true; 1033 } 1034 1035 if (!new) { 1036 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1037 ocelot_mact_forget(ocelot, addr, vid); 1038 } 1039 1040 mc->ports |= BIT(port); 1041 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1042 1043 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1044 } 1045 EXPORT_SYMBOL(ocelot_port_mdb_add); 1046 1047 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1048 const struct switchdev_obj_port_mdb *mdb) 1049 { 1050 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1051 enum macaccess_entry_type entry_type; 1052 unsigned char addr[ETH_ALEN]; 1053 struct ocelot_multicast *mc; 1054 u16 vid = mdb->vid; 1055 1056 if (port == ocelot->npi) 1057 port = ocelot->num_phys_ports; 1058 1059 if (!vid) 1060 vid = ocelot_port->pvid; 1061 1062 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1063 if (!mc) 1064 return -ENOENT; 1065 1066 entry_type = ocelot_classify_mdb(mdb->addr); 1067 1068 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1069 ocelot_mact_forget(ocelot, addr, vid); 1070 1071 mc->ports &= ~BIT(port); 1072 if (!mc->ports) { 1073 list_del(&mc->list); 1074 devm_kfree(ocelot->dev, mc); 1075 return 0; 1076 } 1077 1078 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1079 1080 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1081 } 1082 EXPORT_SYMBOL(ocelot_port_mdb_del); 1083 1084 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1085 struct net_device *bridge) 1086 { 1087 if (!ocelot->bridge_mask) { 1088 ocelot->hw_bridge_dev = bridge; 1089 } else { 1090 if (ocelot->hw_bridge_dev != bridge) 1091 /* This is adding the port to a second bridge, this is 1092 * unsupported */ 1093 return -ENODEV; 1094 } 1095 1096 ocelot->bridge_mask |= BIT(port); 1097 1098 return 0; 1099 } 1100 EXPORT_SYMBOL(ocelot_port_bridge_join); 1101 1102 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1103 struct net_device *bridge) 1104 { 1105 ocelot->bridge_mask &= ~BIT(port); 1106 1107 if (!ocelot->bridge_mask) 1108 ocelot->hw_bridge_dev = NULL; 1109 1110 ocelot_port_vlan_filtering(ocelot, port, 0); 1111 ocelot_port_set_pvid(ocelot, port, 0); 1112 return ocelot_port_set_native_vlan(ocelot, port, 0); 1113 } 1114 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1115 1116 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1117 { 1118 int i, port, lag; 1119 1120 /* Reset destination and aggregation PGIDS */ 1121 for_each_unicast_dest_pgid(ocelot, port) 1122 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1123 1124 for_each_aggr_pgid(ocelot, i) 1125 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1126 ANA_PGID_PGID, i); 1127 1128 /* Now, set PGIDs for each LAG */ 1129 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1130 unsigned long bond_mask; 1131 int aggr_count = 0; 1132 u8 aggr_idx[16]; 1133 1134 bond_mask = ocelot->lags[lag]; 1135 if (!bond_mask) 1136 continue; 1137 1138 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1139 // Destination mask 1140 ocelot_write_rix(ocelot, bond_mask, 1141 ANA_PGID_PGID, port); 1142 aggr_idx[aggr_count] = port; 1143 aggr_count++; 1144 } 1145 1146 for_each_aggr_pgid(ocelot, i) { 1147 u32 ac; 1148 1149 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1150 ac &= ~bond_mask; 1151 ac |= BIT(aggr_idx[i % aggr_count]); 1152 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1153 } 1154 } 1155 } 1156 1157 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1158 { 1159 unsigned long bond_mask = ocelot->lags[lag]; 1160 unsigned int p; 1161 1162 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1163 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1164 1165 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1166 1167 /* Use lag port as logical port for port i */ 1168 ocelot_write_gix(ocelot, port_cfg | 1169 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1170 ANA_PORT_PORT_CFG, p); 1171 } 1172 } 1173 1174 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1175 struct net_device *bond) 1176 { 1177 struct net_device *ndev; 1178 u32 bond_mask = 0; 1179 int lag, lp; 1180 1181 rcu_read_lock(); 1182 for_each_netdev_in_bond_rcu(bond, ndev) { 1183 struct ocelot_port_private *priv = netdev_priv(ndev); 1184 1185 bond_mask |= BIT(priv->chip_port); 1186 } 1187 rcu_read_unlock(); 1188 1189 lp = __ffs(bond_mask); 1190 1191 /* If the new port is the lowest one, use it as the logical port from 1192 * now on 1193 */ 1194 if (port == lp) { 1195 lag = port; 1196 ocelot->lags[port] = bond_mask; 1197 bond_mask &= ~BIT(port); 1198 if (bond_mask) { 1199 lp = __ffs(bond_mask); 1200 ocelot->lags[lp] = 0; 1201 } 1202 } else { 1203 lag = lp; 1204 ocelot->lags[lp] |= BIT(port); 1205 } 1206 1207 ocelot_setup_lag(ocelot, lag); 1208 ocelot_set_aggr_pgids(ocelot); 1209 1210 return 0; 1211 } 1212 EXPORT_SYMBOL(ocelot_port_lag_join); 1213 1214 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1215 struct net_device *bond) 1216 { 1217 u32 port_cfg; 1218 int i; 1219 1220 /* Remove port from any lag */ 1221 for (i = 0; i < ocelot->num_phys_ports; i++) 1222 ocelot->lags[i] &= ~BIT(port); 1223 1224 /* if it was the logical port of the lag, move the lag config to the 1225 * next port 1226 */ 1227 if (ocelot->lags[port]) { 1228 int n = __ffs(ocelot->lags[port]); 1229 1230 ocelot->lags[n] = ocelot->lags[port]; 1231 ocelot->lags[port] = 0; 1232 1233 ocelot_setup_lag(ocelot, n); 1234 } 1235 1236 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1237 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1238 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1239 ANA_PORT_PORT_CFG, port); 1240 1241 ocelot_set_aggr_pgids(ocelot); 1242 } 1243 EXPORT_SYMBOL(ocelot_port_lag_leave); 1244 1245 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1246 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1247 * In the special case that it's the NPI port that we're configuring, the 1248 * length of the tag and optional prefix needs to be accounted for privately, 1249 * in order to be able to sustain communication at the requested @sdu. 1250 */ 1251 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1252 { 1253 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1254 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1255 int pause_start, pause_stop; 1256 int atop_wm; 1257 1258 if (port == ocelot->npi) { 1259 maxlen += OCELOT_TAG_LEN; 1260 1261 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1262 maxlen += OCELOT_SHORT_PREFIX_LEN; 1263 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1264 maxlen += OCELOT_LONG_PREFIX_LEN; 1265 } 1266 1267 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1268 1269 /* Set Pause watermark hysteresis */ 1270 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1271 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1272 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1273 pause_start); 1274 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1275 pause_stop); 1276 1277 /* Tail dropping watermark */ 1278 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) / 1279 OCELOT_BUFFER_CELL_SZ; 1280 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(9 * maxlen), 1281 SYS_ATOP, port); 1282 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 1283 } 1284 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1285 1286 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1287 { 1288 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1289 1290 if (port == ocelot->npi) { 1291 max_mtu -= OCELOT_TAG_LEN; 1292 1293 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1294 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1295 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1296 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1297 } 1298 1299 return max_mtu; 1300 } 1301 EXPORT_SYMBOL(ocelot_get_max_mtu); 1302 1303 void ocelot_init_port(struct ocelot *ocelot, int port) 1304 { 1305 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1306 1307 skb_queue_head_init(&ocelot_port->tx_skbs); 1308 spin_lock_init(&ocelot_port->ts_id_lock); 1309 1310 /* Basic L2 initialization */ 1311 1312 /* Set MAC IFG Gaps 1313 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1314 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1315 */ 1316 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1317 DEV_MAC_IFG_CFG); 1318 1319 /* Load seed (0) and set MAC HDX late collision */ 1320 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1321 DEV_MAC_HDX_CFG_SEED_LOAD, 1322 DEV_MAC_HDX_CFG); 1323 mdelay(1); 1324 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1325 DEV_MAC_HDX_CFG); 1326 1327 /* Set Max Length and maximum tags allowed */ 1328 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1329 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1330 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1331 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1332 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1333 DEV_MAC_TAGS_CFG); 1334 1335 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1336 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1337 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1338 1339 /* Enable transmission of pause frames */ 1340 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1341 1342 /* Drop frames with multicast source address */ 1343 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1344 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1345 ANA_PORT_DROP_CFG, port); 1346 1347 /* Set default VLAN and tag type to 8021Q. */ 1348 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1349 REW_PORT_VLAN_CFG_PORT_TPID_M, 1350 REW_PORT_VLAN_CFG, port); 1351 1352 /* Enable vcap lookups */ 1353 ocelot_vcap_enable(ocelot, port); 1354 } 1355 EXPORT_SYMBOL(ocelot_init_port); 1356 1357 /* Configure and enable the CPU port module, which is a set of queues. 1358 * If @npi contains a valid port index, the CPU port module is connected 1359 * to the Node Processor Interface (NPI). This is the mode through which 1360 * frames can be injected from and extracted to an external CPU, 1361 * over Ethernet. 1362 */ 1363 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 1364 enum ocelot_tag_prefix injection, 1365 enum ocelot_tag_prefix extraction) 1366 { 1367 int cpu = ocelot->num_phys_ports; 1368 1369 ocelot->npi = npi; 1370 ocelot->inj_prefix = injection; 1371 ocelot->xtr_prefix = extraction; 1372 1373 /* The unicast destination PGID for the CPU port module is unused */ 1374 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1375 /* Instead set up a multicast destination PGID for traffic copied to 1376 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1377 * addresses will be copied to the CPU via this PGID. 1378 */ 1379 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1380 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1381 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1382 ANA_PORT_PORT_CFG, cpu); 1383 1384 if (npi >= 0 && npi < ocelot->num_phys_ports) { 1385 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 1386 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi), 1387 QSYS_EXT_CPU_CFG); 1388 1389 /* Enable NPI port */ 1390 ocelot_fields_write(ocelot, npi, 1391 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1392 /* NPI port Injection/Extraction configuration */ 1393 ocelot_fields_write(ocelot, npi, SYS_PORT_MODE_INCL_XTR_HDR, 1394 extraction); 1395 ocelot_fields_write(ocelot, npi, SYS_PORT_MODE_INCL_INJ_HDR, 1396 injection); 1397 1398 /* Disable transmission of pause frames */ 1399 ocelot_fields_write(ocelot, npi, SYS_PAUSE_CFG_PAUSE_ENA, 0); 1400 } 1401 1402 /* Enable CPU port module */ 1403 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1404 /* CPU port Injection/Extraction configuration */ 1405 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1406 extraction); 1407 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1408 injection); 1409 1410 /* Configure the CPU port to be VLAN aware */ 1411 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1412 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1413 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1414 ANA_PORT_VLAN_CFG, cpu); 1415 } 1416 EXPORT_SYMBOL(ocelot_configure_cpu); 1417 1418 int ocelot_init(struct ocelot *ocelot) 1419 { 1420 char queue_name[32]; 1421 int i, ret; 1422 u32 port; 1423 1424 if (ocelot->ops->reset) { 1425 ret = ocelot->ops->reset(ocelot); 1426 if (ret) { 1427 dev_err(ocelot->dev, "Switch reset failed\n"); 1428 return ret; 1429 } 1430 } 1431 1432 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1433 sizeof(u32), GFP_KERNEL); 1434 if (!ocelot->lags) 1435 return -ENOMEM; 1436 1437 ocelot->stats = devm_kcalloc(ocelot->dev, 1438 ocelot->num_phys_ports * ocelot->num_stats, 1439 sizeof(u64), GFP_KERNEL); 1440 if (!ocelot->stats) 1441 return -ENOMEM; 1442 1443 mutex_init(&ocelot->stats_lock); 1444 mutex_init(&ocelot->ptp_lock); 1445 spin_lock_init(&ocelot->ptp_clock_lock); 1446 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1447 dev_name(ocelot->dev)); 1448 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1449 if (!ocelot->stats_queue) 1450 return -ENOMEM; 1451 1452 INIT_LIST_HEAD(&ocelot->multicast); 1453 ocelot_mact_init(ocelot); 1454 ocelot_vlan_init(ocelot); 1455 ocelot_vcap_init(ocelot); 1456 1457 for (port = 0; port < ocelot->num_phys_ports; port++) { 1458 /* Clear all counters (5 groups) */ 1459 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1460 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1461 SYS_STAT_CFG); 1462 } 1463 1464 /* Only use S-Tag */ 1465 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1466 1467 /* Aggregation mode */ 1468 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1469 ANA_AGGR_CFG_AC_DMAC_ENA | 1470 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1471 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1472 1473 /* Set MAC age time to default value. The entry is aged after 1474 * 2*AGE_PERIOD 1475 */ 1476 ocelot_write(ocelot, 1477 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1478 ANA_AUTOAGE); 1479 1480 /* Disable learning for frames discarded by VLAN ingress filtering */ 1481 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1482 1483 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1484 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1485 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1486 1487 /* Setup flooding PGIDs */ 1488 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1489 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1490 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1491 ANA_FLOODING, 0); 1492 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1493 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1494 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1495 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1496 ANA_FLOODING_IPMC); 1497 1498 for (port = 0; port < ocelot->num_phys_ports; port++) { 1499 /* Transmit the frame to the local port. */ 1500 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1501 /* Do not forward BPDU frames to the front ports. */ 1502 ocelot_write_gix(ocelot, 1503 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1504 ANA_PORT_CPU_FWD_BPDU_CFG, 1505 port); 1506 /* Ensure bridging is disabled */ 1507 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1508 } 1509 1510 /* Allow broadcast MAC frames. */ 1511 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1512 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1513 1514 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1515 } 1516 ocelot_write_rix(ocelot, 1517 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1518 ANA_PGID_PGID, PGID_MC); 1519 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1520 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1521 1522 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1523 * registers endianness. 1524 */ 1525 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1526 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1527 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1528 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1529 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1530 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1531 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1532 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1533 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1534 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1535 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1536 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1537 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1538 for (i = 0; i < 16; i++) 1539 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1540 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1541 ANA_CPUQ_8021_CFG, i); 1542 1543 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1544 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1545 OCELOT_STATS_CHECK_DELAY); 1546 1547 return 0; 1548 } 1549 EXPORT_SYMBOL(ocelot_init); 1550 1551 void ocelot_deinit(struct ocelot *ocelot) 1552 { 1553 cancel_delayed_work(&ocelot->stats_work); 1554 destroy_workqueue(ocelot->stats_queue); 1555 mutex_destroy(&ocelot->stats_lock); 1556 } 1557 EXPORT_SYMBOL(ocelot_deinit); 1558 1559 void ocelot_deinit_port(struct ocelot *ocelot, int port) 1560 { 1561 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1562 1563 skb_queue_purge(&ocelot_port->tx_skbs); 1564 } 1565 EXPORT_SYMBOL(ocelot_deinit_port); 1566 1567 MODULE_LICENSE("Dual MIT/GPL"); 1568