1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/skbuff.h> 19 #include <linux/iopoll.h> 20 #include <net/arp.h> 21 #include <net/netevent.h> 22 #include <net/rtnetlink.h> 23 #include <net/switchdev.h> 24 25 #include "ocelot.h" 26 #include "ocelot_ace.h" 27 28 #define TABLE_UPDATE_SLEEP_US 10 29 #define TABLE_UPDATE_TIMEOUT_US 100000 30 31 /* MAC table entry types. 32 * ENTRYTYPE_NORMAL is subject to aging. 33 * ENTRYTYPE_LOCKED is not subject to aging. 34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 36 */ 37 enum macaccess_entry_type { 38 ENTRYTYPE_NORMAL = 0, 39 ENTRYTYPE_LOCKED, 40 ENTRYTYPE_MACv4, 41 ENTRYTYPE_MACv6, 42 }; 43 44 struct ocelot_mact_entry { 45 u8 mac[ETH_ALEN]; 46 u16 vid; 47 enum macaccess_entry_type type; 48 }; 49 50 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 51 { 52 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 53 } 54 55 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 56 { 57 u32 val; 58 59 return readx_poll_timeout(ocelot_mact_read_macaccess, 60 ocelot, val, 61 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 62 MACACCESS_CMD_IDLE, 63 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 64 } 65 66 static void ocelot_mact_select(struct ocelot *ocelot, 67 const unsigned char mac[ETH_ALEN], 68 unsigned int vid) 69 { 70 u32 macl = 0, mach = 0; 71 72 /* Set the MAC address to handle and the vlan associated in a format 73 * understood by the hardware. 74 */ 75 mach |= vid << 16; 76 mach |= mac[0] << 8; 77 mach |= mac[1] << 0; 78 macl |= mac[2] << 24; 79 macl |= mac[3] << 16; 80 macl |= mac[4] << 8; 81 macl |= mac[5] << 0; 82 83 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 84 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 85 86 } 87 88 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 89 const unsigned char mac[ETH_ALEN], 90 unsigned int vid, 91 enum macaccess_entry_type type) 92 { 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 97 ANA_TABLES_MACACCESS_DEST_IDX(port) | 98 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 100 ANA_TABLES_MACACCESS); 101 102 return ocelot_mact_wait_for_completion(ocelot); 103 } 104 105 static int ocelot_mact_forget(struct ocelot *ocelot, 106 const unsigned char mac[ETH_ALEN], 107 unsigned int vid) 108 { 109 ocelot_mact_select(ocelot, mac, vid); 110 111 /* Issue a forget command */ 112 ocelot_write(ocelot, 113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 114 ANA_TABLES_MACACCESS); 115 116 return ocelot_mact_wait_for_completion(ocelot); 117 } 118 119 static void ocelot_mact_init(struct ocelot *ocelot) 120 { 121 /* Configure the learning mode entries attributes: 122 * - Do not copy the frame to the CPU extraction queues. 123 * - Use the vlan and mac_cpoy for dmac lookup. 124 */ 125 ocelot_rmw(ocelot, 0, 126 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 127 | ANA_AGENCTRL_LEARN_FWD_KILL 128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 129 ANA_AGENCTRL); 130 131 /* Clear the MAC table */ 132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 133 } 134 135 static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port) 136 { 137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 139 ANA_PORT_VCAP_S2_CFG, port->chip_port); 140 } 141 142 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 143 { 144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 145 } 146 147 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 148 { 149 u32 val; 150 151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 152 ocelot, 153 val, 154 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 155 ANA_TABLES_VLANACCESS_CMD_IDLE, 156 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 157 } 158 159 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 160 { 161 /* Select the VID to configure */ 162 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 163 ANA_TABLES_VLANTIDX); 164 /* Set the vlan port members mask and issue a write command */ 165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 166 ANA_TABLES_VLANACCESS_CMD_WRITE, 167 ANA_TABLES_VLANACCESS); 168 169 return ocelot_vlant_wait_for_completion(ocelot); 170 } 171 172 static void ocelot_vlan_mode(struct ocelot_port *port, 173 netdev_features_t features) 174 { 175 struct ocelot *ocelot = port->ocelot; 176 u8 p = port->chip_port; 177 u32 val; 178 179 /* Filtering */ 180 val = ocelot_read(ocelot, ANA_VLANMASK); 181 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 182 val |= BIT(p); 183 else 184 val &= ~BIT(p); 185 ocelot_write(ocelot, val, ANA_VLANMASK); 186 } 187 188 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 189 struct ocelot_port *port) 190 { 191 u32 val; 192 193 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 194 /* Default vlan to clasify for untagged frames (may be zero) */ 195 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 196 if (port->vlan_aware) 197 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 198 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 199 200 ocelot_rmw_gix(ocelot, val, 201 ANA_PORT_VLAN_CFG_VLAN_VID_M | 202 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 203 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 204 ANA_PORT_VLAN_CFG, port->chip_port); 205 206 /* Drop frames with multicast source address */ 207 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 208 if (port->vlan_aware && !port->vid) 209 /* If port is vlan-aware and tagged, drop untagged and priority 210 * tagged frames. 211 */ 212 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 215 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 216 217 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 218 val = REW_TAG_CFG_TAG_TPID_CFG(0); 219 220 if (port->vlan_aware) { 221 if (port->vid) 222 /* Tag all frames except when VID == DEFAULT_VLAN */ 223 val |= REW_TAG_CFG_TAG_CFG(1); 224 else 225 /* Tag all frames */ 226 val |= REW_TAG_CFG_TAG_CFG(3); 227 } 228 ocelot_rmw_gix(ocelot, val, 229 REW_TAG_CFG_TAG_TPID_CFG_M | 230 REW_TAG_CFG_TAG_CFG_M, 231 REW_TAG_CFG, port->chip_port); 232 233 /* Set default VLAN and tag type to 8021Q. */ 234 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 235 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 236 ocelot_rmw_gix(ocelot, val, 237 REW_PORT_VLAN_CFG_PORT_TPID_M | 238 REW_PORT_VLAN_CFG_PORT_VID_M, 239 REW_PORT_VLAN_CFG, port->chip_port); 240 } 241 242 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 243 bool untagged) 244 { 245 struct ocelot_port *port = netdev_priv(dev); 246 struct ocelot *ocelot = port->ocelot; 247 int ret; 248 249 /* Add the port MAC address to with the right VLAN information */ 250 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 251 ENTRYTYPE_LOCKED); 252 253 /* Make the port a member of the VLAN */ 254 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 255 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 256 if (ret) 257 return ret; 258 259 /* Default ingress vlan classification */ 260 if (pvid) 261 port->pvid = vid; 262 263 /* Untagged egress vlan clasification */ 264 if (untagged) 265 port->vid = vid; 266 267 ocelot_vlan_port_apply(ocelot, port); 268 269 return 0; 270 } 271 272 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 273 { 274 struct ocelot_port *port = netdev_priv(dev); 275 struct ocelot *ocelot = port->ocelot; 276 int ret; 277 278 /* 8021q removes VID 0 on module unload for all interfaces 279 * with VLAN filtering feature. We need to keep it to receive 280 * untagged traffic. 281 */ 282 if (vid == 0) 283 return 0; 284 285 /* Del the port MAC address to with the right VLAN information */ 286 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 287 288 /* Stop the port from being a member of the vlan */ 289 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 290 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 291 if (ret) 292 return ret; 293 294 /* Ingress */ 295 if (port->pvid == vid) 296 port->pvid = 0; 297 298 /* Egress */ 299 if (port->vid == vid) 300 port->vid = 0; 301 302 ocelot_vlan_port_apply(ocelot, port); 303 304 return 0; 305 } 306 307 static void ocelot_vlan_init(struct ocelot *ocelot) 308 { 309 u16 port, vid; 310 311 /* Clear VLAN table, by default all ports are members of all VLANs */ 312 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 313 ANA_TABLES_VLANACCESS); 314 ocelot_vlant_wait_for_completion(ocelot); 315 316 /* Configure the port VLAN memberships */ 317 for (vid = 1; vid < VLAN_N_VID; vid++) { 318 ocelot->vlan_mask[vid] = 0; 319 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 320 } 321 322 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 323 * traffic. It is added automatically if 8021q module is loaded, but 324 * we can't rely on it since module may be not loaded. 325 */ 326 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 327 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 328 329 /* Configure the CPU port to be VLAN aware */ 330 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 331 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 332 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 333 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 334 335 /* Set vlan ingress filter mask to all ports but the CPU port by 336 * default. 337 */ 338 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 339 340 for (port = 0; port < ocelot->num_phys_ports; port++) { 341 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 342 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 343 } 344 } 345 346 /* Watermark encode 347 * Bit 8: Unit; 0:1, 1:16 348 * Bit 7-0: Value to be multiplied with unit 349 */ 350 static u16 ocelot_wm_enc(u16 value) 351 { 352 if (value >= BIT(8)) 353 return BIT(8) | (value / 16); 354 355 return value; 356 } 357 358 static void ocelot_port_adjust_link(struct net_device *dev) 359 { 360 struct ocelot_port *port = netdev_priv(dev); 361 struct ocelot *ocelot = port->ocelot; 362 u8 p = port->chip_port; 363 int speed, atop_wm, mode = 0; 364 365 switch (dev->phydev->speed) { 366 case SPEED_10: 367 speed = OCELOT_SPEED_10; 368 break; 369 case SPEED_100: 370 speed = OCELOT_SPEED_100; 371 break; 372 case SPEED_1000: 373 speed = OCELOT_SPEED_1000; 374 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 375 break; 376 case SPEED_2500: 377 speed = OCELOT_SPEED_2500; 378 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 379 break; 380 default: 381 netdev_err(dev, "Unsupported PHY speed: %d\n", 382 dev->phydev->speed); 383 return; 384 } 385 386 phy_print_status(dev->phydev); 387 388 if (!dev->phydev->link) 389 return; 390 391 /* Only full duplex supported for now */ 392 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 393 mode, DEV_MAC_MODE_CFG); 394 395 /* Set MAC IFG Gaps 396 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 397 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 398 */ 399 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 400 401 /* Load seed (0) and set MAC HDX late collision */ 402 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 403 DEV_MAC_HDX_CFG_SEED_LOAD, 404 DEV_MAC_HDX_CFG); 405 mdelay(1); 406 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 407 DEV_MAC_HDX_CFG); 408 409 /* Disable HDX fast control */ 410 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 411 412 /* SGMII only for now */ 413 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 414 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 415 416 /* Enable PCS */ 417 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 418 419 /* No aneg on SGMII */ 420 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 421 422 /* No loopback */ 423 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 424 425 /* Set Max Length and maximum tags allowed */ 426 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 427 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 428 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 429 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 430 DEV_MAC_TAGS_CFG); 431 432 /* Enable MAC module */ 433 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 434 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 435 436 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 437 * reset */ 438 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 439 DEV_CLOCK_CFG); 440 441 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 442 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 443 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 444 445 /* No PFC */ 446 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 447 ANA_PFC_PFC_CFG, p); 448 449 /* Set Pause WM hysteresis 450 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 451 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 452 */ 453 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 454 SYS_PAUSE_CFG_PAUSE_STOP(101) | 455 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 456 457 /* Core: Enable port for frame transfer */ 458 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 459 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 460 QSYS_SWITCH_PORT_MODE_PORT_ENA, 461 QSYS_SWITCH_PORT_MODE, p); 462 463 /* Flow control */ 464 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 465 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 466 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 467 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 468 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 469 SYS_MAC_FC_CFG, p); 470 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 471 472 /* Tail dropping watermark */ 473 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 474 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 475 SYS_ATOP, p); 476 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 477 } 478 479 static int ocelot_port_open(struct net_device *dev) 480 { 481 struct ocelot_port *port = netdev_priv(dev); 482 struct ocelot *ocelot = port->ocelot; 483 int err; 484 485 /* Enable receiving frames on the port, and activate auto-learning of 486 * MAC addresses. 487 */ 488 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 489 ANA_PORT_PORT_CFG_RECV_ENA | 490 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 491 ANA_PORT_PORT_CFG, port->chip_port); 492 493 if (port->serdes) { 494 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 495 port->phy_mode); 496 if (err) { 497 netdev_err(dev, "Could not set mode of SerDes\n"); 498 return err; 499 } 500 } 501 502 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 503 port->phy_mode); 504 if (err) { 505 netdev_err(dev, "Could not attach to PHY\n"); 506 return err; 507 } 508 509 dev->phydev = port->phy; 510 511 phy_attached_info(port->phy); 512 phy_start(port->phy); 513 return 0; 514 } 515 516 static int ocelot_port_stop(struct net_device *dev) 517 { 518 struct ocelot_port *port = netdev_priv(dev); 519 520 phy_disconnect(port->phy); 521 522 dev->phydev = NULL; 523 524 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 525 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 526 QSYS_SWITCH_PORT_MODE, port->chip_port); 527 return 0; 528 } 529 530 /* Generate the IFH for frame injection 531 * 532 * The IFH is a 128bit-value 533 * bit 127: bypass the analyzer processing 534 * bit 56-67: destination mask 535 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 536 * bit 20-27: cpu extraction queue mask 537 * bit 16: tag type 0: C-tag, 1: S-tag 538 * bit 0-11: VID 539 */ 540 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 541 { 542 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 543 ifh[1] = (0xf00 & info->port) >> 8; 544 ifh[2] = (0xff & info->port) << 24; 545 ifh[3] = (info->tag_type << 16) | info->vid; 546 547 return 0; 548 } 549 550 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 551 { 552 struct skb_shared_info *shinfo = skb_shinfo(skb); 553 struct ocelot_port *port = netdev_priv(dev); 554 struct ocelot *ocelot = port->ocelot; 555 u32 val, ifh[IFH_LEN]; 556 struct frame_info info = {}; 557 u8 grp = 0; /* Send everything on CPU group 0 */ 558 unsigned int i, count, last; 559 560 val = ocelot_read(ocelot, QS_INJ_STATUS); 561 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 562 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 563 return NETDEV_TX_BUSY; 564 565 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 566 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 567 568 info.port = BIT(port->chip_port); 569 info.tag_type = IFH_TAG_TYPE_C; 570 info.vid = skb_vlan_tag_get(skb); 571 572 /* Check if timestamping is needed */ 573 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 574 info.rew_op = port->ptp_cmd; 575 if (port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 576 info.rew_op |= (port->ts_id % 4) << 3; 577 } 578 579 ocelot_gen_ifh(ifh, &info); 580 581 for (i = 0; i < IFH_LEN; i++) 582 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 583 QS_INJ_WR, grp); 584 585 count = (skb->len + 3) / 4; 586 last = skb->len % 4; 587 for (i = 0; i < count; i++) { 588 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 589 } 590 591 /* Add padding */ 592 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 593 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 594 i++; 595 } 596 597 /* Indicate EOF and valid bytes in last word */ 598 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 599 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 600 QS_INJ_CTRL_EOF, 601 QS_INJ_CTRL, grp); 602 603 /* Add dummy CRC */ 604 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 605 skb_tx_timestamp(skb); 606 607 dev->stats.tx_packets++; 608 dev->stats.tx_bytes += skb->len; 609 610 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 611 port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 612 struct ocelot_skb *oskb = 613 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC); 614 615 if (unlikely(!oskb)) 616 goto out; 617 618 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 619 620 oskb->skb = skb; 621 oskb->id = port->ts_id % 4; 622 port->ts_id++; 623 624 list_add_tail(&oskb->head, &port->skbs); 625 626 return NETDEV_TX_OK; 627 } 628 629 out: 630 dev_kfree_skb_any(skb); 631 return NETDEV_TX_OK; 632 } 633 634 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts) 635 { 636 unsigned long flags; 637 u32 val; 638 639 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 640 641 /* Read current PTP time to get seconds */ 642 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 643 644 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 645 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 646 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 647 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 648 649 /* Read packet HW timestamp from FIFO */ 650 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 651 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 652 653 /* Sec has incremented since the ts was registered */ 654 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 655 ts->tv_sec--; 656 657 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 658 } 659 EXPORT_SYMBOL(ocelot_get_hwtimestamp); 660 661 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 662 { 663 struct ocelot_port *port = netdev_priv(dev); 664 665 return ocelot_mact_forget(port->ocelot, addr, port->pvid); 666 } 667 668 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 669 { 670 struct ocelot_port *port = netdev_priv(dev); 671 672 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid, 673 ENTRYTYPE_LOCKED); 674 } 675 676 static void ocelot_set_rx_mode(struct net_device *dev) 677 { 678 struct ocelot_port *port = netdev_priv(dev); 679 struct ocelot *ocelot = port->ocelot; 680 int i; 681 u32 val; 682 683 /* This doesn't handle promiscuous mode because the bridge core is 684 * setting IFF_PROMISC on all slave interfaces and all frames would be 685 * forwarded to the CPU port. 686 */ 687 val = GENMASK(ocelot->num_phys_ports - 1, 0); 688 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 689 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 690 691 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 692 } 693 694 static int ocelot_port_get_phys_port_name(struct net_device *dev, 695 char *buf, size_t len) 696 { 697 struct ocelot_port *port = netdev_priv(dev); 698 int ret; 699 700 ret = snprintf(buf, len, "p%d", port->chip_port); 701 if (ret >= len) 702 return -EINVAL; 703 704 return 0; 705 } 706 707 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 708 { 709 struct ocelot_port *port = netdev_priv(dev); 710 struct ocelot *ocelot = port->ocelot; 711 const struct sockaddr *addr = p; 712 713 /* Learn the new net device MAC address in the mac table. */ 714 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 715 ENTRYTYPE_LOCKED); 716 /* Then forget the previous one. */ 717 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 718 719 ether_addr_copy(dev->dev_addr, addr->sa_data); 720 return 0; 721 } 722 723 static void ocelot_get_stats64(struct net_device *dev, 724 struct rtnl_link_stats64 *stats) 725 { 726 struct ocelot_port *port = netdev_priv(dev); 727 struct ocelot *ocelot = port->ocelot; 728 729 /* Configure the port to read the stats from */ 730 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 731 SYS_STAT_CFG); 732 733 /* Get Rx stats */ 734 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 735 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 736 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 737 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 738 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 739 ocelot_read(ocelot, SYS_COUNT_RX_64) + 740 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 741 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 742 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 743 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 744 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 745 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 746 stats->rx_dropped = dev->stats.rx_dropped; 747 748 /* Get Tx stats */ 749 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 750 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 751 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 752 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 753 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 754 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 755 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 756 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 757 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 758 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 759 } 760 761 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 762 struct net_device *dev, const unsigned char *addr, 763 u16 vid, u16 flags, 764 struct netlink_ext_ack *extack) 765 { 766 struct ocelot_port *port = netdev_priv(dev); 767 struct ocelot *ocelot = port->ocelot; 768 769 if (!vid) { 770 if (!port->vlan_aware) 771 /* If the bridge is not VLAN aware and no VID was 772 * provided, set it to pvid to ensure the MAC entry 773 * matches incoming untagged packets 774 */ 775 vid = port->pvid; 776 else 777 /* If the bridge is VLAN aware a VID must be provided as 778 * otherwise the learnt entry wouldn't match any frame. 779 */ 780 return -EINVAL; 781 } 782 783 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 784 ENTRYTYPE_LOCKED); 785 } 786 787 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 788 struct net_device *dev, 789 const unsigned char *addr, u16 vid) 790 { 791 struct ocelot_port *port = netdev_priv(dev); 792 struct ocelot *ocelot = port->ocelot; 793 794 return ocelot_mact_forget(ocelot, addr, vid); 795 } 796 797 struct ocelot_dump_ctx { 798 struct net_device *dev; 799 struct sk_buff *skb; 800 struct netlink_callback *cb; 801 int idx; 802 }; 803 804 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 805 struct ocelot_dump_ctx *dump) 806 { 807 u32 portid = NETLINK_CB(dump->cb->skb).portid; 808 u32 seq = dump->cb->nlh->nlmsg_seq; 809 struct nlmsghdr *nlh; 810 struct ndmsg *ndm; 811 812 if (dump->idx < dump->cb->args[2]) 813 goto skip; 814 815 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 816 sizeof(*ndm), NLM_F_MULTI); 817 if (!nlh) 818 return -EMSGSIZE; 819 820 ndm = nlmsg_data(nlh); 821 ndm->ndm_family = AF_BRIDGE; 822 ndm->ndm_pad1 = 0; 823 ndm->ndm_pad2 = 0; 824 ndm->ndm_flags = NTF_SELF; 825 ndm->ndm_type = 0; 826 ndm->ndm_ifindex = dump->dev->ifindex; 827 ndm->ndm_state = NUD_REACHABLE; 828 829 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 830 goto nla_put_failure; 831 832 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 833 goto nla_put_failure; 834 835 nlmsg_end(dump->skb, nlh); 836 837 skip: 838 dump->idx++; 839 return 0; 840 841 nla_put_failure: 842 nlmsg_cancel(dump->skb, nlh); 843 return -EMSGSIZE; 844 } 845 846 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 847 struct ocelot_mact_entry *entry) 848 { 849 struct ocelot *ocelot = port->ocelot; 850 char mac[ETH_ALEN]; 851 u32 val, dst, macl, mach; 852 853 /* Set row and column to read from */ 854 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 855 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 856 857 /* Issue a read command */ 858 ocelot_write(ocelot, 859 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 860 ANA_TABLES_MACACCESS); 861 862 if (ocelot_mact_wait_for_completion(ocelot)) 863 return -ETIMEDOUT; 864 865 /* Read the entry flags */ 866 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 867 if (!(val & ANA_TABLES_MACACCESS_VALID)) 868 return -EINVAL; 869 870 /* If the entry read has another port configured as its destination, 871 * do not report it. 872 */ 873 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 874 if (dst != port->chip_port) 875 return -EINVAL; 876 877 /* Get the entry's MAC address and VLAN id */ 878 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 879 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 880 881 mac[0] = (mach >> 8) & 0xff; 882 mac[1] = (mach >> 0) & 0xff; 883 mac[2] = (macl >> 24) & 0xff; 884 mac[3] = (macl >> 16) & 0xff; 885 mac[4] = (macl >> 8) & 0xff; 886 mac[5] = (macl >> 0) & 0xff; 887 888 entry->vid = (mach >> 16) & 0xfff; 889 ether_addr_copy(entry->mac, mac); 890 891 return 0; 892 } 893 894 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 895 struct net_device *dev, 896 struct net_device *filter_dev, int *idx) 897 { 898 struct ocelot_port *port = netdev_priv(dev); 899 int i, j, ret = 0; 900 struct ocelot_dump_ctx dump = { 901 .dev = dev, 902 .skb = skb, 903 .cb = cb, 904 .idx = *idx, 905 }; 906 907 struct ocelot_mact_entry entry; 908 909 /* Loop through all the mac tables entries. There are 1024 rows of 4 910 * entries. 911 */ 912 for (i = 0; i < 1024; i++) { 913 for (j = 0; j < 4; j++) { 914 ret = ocelot_mact_read(port, i, j, &entry); 915 /* If the entry is invalid (wrong port, invalid...), 916 * skip it. 917 */ 918 if (ret == -EINVAL) 919 continue; 920 else if (ret) 921 goto end; 922 923 ret = ocelot_fdb_do_dump(&entry, &dump); 924 if (ret) 925 goto end; 926 } 927 } 928 929 end: 930 *idx = dump.idx; 931 return ret; 932 } 933 934 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 935 u16 vid) 936 { 937 return ocelot_vlan_vid_add(dev, vid, false, true); 938 } 939 940 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 941 u16 vid) 942 { 943 return ocelot_vlan_vid_del(dev, vid); 944 } 945 946 static int ocelot_set_features(struct net_device *dev, 947 netdev_features_t features) 948 { 949 struct ocelot_port *port = netdev_priv(dev); 950 netdev_features_t changed = dev->features ^ features; 951 952 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 953 port->tc.offload_cnt) { 954 netdev_err(dev, 955 "Cannot disable HW TC offload while offloads active\n"); 956 return -EBUSY; 957 } 958 959 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 960 ocelot_vlan_mode(port, features); 961 962 return 0; 963 } 964 965 static int ocelot_get_port_parent_id(struct net_device *dev, 966 struct netdev_phys_item_id *ppid) 967 { 968 struct ocelot_port *ocelot_port = netdev_priv(dev); 969 struct ocelot *ocelot = ocelot_port->ocelot; 970 971 ppid->id_len = sizeof(ocelot->base_mac); 972 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 973 974 return 0; 975 } 976 977 static int ocelot_hwstamp_get(struct ocelot_port *port, struct ifreq *ifr) 978 { 979 struct ocelot *ocelot = port->ocelot; 980 981 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 982 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 983 } 984 985 static int ocelot_hwstamp_set(struct ocelot_port *port, struct ifreq *ifr) 986 { 987 struct ocelot *ocelot = port->ocelot; 988 struct hwtstamp_config cfg; 989 990 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 991 return -EFAULT; 992 993 /* reserved for future extensions */ 994 if (cfg.flags) 995 return -EINVAL; 996 997 /* Tx type sanity check */ 998 switch (cfg.tx_type) { 999 case HWTSTAMP_TX_ON: 1000 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1001 break; 1002 case HWTSTAMP_TX_ONESTEP_SYNC: 1003 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1004 * need to update the origin time. 1005 */ 1006 port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1007 break; 1008 case HWTSTAMP_TX_OFF: 1009 port->ptp_cmd = 0; 1010 break; 1011 default: 1012 return -ERANGE; 1013 } 1014 1015 mutex_lock(&ocelot->ptp_lock); 1016 1017 switch (cfg.rx_filter) { 1018 case HWTSTAMP_FILTER_NONE: 1019 break; 1020 case HWTSTAMP_FILTER_ALL: 1021 case HWTSTAMP_FILTER_SOME: 1022 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1023 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1024 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1025 case HWTSTAMP_FILTER_NTP_ALL: 1026 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1027 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1028 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1029 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1030 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1031 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1032 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1033 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1034 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1035 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1036 break; 1037 default: 1038 mutex_unlock(&ocelot->ptp_lock); 1039 return -ERANGE; 1040 } 1041 1042 /* Commit back the result & save it */ 1043 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1044 mutex_unlock(&ocelot->ptp_lock); 1045 1046 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1047 } 1048 1049 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1050 { 1051 struct ocelot_port *port = netdev_priv(dev); 1052 struct ocelot *ocelot = port->ocelot; 1053 1054 /* The function is only used for PTP operations for now */ 1055 if (!ocelot->ptp) 1056 return -EOPNOTSUPP; 1057 1058 switch (cmd) { 1059 case SIOCSHWTSTAMP: 1060 return ocelot_hwstamp_set(port, ifr); 1061 case SIOCGHWTSTAMP: 1062 return ocelot_hwstamp_get(port, ifr); 1063 default: 1064 return -EOPNOTSUPP; 1065 } 1066 } 1067 1068 static const struct net_device_ops ocelot_port_netdev_ops = { 1069 .ndo_open = ocelot_port_open, 1070 .ndo_stop = ocelot_port_stop, 1071 .ndo_start_xmit = ocelot_port_xmit, 1072 .ndo_set_rx_mode = ocelot_set_rx_mode, 1073 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1074 .ndo_set_mac_address = ocelot_port_set_mac_address, 1075 .ndo_get_stats64 = ocelot_get_stats64, 1076 .ndo_fdb_add = ocelot_fdb_add, 1077 .ndo_fdb_del = ocelot_fdb_del, 1078 .ndo_fdb_dump = ocelot_fdb_dump, 1079 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1080 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1081 .ndo_set_features = ocelot_set_features, 1082 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1083 .ndo_setup_tc = ocelot_setup_tc, 1084 .ndo_do_ioctl = ocelot_ioctl, 1085 }; 1086 1087 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 1088 { 1089 struct ocelot_port *port = netdev_priv(netdev); 1090 struct ocelot *ocelot = port->ocelot; 1091 int i; 1092 1093 if (sset != ETH_SS_STATS) 1094 return; 1095 1096 for (i = 0; i < ocelot->num_stats; i++) 1097 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1098 ETH_GSTRING_LEN); 1099 } 1100 1101 static void ocelot_update_stats(struct ocelot *ocelot) 1102 { 1103 int i, j; 1104 1105 mutex_lock(&ocelot->stats_lock); 1106 1107 for (i = 0; i < ocelot->num_phys_ports; i++) { 1108 /* Configure the port to read the stats from */ 1109 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1110 1111 for (j = 0; j < ocelot->num_stats; j++) { 1112 u32 val; 1113 unsigned int idx = i * ocelot->num_stats + j; 1114 1115 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1116 ocelot->stats_layout[j].offset); 1117 1118 if (val < (ocelot->stats[idx] & U32_MAX)) 1119 ocelot->stats[idx] += (u64)1 << 32; 1120 1121 ocelot->stats[idx] = (ocelot->stats[idx] & 1122 ~(u64)U32_MAX) + val; 1123 } 1124 } 1125 1126 mutex_unlock(&ocelot->stats_lock); 1127 } 1128 1129 static void ocelot_check_stats_work(struct work_struct *work) 1130 { 1131 struct delayed_work *del_work = to_delayed_work(work); 1132 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1133 stats_work); 1134 1135 ocelot_update_stats(ocelot); 1136 1137 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1138 OCELOT_STATS_CHECK_DELAY); 1139 } 1140 1141 static void ocelot_get_ethtool_stats(struct net_device *dev, 1142 struct ethtool_stats *stats, u64 *data) 1143 { 1144 struct ocelot_port *port = netdev_priv(dev); 1145 struct ocelot *ocelot = port->ocelot; 1146 int i; 1147 1148 /* check and update now */ 1149 ocelot_update_stats(ocelot); 1150 1151 /* Copy all counters */ 1152 for (i = 0; i < ocelot->num_stats; i++) 1153 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 1154 } 1155 1156 static int ocelot_get_sset_count(struct net_device *dev, int sset) 1157 { 1158 struct ocelot_port *port = netdev_priv(dev); 1159 struct ocelot *ocelot = port->ocelot; 1160 1161 if (sset != ETH_SS_STATS) 1162 return -EOPNOTSUPP; 1163 return ocelot->num_stats; 1164 } 1165 1166 static int ocelot_get_ts_info(struct net_device *dev, 1167 struct ethtool_ts_info *info) 1168 { 1169 struct ocelot_port *ocelot_port = netdev_priv(dev); 1170 struct ocelot *ocelot = ocelot_port->ocelot; 1171 1172 if (!ocelot->ptp) 1173 return ethtool_op_get_ts_info(dev, info); 1174 1175 info->phc_index = ocelot->ptp_clock ? 1176 ptp_clock_index(ocelot->ptp_clock) : -1; 1177 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1178 SOF_TIMESTAMPING_RX_SOFTWARE | 1179 SOF_TIMESTAMPING_SOFTWARE | 1180 SOF_TIMESTAMPING_TX_HARDWARE | 1181 SOF_TIMESTAMPING_RX_HARDWARE | 1182 SOF_TIMESTAMPING_RAW_HARDWARE; 1183 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1184 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1185 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1186 1187 return 0; 1188 } 1189 1190 static const struct ethtool_ops ocelot_ethtool_ops = { 1191 .get_strings = ocelot_get_strings, 1192 .get_ethtool_stats = ocelot_get_ethtool_stats, 1193 .get_sset_count = ocelot_get_sset_count, 1194 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1195 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1196 .get_ts_info = ocelot_get_ts_info, 1197 }; 1198 1199 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1200 struct switchdev_trans *trans, 1201 u8 state) 1202 { 1203 struct ocelot *ocelot = ocelot_port->ocelot; 1204 u32 port_cfg; 1205 int port, i; 1206 1207 if (switchdev_trans_ph_prepare(trans)) 1208 return 0; 1209 1210 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1211 return 0; 1212 1213 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1214 ocelot_port->chip_port); 1215 1216 switch (state) { 1217 case BR_STATE_FORWARDING: 1218 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1219 /* Fallthrough */ 1220 case BR_STATE_LEARNING: 1221 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1222 break; 1223 1224 default: 1225 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1226 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1227 break; 1228 } 1229 1230 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1231 ocelot_port->chip_port); 1232 1233 /* Apply FWD mask. The loop is needed to add/remove the current port as 1234 * a source for the other ports. 1235 */ 1236 for (port = 0; port < ocelot->num_phys_ports; port++) { 1237 if (ocelot->bridge_fwd_mask & BIT(port)) { 1238 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1239 1240 for (i = 0; i < ocelot->num_phys_ports; i++) { 1241 unsigned long bond_mask = ocelot->lags[i]; 1242 1243 if (!bond_mask) 1244 continue; 1245 1246 if (bond_mask & BIT(port)) { 1247 mask &= ~bond_mask; 1248 break; 1249 } 1250 } 1251 1252 ocelot_write_rix(ocelot, 1253 BIT(ocelot->num_phys_ports) | mask, 1254 ANA_PGID_PGID, PGID_SRC + port); 1255 } else { 1256 /* Only the CPU port, this is compatible with link 1257 * aggregation. 1258 */ 1259 ocelot_write_rix(ocelot, 1260 BIT(ocelot->num_phys_ports), 1261 ANA_PGID_PGID, PGID_SRC + port); 1262 } 1263 } 1264 1265 return 0; 1266 } 1267 1268 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1269 unsigned long ageing_clock_t) 1270 { 1271 struct ocelot *ocelot = ocelot_port->ocelot; 1272 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1273 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1274 1275 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1276 ANA_AUTOAGE); 1277 } 1278 1279 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1280 { 1281 struct ocelot *ocelot = port->ocelot; 1282 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1283 port->chip_port); 1284 1285 if (mc) 1286 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1287 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1288 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1289 else 1290 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1291 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1292 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1293 1294 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1295 } 1296 1297 static int ocelot_port_attr_set(struct net_device *dev, 1298 const struct switchdev_attr *attr, 1299 struct switchdev_trans *trans) 1300 { 1301 struct ocelot_port *ocelot_port = netdev_priv(dev); 1302 int err = 0; 1303 1304 switch (attr->id) { 1305 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1306 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1307 attr->u.stp_state); 1308 break; 1309 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1310 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1311 break; 1312 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1313 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1314 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1315 break; 1316 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1317 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1318 break; 1319 default: 1320 err = -EOPNOTSUPP; 1321 break; 1322 } 1323 1324 return err; 1325 } 1326 1327 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1328 const struct switchdev_obj_port_vlan *vlan, 1329 struct switchdev_trans *trans) 1330 { 1331 int ret; 1332 u16 vid; 1333 1334 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1335 ret = ocelot_vlan_vid_add(dev, vid, 1336 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1337 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1338 if (ret) 1339 return ret; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1346 const struct switchdev_obj_port_vlan *vlan) 1347 { 1348 int ret; 1349 u16 vid; 1350 1351 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1352 ret = ocelot_vlan_vid_del(dev, vid); 1353 1354 if (ret) 1355 return ret; 1356 } 1357 1358 return 0; 1359 } 1360 1361 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1362 const unsigned char *addr, 1363 u16 vid) 1364 { 1365 struct ocelot_multicast *mc; 1366 1367 list_for_each_entry(mc, &ocelot->multicast, list) { 1368 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1369 return mc; 1370 } 1371 1372 return NULL; 1373 } 1374 1375 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1376 const struct switchdev_obj_port_mdb *mdb, 1377 struct switchdev_trans *trans) 1378 { 1379 struct ocelot_port *port = netdev_priv(dev); 1380 struct ocelot *ocelot = port->ocelot; 1381 struct ocelot_multicast *mc; 1382 unsigned char addr[ETH_ALEN]; 1383 u16 vid = mdb->vid; 1384 bool new = false; 1385 1386 if (!vid) 1387 vid = port->pvid; 1388 1389 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1390 if (!mc) { 1391 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1392 if (!mc) 1393 return -ENOMEM; 1394 1395 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1396 mc->vid = vid; 1397 1398 list_add_tail(&mc->list, &ocelot->multicast); 1399 new = true; 1400 } 1401 1402 memcpy(addr, mc->addr, ETH_ALEN); 1403 addr[0] = 0; 1404 1405 if (!new) { 1406 addr[2] = mc->ports << 0; 1407 addr[1] = mc->ports << 8; 1408 ocelot_mact_forget(ocelot, addr, vid); 1409 } 1410 1411 mc->ports |= BIT(port->chip_port); 1412 addr[2] = mc->ports << 0; 1413 addr[1] = mc->ports << 8; 1414 1415 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1416 } 1417 1418 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1419 const struct switchdev_obj_port_mdb *mdb) 1420 { 1421 struct ocelot_port *port = netdev_priv(dev); 1422 struct ocelot *ocelot = port->ocelot; 1423 struct ocelot_multicast *mc; 1424 unsigned char addr[ETH_ALEN]; 1425 u16 vid = mdb->vid; 1426 1427 if (!vid) 1428 vid = port->pvid; 1429 1430 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1431 if (!mc) 1432 return -ENOENT; 1433 1434 memcpy(addr, mc->addr, ETH_ALEN); 1435 addr[2] = mc->ports << 0; 1436 addr[1] = mc->ports << 8; 1437 addr[0] = 0; 1438 ocelot_mact_forget(ocelot, addr, vid); 1439 1440 mc->ports &= ~BIT(port->chip_port); 1441 if (!mc->ports) { 1442 list_del(&mc->list); 1443 devm_kfree(ocelot->dev, mc); 1444 return 0; 1445 } 1446 1447 addr[2] = mc->ports << 0; 1448 addr[1] = mc->ports << 8; 1449 1450 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1451 } 1452 1453 static int ocelot_port_obj_add(struct net_device *dev, 1454 const struct switchdev_obj *obj, 1455 struct switchdev_trans *trans, 1456 struct netlink_ext_ack *extack) 1457 { 1458 int ret = 0; 1459 1460 switch (obj->id) { 1461 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1462 ret = ocelot_port_obj_add_vlan(dev, 1463 SWITCHDEV_OBJ_PORT_VLAN(obj), 1464 trans); 1465 break; 1466 case SWITCHDEV_OBJ_ID_PORT_MDB: 1467 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1468 trans); 1469 break; 1470 default: 1471 return -EOPNOTSUPP; 1472 } 1473 1474 return ret; 1475 } 1476 1477 static int ocelot_port_obj_del(struct net_device *dev, 1478 const struct switchdev_obj *obj) 1479 { 1480 int ret = 0; 1481 1482 switch (obj->id) { 1483 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1484 ret = ocelot_port_vlan_del_vlan(dev, 1485 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1486 break; 1487 case SWITCHDEV_OBJ_ID_PORT_MDB: 1488 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1489 break; 1490 default: 1491 return -EOPNOTSUPP; 1492 } 1493 1494 return ret; 1495 } 1496 1497 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1498 struct net_device *bridge) 1499 { 1500 struct ocelot *ocelot = ocelot_port->ocelot; 1501 1502 if (!ocelot->bridge_mask) { 1503 ocelot->hw_bridge_dev = bridge; 1504 } else { 1505 if (ocelot->hw_bridge_dev != bridge) 1506 /* This is adding the port to a second bridge, this is 1507 * unsupported */ 1508 return -ENODEV; 1509 } 1510 1511 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1512 1513 return 0; 1514 } 1515 1516 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1517 struct net_device *bridge) 1518 { 1519 struct ocelot *ocelot = ocelot_port->ocelot; 1520 1521 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1522 1523 if (!ocelot->bridge_mask) 1524 ocelot->hw_bridge_dev = NULL; 1525 1526 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1527 ocelot_port->vlan_aware = 0; 1528 ocelot_port->pvid = 0; 1529 ocelot_port->vid = 0; 1530 } 1531 1532 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1533 { 1534 int i, port, lag; 1535 1536 /* Reset destination and aggregation PGIDS */ 1537 for (port = 0; port < ocelot->num_phys_ports; port++) 1538 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1539 1540 for (i = PGID_AGGR; i < PGID_SRC; i++) 1541 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1542 ANA_PGID_PGID, i); 1543 1544 /* Now, set PGIDs for each LAG */ 1545 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1546 unsigned long bond_mask; 1547 int aggr_count = 0; 1548 u8 aggr_idx[16]; 1549 1550 bond_mask = ocelot->lags[lag]; 1551 if (!bond_mask) 1552 continue; 1553 1554 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1555 // Destination mask 1556 ocelot_write_rix(ocelot, bond_mask, 1557 ANA_PGID_PGID, port); 1558 aggr_idx[aggr_count] = port; 1559 aggr_count++; 1560 } 1561 1562 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1563 u32 ac; 1564 1565 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1566 ac &= ~bond_mask; 1567 ac |= BIT(aggr_idx[i % aggr_count]); 1568 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1569 } 1570 } 1571 } 1572 1573 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1574 { 1575 unsigned long bond_mask = ocelot->lags[lag]; 1576 unsigned int p; 1577 1578 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1579 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1580 1581 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1582 1583 /* Use lag port as logical port for port i */ 1584 ocelot_write_gix(ocelot, port_cfg | 1585 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1586 ANA_PORT_PORT_CFG, p); 1587 } 1588 } 1589 1590 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1591 struct net_device *bond) 1592 { 1593 struct ocelot *ocelot = ocelot_port->ocelot; 1594 int p = ocelot_port->chip_port; 1595 int lag, lp; 1596 struct net_device *ndev; 1597 u32 bond_mask = 0; 1598 1599 rcu_read_lock(); 1600 for_each_netdev_in_bond_rcu(bond, ndev) { 1601 struct ocelot_port *port = netdev_priv(ndev); 1602 1603 bond_mask |= BIT(port->chip_port); 1604 } 1605 rcu_read_unlock(); 1606 1607 lp = __ffs(bond_mask); 1608 1609 /* If the new port is the lowest one, use it as the logical port from 1610 * now on 1611 */ 1612 if (p == lp) { 1613 lag = p; 1614 ocelot->lags[p] = bond_mask; 1615 bond_mask &= ~BIT(p); 1616 if (bond_mask) { 1617 lp = __ffs(bond_mask); 1618 ocelot->lags[lp] = 0; 1619 } 1620 } else { 1621 lag = lp; 1622 ocelot->lags[lp] |= BIT(p); 1623 } 1624 1625 ocelot_setup_lag(ocelot, lag); 1626 ocelot_set_aggr_pgids(ocelot); 1627 1628 return 0; 1629 } 1630 1631 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1632 struct net_device *bond) 1633 { 1634 struct ocelot *ocelot = ocelot_port->ocelot; 1635 int p = ocelot_port->chip_port; 1636 u32 port_cfg; 1637 int i; 1638 1639 /* Remove port from any lag */ 1640 for (i = 0; i < ocelot->num_phys_ports; i++) 1641 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1642 1643 /* if it was the logical port of the lag, move the lag config to the 1644 * next port 1645 */ 1646 if (ocelot->lags[p]) { 1647 int n = __ffs(ocelot->lags[p]); 1648 1649 ocelot->lags[n] = ocelot->lags[p]; 1650 ocelot->lags[p] = 0; 1651 1652 ocelot_setup_lag(ocelot, n); 1653 } 1654 1655 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1656 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1657 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1658 ANA_PORT_PORT_CFG, p); 1659 1660 ocelot_set_aggr_pgids(ocelot); 1661 } 1662 1663 /* Checks if the net_device instance given to us originate from our driver. */ 1664 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1665 { 1666 return dev->netdev_ops == &ocelot_port_netdev_ops; 1667 } 1668 1669 static int ocelot_netdevice_port_event(struct net_device *dev, 1670 unsigned long event, 1671 struct netdev_notifier_changeupper_info *info) 1672 { 1673 struct ocelot_port *ocelot_port = netdev_priv(dev); 1674 int err = 0; 1675 1676 if (!ocelot_netdevice_dev_check(dev)) 1677 return 0; 1678 1679 switch (event) { 1680 case NETDEV_CHANGEUPPER: 1681 if (netif_is_bridge_master(info->upper_dev)) { 1682 if (info->linking) 1683 err = ocelot_port_bridge_join(ocelot_port, 1684 info->upper_dev); 1685 else 1686 ocelot_port_bridge_leave(ocelot_port, 1687 info->upper_dev); 1688 1689 ocelot_vlan_port_apply(ocelot_port->ocelot, 1690 ocelot_port); 1691 } 1692 if (netif_is_lag_master(info->upper_dev)) { 1693 if (info->linking) 1694 err = ocelot_port_lag_join(ocelot_port, 1695 info->upper_dev); 1696 else 1697 ocelot_port_lag_leave(ocelot_port, 1698 info->upper_dev); 1699 } 1700 break; 1701 default: 1702 break; 1703 } 1704 1705 return err; 1706 } 1707 1708 static int ocelot_netdevice_event(struct notifier_block *unused, 1709 unsigned long event, void *ptr) 1710 { 1711 struct netdev_notifier_changeupper_info *info = ptr; 1712 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1713 int ret = 0; 1714 1715 if (event == NETDEV_PRECHANGEUPPER && 1716 netif_is_lag_master(info->upper_dev)) { 1717 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1718 struct netlink_ext_ack *extack; 1719 1720 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1721 extack = netdev_notifier_info_to_extack(&info->info); 1722 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1723 1724 ret = -EINVAL; 1725 goto notify; 1726 } 1727 } 1728 1729 if (netif_is_lag_master(dev)) { 1730 struct net_device *slave; 1731 struct list_head *iter; 1732 1733 netdev_for_each_lower_dev(dev, slave, iter) { 1734 ret = ocelot_netdevice_port_event(slave, event, info); 1735 if (ret) 1736 goto notify; 1737 } 1738 } else { 1739 ret = ocelot_netdevice_port_event(dev, event, info); 1740 } 1741 1742 notify: 1743 return notifier_from_errno(ret); 1744 } 1745 1746 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1747 .notifier_call = ocelot_netdevice_event, 1748 }; 1749 EXPORT_SYMBOL(ocelot_netdevice_nb); 1750 1751 static int ocelot_switchdev_event(struct notifier_block *unused, 1752 unsigned long event, void *ptr) 1753 { 1754 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1755 int err; 1756 1757 switch (event) { 1758 case SWITCHDEV_PORT_ATTR_SET: 1759 err = switchdev_handle_port_attr_set(dev, ptr, 1760 ocelot_netdevice_dev_check, 1761 ocelot_port_attr_set); 1762 return notifier_from_errno(err); 1763 } 1764 1765 return NOTIFY_DONE; 1766 } 1767 1768 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1769 .notifier_call = ocelot_switchdev_event, 1770 }; 1771 EXPORT_SYMBOL(ocelot_switchdev_nb); 1772 1773 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1774 unsigned long event, void *ptr) 1775 { 1776 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1777 int err; 1778 1779 switch (event) { 1780 /* Blocking events. */ 1781 case SWITCHDEV_PORT_OBJ_ADD: 1782 err = switchdev_handle_port_obj_add(dev, ptr, 1783 ocelot_netdevice_dev_check, 1784 ocelot_port_obj_add); 1785 return notifier_from_errno(err); 1786 case SWITCHDEV_PORT_OBJ_DEL: 1787 err = switchdev_handle_port_obj_del(dev, ptr, 1788 ocelot_netdevice_dev_check, 1789 ocelot_port_obj_del); 1790 return notifier_from_errno(err); 1791 case SWITCHDEV_PORT_ATTR_SET: 1792 err = switchdev_handle_port_attr_set(dev, ptr, 1793 ocelot_netdevice_dev_check, 1794 ocelot_port_attr_set); 1795 return notifier_from_errno(err); 1796 } 1797 1798 return NOTIFY_DONE; 1799 } 1800 1801 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1802 .notifier_call = ocelot_switchdev_blocking_event, 1803 }; 1804 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1805 1806 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts) 1807 { 1808 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1809 unsigned long flags; 1810 time64_t s; 1811 u32 val; 1812 s64 ns; 1813 1814 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1815 1816 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1817 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1818 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 1819 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1820 1821 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; 1822 s <<= 32; 1823 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1824 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1825 1826 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1827 1828 /* Deal with negative values */ 1829 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) { 1830 s--; 1831 ns &= 0xf; 1832 ns += 999999984; 1833 } 1834 1835 set_normalized_timespec64(ts, s, ns); 1836 return 0; 1837 } 1838 EXPORT_SYMBOL(ocelot_ptp_gettime64); 1839 1840 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp, 1841 const struct timespec64 *ts) 1842 { 1843 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1844 unsigned long flags; 1845 u32 val; 1846 1847 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1848 1849 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1850 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1851 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1852 1853 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1854 1855 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB, 1856 TOD_ACC_PIN); 1857 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, 1858 TOD_ACC_PIN); 1859 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1860 1861 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1862 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1863 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); 1864 1865 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1866 1867 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1868 return 0; 1869 } 1870 1871 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 1872 { 1873 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 1874 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1875 unsigned long flags; 1876 u32 val; 1877 1878 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1879 1880 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1881 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1882 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1883 1884 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1885 1886 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1887 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN); 1888 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1889 1890 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1891 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1892 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); 1893 1894 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1895 1896 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1897 } else { 1898 /* Fall back using ocelot_ptp_settime64 which is not exact. */ 1899 struct timespec64 ts; 1900 u64 now; 1901 1902 ocelot_ptp_gettime64(ptp, &ts); 1903 1904 now = ktime_to_ns(timespec64_to_ktime(ts)); 1905 ts = ns_to_timespec64(now + delta); 1906 1907 ocelot_ptp_settime64(ptp, &ts); 1908 } 1909 return 0; 1910 } 1911 1912 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 1913 { 1914 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1915 u32 unit = 0, direction = 0; 1916 unsigned long flags; 1917 u64 adj = 0; 1918 1919 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1920 1921 if (!scaled_ppm) 1922 goto disable_adj; 1923 1924 if (scaled_ppm < 0) { 1925 direction = PTP_CFG_CLK_ADJ_CFG_DIR; 1926 scaled_ppm = -scaled_ppm; 1927 } 1928 1929 adj = PSEC_PER_SEC << 16; 1930 do_div(adj, scaled_ppm); 1931 do_div(adj, 1000); 1932 1933 /* If the adjustment value is too large, use ns instead */ 1934 if (adj >= (1L << 30)) { 1935 unit = PTP_CFG_CLK_ADJ_FREQ_NS; 1936 do_div(adj, 1000); 1937 } 1938 1939 /* Still too big */ 1940 if (adj >= (1L << 30)) 1941 goto disable_adj; 1942 1943 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ); 1944 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction, 1945 PTP_CLK_CFG_ADJ_CFG); 1946 1947 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1948 return 0; 1949 1950 disable_adj: 1951 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG); 1952 1953 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1954 return 0; 1955 } 1956 1957 static struct ptp_clock_info ocelot_ptp_clock_info = { 1958 .owner = THIS_MODULE, 1959 .name = "ocelot ptp", 1960 .max_adj = 0x7fffffff, 1961 .n_alarm = 0, 1962 .n_ext_ts = 0, 1963 .n_per_out = 0, 1964 .n_pins = 0, 1965 .pps = 0, 1966 .gettime64 = ocelot_ptp_gettime64, 1967 .settime64 = ocelot_ptp_settime64, 1968 .adjtime = ocelot_ptp_adjtime, 1969 .adjfine = ocelot_ptp_adjfine, 1970 }; 1971 1972 static int ocelot_init_timestamp(struct ocelot *ocelot) 1973 { 1974 ocelot->ptp_info = ocelot_ptp_clock_info; 1975 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev); 1976 if (IS_ERR(ocelot->ptp_clock)) 1977 return PTR_ERR(ocelot->ptp_clock); 1978 /* Check if PHC support is missing at the configuration level */ 1979 if (!ocelot->ptp_clock) 1980 return 0; 1981 1982 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG); 1983 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW); 1984 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH); 1985 1986 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); 1987 1988 /* There is no device reconfiguration, PTP Rx stamping is always 1989 * enabled. 1990 */ 1991 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1992 1993 return 0; 1994 } 1995 1996 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1997 void __iomem *regs, 1998 struct phy_device *phy) 1999 { 2000 struct ocelot_port *ocelot_port; 2001 struct net_device *dev; 2002 int err; 2003 2004 dev = alloc_etherdev(sizeof(struct ocelot_port)); 2005 if (!dev) 2006 return -ENOMEM; 2007 SET_NETDEV_DEV(dev, ocelot->dev); 2008 ocelot_port = netdev_priv(dev); 2009 ocelot_port->dev = dev; 2010 ocelot_port->ocelot = ocelot; 2011 ocelot_port->regs = regs; 2012 ocelot_port->chip_port = port; 2013 ocelot_port->phy = phy; 2014 ocelot->ports[port] = ocelot_port; 2015 2016 dev->netdev_ops = &ocelot_port_netdev_ops; 2017 dev->ethtool_ops = &ocelot_ethtool_ops; 2018 2019 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2020 NETIF_F_HW_TC; 2021 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2022 2023 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2024 dev->dev_addr[ETH_ALEN - 1] += port; 2025 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2026 ENTRYTYPE_LOCKED); 2027 2028 INIT_LIST_HEAD(&ocelot_port->skbs); 2029 2030 err = register_netdev(dev); 2031 if (err) { 2032 dev_err(ocelot->dev, "register_netdev failed\n"); 2033 goto err_register_netdev; 2034 } 2035 2036 /* Basic L2 initialization */ 2037 ocelot_vlan_port_apply(ocelot, ocelot_port); 2038 2039 /* Enable vcap lookups */ 2040 ocelot_vcap_enable(ocelot, ocelot_port); 2041 2042 return 0; 2043 2044 err_register_netdev: 2045 free_netdev(dev); 2046 return err; 2047 } 2048 EXPORT_SYMBOL(ocelot_probe_port); 2049 2050 int ocelot_init(struct ocelot *ocelot) 2051 { 2052 u32 port; 2053 int i, ret, cpu = ocelot->num_phys_ports; 2054 char queue_name[32]; 2055 2056 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2057 sizeof(u32), GFP_KERNEL); 2058 if (!ocelot->lags) 2059 return -ENOMEM; 2060 2061 ocelot->stats = devm_kcalloc(ocelot->dev, 2062 ocelot->num_phys_ports * ocelot->num_stats, 2063 sizeof(u64), GFP_KERNEL); 2064 if (!ocelot->stats) 2065 return -ENOMEM; 2066 2067 mutex_init(&ocelot->stats_lock); 2068 mutex_init(&ocelot->ptp_lock); 2069 spin_lock_init(&ocelot->ptp_clock_lock); 2070 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2071 dev_name(ocelot->dev)); 2072 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2073 if (!ocelot->stats_queue) 2074 return -ENOMEM; 2075 2076 ocelot_mact_init(ocelot); 2077 ocelot_vlan_init(ocelot); 2078 ocelot_ace_init(ocelot); 2079 2080 for (port = 0; port < ocelot->num_phys_ports; port++) { 2081 /* Clear all counters (5 groups) */ 2082 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2083 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2084 SYS_STAT_CFG); 2085 } 2086 2087 /* Only use S-Tag */ 2088 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2089 2090 /* Aggregation mode */ 2091 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2092 ANA_AGGR_CFG_AC_DMAC_ENA | 2093 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2094 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2095 2096 /* Set MAC age time to default value. The entry is aged after 2097 * 2*AGE_PERIOD 2098 */ 2099 ocelot_write(ocelot, 2100 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2101 ANA_AUTOAGE); 2102 2103 /* Disable learning for frames discarded by VLAN ingress filtering */ 2104 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2105 2106 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2107 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2108 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2109 2110 /* Setup flooding PGIDs */ 2111 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2112 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2113 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2114 ANA_FLOODING, 0); 2115 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2116 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2117 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2118 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2119 ANA_FLOODING_IPMC); 2120 2121 for (port = 0; port < ocelot->num_phys_ports; port++) { 2122 /* Transmit the frame to the local port. */ 2123 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2124 /* Do not forward BPDU frames to the front ports. */ 2125 ocelot_write_gix(ocelot, 2126 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2127 ANA_PORT_CPU_FWD_BPDU_CFG, 2128 port); 2129 /* Ensure bridging is disabled */ 2130 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2131 } 2132 2133 /* Configure and enable the CPU port. */ 2134 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2135 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2136 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2137 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2138 ANA_PORT_PORT_CFG, cpu); 2139 2140 /* Allow broadcast MAC frames. */ 2141 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2142 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2143 2144 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2145 } 2146 ocelot_write_rix(ocelot, 2147 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2148 ANA_PGID_PGID, PGID_MC); 2149 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2150 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2151 2152 /* CPU port Injection/Extraction configuration */ 2153 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2154 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2155 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2156 QSYS_SWITCH_PORT_MODE, cpu); 2157 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 2158 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 2159 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2160 * registers endianness. 2161 */ 2162 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2163 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2164 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2165 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2166 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2167 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2168 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2169 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2170 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2171 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2172 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2173 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2174 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2175 for (i = 0; i < 16; i++) 2176 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2177 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2178 ANA_CPUQ_8021_CFG, i); 2179 2180 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2181 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2182 OCELOT_STATS_CHECK_DELAY); 2183 2184 if (ocelot->ptp) { 2185 ret = ocelot_init_timestamp(ocelot); 2186 if (ret) { 2187 dev_err(ocelot->dev, 2188 "Timestamp initialization failed\n"); 2189 return ret; 2190 } 2191 } 2192 2193 return 0; 2194 } 2195 EXPORT_SYMBOL(ocelot_init); 2196 2197 void ocelot_deinit(struct ocelot *ocelot) 2198 { 2199 struct list_head *pos, *tmp; 2200 struct ocelot_port *port; 2201 struct ocelot_skb *entry; 2202 int i; 2203 2204 cancel_delayed_work(&ocelot->stats_work); 2205 destroy_workqueue(ocelot->stats_queue); 2206 mutex_destroy(&ocelot->stats_lock); 2207 ocelot_ace_deinit(); 2208 2209 for (i = 0; i < ocelot->num_phys_ports; i++) { 2210 port = ocelot->ports[i]; 2211 2212 list_for_each_safe(pos, tmp, &port->skbs) { 2213 entry = list_entry(pos, struct ocelot_skb, head); 2214 2215 list_del(pos); 2216 dev_kfree_skb_any(entry->skb); 2217 kfree(entry); 2218 } 2219 } 2220 } 2221 EXPORT_SYMBOL(ocelot_deinit); 2222 2223 MODULE_LICENSE("Dual MIT/GPL"); 2224