1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <net/arp.h> 19 #include <net/netevent.h> 20 #include <net/rtnetlink.h> 21 #include <net/switchdev.h> 22 23 #include "ocelot.h" 24 25 /* MAC table entry types. 26 * ENTRYTYPE_NORMAL is subject to aging. 27 * ENTRYTYPE_LOCKED is not subject to aging. 28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 30 */ 31 enum macaccess_entry_type { 32 ENTRYTYPE_NORMAL = 0, 33 ENTRYTYPE_LOCKED, 34 ENTRYTYPE_MACv4, 35 ENTRYTYPE_MACv6, 36 }; 37 38 struct ocelot_mact_entry { 39 u8 mac[ETH_ALEN]; 40 u16 vid; 41 enum macaccess_entry_type type; 42 }; 43 44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 45 { 46 unsigned int val, timeout = 10; 47 48 /* Wait for the issued mac table command to be completed, or timeout. 49 * When the command read from ANA_TABLES_MACACCESS is 50 * MACACCESS_CMD_IDLE, the issued command completed successfully. 51 */ 52 do { 53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M; 55 } while (val != MACACCESS_CMD_IDLE && timeout--); 56 57 if (!timeout) 58 return -ETIMEDOUT; 59 60 return 0; 61 } 62 63 static void ocelot_mact_select(struct ocelot *ocelot, 64 const unsigned char mac[ETH_ALEN], 65 unsigned int vid) 66 { 67 u32 macl = 0, mach = 0; 68 69 /* Set the MAC address to handle and the vlan associated in a format 70 * understood by the hardware. 71 */ 72 mach |= vid << 16; 73 mach |= mac[0] << 8; 74 mach |= mac[1] << 0; 75 macl |= mac[2] << 24; 76 macl |= mac[3] << 16; 77 macl |= mac[4] << 8; 78 macl |= mac[5] << 0; 79 80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 82 83 } 84 85 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 86 const unsigned char mac[ETH_ALEN], 87 unsigned int vid, 88 enum macaccess_entry_type type) 89 { 90 ocelot_mact_select(ocelot, mac, vid); 91 92 /* Issue a write command */ 93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 94 ANA_TABLES_MACACCESS_DEST_IDX(port) | 95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 97 ANA_TABLES_MACACCESS); 98 99 return ocelot_mact_wait_for_completion(ocelot); 100 } 101 102 static int ocelot_mact_forget(struct ocelot *ocelot, 103 const unsigned char mac[ETH_ALEN], 104 unsigned int vid) 105 { 106 ocelot_mact_select(ocelot, mac, vid); 107 108 /* Issue a forget command */ 109 ocelot_write(ocelot, 110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 111 ANA_TABLES_MACACCESS); 112 113 return ocelot_mact_wait_for_completion(ocelot); 114 } 115 116 static void ocelot_mact_init(struct ocelot *ocelot) 117 { 118 /* Configure the learning mode entries attributes: 119 * - Do not copy the frame to the CPU extraction queues. 120 * - Use the vlan and mac_cpoy for dmac lookup. 121 */ 122 ocelot_rmw(ocelot, 0, 123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 124 | ANA_AGENCTRL_LEARN_FWD_KILL 125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 126 ANA_AGENCTRL); 127 128 /* Clear the MAC table */ 129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 130 } 131 132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 133 { 134 unsigned int val, timeout = 10; 135 136 /* Wait for the issued mac table command to be completed, or timeout. 137 * When the command read from ANA_TABLES_MACACCESS is 138 * MACACCESS_CMD_IDLE, the issued command completed successfully. 139 */ 140 do { 141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M; 143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--); 144 145 if (!timeout) 146 return -ETIMEDOUT; 147 148 return 0; 149 } 150 151 static void ocelot_vlan_init(struct ocelot *ocelot) 152 { 153 /* Clear VLAN table, by default all ports are members of all VLANs */ 154 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 155 ANA_TABLES_VLANACCESS); 156 ocelot_vlant_wait_for_completion(ocelot); 157 } 158 159 /* Watermark encode 160 * Bit 8: Unit; 0:1, 1:16 161 * Bit 7-0: Value to be multiplied with unit 162 */ 163 static u16 ocelot_wm_enc(u16 value) 164 { 165 if (value >= BIT(8)) 166 return BIT(8) | (value / 16); 167 168 return value; 169 } 170 171 static void ocelot_port_adjust_link(struct net_device *dev) 172 { 173 struct ocelot_port *port = netdev_priv(dev); 174 struct ocelot *ocelot = port->ocelot; 175 u8 p = port->chip_port; 176 int speed, atop_wm, mode = 0; 177 178 switch (dev->phydev->speed) { 179 case SPEED_10: 180 speed = OCELOT_SPEED_10; 181 break; 182 case SPEED_100: 183 speed = OCELOT_SPEED_100; 184 break; 185 case SPEED_1000: 186 speed = OCELOT_SPEED_1000; 187 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 188 break; 189 case SPEED_2500: 190 speed = OCELOT_SPEED_2500; 191 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 192 break; 193 default: 194 netdev_err(dev, "Unsupported PHY speed: %d\n", 195 dev->phydev->speed); 196 return; 197 } 198 199 phy_print_status(dev->phydev); 200 201 if (!dev->phydev->link) 202 return; 203 204 /* Only full duplex supported for now */ 205 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 206 mode, DEV_MAC_MODE_CFG); 207 208 /* Set MAC IFG Gaps 209 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 210 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 211 */ 212 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 213 214 /* Load seed (0) and set MAC HDX late collision */ 215 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 216 DEV_MAC_HDX_CFG_SEED_LOAD, 217 DEV_MAC_HDX_CFG); 218 mdelay(1); 219 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 220 DEV_MAC_HDX_CFG); 221 222 /* Disable HDX fast control */ 223 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 224 225 /* SGMII only for now */ 226 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 227 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 228 229 /* Enable PCS */ 230 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 231 232 /* No aneg on SGMII */ 233 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 234 235 /* No loopback */ 236 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 237 238 /* Set Max Length and maximum tags allowed */ 239 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 240 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 241 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 242 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 243 DEV_MAC_TAGS_CFG); 244 245 /* Enable MAC module */ 246 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 247 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 248 249 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 250 * reset */ 251 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 252 DEV_CLOCK_CFG); 253 254 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 255 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 256 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 257 258 /* No PFC */ 259 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 260 ANA_PFC_PFC_CFG, p); 261 262 /* Set Pause WM hysteresis 263 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 264 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 265 */ 266 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 267 SYS_PAUSE_CFG_PAUSE_STOP(101) | 268 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 269 270 /* Core: Enable port for frame transfer */ 271 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 272 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 273 QSYS_SWITCH_PORT_MODE_PORT_ENA, 274 QSYS_SWITCH_PORT_MODE, p); 275 276 /* Flow control */ 277 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 278 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 279 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 280 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 281 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 282 SYS_MAC_FC_CFG, p); 283 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 284 285 /* Tail dropping watermark */ 286 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 287 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 288 SYS_ATOP, p); 289 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 290 } 291 292 static int ocelot_port_open(struct net_device *dev) 293 { 294 struct ocelot_port *port = netdev_priv(dev); 295 struct ocelot *ocelot = port->ocelot; 296 int err; 297 298 /* Enable receiving frames on the port, and activate auto-learning of 299 * MAC addresses. 300 */ 301 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 302 ANA_PORT_PORT_CFG_RECV_ENA | 303 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 304 ANA_PORT_PORT_CFG, port->chip_port); 305 306 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 307 PHY_INTERFACE_MODE_NA); 308 if (err) { 309 netdev_err(dev, "Could not attach to PHY\n"); 310 return err; 311 } 312 313 dev->phydev = port->phy; 314 315 phy_attached_info(port->phy); 316 phy_start(port->phy); 317 return 0; 318 } 319 320 static int ocelot_port_stop(struct net_device *dev) 321 { 322 struct ocelot_port *port = netdev_priv(dev); 323 324 phy_disconnect(port->phy); 325 326 dev->phydev = NULL; 327 328 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 329 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 330 QSYS_SWITCH_PORT_MODE, port->chip_port); 331 return 0; 332 } 333 334 /* Generate the IFH for frame injection 335 * 336 * The IFH is a 128bit-value 337 * bit 127: bypass the analyzer processing 338 * bit 56-67: destination mask 339 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 340 * bit 20-27: cpu extraction queue mask 341 * bit 16: tag type 0: C-tag, 1: S-tag 342 * bit 0-11: VID 343 */ 344 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 345 { 346 ifh[0] = IFH_INJ_BYPASS; 347 ifh[1] = (0xf00 & info->port) >> 8; 348 ifh[2] = (0xff & info->port) << 24; 349 ifh[3] = (info->tag_type << 16) | info->vid; 350 351 return 0; 352 } 353 354 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 355 { 356 struct ocelot_port *port = netdev_priv(dev); 357 struct ocelot *ocelot = port->ocelot; 358 u32 val, ifh[IFH_LEN]; 359 struct frame_info info = {}; 360 u8 grp = 0; /* Send everything on CPU group 0 */ 361 unsigned int i, count, last; 362 363 val = ocelot_read(ocelot, QS_INJ_STATUS); 364 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 365 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 366 return NETDEV_TX_BUSY; 367 368 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 369 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 370 371 info.port = BIT(port->chip_port); 372 info.tag_type = IFH_TAG_TYPE_C; 373 info.vid = skb_vlan_tag_get(skb); 374 ocelot_gen_ifh(ifh, &info); 375 376 for (i = 0; i < IFH_LEN; i++) 377 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 378 QS_INJ_WR, grp); 379 380 count = (skb->len + 3) / 4; 381 last = skb->len % 4; 382 for (i = 0; i < count; i++) { 383 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 384 } 385 386 /* Add padding */ 387 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 388 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 389 i++; 390 } 391 392 /* Indicate EOF and valid bytes in last word */ 393 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 394 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 395 QS_INJ_CTRL_EOF, 396 QS_INJ_CTRL, grp); 397 398 /* Add dummy CRC */ 399 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 400 skb_tx_timestamp(skb); 401 402 dev->stats.tx_packets++; 403 dev->stats.tx_bytes += skb->len; 404 dev_kfree_skb_any(skb); 405 406 return NETDEV_TX_OK; 407 } 408 409 static void ocelot_mact_mc_reset(struct ocelot_port *port) 410 { 411 struct ocelot *ocelot = port->ocelot; 412 struct netdev_hw_addr *ha, *n; 413 414 /* Free and forget all the MAC addresses stored in the port private mc 415 * list. These are mc addresses that were previously added by calling 416 * ocelot_mact_mc_add(). 417 */ 418 list_for_each_entry_safe(ha, n, &port->mc, list) { 419 ocelot_mact_forget(ocelot, ha->addr, port->pvid); 420 list_del(&ha->list); 421 kfree(ha); 422 } 423 } 424 425 static int ocelot_mact_mc_add(struct ocelot_port *port, 426 struct netdev_hw_addr *hw_addr) 427 { 428 struct ocelot *ocelot = port->ocelot; 429 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL); 430 431 if (!ha) 432 return -ENOMEM; 433 434 memcpy(ha, hw_addr, sizeof(*ha)); 435 list_add_tail(&ha->list, &port->mc); 436 437 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid, 438 ENTRYTYPE_LOCKED); 439 440 return 0; 441 } 442 443 static void ocelot_set_rx_mode(struct net_device *dev) 444 { 445 struct ocelot_port *port = netdev_priv(dev); 446 struct ocelot *ocelot = port->ocelot; 447 struct netdev_hw_addr *ha; 448 int i; 449 u32 val; 450 451 /* This doesn't handle promiscuous mode because the bridge core is 452 * setting IFF_PROMISC on all slave interfaces and all frames would be 453 * forwarded to the CPU port. 454 */ 455 val = GENMASK(ocelot->num_phys_ports - 1, 0); 456 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 457 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 458 459 /* Handle the device multicast addresses. First remove all the 460 * previously installed addresses and then add the latest ones to the 461 * mac table. 462 */ 463 ocelot_mact_mc_reset(port); 464 netdev_for_each_mc_addr(ha, dev) 465 ocelot_mact_mc_add(port, ha); 466 } 467 468 static int ocelot_port_get_phys_port_name(struct net_device *dev, 469 char *buf, size_t len) 470 { 471 struct ocelot_port *port = netdev_priv(dev); 472 int ret; 473 474 ret = snprintf(buf, len, "p%d", port->chip_port); 475 if (ret >= len) 476 return -EINVAL; 477 478 return 0; 479 } 480 481 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 482 { 483 struct ocelot_port *port = netdev_priv(dev); 484 struct ocelot *ocelot = port->ocelot; 485 const struct sockaddr *addr = p; 486 487 /* Learn the new net device MAC address in the mac table. */ 488 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 489 ENTRYTYPE_LOCKED); 490 /* Then forget the previous one. */ 491 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 492 493 ether_addr_copy(dev->dev_addr, addr->sa_data); 494 return 0; 495 } 496 497 static void ocelot_get_stats64(struct net_device *dev, 498 struct rtnl_link_stats64 *stats) 499 { 500 struct ocelot_port *port = netdev_priv(dev); 501 struct ocelot *ocelot = port->ocelot; 502 503 /* Configure the port to read the stats from */ 504 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 505 SYS_STAT_CFG); 506 507 /* Get Rx stats */ 508 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 509 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 510 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 511 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 512 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 513 ocelot_read(ocelot, SYS_COUNT_RX_64) + 514 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 515 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 516 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 517 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 518 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 519 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 520 stats->rx_dropped = dev->stats.rx_dropped; 521 522 /* Get Tx stats */ 523 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 524 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 525 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 526 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 527 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 528 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 529 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 530 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 531 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 532 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 533 } 534 535 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 536 struct net_device *dev, const unsigned char *addr, 537 u16 vid, u16 flags) 538 { 539 struct ocelot_port *port = netdev_priv(dev); 540 struct ocelot *ocelot = port->ocelot; 541 542 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 543 ENTRYTYPE_NORMAL); 544 } 545 546 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 547 struct net_device *dev, 548 const unsigned char *addr, u16 vid) 549 { 550 struct ocelot_port *port = netdev_priv(dev); 551 struct ocelot *ocelot = port->ocelot; 552 553 return ocelot_mact_forget(ocelot, addr, vid); 554 } 555 556 struct ocelot_dump_ctx { 557 struct net_device *dev; 558 struct sk_buff *skb; 559 struct netlink_callback *cb; 560 int idx; 561 }; 562 563 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 564 struct ocelot_dump_ctx *dump) 565 { 566 u32 portid = NETLINK_CB(dump->cb->skb).portid; 567 u32 seq = dump->cb->nlh->nlmsg_seq; 568 struct nlmsghdr *nlh; 569 struct ndmsg *ndm; 570 571 if (dump->idx < dump->cb->args[2]) 572 goto skip; 573 574 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 575 sizeof(*ndm), NLM_F_MULTI); 576 if (!nlh) 577 return -EMSGSIZE; 578 579 ndm = nlmsg_data(nlh); 580 ndm->ndm_family = AF_BRIDGE; 581 ndm->ndm_pad1 = 0; 582 ndm->ndm_pad2 = 0; 583 ndm->ndm_flags = NTF_SELF; 584 ndm->ndm_type = 0; 585 ndm->ndm_ifindex = dump->dev->ifindex; 586 ndm->ndm_state = NUD_REACHABLE; 587 588 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 589 goto nla_put_failure; 590 591 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 592 goto nla_put_failure; 593 594 nlmsg_end(dump->skb, nlh); 595 596 skip: 597 dump->idx++; 598 return 0; 599 600 nla_put_failure: 601 nlmsg_cancel(dump->skb, nlh); 602 return -EMSGSIZE; 603 } 604 605 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 606 struct ocelot_mact_entry *entry) 607 { 608 struct ocelot *ocelot = port->ocelot; 609 char mac[ETH_ALEN]; 610 u32 val, dst, macl, mach; 611 612 /* Set row and column to read from */ 613 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 614 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 615 616 /* Issue a read command */ 617 ocelot_write(ocelot, 618 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 619 ANA_TABLES_MACACCESS); 620 621 if (ocelot_mact_wait_for_completion(ocelot)) 622 return -ETIMEDOUT; 623 624 /* Read the entry flags */ 625 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 626 if (!(val & ANA_TABLES_MACACCESS_VALID)) 627 return -EINVAL; 628 629 /* If the entry read has another port configured as its destination, 630 * do not report it. 631 */ 632 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 633 if (dst != port->chip_port) 634 return -EINVAL; 635 636 /* Get the entry's MAC address and VLAN id */ 637 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 638 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 639 640 mac[0] = (mach >> 8) & 0xff; 641 mac[1] = (mach >> 0) & 0xff; 642 mac[2] = (macl >> 24) & 0xff; 643 mac[3] = (macl >> 16) & 0xff; 644 mac[4] = (macl >> 8) & 0xff; 645 mac[5] = (macl >> 0) & 0xff; 646 647 entry->vid = (mach >> 16) & 0xfff; 648 ether_addr_copy(entry->mac, mac); 649 650 return 0; 651 } 652 653 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 654 struct net_device *dev, 655 struct net_device *filter_dev, int *idx) 656 { 657 struct ocelot_port *port = netdev_priv(dev); 658 int i, j, ret = 0; 659 struct ocelot_dump_ctx dump = { 660 .dev = dev, 661 .skb = skb, 662 .cb = cb, 663 .idx = *idx, 664 }; 665 666 struct ocelot_mact_entry entry; 667 668 /* Loop through all the mac tables entries. There are 1024 rows of 4 669 * entries. 670 */ 671 for (i = 0; i < 1024; i++) { 672 for (j = 0; j < 4; j++) { 673 ret = ocelot_mact_read(port, i, j, &entry); 674 /* If the entry is invalid (wrong port, invalid...), 675 * skip it. 676 */ 677 if (ret == -EINVAL) 678 continue; 679 else if (ret) 680 goto end; 681 682 ret = ocelot_fdb_do_dump(&entry, &dump); 683 if (ret) 684 goto end; 685 } 686 } 687 688 end: 689 *idx = dump.idx; 690 return ret; 691 } 692 693 static const struct net_device_ops ocelot_port_netdev_ops = { 694 .ndo_open = ocelot_port_open, 695 .ndo_stop = ocelot_port_stop, 696 .ndo_start_xmit = ocelot_port_xmit, 697 .ndo_set_rx_mode = ocelot_set_rx_mode, 698 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 699 .ndo_set_mac_address = ocelot_port_set_mac_address, 700 .ndo_get_stats64 = ocelot_get_stats64, 701 .ndo_fdb_add = ocelot_fdb_add, 702 .ndo_fdb_del = ocelot_fdb_del, 703 .ndo_fdb_dump = ocelot_fdb_dump, 704 }; 705 706 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 707 { 708 struct ocelot_port *port = netdev_priv(netdev); 709 struct ocelot *ocelot = port->ocelot; 710 int i; 711 712 if (sset != ETH_SS_STATS) 713 return; 714 715 for (i = 0; i < ocelot->num_stats; i++) 716 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 717 ETH_GSTRING_LEN); 718 } 719 720 static void ocelot_check_stats(struct work_struct *work) 721 { 722 struct delayed_work *del_work = to_delayed_work(work); 723 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work); 724 int i, j; 725 726 mutex_lock(&ocelot->stats_lock); 727 728 for (i = 0; i < ocelot->num_phys_ports; i++) { 729 /* Configure the port to read the stats from */ 730 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 731 732 for (j = 0; j < ocelot->num_stats; j++) { 733 u32 val; 734 unsigned int idx = i * ocelot->num_stats + j; 735 736 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 737 ocelot->stats_layout[j].offset); 738 739 if (val < (ocelot->stats[idx] & U32_MAX)) 740 ocelot->stats[idx] += (u64)1 << 32; 741 742 ocelot->stats[idx] = (ocelot->stats[idx] & 743 ~(u64)U32_MAX) + val; 744 } 745 } 746 747 cancel_delayed_work(&ocelot->stats_work); 748 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 749 OCELOT_STATS_CHECK_DELAY); 750 751 mutex_unlock(&ocelot->stats_lock); 752 } 753 754 static void ocelot_get_ethtool_stats(struct net_device *dev, 755 struct ethtool_stats *stats, u64 *data) 756 { 757 struct ocelot_port *port = netdev_priv(dev); 758 struct ocelot *ocelot = port->ocelot; 759 int i; 760 761 /* check and update now */ 762 ocelot_check_stats(&ocelot->stats_work.work); 763 764 /* Copy all counters */ 765 for (i = 0; i < ocelot->num_stats; i++) 766 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 767 } 768 769 static int ocelot_get_sset_count(struct net_device *dev, int sset) 770 { 771 struct ocelot_port *port = netdev_priv(dev); 772 struct ocelot *ocelot = port->ocelot; 773 774 if (sset != ETH_SS_STATS) 775 return -EOPNOTSUPP; 776 return ocelot->num_stats; 777 } 778 779 static const struct ethtool_ops ocelot_ethtool_ops = { 780 .get_strings = ocelot_get_strings, 781 .get_ethtool_stats = ocelot_get_ethtool_stats, 782 .get_sset_count = ocelot_get_sset_count, 783 }; 784 785 static int ocelot_port_attr_get(struct net_device *dev, 786 struct switchdev_attr *attr) 787 { 788 struct ocelot_port *ocelot_port = netdev_priv(dev); 789 struct ocelot *ocelot = ocelot_port->ocelot; 790 791 switch (attr->id) { 792 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 793 attr->u.ppid.id_len = sizeof(ocelot->base_mac); 794 memcpy(&attr->u.ppid.id, &ocelot->base_mac, 795 attr->u.ppid.id_len); 796 break; 797 default: 798 return -EOPNOTSUPP; 799 } 800 801 return 0; 802 } 803 804 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 805 struct switchdev_trans *trans, 806 u8 state) 807 { 808 struct ocelot *ocelot = ocelot_port->ocelot; 809 u32 port_cfg; 810 int port, i; 811 812 if (switchdev_trans_ph_prepare(trans)) 813 return 0; 814 815 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 816 return 0; 817 818 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 819 ocelot_port->chip_port); 820 821 switch (state) { 822 case BR_STATE_FORWARDING: 823 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 824 /* Fallthrough */ 825 case BR_STATE_LEARNING: 826 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 827 break; 828 829 default: 830 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 831 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 832 break; 833 } 834 835 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 836 ocelot_port->chip_port); 837 838 /* Apply FWD mask. The loop is needed to add/remove the current port as 839 * a source for the other ports. 840 */ 841 for (port = 0; port < ocelot->num_phys_ports; port++) { 842 if (ocelot->bridge_fwd_mask & BIT(port)) { 843 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 844 845 for (i = 0; i < ocelot->num_phys_ports; i++) { 846 unsigned long bond_mask = ocelot->lags[i]; 847 848 if (!bond_mask) 849 continue; 850 851 if (bond_mask & BIT(port)) { 852 mask &= ~bond_mask; 853 break; 854 } 855 } 856 857 ocelot_write_rix(ocelot, 858 BIT(ocelot->num_phys_ports) | mask, 859 ANA_PGID_PGID, PGID_SRC + port); 860 } else { 861 /* Only the CPU port, this is compatible with link 862 * aggregation. 863 */ 864 ocelot_write_rix(ocelot, 865 BIT(ocelot->num_phys_ports), 866 ANA_PGID_PGID, PGID_SRC + port); 867 } 868 } 869 870 return 0; 871 } 872 873 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 874 unsigned long ageing_clock_t) 875 { 876 struct ocelot *ocelot = ocelot_port->ocelot; 877 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 878 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 879 880 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 881 ANA_AUTOAGE); 882 } 883 884 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 885 { 886 struct ocelot *ocelot = port->ocelot; 887 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 888 port->chip_port); 889 890 if (mc) 891 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 892 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 893 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 894 else 895 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 896 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 897 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 898 899 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 900 } 901 902 static int ocelot_port_attr_set(struct net_device *dev, 903 const struct switchdev_attr *attr, 904 struct switchdev_trans *trans) 905 { 906 struct ocelot_port *ocelot_port = netdev_priv(dev); 907 int err = 0; 908 909 switch (attr->id) { 910 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 911 ocelot_port_attr_stp_state_set(ocelot_port, trans, 912 attr->u.stp_state); 913 break; 914 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 915 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 916 break; 917 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 918 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 919 break; 920 default: 921 err = -EOPNOTSUPP; 922 break; 923 } 924 925 return err; 926 } 927 928 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 929 const unsigned char *addr, 930 u16 vid) 931 { 932 struct ocelot_multicast *mc; 933 934 list_for_each_entry(mc, &ocelot->multicast, list) { 935 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 936 return mc; 937 } 938 939 return NULL; 940 } 941 942 static int ocelot_port_obj_add_mdb(struct net_device *dev, 943 const struct switchdev_obj_port_mdb *mdb, 944 struct switchdev_trans *trans) 945 { 946 struct ocelot_port *port = netdev_priv(dev); 947 struct ocelot *ocelot = port->ocelot; 948 struct ocelot_multicast *mc; 949 unsigned char addr[ETH_ALEN]; 950 u16 vid = mdb->vid; 951 bool new = false; 952 953 if (!vid) 954 vid = 1; 955 956 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 957 if (!mc) { 958 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 959 if (!mc) 960 return -ENOMEM; 961 962 memcpy(mc->addr, mdb->addr, ETH_ALEN); 963 mc->vid = vid; 964 965 list_add_tail(&mc->list, &ocelot->multicast); 966 new = true; 967 } 968 969 memcpy(addr, mc->addr, ETH_ALEN); 970 addr[0] = 0; 971 972 if (!new) { 973 addr[2] = mc->ports << 0; 974 addr[1] = mc->ports << 8; 975 ocelot_mact_forget(ocelot, addr, vid); 976 } 977 978 mc->ports |= BIT(port->chip_port); 979 addr[2] = mc->ports << 0; 980 addr[1] = mc->ports << 8; 981 982 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 983 } 984 985 static int ocelot_port_obj_del_mdb(struct net_device *dev, 986 const struct switchdev_obj_port_mdb *mdb) 987 { 988 struct ocelot_port *port = netdev_priv(dev); 989 struct ocelot *ocelot = port->ocelot; 990 struct ocelot_multicast *mc; 991 unsigned char addr[ETH_ALEN]; 992 u16 vid = mdb->vid; 993 994 if (!vid) 995 vid = 1; 996 997 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 998 if (!mc) 999 return -ENOENT; 1000 1001 memcpy(addr, mc->addr, ETH_ALEN); 1002 addr[2] = mc->ports << 0; 1003 addr[1] = mc->ports << 8; 1004 addr[0] = 0; 1005 ocelot_mact_forget(ocelot, addr, vid); 1006 1007 mc->ports &= ~BIT(port->chip_port); 1008 if (!mc->ports) { 1009 list_del(&mc->list); 1010 devm_kfree(ocelot->dev, mc); 1011 return 0; 1012 } 1013 1014 addr[2] = mc->ports << 0; 1015 addr[1] = mc->ports << 8; 1016 1017 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1018 } 1019 1020 static int ocelot_port_obj_add(struct net_device *dev, 1021 const struct switchdev_obj *obj, 1022 struct switchdev_trans *trans) 1023 { 1024 int ret = 0; 1025 1026 switch (obj->id) { 1027 case SWITCHDEV_OBJ_ID_PORT_MDB: 1028 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1029 trans); 1030 break; 1031 default: 1032 return -EOPNOTSUPP; 1033 } 1034 1035 return ret; 1036 } 1037 1038 static int ocelot_port_obj_del(struct net_device *dev, 1039 const struct switchdev_obj *obj) 1040 { 1041 int ret = 0; 1042 1043 switch (obj->id) { 1044 case SWITCHDEV_OBJ_ID_PORT_MDB: 1045 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1046 break; 1047 default: 1048 return -EOPNOTSUPP; 1049 } 1050 1051 return ret; 1052 } 1053 1054 static const struct switchdev_ops ocelot_port_switchdev_ops = { 1055 .switchdev_port_attr_get = ocelot_port_attr_get, 1056 .switchdev_port_attr_set = ocelot_port_attr_set, 1057 .switchdev_port_obj_add = ocelot_port_obj_add, 1058 .switchdev_port_obj_del = ocelot_port_obj_del, 1059 }; 1060 1061 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1062 struct net_device *bridge) 1063 { 1064 struct ocelot *ocelot = ocelot_port->ocelot; 1065 1066 if (!ocelot->bridge_mask) { 1067 ocelot->hw_bridge_dev = bridge; 1068 } else { 1069 if (ocelot->hw_bridge_dev != bridge) 1070 /* This is adding the port to a second bridge, this is 1071 * unsupported */ 1072 return -ENODEV; 1073 } 1074 1075 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1076 1077 return 0; 1078 } 1079 1080 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1081 struct net_device *bridge) 1082 { 1083 struct ocelot *ocelot = ocelot_port->ocelot; 1084 1085 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1086 1087 if (!ocelot->bridge_mask) 1088 ocelot->hw_bridge_dev = NULL; 1089 } 1090 1091 /* Checks if the net_device instance given to us originate from our driver. */ 1092 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1093 { 1094 return dev->netdev_ops == &ocelot_port_netdev_ops; 1095 } 1096 1097 static int ocelot_netdevice_port_event(struct net_device *dev, 1098 unsigned long event, 1099 struct netdev_notifier_changeupper_info *info) 1100 { 1101 struct ocelot_port *ocelot_port = netdev_priv(dev); 1102 int err = 0; 1103 1104 if (!ocelot_netdevice_dev_check(dev)) 1105 return 0; 1106 1107 switch (event) { 1108 case NETDEV_CHANGEUPPER: 1109 if (netif_is_bridge_master(info->upper_dev)) { 1110 if (info->linking) 1111 err = ocelot_port_bridge_join(ocelot_port, 1112 info->upper_dev); 1113 else 1114 ocelot_port_bridge_leave(ocelot_port, 1115 info->upper_dev); 1116 } 1117 break; 1118 default: 1119 break; 1120 } 1121 1122 return err; 1123 } 1124 1125 static int ocelot_netdevice_event(struct notifier_block *unused, 1126 unsigned long event, void *ptr) 1127 { 1128 struct netdev_notifier_changeupper_info *info = ptr; 1129 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1130 int ret = 0; 1131 1132 if (netif_is_lag_master(dev)) { 1133 struct net_device *slave; 1134 struct list_head *iter; 1135 1136 netdev_for_each_lower_dev(dev, slave, iter) { 1137 ret = ocelot_netdevice_port_event(slave, event, info); 1138 if (ret) 1139 goto notify; 1140 } 1141 } else { 1142 ret = ocelot_netdevice_port_event(dev, event, info); 1143 } 1144 1145 notify: 1146 return notifier_from_errno(ret); 1147 } 1148 1149 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1150 .notifier_call = ocelot_netdevice_event, 1151 }; 1152 EXPORT_SYMBOL(ocelot_netdevice_nb); 1153 1154 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1155 void __iomem *regs, 1156 struct phy_device *phy) 1157 { 1158 struct ocelot_port *ocelot_port; 1159 struct net_device *dev; 1160 int err; 1161 1162 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1163 if (!dev) 1164 return -ENOMEM; 1165 SET_NETDEV_DEV(dev, ocelot->dev); 1166 ocelot_port = netdev_priv(dev); 1167 ocelot_port->dev = dev; 1168 ocelot_port->ocelot = ocelot; 1169 ocelot_port->regs = regs; 1170 ocelot_port->chip_port = port; 1171 ocelot_port->phy = phy; 1172 INIT_LIST_HEAD(&ocelot_port->mc); 1173 ocelot->ports[port] = ocelot_port; 1174 1175 dev->netdev_ops = &ocelot_port_netdev_ops; 1176 dev->ethtool_ops = &ocelot_ethtool_ops; 1177 dev->switchdev_ops = &ocelot_port_switchdev_ops; 1178 1179 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1180 dev->dev_addr[ETH_ALEN - 1] += port; 1181 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1182 ENTRYTYPE_LOCKED); 1183 1184 err = register_netdev(dev); 1185 if (err) { 1186 dev_err(ocelot->dev, "register_netdev failed\n"); 1187 goto err_register_netdev; 1188 } 1189 1190 return 0; 1191 1192 err_register_netdev: 1193 free_netdev(dev); 1194 return err; 1195 } 1196 EXPORT_SYMBOL(ocelot_probe_port); 1197 1198 int ocelot_init(struct ocelot *ocelot) 1199 { 1200 u32 port; 1201 int i, cpu = ocelot->num_phys_ports; 1202 char queue_name[32]; 1203 1204 ocelot->stats = devm_kcalloc(ocelot->dev, 1205 ocelot->num_phys_ports * ocelot->num_stats, 1206 sizeof(u64), GFP_KERNEL); 1207 if (!ocelot->stats) 1208 return -ENOMEM; 1209 1210 mutex_init(&ocelot->stats_lock); 1211 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1212 dev_name(ocelot->dev)); 1213 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1214 if (!ocelot->stats_queue) 1215 return -ENOMEM; 1216 1217 ocelot_mact_init(ocelot); 1218 ocelot_vlan_init(ocelot); 1219 1220 for (port = 0; port < ocelot->num_phys_ports; port++) { 1221 /* Clear all counters (5 groups) */ 1222 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1223 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1224 SYS_STAT_CFG); 1225 } 1226 1227 /* Only use S-Tag */ 1228 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1229 1230 /* Aggregation mode */ 1231 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1232 ANA_AGGR_CFG_AC_DMAC_ENA | 1233 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1234 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1235 1236 /* Set MAC age time to default value. The entry is aged after 1237 * 2*AGE_PERIOD 1238 */ 1239 ocelot_write(ocelot, 1240 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1241 ANA_AUTOAGE); 1242 1243 /* Disable learning for frames discarded by VLAN ingress filtering */ 1244 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1245 1246 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1247 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1248 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1249 1250 /* Setup flooding PGIDs */ 1251 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1252 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1253 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1254 ANA_FLOODING, 0); 1255 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1256 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1257 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1258 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1259 ANA_FLOODING_IPMC); 1260 1261 for (port = 0; port < ocelot->num_phys_ports; port++) { 1262 /* Transmit the frame to the local port. */ 1263 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1264 /* Do not forward BPDU frames to the front ports. */ 1265 ocelot_write_gix(ocelot, 1266 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1267 ANA_PORT_CPU_FWD_BPDU_CFG, 1268 port); 1269 /* Ensure bridging is disabled */ 1270 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1271 } 1272 1273 /* Configure and enable the CPU port. */ 1274 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1275 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1276 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1277 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1278 ANA_PORT_PORT_CFG, cpu); 1279 1280 /* Allow broadcast MAC frames. */ 1281 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1282 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1283 1284 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1285 } 1286 ocelot_write_rix(ocelot, 1287 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1288 ANA_PGID_PGID, PGID_MC); 1289 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1290 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1291 1292 /* CPU port Injection/Extraction configuration */ 1293 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1294 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1295 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1296 QSYS_SWITCH_PORT_MODE, cpu); 1297 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1298 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1299 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1300 * registers endianness. 1301 */ 1302 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1303 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1304 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1305 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1306 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1307 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1308 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1309 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1310 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1311 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1312 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1313 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1314 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1315 for (i = 0; i < 16; i++) 1316 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1317 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1318 ANA_CPUQ_8021_CFG, i); 1319 1320 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats); 1321 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1322 OCELOT_STATS_CHECK_DELAY); 1323 return 0; 1324 } 1325 EXPORT_SYMBOL(ocelot_init); 1326 1327 void ocelot_deinit(struct ocelot *ocelot) 1328 { 1329 destroy_workqueue(ocelot->stats_queue); 1330 mutex_destroy(&ocelot->stats_lock); 1331 } 1332 EXPORT_SYMBOL(ocelot_deinit); 1333 1334 MODULE_LICENSE("Dual MIT/GPL"); 1335