1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 static int ocelot_vlan_member_set(struct ocelot *ocelot, u32 vlan_mask, u16 vid) 226 { 227 int err; 228 229 err = ocelot_vlant_set_mask(ocelot, vid, vlan_mask); 230 if (err) 231 return err; 232 233 ocelot->vlan_mask[vid] = vlan_mask; 234 235 return 0; 236 } 237 238 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid) 239 { 240 return ocelot_vlan_member_set(ocelot, 241 ocelot->vlan_mask[vid] | BIT(port), 242 vid); 243 } 244 245 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 246 { 247 return ocelot_vlan_member_set(ocelot, 248 ocelot->vlan_mask[vid] & ~BIT(port), 249 vid); 250 } 251 252 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 253 bool vlan_aware, struct netlink_ext_ack *extack) 254 { 255 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 256 struct ocelot_port *ocelot_port = ocelot->ports[port]; 257 struct ocelot_vcap_filter *filter; 258 u32 val; 259 260 list_for_each_entry(filter, &block->rules, list) { 261 if (filter->ingress_port_mask & BIT(port) && 262 filter->action.vid_replace_ena) { 263 NL_SET_ERR_MSG_MOD(extack, 264 "Cannot change VLAN state with vlan modify rules active"); 265 return -EBUSY; 266 } 267 } 268 269 ocelot_port->vlan_aware = vlan_aware; 270 271 if (vlan_aware) 272 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 273 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 274 else 275 val = 0; 276 ocelot_rmw_gix(ocelot, val, 277 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 278 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 279 ANA_PORT_VLAN_CFG, port); 280 281 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 282 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 283 284 return 0; 285 } 286 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 287 288 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 289 bool untagged, struct netlink_ext_ack *extack) 290 { 291 struct ocelot_port *ocelot_port = ocelot->ports[port]; 292 293 /* Deny changing the native VLAN, but always permit deleting it */ 294 if (untagged && ocelot_port->native_vlan.vid != vid && 295 ocelot_port->native_vlan.valid) { 296 NL_SET_ERR_MSG_MOD(extack, 297 "Port already has a native VLAN"); 298 return -EBUSY; 299 } 300 301 return 0; 302 } 303 EXPORT_SYMBOL(ocelot_vlan_prepare); 304 305 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 306 bool untagged) 307 { 308 int err; 309 310 err = ocelot_vlan_member_add(ocelot, port, vid); 311 if (err) 312 return err; 313 314 /* Default ingress vlan classification */ 315 if (pvid) { 316 struct ocelot_vlan pvid_vlan; 317 318 pvid_vlan.vid = vid; 319 pvid_vlan.valid = true; 320 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 321 } 322 323 /* Untagged egress vlan clasification */ 324 if (untagged) { 325 struct ocelot_vlan native_vlan; 326 327 native_vlan.vid = vid; 328 native_vlan.valid = true; 329 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 330 } 331 332 return 0; 333 } 334 EXPORT_SYMBOL(ocelot_vlan_add); 335 336 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 337 { 338 struct ocelot_port *ocelot_port = ocelot->ports[port]; 339 int err; 340 341 err = ocelot_vlan_member_del(ocelot, port, vid); 342 if (err) 343 return err; 344 345 /* Ingress */ 346 if (ocelot_port->pvid_vlan.vid == vid) { 347 struct ocelot_vlan pvid_vlan = {0}; 348 349 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 350 } 351 352 /* Egress */ 353 if (ocelot_port->native_vlan.vid == vid) { 354 struct ocelot_vlan native_vlan = {0}; 355 356 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 357 } 358 359 return 0; 360 } 361 EXPORT_SYMBOL(ocelot_vlan_del); 362 363 static void ocelot_vlan_init(struct ocelot *ocelot) 364 { 365 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 366 u16 port, vid; 367 368 /* Clear VLAN table, by default all ports are members of all VLANs */ 369 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 370 ANA_TABLES_VLANACCESS); 371 ocelot_vlant_wait_for_completion(ocelot); 372 373 /* Configure the port VLAN memberships */ 374 for (vid = 1; vid < VLAN_N_VID; vid++) 375 ocelot_vlan_member_set(ocelot, 0, vid); 376 377 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 378 * traffic. It is added automatically if 8021q module is loaded, but 379 * we can't rely on it since module may be not loaded. 380 */ 381 ocelot_vlan_member_set(ocelot, all_ports, 0); 382 383 /* Set vlan ingress filter mask to all ports but the CPU port by 384 * default. 385 */ 386 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 387 388 for (port = 0; port < ocelot->num_phys_ports; port++) { 389 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 390 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 391 } 392 } 393 394 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 395 { 396 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 397 } 398 399 static int ocelot_port_flush(struct ocelot *ocelot, int port) 400 { 401 unsigned int pause_ena; 402 int err, val; 403 404 /* Disable dequeuing from the egress queues */ 405 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 406 QSYS_PORT_MODE_DEQUEUE_DIS, 407 QSYS_PORT_MODE, port); 408 409 /* Disable flow control */ 410 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 411 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 412 413 /* Disable priority flow control */ 414 ocelot_fields_write(ocelot, port, 415 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 416 417 /* Wait at least the time it takes to receive a frame of maximum length 418 * at the port. 419 * Worst-case delays for 10 kilobyte jumbo frames are: 420 * 8 ms on a 10M port 421 * 800 μs on a 100M port 422 * 80 μs on a 1G port 423 * 32 μs on a 2.5G port 424 */ 425 usleep_range(8000, 10000); 426 427 /* Disable half duplex backpressure. */ 428 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 429 SYS_FRONT_PORT_MODE, port); 430 431 /* Flush the queues associated with the port. */ 432 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 433 REW_PORT_CFG, port); 434 435 /* Enable dequeuing from the egress queues. */ 436 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 437 port); 438 439 /* Wait until flushing is complete. */ 440 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 441 100, 2000000, false, ocelot, port); 442 443 /* Clear flushing again. */ 444 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 445 446 /* Re-enable flow control */ 447 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 448 449 return err; 450 } 451 452 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 453 unsigned int link_an_mode, 454 phy_interface_t interface, 455 unsigned long quirks) 456 { 457 struct ocelot_port *ocelot_port = ocelot->ports[port]; 458 int err; 459 460 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 461 DEV_MAC_ENA_CFG); 462 463 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 464 465 err = ocelot_port_flush(ocelot, port); 466 if (err) 467 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 468 port, err); 469 470 /* Put the port in reset. */ 471 if (interface != PHY_INTERFACE_MODE_QSGMII || 472 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 473 ocelot_port_rmwl(ocelot_port, 474 DEV_CLOCK_CFG_MAC_TX_RST | 475 DEV_CLOCK_CFG_MAC_RX_RST, 476 DEV_CLOCK_CFG_MAC_TX_RST | 477 DEV_CLOCK_CFG_MAC_RX_RST, 478 DEV_CLOCK_CFG); 479 } 480 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 481 482 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 483 struct phy_device *phydev, 484 unsigned int link_an_mode, 485 phy_interface_t interface, 486 int speed, int duplex, 487 bool tx_pause, bool rx_pause, 488 unsigned long quirks) 489 { 490 struct ocelot_port *ocelot_port = ocelot->ports[port]; 491 int mac_speed, mode = 0; 492 u32 mac_fc_cfg; 493 494 /* The MAC might be integrated in systems where the MAC speed is fixed 495 * and it's the PCS who is performing the rate adaptation, so we have 496 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 497 * (which is also its default value). 498 */ 499 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 500 speed == SPEED_1000) { 501 mac_speed = OCELOT_SPEED_1000; 502 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 503 } else if (speed == SPEED_2500) { 504 mac_speed = OCELOT_SPEED_2500; 505 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 506 } else if (speed == SPEED_100) { 507 mac_speed = OCELOT_SPEED_100; 508 } else { 509 mac_speed = OCELOT_SPEED_10; 510 } 511 512 if (duplex == DUPLEX_FULL) 513 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 514 515 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 516 517 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 518 * PORT_RST bits in DEV_CLOCK_CFG. 519 */ 520 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 521 DEV_CLOCK_CFG); 522 523 switch (speed) { 524 case SPEED_10: 525 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 526 break; 527 case SPEED_100: 528 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 529 break; 530 case SPEED_1000: 531 case SPEED_2500: 532 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 533 break; 534 default: 535 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 536 port, speed); 537 return; 538 } 539 540 /* Handle RX pause in all cases, with 2500base-X this is used for rate 541 * adaptation. 542 */ 543 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 544 545 if (tx_pause) 546 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 547 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 548 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 549 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 550 551 /* Flow control. Link speed is only used here to evaluate the time 552 * specification in incoming pause frames. 553 */ 554 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 555 556 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 557 558 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 559 560 /* Undo the effects of ocelot_phylink_mac_link_down: 561 * enable MAC module 562 */ 563 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 564 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 565 566 /* Core: Enable port for frame transfer */ 567 ocelot_fields_write(ocelot, port, 568 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 569 } 570 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 571 572 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 573 struct sk_buff *clone) 574 { 575 struct ocelot_port *ocelot_port = ocelot->ports[port]; 576 unsigned long flags; 577 578 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 579 580 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 581 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 582 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 583 return -EBUSY; 584 } 585 586 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 587 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 588 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 589 590 ocelot_port->ts_id++; 591 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 592 ocelot_port->ts_id = 0; 593 594 ocelot_port->ptp_skbs_in_flight++; 595 ocelot->ptp_skbs_in_flight++; 596 597 skb_queue_tail(&ocelot_port->tx_skbs, clone); 598 599 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 600 601 return 0; 602 } 603 604 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 605 unsigned int ptp_class) 606 { 607 struct ptp_header *hdr; 608 u8 msgtype, twostep; 609 610 hdr = ptp_parse_header(skb, ptp_class); 611 if (!hdr) 612 return false; 613 614 msgtype = ptp_get_msgtype(hdr, ptp_class); 615 twostep = hdr->flag_field[0] & 0x2; 616 617 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 618 return true; 619 620 return false; 621 } 622 623 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 624 struct sk_buff *skb, 625 struct sk_buff **clone) 626 { 627 struct ocelot_port *ocelot_port = ocelot->ports[port]; 628 u8 ptp_cmd = ocelot_port->ptp_cmd; 629 unsigned int ptp_class; 630 int err; 631 632 /* Don't do anything if PTP timestamping not enabled */ 633 if (!ptp_cmd) 634 return 0; 635 636 ptp_class = ptp_classify_raw(skb); 637 if (ptp_class == PTP_CLASS_NONE) 638 return -EINVAL; 639 640 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 641 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 642 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 643 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 644 return 0; 645 } 646 647 /* Fall back to two-step timestamping */ 648 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 649 } 650 651 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 652 *clone = skb_clone_sk(skb); 653 if (!(*clone)) 654 return -ENOMEM; 655 656 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 657 if (err) 658 return err; 659 660 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 661 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 662 } 663 664 return 0; 665 } 666 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 667 668 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 669 struct timespec64 *ts) 670 { 671 unsigned long flags; 672 u32 val; 673 674 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 675 676 /* Read current PTP time to get seconds */ 677 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 678 679 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 680 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 681 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 682 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 683 684 /* Read packet HW timestamp from FIFO */ 685 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 686 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 687 688 /* Sec has incremented since the ts was registered */ 689 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 690 ts->tv_sec--; 691 692 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 693 } 694 695 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 696 { 697 struct ptp_header *hdr; 698 699 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 700 if (WARN_ON(!hdr)) 701 return false; 702 703 return seqid == ntohs(hdr->sequence_id); 704 } 705 706 void ocelot_get_txtstamp(struct ocelot *ocelot) 707 { 708 int budget = OCELOT_PTP_QUEUE_SZ; 709 710 while (budget--) { 711 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 712 struct skb_shared_hwtstamps shhwtstamps; 713 u32 val, id, seqid, txport; 714 struct ocelot_port *port; 715 struct timespec64 ts; 716 unsigned long flags; 717 718 val = ocelot_read(ocelot, SYS_PTP_STATUS); 719 720 /* Check if a timestamp can be retrieved */ 721 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 722 break; 723 724 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 725 726 /* Retrieve the ts ID and Tx port */ 727 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 728 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 729 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 730 731 port = ocelot->ports[txport]; 732 733 spin_lock(&ocelot->ts_id_lock); 734 port->ptp_skbs_in_flight--; 735 ocelot->ptp_skbs_in_flight--; 736 spin_unlock(&ocelot->ts_id_lock); 737 738 /* Retrieve its associated skb */ 739 try_again: 740 spin_lock_irqsave(&port->tx_skbs.lock, flags); 741 742 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 743 if (OCELOT_SKB_CB(skb)->ts_id != id) 744 continue; 745 __skb_unlink(skb, &port->tx_skbs); 746 skb_match = skb; 747 break; 748 } 749 750 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 751 752 if (WARN_ON(!skb_match)) 753 continue; 754 755 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 756 dev_err_ratelimited(ocelot->dev, 757 "port %d received stale TX timestamp for seqid %d, discarding\n", 758 txport, seqid); 759 dev_kfree_skb_any(skb); 760 goto try_again; 761 } 762 763 /* Get the h/w timestamp */ 764 ocelot_get_hwtimestamp(ocelot, &ts); 765 766 /* Set the timestamp into the skb */ 767 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 768 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 769 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 770 771 /* Next ts */ 772 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 773 } 774 } 775 EXPORT_SYMBOL(ocelot_get_txtstamp); 776 777 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 778 u32 *rval) 779 { 780 u32 bytes_valid, val; 781 782 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 783 if (val == XTR_NOT_READY) { 784 if (ifh) 785 return -EIO; 786 787 do { 788 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 789 } while (val == XTR_NOT_READY); 790 } 791 792 switch (val) { 793 case XTR_ABORT: 794 return -EIO; 795 case XTR_EOF_0: 796 case XTR_EOF_1: 797 case XTR_EOF_2: 798 case XTR_EOF_3: 799 case XTR_PRUNED: 800 bytes_valid = XTR_VALID_BYTES(val); 801 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 802 if (val == XTR_ESCAPE) 803 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 804 else 805 *rval = val; 806 807 return bytes_valid; 808 case XTR_ESCAPE: 809 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 810 811 return 4; 812 default: 813 *rval = val; 814 815 return 4; 816 } 817 } 818 819 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 820 { 821 int i, err = 0; 822 823 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 824 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 825 if (err != 4) 826 return (err < 0) ? err : -EIO; 827 } 828 829 return 0; 830 } 831 832 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 833 { 834 struct skb_shared_hwtstamps *shhwtstamps; 835 u64 tod_in_ns, full_ts_in_ns; 836 u64 timestamp, src_port, len; 837 u32 xfh[OCELOT_TAG_LEN / 4]; 838 struct net_device *dev; 839 struct timespec64 ts; 840 struct sk_buff *skb; 841 int sz, buf_len; 842 u32 val, *buf; 843 int err; 844 845 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 846 if (err) 847 return err; 848 849 ocelot_xfh_get_src_port(xfh, &src_port); 850 ocelot_xfh_get_len(xfh, &len); 851 ocelot_xfh_get_rew_val(xfh, ×tamp); 852 853 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 854 return -EINVAL; 855 856 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 857 if (!dev) 858 return -EINVAL; 859 860 skb = netdev_alloc_skb(dev, len); 861 if (unlikely(!skb)) { 862 netdev_err(dev, "Unable to allocate sk_buff\n"); 863 return -ENOMEM; 864 } 865 866 buf_len = len - ETH_FCS_LEN; 867 buf = (u32 *)skb_put(skb, buf_len); 868 869 len = 0; 870 do { 871 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 872 if (sz < 0) { 873 err = sz; 874 goto out_free_skb; 875 } 876 *buf++ = val; 877 len += sz; 878 } while (len < buf_len); 879 880 /* Read the FCS */ 881 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 882 if (sz < 0) { 883 err = sz; 884 goto out_free_skb; 885 } 886 887 /* Update the statistics if part of the FCS was read before */ 888 len -= ETH_FCS_LEN - sz; 889 890 if (unlikely(dev->features & NETIF_F_RXFCS)) { 891 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 892 *buf = val; 893 } 894 895 if (ocelot->ptp) { 896 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 897 898 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 899 if ((tod_in_ns & 0xffffffff) < timestamp) 900 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 901 timestamp; 902 else 903 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 904 timestamp; 905 906 shhwtstamps = skb_hwtstamps(skb); 907 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 908 shhwtstamps->hwtstamp = full_ts_in_ns; 909 } 910 911 /* Everything we see on an interface that is in the HW bridge 912 * has already been forwarded. 913 */ 914 if (ocelot->ports[src_port]->bridge) 915 skb->offload_fwd_mark = 1; 916 917 skb->protocol = eth_type_trans(skb, dev); 918 919 *nskb = skb; 920 921 return 0; 922 923 out_free_skb: 924 kfree_skb(skb); 925 return err; 926 } 927 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 928 929 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 930 { 931 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 932 933 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 934 return false; 935 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 936 return false; 937 938 return true; 939 } 940 EXPORT_SYMBOL(ocelot_can_inject); 941 942 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 943 u32 rew_op, struct sk_buff *skb) 944 { 945 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 946 unsigned int i, count, last; 947 948 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 949 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 950 951 ocelot_ifh_set_bypass(ifh, 1); 952 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 953 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 954 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 955 ocelot_ifh_set_rew_op(ifh, rew_op); 956 957 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 958 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 959 960 count = DIV_ROUND_UP(skb->len, 4); 961 last = skb->len % 4; 962 for (i = 0; i < count; i++) 963 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 964 965 /* Add padding */ 966 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 967 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 968 i++; 969 } 970 971 /* Indicate EOF and valid bytes in last word */ 972 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 973 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 974 QS_INJ_CTRL_EOF, 975 QS_INJ_CTRL, grp); 976 977 /* Add dummy CRC */ 978 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 979 skb_tx_timestamp(skb); 980 981 skb->dev->stats.tx_packets++; 982 skb->dev->stats.tx_bytes += skb->len; 983 } 984 EXPORT_SYMBOL(ocelot_port_inject_frame); 985 986 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 987 { 988 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 989 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 990 } 991 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 992 993 int ocelot_fdb_add(struct ocelot *ocelot, int port, 994 const unsigned char *addr, u16 vid) 995 { 996 int pgid = port; 997 998 if (port == ocelot->npi) 999 pgid = PGID_CPU; 1000 1001 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1002 } 1003 EXPORT_SYMBOL(ocelot_fdb_add); 1004 1005 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1006 const unsigned char *addr, u16 vid) 1007 { 1008 return ocelot_mact_forget(ocelot, addr, vid); 1009 } 1010 EXPORT_SYMBOL(ocelot_fdb_del); 1011 1012 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1013 bool is_static, void *data) 1014 { 1015 struct ocelot_dump_ctx *dump = data; 1016 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1017 u32 seq = dump->cb->nlh->nlmsg_seq; 1018 struct nlmsghdr *nlh; 1019 struct ndmsg *ndm; 1020 1021 if (dump->idx < dump->cb->args[2]) 1022 goto skip; 1023 1024 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1025 sizeof(*ndm), NLM_F_MULTI); 1026 if (!nlh) 1027 return -EMSGSIZE; 1028 1029 ndm = nlmsg_data(nlh); 1030 ndm->ndm_family = AF_BRIDGE; 1031 ndm->ndm_pad1 = 0; 1032 ndm->ndm_pad2 = 0; 1033 ndm->ndm_flags = NTF_SELF; 1034 ndm->ndm_type = 0; 1035 ndm->ndm_ifindex = dump->dev->ifindex; 1036 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1037 1038 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1039 goto nla_put_failure; 1040 1041 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1042 goto nla_put_failure; 1043 1044 nlmsg_end(dump->skb, nlh); 1045 1046 skip: 1047 dump->idx++; 1048 return 0; 1049 1050 nla_put_failure: 1051 nlmsg_cancel(dump->skb, nlh); 1052 return -EMSGSIZE; 1053 } 1054 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1055 1056 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1057 struct ocelot_mact_entry *entry) 1058 { 1059 u32 val, dst, macl, mach; 1060 char mac[ETH_ALEN]; 1061 1062 /* Set row and column to read from */ 1063 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1064 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1065 1066 /* Issue a read command */ 1067 ocelot_write(ocelot, 1068 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1069 ANA_TABLES_MACACCESS); 1070 1071 if (ocelot_mact_wait_for_completion(ocelot)) 1072 return -ETIMEDOUT; 1073 1074 /* Read the entry flags */ 1075 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1076 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1077 return -EINVAL; 1078 1079 /* If the entry read has another port configured as its destination, 1080 * do not report it. 1081 */ 1082 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1083 if (dst != port) 1084 return -EINVAL; 1085 1086 /* Get the entry's MAC address and VLAN id */ 1087 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1088 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1089 1090 mac[0] = (mach >> 8) & 0xff; 1091 mac[1] = (mach >> 0) & 0xff; 1092 mac[2] = (macl >> 24) & 0xff; 1093 mac[3] = (macl >> 16) & 0xff; 1094 mac[4] = (macl >> 8) & 0xff; 1095 mac[5] = (macl >> 0) & 0xff; 1096 1097 entry->vid = (mach >> 16) & 0xfff; 1098 ether_addr_copy(entry->mac, mac); 1099 1100 return 0; 1101 } 1102 1103 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1104 dsa_fdb_dump_cb_t *cb, void *data) 1105 { 1106 int i, j; 1107 1108 /* Loop through all the mac tables entries. */ 1109 for (i = 0; i < ocelot->num_mact_rows; i++) { 1110 for (j = 0; j < 4; j++) { 1111 struct ocelot_mact_entry entry; 1112 bool is_static; 1113 int ret; 1114 1115 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1116 /* If the entry is invalid (wrong port, invalid...), 1117 * skip it. 1118 */ 1119 if (ret == -EINVAL) 1120 continue; 1121 else if (ret) 1122 return ret; 1123 1124 is_static = (entry.type == ENTRYTYPE_LOCKED); 1125 1126 ret = cb(entry.mac, entry.vid, is_static, data); 1127 if (ret) 1128 return ret; 1129 } 1130 } 1131 1132 return 0; 1133 } 1134 EXPORT_SYMBOL(ocelot_fdb_dump); 1135 1136 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1137 { 1138 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1139 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1140 } 1141 EXPORT_SYMBOL(ocelot_hwstamp_get); 1142 1143 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1144 { 1145 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1146 struct hwtstamp_config cfg; 1147 1148 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1149 return -EFAULT; 1150 1151 /* reserved for future extensions */ 1152 if (cfg.flags) 1153 return -EINVAL; 1154 1155 /* Tx type sanity check */ 1156 switch (cfg.tx_type) { 1157 case HWTSTAMP_TX_ON: 1158 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1159 break; 1160 case HWTSTAMP_TX_ONESTEP_SYNC: 1161 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1162 * need to update the origin time. 1163 */ 1164 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1165 break; 1166 case HWTSTAMP_TX_OFF: 1167 ocelot_port->ptp_cmd = 0; 1168 break; 1169 default: 1170 return -ERANGE; 1171 } 1172 1173 mutex_lock(&ocelot->ptp_lock); 1174 1175 switch (cfg.rx_filter) { 1176 case HWTSTAMP_FILTER_NONE: 1177 break; 1178 case HWTSTAMP_FILTER_ALL: 1179 case HWTSTAMP_FILTER_SOME: 1180 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1181 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1182 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1183 case HWTSTAMP_FILTER_NTP_ALL: 1184 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1185 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1186 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1187 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1188 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1189 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1190 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1191 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1192 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1193 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1194 break; 1195 default: 1196 mutex_unlock(&ocelot->ptp_lock); 1197 return -ERANGE; 1198 } 1199 1200 /* Commit back the result & save it */ 1201 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1202 mutex_unlock(&ocelot->ptp_lock); 1203 1204 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1205 } 1206 EXPORT_SYMBOL(ocelot_hwstamp_set); 1207 1208 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1209 { 1210 int i; 1211 1212 if (sset != ETH_SS_STATS) 1213 return; 1214 1215 for (i = 0; i < ocelot->num_stats; i++) 1216 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1217 ETH_GSTRING_LEN); 1218 } 1219 EXPORT_SYMBOL(ocelot_get_strings); 1220 1221 static void ocelot_update_stats(struct ocelot *ocelot) 1222 { 1223 int i, j; 1224 1225 mutex_lock(&ocelot->stats_lock); 1226 1227 for (i = 0; i < ocelot->num_phys_ports; i++) { 1228 /* Configure the port to read the stats from */ 1229 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1230 1231 for (j = 0; j < ocelot->num_stats; j++) { 1232 u32 val; 1233 unsigned int idx = i * ocelot->num_stats + j; 1234 1235 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1236 ocelot->stats_layout[j].offset); 1237 1238 if (val < (ocelot->stats[idx] & U32_MAX)) 1239 ocelot->stats[idx] += (u64)1 << 32; 1240 1241 ocelot->stats[idx] = (ocelot->stats[idx] & 1242 ~(u64)U32_MAX) + val; 1243 } 1244 } 1245 1246 mutex_unlock(&ocelot->stats_lock); 1247 } 1248 1249 static void ocelot_check_stats_work(struct work_struct *work) 1250 { 1251 struct delayed_work *del_work = to_delayed_work(work); 1252 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1253 stats_work); 1254 1255 ocelot_update_stats(ocelot); 1256 1257 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1258 OCELOT_STATS_CHECK_DELAY); 1259 } 1260 1261 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1262 { 1263 int i; 1264 1265 /* check and update now */ 1266 ocelot_update_stats(ocelot); 1267 1268 /* Copy all counters */ 1269 for (i = 0; i < ocelot->num_stats; i++) 1270 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1271 } 1272 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1273 1274 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1275 { 1276 if (sset != ETH_SS_STATS) 1277 return -EOPNOTSUPP; 1278 1279 return ocelot->num_stats; 1280 } 1281 EXPORT_SYMBOL(ocelot_get_sset_count); 1282 1283 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1284 struct ethtool_ts_info *info) 1285 { 1286 info->phc_index = ocelot->ptp_clock ? 1287 ptp_clock_index(ocelot->ptp_clock) : -1; 1288 if (info->phc_index == -1) { 1289 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1290 SOF_TIMESTAMPING_RX_SOFTWARE | 1291 SOF_TIMESTAMPING_SOFTWARE; 1292 return 0; 1293 } 1294 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1295 SOF_TIMESTAMPING_RX_SOFTWARE | 1296 SOF_TIMESTAMPING_SOFTWARE | 1297 SOF_TIMESTAMPING_TX_HARDWARE | 1298 SOF_TIMESTAMPING_RX_HARDWARE | 1299 SOF_TIMESTAMPING_RAW_HARDWARE; 1300 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1301 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1302 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1303 1304 return 0; 1305 } 1306 EXPORT_SYMBOL(ocelot_get_ts_info); 1307 1308 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1309 bool only_active_ports) 1310 { 1311 u32 mask = 0; 1312 int port; 1313 1314 for (port = 0; port < ocelot->num_phys_ports; port++) { 1315 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1316 1317 if (!ocelot_port) 1318 continue; 1319 1320 if (ocelot_port->bond == bond) { 1321 if (only_active_ports && !ocelot_port->lag_tx_active) 1322 continue; 1323 1324 mask |= BIT(port); 1325 } 1326 } 1327 1328 return mask; 1329 } 1330 1331 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port, 1332 struct net_device *bridge) 1333 { 1334 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1335 u32 mask = 0; 1336 int port; 1337 1338 if (!ocelot_port || ocelot_port->bridge != bridge || 1339 ocelot_port->stp_state != BR_STATE_FORWARDING) 1340 return 0; 1341 1342 for (port = 0; port < ocelot->num_phys_ports; port++) { 1343 ocelot_port = ocelot->ports[port]; 1344 1345 if (!ocelot_port) 1346 continue; 1347 1348 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1349 ocelot_port->bridge == bridge) 1350 mask |= BIT(port); 1351 } 1352 1353 return mask; 1354 } 1355 1356 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1357 { 1358 u32 mask = 0; 1359 int port; 1360 1361 for (port = 0; port < ocelot->num_phys_ports; port++) { 1362 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1363 1364 if (!ocelot_port) 1365 continue; 1366 1367 if (ocelot_port->is_dsa_8021q_cpu) 1368 mask |= BIT(port); 1369 } 1370 1371 return mask; 1372 } 1373 1374 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1375 { 1376 unsigned long cpu_fwd_mask; 1377 int port; 1378 1379 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1380 * regular forwarding path of the front ports regardless of whether 1381 * those are bridged or standalone. 1382 * If DSA tag_8021q is not used, this returns 0, which is fine because 1383 * the hardware-based CPU port module can be a destination for packets 1384 * even if it isn't part of PGID_SRC. 1385 */ 1386 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1387 1388 /* Apply FWD mask. The loop is needed to add/remove the current port as 1389 * a source for the other ports. 1390 */ 1391 for (port = 0; port < ocelot->num_phys_ports; port++) { 1392 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1393 unsigned long mask; 1394 1395 if (!ocelot_port) { 1396 /* Unused ports can't send anywhere */ 1397 mask = 0; 1398 } else if (ocelot_port->is_dsa_8021q_cpu) { 1399 /* The DSA tag_8021q CPU ports need to be able to 1400 * forward packets to all other ports except for 1401 * themselves 1402 */ 1403 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1404 mask &= ~cpu_fwd_mask; 1405 } else if (ocelot_port->bridge) { 1406 struct net_device *bridge = ocelot_port->bridge; 1407 struct net_device *bond = ocelot_port->bond; 1408 1409 mask = ocelot_get_bridge_fwd_mask(ocelot, port, bridge); 1410 mask |= cpu_fwd_mask; 1411 mask &= ~BIT(port); 1412 if (bond) { 1413 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1414 false); 1415 } 1416 } else { 1417 /* Standalone ports forward only to DSA tag_8021q CPU 1418 * ports (if those exist), or to the hardware CPU port 1419 * module otherwise. 1420 */ 1421 mask = cpu_fwd_mask; 1422 } 1423 1424 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1425 } 1426 } 1427 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1428 1429 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1430 { 1431 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1432 u32 learn_ena = 0; 1433 1434 ocelot_port->stp_state = state; 1435 1436 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1437 ocelot_port->learn_ena) 1438 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1439 1440 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1441 ANA_PORT_PORT_CFG, port); 1442 1443 ocelot_apply_bridge_fwd_mask(ocelot); 1444 } 1445 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1446 1447 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1448 { 1449 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1450 1451 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1452 * which is clearly not what our intention is. So avoid that. 1453 */ 1454 if (!age_period) 1455 age_period = 1; 1456 1457 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1458 } 1459 EXPORT_SYMBOL(ocelot_set_ageing_time); 1460 1461 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1462 const unsigned char *addr, 1463 u16 vid) 1464 { 1465 struct ocelot_multicast *mc; 1466 1467 list_for_each_entry(mc, &ocelot->multicast, list) { 1468 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1469 return mc; 1470 } 1471 1472 return NULL; 1473 } 1474 1475 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1476 { 1477 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1478 return ENTRYTYPE_MACv4; 1479 if (addr[0] == 0x33 && addr[1] == 0x33) 1480 return ENTRYTYPE_MACv6; 1481 return ENTRYTYPE_LOCKED; 1482 } 1483 1484 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1485 unsigned long ports) 1486 { 1487 struct ocelot_pgid *pgid; 1488 1489 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1490 if (!pgid) 1491 return ERR_PTR(-ENOMEM); 1492 1493 pgid->ports = ports; 1494 pgid->index = index; 1495 refcount_set(&pgid->refcount, 1); 1496 list_add_tail(&pgid->list, &ocelot->pgids); 1497 1498 return pgid; 1499 } 1500 1501 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1502 { 1503 if (!refcount_dec_and_test(&pgid->refcount)) 1504 return; 1505 1506 list_del(&pgid->list); 1507 kfree(pgid); 1508 } 1509 1510 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1511 const struct ocelot_multicast *mc) 1512 { 1513 struct ocelot_pgid *pgid; 1514 int index; 1515 1516 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1517 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1518 * destination mask table (PGID), the destination set is programmed as 1519 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1520 */ 1521 if (mc->entry_type == ENTRYTYPE_MACv4 || 1522 mc->entry_type == ENTRYTYPE_MACv6) 1523 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1524 1525 list_for_each_entry(pgid, &ocelot->pgids, list) { 1526 /* When searching for a nonreserved multicast PGID, ignore the 1527 * dummy PGID of zero that we have for MACv4/MACv6 entries 1528 */ 1529 if (pgid->index && pgid->ports == mc->ports) { 1530 refcount_inc(&pgid->refcount); 1531 return pgid; 1532 } 1533 } 1534 1535 /* Search for a free index in the nonreserved multicast PGID area */ 1536 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1537 bool used = false; 1538 1539 list_for_each_entry(pgid, &ocelot->pgids, list) { 1540 if (pgid->index == index) { 1541 used = true; 1542 break; 1543 } 1544 } 1545 1546 if (!used) 1547 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1548 } 1549 1550 return ERR_PTR(-ENOSPC); 1551 } 1552 1553 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1554 struct ocelot_multicast *mc) 1555 { 1556 ether_addr_copy(addr, mc->addr); 1557 1558 if (mc->entry_type == ENTRYTYPE_MACv4) { 1559 addr[0] = 0; 1560 addr[1] = mc->ports >> 8; 1561 addr[2] = mc->ports & 0xff; 1562 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1563 addr[0] = mc->ports >> 8; 1564 addr[1] = mc->ports & 0xff; 1565 } 1566 } 1567 1568 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1569 const struct switchdev_obj_port_mdb *mdb) 1570 { 1571 unsigned char addr[ETH_ALEN]; 1572 struct ocelot_multicast *mc; 1573 struct ocelot_pgid *pgid; 1574 u16 vid = mdb->vid; 1575 1576 if (port == ocelot->npi) 1577 port = ocelot->num_phys_ports; 1578 1579 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1580 if (!mc) { 1581 /* New entry */ 1582 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1583 if (!mc) 1584 return -ENOMEM; 1585 1586 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1587 ether_addr_copy(mc->addr, mdb->addr); 1588 mc->vid = vid; 1589 1590 list_add_tail(&mc->list, &ocelot->multicast); 1591 } else { 1592 /* Existing entry. Clean up the current port mask from 1593 * hardware now, because we'll be modifying it. 1594 */ 1595 ocelot_pgid_free(ocelot, mc->pgid); 1596 ocelot_encode_ports_to_mdb(addr, mc); 1597 ocelot_mact_forget(ocelot, addr, vid); 1598 } 1599 1600 mc->ports |= BIT(port); 1601 1602 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1603 if (IS_ERR(pgid)) { 1604 dev_err(ocelot->dev, 1605 "Cannot allocate PGID for mdb %pM vid %d\n", 1606 mc->addr, mc->vid); 1607 devm_kfree(ocelot->dev, mc); 1608 return PTR_ERR(pgid); 1609 } 1610 mc->pgid = pgid; 1611 1612 ocelot_encode_ports_to_mdb(addr, mc); 1613 1614 if (mc->entry_type != ENTRYTYPE_MACv4 && 1615 mc->entry_type != ENTRYTYPE_MACv6) 1616 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1617 pgid->index); 1618 1619 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1620 mc->entry_type); 1621 } 1622 EXPORT_SYMBOL(ocelot_port_mdb_add); 1623 1624 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1625 const struct switchdev_obj_port_mdb *mdb) 1626 { 1627 unsigned char addr[ETH_ALEN]; 1628 struct ocelot_multicast *mc; 1629 struct ocelot_pgid *pgid; 1630 u16 vid = mdb->vid; 1631 1632 if (port == ocelot->npi) 1633 port = ocelot->num_phys_ports; 1634 1635 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1636 if (!mc) 1637 return -ENOENT; 1638 1639 ocelot_encode_ports_to_mdb(addr, mc); 1640 ocelot_mact_forget(ocelot, addr, vid); 1641 1642 ocelot_pgid_free(ocelot, mc->pgid); 1643 mc->ports &= ~BIT(port); 1644 if (!mc->ports) { 1645 list_del(&mc->list); 1646 devm_kfree(ocelot->dev, mc); 1647 return 0; 1648 } 1649 1650 /* We have a PGID with fewer ports now */ 1651 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1652 if (IS_ERR(pgid)) 1653 return PTR_ERR(pgid); 1654 mc->pgid = pgid; 1655 1656 ocelot_encode_ports_to_mdb(addr, mc); 1657 1658 if (mc->entry_type != ENTRYTYPE_MACv4 && 1659 mc->entry_type != ENTRYTYPE_MACv6) 1660 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1661 pgid->index); 1662 1663 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1664 mc->entry_type); 1665 } 1666 EXPORT_SYMBOL(ocelot_port_mdb_del); 1667 1668 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1669 struct net_device *bridge) 1670 { 1671 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1672 1673 ocelot_port->bridge = bridge; 1674 1675 ocelot_apply_bridge_fwd_mask(ocelot); 1676 } 1677 EXPORT_SYMBOL(ocelot_port_bridge_join); 1678 1679 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1680 struct net_device *bridge) 1681 { 1682 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1683 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1684 1685 ocelot_port->bridge = NULL; 1686 1687 ocelot_port_set_pvid(ocelot, port, pvid); 1688 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1689 ocelot_apply_bridge_fwd_mask(ocelot); 1690 } 1691 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1692 1693 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1694 { 1695 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1696 int i, port, lag; 1697 1698 /* Reset destination and aggregation PGIDS */ 1699 for_each_unicast_dest_pgid(ocelot, port) 1700 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1701 1702 for_each_aggr_pgid(ocelot, i) 1703 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1704 ANA_PGID_PGID, i); 1705 1706 /* The visited ports bitmask holds the list of ports offloading any 1707 * bonding interface. Initially we mark all these ports as unvisited, 1708 * then every time we visit a port in this bitmask, we know that it is 1709 * the lowest numbered port, i.e. the one whose logical ID == physical 1710 * port ID == LAG ID. So we mark as visited all further ports in the 1711 * bitmask that are offloading the same bonding interface. This way, 1712 * we set up the aggregation PGIDs only once per bonding interface. 1713 */ 1714 for (port = 0; port < ocelot->num_phys_ports; port++) { 1715 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1716 1717 if (!ocelot_port || !ocelot_port->bond) 1718 continue; 1719 1720 visited &= ~BIT(port); 1721 } 1722 1723 /* Now, set PGIDs for each active LAG */ 1724 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1725 struct net_device *bond = ocelot->ports[lag]->bond; 1726 int num_active_ports = 0; 1727 unsigned long bond_mask; 1728 u8 aggr_idx[16]; 1729 1730 if (!bond || (visited & BIT(lag))) 1731 continue; 1732 1733 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1734 1735 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1736 // Destination mask 1737 ocelot_write_rix(ocelot, bond_mask, 1738 ANA_PGID_PGID, port); 1739 aggr_idx[num_active_ports++] = port; 1740 } 1741 1742 for_each_aggr_pgid(ocelot, i) { 1743 u32 ac; 1744 1745 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1746 ac &= ~bond_mask; 1747 /* Don't do division by zero if there was no active 1748 * port. Just make all aggregation codes zero. 1749 */ 1750 if (num_active_ports) 1751 ac |= BIT(aggr_idx[i % num_active_ports]); 1752 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1753 } 1754 1755 /* Mark all ports in the same LAG as visited to avoid applying 1756 * the same config again. 1757 */ 1758 for (port = lag; port < ocelot->num_phys_ports; port++) { 1759 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1760 1761 if (!ocelot_port) 1762 continue; 1763 1764 if (ocelot_port->bond == bond) 1765 visited |= BIT(port); 1766 } 1767 } 1768 } 1769 1770 /* When offloading a bonding interface, the switch ports configured under the 1771 * same bond must have the same logical port ID, equal to the physical port ID 1772 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1773 * bridged mode, each port has a logical port ID equal to its physical port ID. 1774 */ 1775 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1776 { 1777 int port; 1778 1779 for (port = 0; port < ocelot->num_phys_ports; port++) { 1780 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1781 struct net_device *bond; 1782 1783 if (!ocelot_port) 1784 continue; 1785 1786 bond = ocelot_port->bond; 1787 if (bond) { 1788 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1789 false)); 1790 1791 ocelot_rmw_gix(ocelot, 1792 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1793 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1794 ANA_PORT_PORT_CFG, port); 1795 } else { 1796 ocelot_rmw_gix(ocelot, 1797 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1798 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1799 ANA_PORT_PORT_CFG, port); 1800 } 1801 } 1802 } 1803 1804 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1805 struct net_device *bond, 1806 struct netdev_lag_upper_info *info) 1807 { 1808 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1809 return -EOPNOTSUPP; 1810 1811 ocelot->ports[port]->bond = bond; 1812 1813 ocelot_setup_logical_port_ids(ocelot); 1814 ocelot_apply_bridge_fwd_mask(ocelot); 1815 ocelot_set_aggr_pgids(ocelot); 1816 1817 return 0; 1818 } 1819 EXPORT_SYMBOL(ocelot_port_lag_join); 1820 1821 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1822 struct net_device *bond) 1823 { 1824 ocelot->ports[port]->bond = NULL; 1825 1826 ocelot_setup_logical_port_ids(ocelot); 1827 ocelot_apply_bridge_fwd_mask(ocelot); 1828 ocelot_set_aggr_pgids(ocelot); 1829 } 1830 EXPORT_SYMBOL(ocelot_port_lag_leave); 1831 1832 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1833 { 1834 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1835 1836 ocelot_port->lag_tx_active = lag_tx_active; 1837 1838 /* Rebalance the LAGs */ 1839 ocelot_set_aggr_pgids(ocelot); 1840 } 1841 EXPORT_SYMBOL(ocelot_port_lag_change); 1842 1843 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1844 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1845 * In the special case that it's the NPI port that we're configuring, the 1846 * length of the tag and optional prefix needs to be accounted for privately, 1847 * in order to be able to sustain communication at the requested @sdu. 1848 */ 1849 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1850 { 1851 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1852 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1853 int pause_start, pause_stop; 1854 int atop, atop_tot; 1855 1856 if (port == ocelot->npi) { 1857 maxlen += OCELOT_TAG_LEN; 1858 1859 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1860 maxlen += OCELOT_SHORT_PREFIX_LEN; 1861 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1862 maxlen += OCELOT_LONG_PREFIX_LEN; 1863 } 1864 1865 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1866 1867 /* Set Pause watermark hysteresis */ 1868 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1869 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1870 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1871 pause_start); 1872 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1873 pause_stop); 1874 1875 /* Tail dropping watermarks */ 1876 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1877 OCELOT_BUFFER_CELL_SZ; 1878 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1879 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1880 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1881 } 1882 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1883 1884 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1885 { 1886 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1887 1888 if (port == ocelot->npi) { 1889 max_mtu -= OCELOT_TAG_LEN; 1890 1891 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1892 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1893 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1894 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1895 } 1896 1897 return max_mtu; 1898 } 1899 EXPORT_SYMBOL(ocelot_get_max_mtu); 1900 1901 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1902 bool enabled) 1903 { 1904 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1905 u32 val = 0; 1906 1907 if (enabled) 1908 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1909 1910 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1911 ANA_PORT_PORT_CFG, port); 1912 1913 ocelot_port->learn_ena = enabled; 1914 } 1915 1916 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1917 bool enabled) 1918 { 1919 u32 val = 0; 1920 1921 if (enabled) 1922 val = BIT(port); 1923 1924 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1925 } 1926 1927 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1928 bool enabled) 1929 { 1930 u32 val = 0; 1931 1932 if (enabled) 1933 val = BIT(port); 1934 1935 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1936 } 1937 1938 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1939 bool enabled) 1940 { 1941 u32 val = 0; 1942 1943 if (enabled) 1944 val = BIT(port); 1945 1946 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1947 } 1948 1949 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1950 struct switchdev_brport_flags flags) 1951 { 1952 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1953 BR_BCAST_FLOOD)) 1954 return -EINVAL; 1955 1956 return 0; 1957 } 1958 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1959 1960 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1961 struct switchdev_brport_flags flags) 1962 { 1963 if (flags.mask & BR_LEARNING) 1964 ocelot_port_set_learning(ocelot, port, 1965 !!(flags.val & BR_LEARNING)); 1966 1967 if (flags.mask & BR_FLOOD) 1968 ocelot_port_set_ucast_flood(ocelot, port, 1969 !!(flags.val & BR_FLOOD)); 1970 1971 if (flags.mask & BR_MCAST_FLOOD) 1972 ocelot_port_set_mcast_flood(ocelot, port, 1973 !!(flags.val & BR_MCAST_FLOOD)); 1974 1975 if (flags.mask & BR_BCAST_FLOOD) 1976 ocelot_port_set_bcast_flood(ocelot, port, 1977 !!(flags.val & BR_BCAST_FLOOD)); 1978 } 1979 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1980 1981 void ocelot_init_port(struct ocelot *ocelot, int port) 1982 { 1983 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1984 1985 skb_queue_head_init(&ocelot_port->tx_skbs); 1986 1987 /* Basic L2 initialization */ 1988 1989 /* Set MAC IFG Gaps 1990 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1991 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1992 */ 1993 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1994 DEV_MAC_IFG_CFG); 1995 1996 /* Load seed (0) and set MAC HDX late collision */ 1997 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1998 DEV_MAC_HDX_CFG_SEED_LOAD, 1999 DEV_MAC_HDX_CFG); 2000 mdelay(1); 2001 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2002 DEV_MAC_HDX_CFG); 2003 2004 /* Set Max Length and maximum tags allowed */ 2005 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2006 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2007 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2008 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2009 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2010 DEV_MAC_TAGS_CFG); 2011 2012 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2013 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2014 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2015 2016 /* Enable transmission of pause frames */ 2017 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2018 2019 /* Drop frames with multicast source address */ 2020 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2021 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2022 ANA_PORT_DROP_CFG, port); 2023 2024 /* Set default VLAN and tag type to 8021Q. */ 2025 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2026 REW_PORT_VLAN_CFG_PORT_TPID_M, 2027 REW_PORT_VLAN_CFG, port); 2028 2029 /* Disable source address learning for standalone mode */ 2030 ocelot_port_set_learning(ocelot, port, false); 2031 2032 /* Set the port's initial logical port ID value, enable receiving 2033 * frames on it, and configure the MAC address learning type to 2034 * automatic. 2035 */ 2036 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2037 ANA_PORT_PORT_CFG_RECV_ENA | 2038 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2039 ANA_PORT_PORT_CFG, port); 2040 2041 /* Enable vcap lookups */ 2042 ocelot_vcap_enable(ocelot, port); 2043 } 2044 EXPORT_SYMBOL(ocelot_init_port); 2045 2046 /* Configure and enable the CPU port module, which is a set of queues 2047 * accessible through register MMIO, frame DMA or Ethernet (in case 2048 * NPI mode is used). 2049 */ 2050 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2051 { 2052 int cpu = ocelot->num_phys_ports; 2053 2054 /* The unicast destination PGID for the CPU port module is unused */ 2055 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2056 /* Instead set up a multicast destination PGID for traffic copied to 2057 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2058 * addresses will be copied to the CPU via this PGID. 2059 */ 2060 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2061 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2062 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2063 ANA_PORT_PORT_CFG, cpu); 2064 2065 /* Enable CPU port module */ 2066 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2067 /* CPU port Injection/Extraction configuration */ 2068 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2069 OCELOT_TAG_PREFIX_NONE); 2070 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2071 OCELOT_TAG_PREFIX_NONE); 2072 2073 /* Configure the CPU port to be VLAN aware */ 2074 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2075 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2076 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2077 ANA_PORT_VLAN_CFG, cpu); 2078 } 2079 2080 static void ocelot_detect_features(struct ocelot *ocelot) 2081 { 2082 int mmgt, eq_ctrl; 2083 2084 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2085 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2086 * 192 bytes as the documentation incorrectly says. 2087 */ 2088 mmgt = ocelot_read(ocelot, SYS_MMGT); 2089 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2090 2091 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2092 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2093 } 2094 2095 int ocelot_init(struct ocelot *ocelot) 2096 { 2097 char queue_name[32]; 2098 int i, ret; 2099 u32 port; 2100 2101 if (ocelot->ops->reset) { 2102 ret = ocelot->ops->reset(ocelot); 2103 if (ret) { 2104 dev_err(ocelot->dev, "Switch reset failed\n"); 2105 return ret; 2106 } 2107 } 2108 2109 ocelot->stats = devm_kcalloc(ocelot->dev, 2110 ocelot->num_phys_ports * ocelot->num_stats, 2111 sizeof(u64), GFP_KERNEL); 2112 if (!ocelot->stats) 2113 return -ENOMEM; 2114 2115 mutex_init(&ocelot->stats_lock); 2116 mutex_init(&ocelot->ptp_lock); 2117 spin_lock_init(&ocelot->ptp_clock_lock); 2118 spin_lock_init(&ocelot->ts_id_lock); 2119 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2120 dev_name(ocelot->dev)); 2121 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2122 if (!ocelot->stats_queue) 2123 return -ENOMEM; 2124 2125 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2126 if (!ocelot->owq) { 2127 destroy_workqueue(ocelot->stats_queue); 2128 return -ENOMEM; 2129 } 2130 2131 INIT_LIST_HEAD(&ocelot->multicast); 2132 INIT_LIST_HEAD(&ocelot->pgids); 2133 ocelot_detect_features(ocelot); 2134 ocelot_mact_init(ocelot); 2135 ocelot_vlan_init(ocelot); 2136 ocelot_vcap_init(ocelot); 2137 ocelot_cpu_port_init(ocelot); 2138 2139 for (port = 0; port < ocelot->num_phys_ports; port++) { 2140 /* Clear all counters (5 groups) */ 2141 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2142 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2143 SYS_STAT_CFG); 2144 } 2145 2146 /* Only use S-Tag */ 2147 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2148 2149 /* Aggregation mode */ 2150 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2151 ANA_AGGR_CFG_AC_DMAC_ENA | 2152 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2153 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2154 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2155 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2156 ANA_AGGR_CFG); 2157 2158 /* Set MAC age time to default value. The entry is aged after 2159 * 2*AGE_PERIOD 2160 */ 2161 ocelot_write(ocelot, 2162 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2163 ANA_AUTOAGE); 2164 2165 /* Disable learning for frames discarded by VLAN ingress filtering */ 2166 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2167 2168 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2169 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2170 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2171 2172 /* Setup flooding PGIDs */ 2173 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2174 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2175 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2176 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2177 ANA_FLOODING, i); 2178 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2179 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2180 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2181 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2182 ANA_FLOODING_IPMC); 2183 2184 for (port = 0; port < ocelot->num_phys_ports; port++) { 2185 /* Transmit the frame to the local port. */ 2186 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2187 /* Do not forward BPDU frames to the front ports. */ 2188 ocelot_write_gix(ocelot, 2189 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2190 ANA_PORT_CPU_FWD_BPDU_CFG, 2191 port); 2192 /* Ensure bridging is disabled */ 2193 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2194 } 2195 2196 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2197 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2198 2199 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2200 } 2201 2202 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2203 2204 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2205 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2206 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2207 ANA_PGID_PGID, PGID_MC); 2208 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2209 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2210 ANA_PGID_PGID, PGID_BC); 2211 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2212 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2213 2214 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2215 * registers endianness. 2216 */ 2217 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2218 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2219 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2220 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2221 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2222 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2223 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2224 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2225 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2226 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2227 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2228 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2229 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2230 for (i = 0; i < 16; i++) 2231 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2232 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2233 ANA_CPUQ_8021_CFG, i); 2234 2235 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2236 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2237 OCELOT_STATS_CHECK_DELAY); 2238 2239 return 0; 2240 } 2241 EXPORT_SYMBOL(ocelot_init); 2242 2243 void ocelot_deinit(struct ocelot *ocelot) 2244 { 2245 cancel_delayed_work(&ocelot->stats_work); 2246 destroy_workqueue(ocelot->stats_queue); 2247 destroy_workqueue(ocelot->owq); 2248 mutex_destroy(&ocelot->stats_lock); 2249 } 2250 EXPORT_SYMBOL(ocelot_deinit); 2251 2252 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2253 { 2254 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2255 2256 skb_queue_purge(&ocelot_port->tx_skbs); 2257 } 2258 EXPORT_SYMBOL(ocelot_deinit_port); 2259 2260 MODULE_LICENSE("Dual MIT/GPL"); 2261