1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/iopoll.h> 10 #include <linux/phy/phy.h> 11 #include <soc/mscc/ocelot_hsio.h> 12 #include <soc/mscc/ocelot_vcap.h> 13 #include "ocelot.h" 14 #include "ocelot_vcap.h" 15 16 #define TABLE_UPDATE_SLEEP_US 10 17 #define TABLE_UPDATE_TIMEOUT_US 100000 18 #define MEM_INIT_SLEEP_US 1000 19 #define MEM_INIT_TIMEOUT_US 100000 20 21 #define OCELOT_RSV_VLAN_RANGE_START 4000 22 23 struct ocelot_mact_entry { 24 u8 mac[ETH_ALEN]; 25 u16 vid; 26 enum macaccess_entry_type type; 27 }; 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 31 { 32 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 33 } 34 35 /* Caller must hold &ocelot->mact_lock */ 36 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 37 { 38 u32 val; 39 40 return readx_poll_timeout(ocelot_mact_read_macaccess, 41 ocelot, val, 42 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 43 MACACCESS_CMD_IDLE, 44 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 45 } 46 47 /* Caller must hold &ocelot->mact_lock */ 48 static void ocelot_mact_select(struct ocelot *ocelot, 49 const unsigned char mac[ETH_ALEN], 50 unsigned int vid) 51 { 52 u32 macl = 0, mach = 0; 53 54 /* Set the MAC address to handle and the vlan associated in a format 55 * understood by the hardware. 56 */ 57 mach |= vid << 16; 58 mach |= mac[0] << 8; 59 mach |= mac[1] << 0; 60 macl |= mac[2] << 24; 61 macl |= mac[3] << 16; 62 macl |= mac[4] << 8; 63 macl |= mac[5] << 0; 64 65 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 66 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 67 68 } 69 70 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 71 const unsigned char mac[ETH_ALEN], 72 unsigned int vid, enum macaccess_entry_type type) 73 { 74 u32 cmd = ANA_TABLES_MACACCESS_VALID | 75 ANA_TABLES_MACACCESS_DEST_IDX(port) | 76 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 77 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 78 unsigned int mc_ports; 79 int err; 80 81 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 82 if (type == ENTRYTYPE_MACv4) 83 mc_ports = (mac[1] << 8) | mac[2]; 84 else if (type == ENTRYTYPE_MACv6) 85 mc_ports = (mac[0] << 8) | mac[1]; 86 else 87 mc_ports = 0; 88 89 if (mc_ports & BIT(ocelot->num_phys_ports)) 90 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 91 92 ocelot_mact_select(ocelot, mac, vid); 93 94 /* Issue a write command */ 95 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 96 97 err = ocelot_mact_wait_for_completion(ocelot); 98 99 return err; 100 } 101 102 int ocelot_mact_learn(struct ocelot *ocelot, int port, 103 const unsigned char mac[ETH_ALEN], 104 unsigned int vid, enum macaccess_entry_type type) 105 { 106 int ret; 107 108 mutex_lock(&ocelot->mact_lock); 109 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 110 mutex_unlock(&ocelot->mact_lock); 111 112 return ret; 113 } 114 EXPORT_SYMBOL(ocelot_mact_learn); 115 116 int ocelot_mact_forget(struct ocelot *ocelot, 117 const unsigned char mac[ETH_ALEN], unsigned int vid) 118 { 119 int err; 120 121 mutex_lock(&ocelot->mact_lock); 122 123 ocelot_mact_select(ocelot, mac, vid); 124 125 /* Issue a forget command */ 126 ocelot_write(ocelot, 127 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 128 ANA_TABLES_MACACCESS); 129 130 err = ocelot_mact_wait_for_completion(ocelot); 131 132 mutex_unlock(&ocelot->mact_lock); 133 134 return err; 135 } 136 EXPORT_SYMBOL(ocelot_mact_forget); 137 138 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 139 const unsigned char mac[ETH_ALEN], 140 unsigned int vid, enum macaccess_entry_type *type) 141 { 142 int val; 143 144 mutex_lock(&ocelot->mact_lock); 145 146 ocelot_mact_select(ocelot, mac, vid); 147 148 /* Issue a read command with MACACCESS_VALID=1. */ 149 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 150 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 151 ANA_TABLES_MACACCESS); 152 153 if (ocelot_mact_wait_for_completion(ocelot)) { 154 mutex_unlock(&ocelot->mact_lock); 155 return -ETIMEDOUT; 156 } 157 158 /* Read back the entry flags */ 159 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 160 161 mutex_unlock(&ocelot->mact_lock); 162 163 if (!(val & ANA_TABLES_MACACCESS_VALID)) 164 return -ENOENT; 165 166 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 167 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 168 169 return 0; 170 } 171 EXPORT_SYMBOL(ocelot_mact_lookup); 172 173 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 174 const unsigned char mac[ETH_ALEN], 175 unsigned int vid, 176 enum macaccess_entry_type type, 177 int sfid, int ssid) 178 { 179 int ret; 180 181 mutex_lock(&ocelot->mact_lock); 182 183 ocelot_write(ocelot, 184 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 185 ANA_TABLES_STREAMDATA_SFID(sfid) | 186 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 187 ANA_TABLES_STREAMDATA_SSID(ssid), 188 ANA_TABLES_STREAMDATA); 189 190 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 191 192 mutex_unlock(&ocelot->mact_lock); 193 194 return ret; 195 } 196 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 197 198 static void ocelot_mact_init(struct ocelot *ocelot) 199 { 200 /* Configure the learning mode entries attributes: 201 * - Do not copy the frame to the CPU extraction queues. 202 * - Use the vlan and mac_cpoy for dmac lookup. 203 */ 204 ocelot_rmw(ocelot, 0, 205 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 206 | ANA_AGENCTRL_LEARN_FWD_KILL 207 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 208 ANA_AGENCTRL); 209 210 /* Clear the MAC table. We are not concurrent with anyone, so 211 * holding &ocelot->mact_lock is pointless. 212 */ 213 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 214 } 215 216 void ocelot_pll5_init(struct ocelot *ocelot) 217 { 218 /* Configure PLL5. This will need a proper CCF driver 219 * The values are coming from the VTSS API for Ocelot 220 */ 221 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, 222 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | 223 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); 224 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, 225 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | 226 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | 227 HSIO_PLL5G_CFG0_ENA_BIAS | 228 HSIO_PLL5G_CFG0_ENA_VCO_BUF | 229 HSIO_PLL5G_CFG0_ENA_CP1 | 230 HSIO_PLL5G_CFG0_SELCPI(2) | 231 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | 232 HSIO_PLL5G_CFG0_SELBGV820(4) | 233 HSIO_PLL5G_CFG0_DIV4 | 234 HSIO_PLL5G_CFG0_ENA_CLKTREE | 235 HSIO_PLL5G_CFG0_ENA_LANE); 236 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, 237 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | 238 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | 239 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | 240 HSIO_PLL5G_CFG2_ENA_AMPCTRL | 241 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | 242 HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); 243 } 244 EXPORT_SYMBOL(ocelot_pll5_init); 245 246 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 247 { 248 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 249 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 250 ANA_PORT_VCAP_S2_CFG, port); 251 252 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 253 ANA_PORT_VCAP_CFG, port); 254 255 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 256 REW_PORT_CFG_ES0_EN, 257 REW_PORT_CFG, port); 258 } 259 260 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 261 struct netlink_ext_ack *extack) 262 { 263 struct net_device *bridge = NULL; 264 int port; 265 266 for (port = 0; port < ocelot->num_phys_ports; port++) { 267 struct ocelot_port *ocelot_port = ocelot->ports[port]; 268 269 if (!ocelot_port || !ocelot_port->bridge || 270 !br_vlan_enabled(ocelot_port->bridge)) 271 continue; 272 273 if (!bridge) { 274 bridge = ocelot_port->bridge; 275 continue; 276 } 277 278 if (bridge == ocelot_port->bridge) 279 continue; 280 281 NL_SET_ERR_MSG_MOD(extack, 282 "Only one VLAN-aware bridge is supported"); 283 return -EBUSY; 284 } 285 286 return 0; 287 } 288 289 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 290 { 291 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 292 } 293 294 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 295 { 296 u32 val; 297 298 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 299 ocelot, 300 val, 301 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 302 ANA_TABLES_VLANACCESS_CMD_IDLE, 303 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 304 } 305 306 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 307 { 308 /* Select the VID to configure */ 309 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 310 ANA_TABLES_VLANTIDX); 311 /* Set the vlan port members mask and issue a write command */ 312 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 313 ANA_TABLES_VLANACCESS_CMD_WRITE, 314 ANA_TABLES_VLANACCESS); 315 316 return ocelot_vlant_wait_for_completion(ocelot); 317 } 318 319 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 320 { 321 struct ocelot_bridge_vlan *vlan; 322 int num_untagged = 0; 323 324 list_for_each_entry(vlan, &ocelot->vlans, list) { 325 if (!(vlan->portmask & BIT(port))) 326 continue; 327 328 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(), 329 * because this is never active in hardware at the same time as 330 * the bridge VLANs, which only matter in VLAN-aware mode. 331 */ 332 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START) 333 continue; 334 335 if (vlan->untagged & BIT(port)) 336 num_untagged++; 337 } 338 339 return num_untagged; 340 } 341 342 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 343 { 344 struct ocelot_bridge_vlan *vlan; 345 int num_tagged = 0; 346 347 list_for_each_entry(vlan, &ocelot->vlans, list) { 348 if (!(vlan->portmask & BIT(port))) 349 continue; 350 351 if (!(vlan->untagged & BIT(port))) 352 num_tagged++; 353 } 354 355 return num_tagged; 356 } 357 358 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 359 * _one_ egress-untagged VLAN (_the_ native VLAN) 360 */ 361 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 362 { 363 return ocelot_port_num_tagged_vlans(ocelot, port) && 364 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 365 } 366 367 static struct ocelot_bridge_vlan * 368 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 369 { 370 struct ocelot_bridge_vlan *vlan; 371 372 list_for_each_entry(vlan, &ocelot->vlans, list) 373 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 374 return vlan; 375 376 return NULL; 377 } 378 379 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 380 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 381 * state of the port. 382 */ 383 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 384 { 385 struct ocelot_port *ocelot_port = ocelot->ports[port]; 386 enum ocelot_port_tag_config tag_cfg; 387 bool uses_native_vlan = false; 388 389 if (ocelot_port->vlan_aware) { 390 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 391 392 if (uses_native_vlan) 393 tag_cfg = OCELOT_PORT_TAG_NATIVE; 394 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 395 tag_cfg = OCELOT_PORT_TAG_DISABLED; 396 else 397 tag_cfg = OCELOT_PORT_TAG_TRUNK; 398 } else { 399 tag_cfg = OCELOT_PORT_TAG_DISABLED; 400 } 401 402 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 403 REW_TAG_CFG_TAG_CFG_M, 404 REW_TAG_CFG, port); 405 406 if (uses_native_vlan) { 407 struct ocelot_bridge_vlan *native_vlan; 408 409 /* Not having a native VLAN is impossible, because 410 * ocelot_port_num_untagged_vlans has returned 1. 411 * So there is no use in checking for NULL here. 412 */ 413 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 414 415 ocelot_rmw_gix(ocelot, 416 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 417 REW_PORT_VLAN_CFG_PORT_VID_M, 418 REW_PORT_VLAN_CFG, port); 419 } 420 } 421 422 int ocelot_bridge_num_find(struct ocelot *ocelot, 423 const struct net_device *bridge) 424 { 425 int port; 426 427 for (port = 0; port < ocelot->num_phys_ports; port++) { 428 struct ocelot_port *ocelot_port = ocelot->ports[port]; 429 430 if (ocelot_port && ocelot_port->bridge == bridge) 431 return ocelot_port->bridge_num; 432 } 433 434 return -1; 435 } 436 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 437 438 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 439 const struct net_device *bridge) 440 { 441 int bridge_num; 442 443 /* Standalone ports use VID 0 */ 444 if (!bridge) 445 return 0; 446 447 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 448 if (WARN_ON(bridge_num < 0)) 449 return 0; 450 451 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 452 return VLAN_N_VID - bridge_num - 1; 453 } 454 455 /* Default vlan to clasify for untagged frames (may be zero) */ 456 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 457 const struct ocelot_bridge_vlan *pvid_vlan) 458 { 459 struct ocelot_port *ocelot_port = ocelot->ports[port]; 460 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 461 u32 val = 0; 462 463 ocelot_port->pvid_vlan = pvid_vlan; 464 465 if (ocelot_port->vlan_aware && pvid_vlan) 466 pvid = pvid_vlan->vid; 467 468 ocelot_rmw_gix(ocelot, 469 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 470 ANA_PORT_VLAN_CFG_VLAN_VID_M, 471 ANA_PORT_VLAN_CFG, port); 472 473 /* If there's no pvid, we should drop not only untagged traffic (which 474 * happens automatically), but also 802.1p traffic which gets 475 * classified to VLAN 0, but that is always in our RX filter, so it 476 * would get accepted were it not for this setting. 477 */ 478 if (!pvid_vlan && ocelot_port->vlan_aware) 479 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 480 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 481 482 ocelot_rmw_gix(ocelot, val, 483 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 484 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 485 ANA_PORT_DROP_CFG, port); 486 } 487 488 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 489 u16 vid) 490 { 491 struct ocelot_bridge_vlan *vlan; 492 493 list_for_each_entry(vlan, &ocelot->vlans, list) 494 if (vlan->vid == vid) 495 return vlan; 496 497 return NULL; 498 } 499 500 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 501 bool untagged) 502 { 503 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 504 unsigned long portmask; 505 int err; 506 507 if (vlan) { 508 portmask = vlan->portmask | BIT(port); 509 510 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 511 if (err) 512 return err; 513 514 vlan->portmask = portmask; 515 /* Bridge VLANs can be overwritten with a different 516 * egress-tagging setting, so make sure to override an untagged 517 * with a tagged VID if that's going on. 518 */ 519 if (untagged) 520 vlan->untagged |= BIT(port); 521 else 522 vlan->untagged &= ~BIT(port); 523 524 return 0; 525 } 526 527 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 528 if (!vlan) 529 return -ENOMEM; 530 531 portmask = BIT(port); 532 533 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 534 if (err) { 535 kfree(vlan); 536 return err; 537 } 538 539 vlan->vid = vid; 540 vlan->portmask = portmask; 541 if (untagged) 542 vlan->untagged = BIT(port); 543 INIT_LIST_HEAD(&vlan->list); 544 list_add_tail(&vlan->list, &ocelot->vlans); 545 546 return 0; 547 } 548 549 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 552 unsigned long portmask; 553 int err; 554 555 if (!vlan) 556 return 0; 557 558 portmask = vlan->portmask & ~BIT(port); 559 560 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 561 if (err) 562 return err; 563 564 vlan->portmask = portmask; 565 if (vlan->portmask) 566 return 0; 567 568 list_del(&vlan->list); 569 kfree(vlan); 570 571 return 0; 572 } 573 574 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 575 const struct net_device *bridge) 576 { 577 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 578 579 return ocelot_vlan_member_add(ocelot, port, vid, true); 580 } 581 582 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 583 const struct net_device *bridge) 584 { 585 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 586 587 return ocelot_vlan_member_del(ocelot, port, vid); 588 } 589 590 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 591 bool vlan_aware, struct netlink_ext_ack *extack) 592 { 593 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 594 struct ocelot_port *ocelot_port = ocelot->ports[port]; 595 struct ocelot_vcap_filter *filter; 596 int err = 0; 597 u32 val; 598 599 list_for_each_entry(filter, &block->rules, list) { 600 if (filter->ingress_port_mask & BIT(port) && 601 filter->action.vid_replace_ena) { 602 NL_SET_ERR_MSG_MOD(extack, 603 "Cannot change VLAN state with vlan modify rules active"); 604 return -EBUSY; 605 } 606 } 607 608 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 609 if (err) 610 return err; 611 612 if (vlan_aware) 613 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 614 ocelot_port->bridge); 615 else if (ocelot_port->bridge) 616 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 617 ocelot_port->bridge); 618 if (err) 619 return err; 620 621 ocelot_port->vlan_aware = vlan_aware; 622 623 if (vlan_aware) 624 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 625 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 626 else 627 val = 0; 628 ocelot_rmw_gix(ocelot, val, 629 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 630 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 631 ANA_PORT_VLAN_CFG, port); 632 633 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 634 ocelot_port_manage_port_tag(ocelot, port); 635 636 return 0; 637 } 638 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 639 640 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 641 bool untagged, struct netlink_ext_ack *extack) 642 { 643 if (untagged) { 644 /* We are adding an egress-tagged VLAN */ 645 if (ocelot_port_uses_native_vlan(ocelot, port)) { 646 NL_SET_ERR_MSG_MOD(extack, 647 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 648 return -EBUSY; 649 } 650 } else { 651 /* We are adding an egress-tagged VLAN */ 652 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 653 NL_SET_ERR_MSG_MOD(extack, 654 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 655 return -EBUSY; 656 } 657 } 658 659 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 660 NL_SET_ERR_MSG_MOD(extack, 661 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 662 return -EBUSY; 663 } 664 665 return 0; 666 } 667 EXPORT_SYMBOL(ocelot_vlan_prepare); 668 669 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 670 bool untagged) 671 { 672 int err; 673 674 /* Ignore VID 0 added to our RX filter by the 8021q module, since 675 * that collides with OCELOT_STANDALONE_PVID and changes it from 676 * egress-untagged to egress-tagged. 677 */ 678 if (!vid) 679 return 0; 680 681 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 682 if (err) 683 return err; 684 685 /* Default ingress vlan classification */ 686 if (pvid) 687 ocelot_port_set_pvid(ocelot, port, 688 ocelot_bridge_vlan_find(ocelot, vid)); 689 690 /* Untagged egress vlan clasification */ 691 ocelot_port_manage_port_tag(ocelot, port); 692 693 return 0; 694 } 695 EXPORT_SYMBOL(ocelot_vlan_add); 696 697 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 698 { 699 struct ocelot_port *ocelot_port = ocelot->ports[port]; 700 bool del_pvid = false; 701 int err; 702 703 if (!vid) 704 return 0; 705 706 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 707 del_pvid = true; 708 709 err = ocelot_vlan_member_del(ocelot, port, vid); 710 if (err) 711 return err; 712 713 /* Ingress */ 714 if (del_pvid) 715 ocelot_port_set_pvid(ocelot, port, NULL); 716 717 /* Egress */ 718 ocelot_port_manage_port_tag(ocelot, port); 719 720 return 0; 721 } 722 EXPORT_SYMBOL(ocelot_vlan_del); 723 724 static void ocelot_vlan_init(struct ocelot *ocelot) 725 { 726 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 727 u16 port, vid; 728 729 /* Clear VLAN table, by default all ports are members of all VLANs */ 730 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 731 ANA_TABLES_VLANACCESS); 732 ocelot_vlant_wait_for_completion(ocelot); 733 734 /* Configure the port VLAN memberships */ 735 for (vid = 1; vid < VLAN_N_VID; vid++) 736 ocelot_vlant_set_mask(ocelot, vid, 0); 737 738 /* We need VID 0 to get traffic on standalone ports. 739 * It is added automatically if the 8021q module is loaded, but we 740 * can't rely on that since it might not be. 741 */ 742 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 743 744 /* Set vlan ingress filter mask to all ports but the CPU port by 745 * default. 746 */ 747 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 748 749 for (port = 0; port < ocelot->num_phys_ports; port++) { 750 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 751 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 752 } 753 } 754 755 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 756 { 757 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 758 } 759 760 static int ocelot_port_flush(struct ocelot *ocelot, int port) 761 { 762 unsigned int pause_ena; 763 int err, val; 764 765 /* Disable dequeuing from the egress queues */ 766 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 767 QSYS_PORT_MODE_DEQUEUE_DIS, 768 QSYS_PORT_MODE, port); 769 770 /* Disable flow control */ 771 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 772 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 773 774 /* Disable priority flow control */ 775 ocelot_fields_write(ocelot, port, 776 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 777 778 /* Wait at least the time it takes to receive a frame of maximum length 779 * at the port. 780 * Worst-case delays for 10 kilobyte jumbo frames are: 781 * 8 ms on a 10M port 782 * 800 μs on a 100M port 783 * 80 μs on a 1G port 784 * 32 μs on a 2.5G port 785 */ 786 usleep_range(8000, 10000); 787 788 /* Disable half duplex backpressure. */ 789 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 790 SYS_FRONT_PORT_MODE, port); 791 792 /* Flush the queues associated with the port. */ 793 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 794 REW_PORT_CFG, port); 795 796 /* Enable dequeuing from the egress queues. */ 797 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 798 port); 799 800 /* Wait until flushing is complete. */ 801 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 802 100, 2000000, false, ocelot, port); 803 804 /* Clear flushing again. */ 805 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 806 807 /* Re-enable flow control */ 808 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 809 810 return err; 811 } 812 813 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port, 814 struct device_node *portnp) 815 { 816 struct ocelot_port *ocelot_port = ocelot->ports[port]; 817 struct device *dev = ocelot->dev; 818 int err; 819 820 /* Ensure clock signals and speed are set on all QSGMII links */ 821 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII) 822 ocelot_port_rmwl(ocelot_port, 0, 823 DEV_CLOCK_CFG_MAC_TX_RST | 824 DEV_CLOCK_CFG_MAC_RX_RST, 825 DEV_CLOCK_CFG); 826 827 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) { 828 struct phy *serdes = of_phy_get(portnp, NULL); 829 830 if (IS_ERR(serdes)) { 831 err = PTR_ERR(serdes); 832 dev_err_probe(dev, err, 833 "missing SerDes phys for port %d\n", 834 port); 835 return err; 836 } 837 838 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, 839 ocelot_port->phy_mode); 840 of_phy_put(serdes); 841 if (err) { 842 dev_err(dev, "Could not SerDes mode on port %d: %pe\n", 843 port, ERR_PTR(err)); 844 return err; 845 } 846 } 847 848 return 0; 849 } 850 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes); 851 852 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, 853 unsigned int link_an_mode, 854 const struct phylink_link_state *state) 855 { 856 struct ocelot_port *ocelot_port = ocelot->ports[port]; 857 858 /* Disable HDX fast control */ 859 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 860 DEV_PORT_MISC); 861 862 /* SGMII only for now */ 863 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 864 PCS1G_MODE_CFG); 865 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 866 867 /* Enable PCS */ 868 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 869 870 /* No aneg on SGMII */ 871 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 872 873 /* No loopback */ 874 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 875 } 876 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config); 877 878 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 879 unsigned int link_an_mode, 880 phy_interface_t interface, 881 unsigned long quirks) 882 { 883 struct ocelot_port *ocelot_port = ocelot->ports[port]; 884 int err; 885 886 ocelot_port->speed = SPEED_UNKNOWN; 887 888 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 889 DEV_MAC_ENA_CFG); 890 891 if (ocelot->ops->cut_through_fwd) { 892 mutex_lock(&ocelot->fwd_domain_lock); 893 ocelot->ops->cut_through_fwd(ocelot); 894 mutex_unlock(&ocelot->fwd_domain_lock); 895 } 896 897 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 898 899 err = ocelot_port_flush(ocelot, port); 900 if (err) 901 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 902 port, err); 903 904 /* Put the port in reset. */ 905 if (interface != PHY_INTERFACE_MODE_QSGMII || 906 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 907 ocelot_port_rmwl(ocelot_port, 908 DEV_CLOCK_CFG_MAC_TX_RST | 909 DEV_CLOCK_CFG_MAC_RX_RST, 910 DEV_CLOCK_CFG_MAC_TX_RST | 911 DEV_CLOCK_CFG_MAC_RX_RST, 912 DEV_CLOCK_CFG); 913 } 914 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 915 916 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 917 struct phy_device *phydev, 918 unsigned int link_an_mode, 919 phy_interface_t interface, 920 int speed, int duplex, 921 bool tx_pause, bool rx_pause, 922 unsigned long quirks) 923 { 924 struct ocelot_port *ocelot_port = ocelot->ports[port]; 925 int mac_speed, mode = 0; 926 u32 mac_fc_cfg; 927 928 ocelot_port->speed = speed; 929 930 /* The MAC might be integrated in systems where the MAC speed is fixed 931 * and it's the PCS who is performing the rate adaptation, so we have 932 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 933 * (which is also its default value). 934 */ 935 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 936 speed == SPEED_1000) { 937 mac_speed = OCELOT_SPEED_1000; 938 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 939 } else if (speed == SPEED_2500) { 940 mac_speed = OCELOT_SPEED_2500; 941 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 942 } else if (speed == SPEED_100) { 943 mac_speed = OCELOT_SPEED_100; 944 } else { 945 mac_speed = OCELOT_SPEED_10; 946 } 947 948 if (duplex == DUPLEX_FULL) 949 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 950 951 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 952 953 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 954 * PORT_RST bits in DEV_CLOCK_CFG. 955 */ 956 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 957 DEV_CLOCK_CFG); 958 959 switch (speed) { 960 case SPEED_10: 961 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 962 break; 963 case SPEED_100: 964 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 965 break; 966 case SPEED_1000: 967 case SPEED_2500: 968 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 969 break; 970 default: 971 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 972 port, speed); 973 return; 974 } 975 976 if (rx_pause) 977 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 978 979 if (tx_pause) 980 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 981 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 982 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 983 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 984 985 /* Flow control. Link speed is only used here to evaluate the time 986 * specification in incoming pause frames. 987 */ 988 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 989 990 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 991 992 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 993 if (port != ocelot->npi) 994 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 995 tx_pause); 996 997 /* Undo the effects of ocelot_phylink_mac_link_down: 998 * enable MAC module 999 */ 1000 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 1001 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 1002 1003 /* If the port supports cut-through forwarding, update the masks before 1004 * enabling forwarding on the port. 1005 */ 1006 if (ocelot->ops->cut_through_fwd) { 1007 mutex_lock(&ocelot->fwd_domain_lock); 1008 ocelot->ops->cut_through_fwd(ocelot); 1009 mutex_unlock(&ocelot->fwd_domain_lock); 1010 } 1011 1012 /* Core: Enable port for frame transfer */ 1013 ocelot_fields_write(ocelot, port, 1014 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1015 } 1016 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 1017 1018 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1019 u32 *rval) 1020 { 1021 u32 bytes_valid, val; 1022 1023 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1024 if (val == XTR_NOT_READY) { 1025 if (ifh) 1026 return -EIO; 1027 1028 do { 1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1030 } while (val == XTR_NOT_READY); 1031 } 1032 1033 switch (val) { 1034 case XTR_ABORT: 1035 return -EIO; 1036 case XTR_EOF_0: 1037 case XTR_EOF_1: 1038 case XTR_EOF_2: 1039 case XTR_EOF_3: 1040 case XTR_PRUNED: 1041 bytes_valid = XTR_VALID_BYTES(val); 1042 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1043 if (val == XTR_ESCAPE) 1044 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1045 else 1046 *rval = val; 1047 1048 return bytes_valid; 1049 case XTR_ESCAPE: 1050 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1051 1052 return 4; 1053 default: 1054 *rval = val; 1055 1056 return 4; 1057 } 1058 } 1059 1060 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1061 { 1062 int i, err = 0; 1063 1064 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1065 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1066 if (err != 4) 1067 return (err < 0) ? err : -EIO; 1068 } 1069 1070 return 0; 1071 } 1072 1073 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1074 u64 timestamp) 1075 { 1076 struct skb_shared_hwtstamps *shhwtstamps; 1077 u64 tod_in_ns, full_ts_in_ns; 1078 struct timespec64 ts; 1079 1080 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1081 1082 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1083 if ((tod_in_ns & 0xffffffff) < timestamp) 1084 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1085 timestamp; 1086 else 1087 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1088 timestamp; 1089 1090 shhwtstamps = skb_hwtstamps(skb); 1091 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1092 shhwtstamps->hwtstamp = full_ts_in_ns; 1093 } 1094 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1095 1096 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1097 { 1098 u64 timestamp, src_port, len; 1099 u32 xfh[OCELOT_TAG_LEN / 4]; 1100 struct net_device *dev; 1101 struct sk_buff *skb; 1102 int sz, buf_len; 1103 u32 val, *buf; 1104 int err; 1105 1106 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1107 if (err) 1108 return err; 1109 1110 ocelot_xfh_get_src_port(xfh, &src_port); 1111 ocelot_xfh_get_len(xfh, &len); 1112 ocelot_xfh_get_rew_val(xfh, ×tamp); 1113 1114 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1115 return -EINVAL; 1116 1117 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1118 if (!dev) 1119 return -EINVAL; 1120 1121 skb = netdev_alloc_skb(dev, len); 1122 if (unlikely(!skb)) { 1123 netdev_err(dev, "Unable to allocate sk_buff\n"); 1124 return -ENOMEM; 1125 } 1126 1127 buf_len = len - ETH_FCS_LEN; 1128 buf = (u32 *)skb_put(skb, buf_len); 1129 1130 len = 0; 1131 do { 1132 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1133 if (sz < 0) { 1134 err = sz; 1135 goto out_free_skb; 1136 } 1137 *buf++ = val; 1138 len += sz; 1139 } while (len < buf_len); 1140 1141 /* Read the FCS */ 1142 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1143 if (sz < 0) { 1144 err = sz; 1145 goto out_free_skb; 1146 } 1147 1148 /* Update the statistics if part of the FCS was read before */ 1149 len -= ETH_FCS_LEN - sz; 1150 1151 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1152 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1153 *buf = val; 1154 } 1155 1156 if (ocelot->ptp) 1157 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1158 1159 /* Everything we see on an interface that is in the HW bridge 1160 * has already been forwarded. 1161 */ 1162 if (ocelot->ports[src_port]->bridge) 1163 skb->offload_fwd_mark = 1; 1164 1165 skb->protocol = eth_type_trans(skb, dev); 1166 1167 *nskb = skb; 1168 1169 return 0; 1170 1171 out_free_skb: 1172 kfree_skb(skb); 1173 return err; 1174 } 1175 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1176 1177 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1178 { 1179 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1180 1181 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1182 return false; 1183 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1184 return false; 1185 1186 return true; 1187 } 1188 EXPORT_SYMBOL(ocelot_can_inject); 1189 1190 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1191 { 1192 ocelot_ifh_set_bypass(ifh, 1); 1193 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1194 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1195 if (vlan_tag) 1196 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1197 if (rew_op) 1198 ocelot_ifh_set_rew_op(ifh, rew_op); 1199 } 1200 EXPORT_SYMBOL(ocelot_ifh_port_set); 1201 1202 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1203 u32 rew_op, struct sk_buff *skb) 1204 { 1205 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1206 unsigned int i, count, last; 1207 1208 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1209 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1210 1211 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1212 1213 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1214 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1215 1216 count = DIV_ROUND_UP(skb->len, 4); 1217 last = skb->len % 4; 1218 for (i = 0; i < count; i++) 1219 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1220 1221 /* Add padding */ 1222 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1223 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1224 i++; 1225 } 1226 1227 /* Indicate EOF and valid bytes in last word */ 1228 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1229 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1230 QS_INJ_CTRL_EOF, 1231 QS_INJ_CTRL, grp); 1232 1233 /* Add dummy CRC */ 1234 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1235 skb_tx_timestamp(skb); 1236 1237 skb->dev->stats.tx_packets++; 1238 skb->dev->stats.tx_bytes += skb->len; 1239 } 1240 EXPORT_SYMBOL(ocelot_port_inject_frame); 1241 1242 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1243 { 1244 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1245 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1246 } 1247 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1248 1249 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1250 u16 vid, const struct net_device *bridge) 1251 { 1252 if (!vid) 1253 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1254 1255 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 1256 } 1257 EXPORT_SYMBOL(ocelot_fdb_add); 1258 1259 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1260 u16 vid, const struct net_device *bridge) 1261 { 1262 if (!vid) 1263 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1264 1265 return ocelot_mact_forget(ocelot, addr, vid); 1266 } 1267 EXPORT_SYMBOL(ocelot_fdb_del); 1268 1269 /* Caller must hold &ocelot->mact_lock */ 1270 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1271 struct ocelot_mact_entry *entry) 1272 { 1273 u32 val, dst, macl, mach; 1274 char mac[ETH_ALEN]; 1275 1276 /* Set row and column to read from */ 1277 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1278 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1279 1280 /* Issue a read command */ 1281 ocelot_write(ocelot, 1282 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1283 ANA_TABLES_MACACCESS); 1284 1285 if (ocelot_mact_wait_for_completion(ocelot)) 1286 return -ETIMEDOUT; 1287 1288 /* Read the entry flags */ 1289 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1290 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1291 return -EINVAL; 1292 1293 /* If the entry read has another port configured as its destination, 1294 * do not report it. 1295 */ 1296 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1297 if (dst != port) 1298 return -EINVAL; 1299 1300 /* Get the entry's MAC address and VLAN id */ 1301 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1302 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1303 1304 mac[0] = (mach >> 8) & 0xff; 1305 mac[1] = (mach >> 0) & 0xff; 1306 mac[2] = (macl >> 24) & 0xff; 1307 mac[3] = (macl >> 16) & 0xff; 1308 mac[4] = (macl >> 8) & 0xff; 1309 mac[5] = (macl >> 0) & 0xff; 1310 1311 entry->vid = (mach >> 16) & 0xfff; 1312 ether_addr_copy(entry->mac, mac); 1313 1314 return 0; 1315 } 1316 1317 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1318 { 1319 int err; 1320 1321 mutex_lock(&ocelot->mact_lock); 1322 1323 /* Program ageing filter for a single port */ 1324 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1325 ANA_ANAGEFIL); 1326 1327 /* Flushing dynamic FDB entries requires two successive age scans */ 1328 ocelot_write(ocelot, 1329 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1330 ANA_TABLES_MACACCESS); 1331 1332 err = ocelot_mact_wait_for_completion(ocelot); 1333 if (err) { 1334 mutex_unlock(&ocelot->mact_lock); 1335 return err; 1336 } 1337 1338 /* And second... */ 1339 ocelot_write(ocelot, 1340 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1341 ANA_TABLES_MACACCESS); 1342 1343 err = ocelot_mact_wait_for_completion(ocelot); 1344 1345 /* Restore ageing filter */ 1346 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1347 1348 mutex_unlock(&ocelot->mact_lock); 1349 1350 return err; 1351 } 1352 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1353 1354 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1355 dsa_fdb_dump_cb_t *cb, void *data) 1356 { 1357 int err = 0; 1358 int i, j; 1359 1360 /* We could take the lock just around ocelot_mact_read, but doing so 1361 * thousands of times in a row seems rather pointless and inefficient. 1362 */ 1363 mutex_lock(&ocelot->mact_lock); 1364 1365 /* Loop through all the mac tables entries. */ 1366 for (i = 0; i < ocelot->num_mact_rows; i++) { 1367 for (j = 0; j < 4; j++) { 1368 struct ocelot_mact_entry entry; 1369 bool is_static; 1370 1371 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1372 /* If the entry is invalid (wrong port, invalid...), 1373 * skip it. 1374 */ 1375 if (err == -EINVAL) 1376 continue; 1377 else if (err) 1378 break; 1379 1380 is_static = (entry.type == ENTRYTYPE_LOCKED); 1381 1382 /* Hide the reserved VLANs used for 1383 * VLAN-unaware bridging. 1384 */ 1385 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1386 entry.vid = 0; 1387 1388 err = cb(entry.mac, entry.vid, is_static, data); 1389 if (err) 1390 break; 1391 } 1392 } 1393 1394 mutex_unlock(&ocelot->mact_lock); 1395 1396 return err; 1397 } 1398 EXPORT_SYMBOL(ocelot_fdb_dump); 1399 1400 int ocelot_trap_add(struct ocelot *ocelot, int port, 1401 unsigned long cookie, bool take_ts, 1402 void (*populate)(struct ocelot_vcap_filter *f)) 1403 { 1404 struct ocelot_vcap_block *block_vcap_is2; 1405 struct ocelot_vcap_filter *trap; 1406 bool new = false; 1407 int err; 1408 1409 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1410 1411 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1412 false); 1413 if (!trap) { 1414 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1415 if (!trap) 1416 return -ENOMEM; 1417 1418 populate(trap); 1419 trap->prio = 1; 1420 trap->id.cookie = cookie; 1421 trap->id.tc_offload = false; 1422 trap->block_id = VCAP_IS2; 1423 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1424 trap->lookup = 0; 1425 trap->action.cpu_copy_ena = true; 1426 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1427 trap->action.port_mask = 0; 1428 trap->take_ts = take_ts; 1429 trap->is_trap = true; 1430 new = true; 1431 } 1432 1433 trap->ingress_port_mask |= BIT(port); 1434 1435 if (new) 1436 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1437 else 1438 err = ocelot_vcap_filter_replace(ocelot, trap); 1439 if (err) { 1440 trap->ingress_port_mask &= ~BIT(port); 1441 if (!trap->ingress_port_mask) 1442 kfree(trap); 1443 return err; 1444 } 1445 1446 return 0; 1447 } 1448 1449 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1450 { 1451 struct ocelot_vcap_block *block_vcap_is2; 1452 struct ocelot_vcap_filter *trap; 1453 1454 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1455 1456 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1457 false); 1458 if (!trap) 1459 return 0; 1460 1461 trap->ingress_port_mask &= ~BIT(port); 1462 if (!trap->ingress_port_mask) 1463 return ocelot_vcap_filter_del(ocelot, trap); 1464 1465 return ocelot_vcap_filter_replace(ocelot, trap); 1466 } 1467 1468 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1469 { 1470 u32 mask = 0; 1471 int port; 1472 1473 lockdep_assert_held(&ocelot->fwd_domain_lock); 1474 1475 for (port = 0; port < ocelot->num_phys_ports; port++) { 1476 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1477 1478 if (!ocelot_port) 1479 continue; 1480 1481 if (ocelot_port->bond == bond) 1482 mask |= BIT(port); 1483 } 1484 1485 return mask; 1486 } 1487 1488 /* The logical port number of a LAG is equal to the lowest numbered physical 1489 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1490 */ 1491 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1492 { 1493 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1494 1495 if (!bond_mask) 1496 return -ENOENT; 1497 1498 return __ffs(bond_mask); 1499 } 1500 EXPORT_SYMBOL_GPL(ocelot_bond_get_id); 1501 1502 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port. 1503 * Note that when CPU ports are in a LAG, the user ports are assigned to the 1504 * 'primary' CPU port, the one whose physical port number gives the logical 1505 * port number of the LAG. 1506 * 1507 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG 1508 * (to which no user port is assigned), but it appears that forwarding from 1509 * this secondary CPU port looks at the PGID_SRC associated with the logical 1510 * port ID that it's assigned to, which *is* configured properly. 1511 */ 1512 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot, 1513 struct ocelot_port *cpu) 1514 { 1515 u32 mask = 0; 1516 int port; 1517 1518 for (port = 0; port < ocelot->num_phys_ports; port++) { 1519 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1520 1521 if (!ocelot_port) 1522 continue; 1523 1524 if (ocelot_port->dsa_8021q_cpu == cpu) 1525 mask |= BIT(port); 1526 } 1527 1528 if (cpu->bond) 1529 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond); 1530 1531 return mask; 1532 } 1533 1534 /* Returns the DSA tag_8021q CPU port that the given port is assigned to, 1535 * or the bit mask of CPU ports if said CPU port is in a LAG. 1536 */ 1537 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port) 1538 { 1539 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1540 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu; 1541 1542 if (!cpu_port) 1543 return 0; 1544 1545 if (cpu_port->bond) 1546 return ocelot_get_bond_mask(ocelot, cpu_port->bond); 1547 1548 return BIT(cpu_port->index); 1549 } 1550 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask); 1551 1552 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1553 { 1554 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1555 const struct net_device *bridge; 1556 u32 mask = 0; 1557 int port; 1558 1559 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1560 return 0; 1561 1562 bridge = ocelot_port->bridge; 1563 if (!bridge) 1564 return 0; 1565 1566 for (port = 0; port < ocelot->num_phys_ports; port++) { 1567 ocelot_port = ocelot->ports[port]; 1568 1569 if (!ocelot_port) 1570 continue; 1571 1572 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1573 ocelot_port->bridge == bridge) 1574 mask |= BIT(port); 1575 } 1576 1577 return mask; 1578 } 1579 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1580 1581 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1582 { 1583 int port; 1584 1585 lockdep_assert_held(&ocelot->fwd_domain_lock); 1586 1587 /* If cut-through forwarding is supported, update the masks before a 1588 * port joins the forwarding domain, to avoid potential underruns if it 1589 * has the highest speed from the new domain. 1590 */ 1591 if (joining && ocelot->ops->cut_through_fwd) 1592 ocelot->ops->cut_through_fwd(ocelot); 1593 1594 /* Apply FWD mask. The loop is needed to add/remove the current port as 1595 * a source for the other ports. 1596 */ 1597 for (port = 0; port < ocelot->num_phys_ports; port++) { 1598 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1599 unsigned long mask; 1600 1601 if (!ocelot_port) { 1602 /* Unused ports can't send anywhere */ 1603 mask = 0; 1604 } else if (ocelot_port->is_dsa_8021q_cpu) { 1605 /* The DSA tag_8021q CPU ports need to be able to 1606 * forward packets to all ports assigned to them. 1607 */ 1608 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot, 1609 ocelot_port); 1610 } else if (ocelot_port->bridge) { 1611 struct net_device *bond = ocelot_port->bond; 1612 1613 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1614 mask &= ~BIT(port); 1615 1616 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1617 port); 1618 1619 if (bond) 1620 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1621 } else { 1622 /* Standalone ports forward only to DSA tag_8021q CPU 1623 * ports (if those exist), or to the hardware CPU port 1624 * module otherwise. 1625 */ 1626 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1627 port); 1628 } 1629 1630 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1631 } 1632 1633 /* If cut-through forwarding is supported and a port is leaving, there 1634 * is a chance that cut-through was disabled on the other ports due to 1635 * the port which is leaving (it has a higher link speed). We need to 1636 * update the cut-through masks of the remaining ports no earlier than 1637 * after the port has left, to prevent underruns from happening between 1638 * the cut-through update and the forwarding domain update. 1639 */ 1640 if (!joining && ocelot->ops->cut_through_fwd) 1641 ocelot->ops->cut_through_fwd(ocelot); 1642 } 1643 1644 /* Update PGID_CPU which is the destination port mask used for whitelisting 1645 * unicast addresses filtered towards the host. In the normal and NPI modes, 1646 * this points to the analyzer entry for the CPU port module, while in DSA 1647 * tag_8021q mode, it is a bit mask of all active CPU ports. 1648 * PGID_SRC will take care of forwarding a packet from one user port to 1649 * no more than a single CPU port. 1650 */ 1651 static void ocelot_update_pgid_cpu(struct ocelot *ocelot) 1652 { 1653 int pgid_cpu = 0; 1654 int port; 1655 1656 for (port = 0; port < ocelot->num_phys_ports; port++) { 1657 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1658 1659 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu) 1660 continue; 1661 1662 pgid_cpu |= BIT(port); 1663 } 1664 1665 if (!pgid_cpu) 1666 pgid_cpu = BIT(ocelot->num_phys_ports); 1667 1668 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); 1669 } 1670 1671 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1672 { 1673 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1674 u16 vid; 1675 1676 mutex_lock(&ocelot->fwd_domain_lock); 1677 1678 cpu_port->is_dsa_8021q_cpu = true; 1679 1680 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1681 ocelot_vlan_member_add(ocelot, cpu, vid, true); 1682 1683 ocelot_update_pgid_cpu(ocelot); 1684 1685 mutex_unlock(&ocelot->fwd_domain_lock); 1686 } 1687 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); 1688 1689 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1690 { 1691 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1692 u16 vid; 1693 1694 mutex_lock(&ocelot->fwd_domain_lock); 1695 1696 cpu_port->is_dsa_8021q_cpu = false; 1697 1698 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1699 ocelot_vlan_member_del(ocelot, cpu_port->index, vid); 1700 1701 ocelot_update_pgid_cpu(ocelot); 1702 1703 mutex_unlock(&ocelot->fwd_domain_lock); 1704 } 1705 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); 1706 1707 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, 1708 int cpu) 1709 { 1710 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1711 1712 mutex_lock(&ocelot->fwd_domain_lock); 1713 1714 ocelot->ports[port]->dsa_8021q_cpu = cpu_port; 1715 ocelot_apply_bridge_fwd_mask(ocelot, true); 1716 1717 mutex_unlock(&ocelot->fwd_domain_lock); 1718 } 1719 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); 1720 1721 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) 1722 { 1723 mutex_lock(&ocelot->fwd_domain_lock); 1724 1725 ocelot->ports[port]->dsa_8021q_cpu = NULL; 1726 ocelot_apply_bridge_fwd_mask(ocelot, true); 1727 1728 mutex_unlock(&ocelot->fwd_domain_lock); 1729 } 1730 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu); 1731 1732 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1733 { 1734 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1735 u32 learn_ena = 0; 1736 1737 mutex_lock(&ocelot->fwd_domain_lock); 1738 1739 ocelot_port->stp_state = state; 1740 1741 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1742 ocelot_port->learn_ena) 1743 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1744 1745 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1746 ANA_PORT_PORT_CFG, port); 1747 1748 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1749 1750 mutex_unlock(&ocelot->fwd_domain_lock); 1751 } 1752 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1753 1754 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1755 { 1756 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1757 1758 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1759 * which is clearly not what our intention is. So avoid that. 1760 */ 1761 if (!age_period) 1762 age_period = 1; 1763 1764 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1765 } 1766 EXPORT_SYMBOL(ocelot_set_ageing_time); 1767 1768 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1769 const unsigned char *addr, 1770 u16 vid) 1771 { 1772 struct ocelot_multicast *mc; 1773 1774 list_for_each_entry(mc, &ocelot->multicast, list) { 1775 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1776 return mc; 1777 } 1778 1779 return NULL; 1780 } 1781 1782 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1783 { 1784 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1785 return ENTRYTYPE_MACv4; 1786 if (addr[0] == 0x33 && addr[1] == 0x33) 1787 return ENTRYTYPE_MACv6; 1788 return ENTRYTYPE_LOCKED; 1789 } 1790 1791 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1792 unsigned long ports) 1793 { 1794 struct ocelot_pgid *pgid; 1795 1796 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1797 if (!pgid) 1798 return ERR_PTR(-ENOMEM); 1799 1800 pgid->ports = ports; 1801 pgid->index = index; 1802 refcount_set(&pgid->refcount, 1); 1803 list_add_tail(&pgid->list, &ocelot->pgids); 1804 1805 return pgid; 1806 } 1807 1808 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1809 { 1810 if (!refcount_dec_and_test(&pgid->refcount)) 1811 return; 1812 1813 list_del(&pgid->list); 1814 kfree(pgid); 1815 } 1816 1817 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1818 const struct ocelot_multicast *mc) 1819 { 1820 struct ocelot_pgid *pgid; 1821 int index; 1822 1823 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1824 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1825 * destination mask table (PGID), the destination set is programmed as 1826 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1827 */ 1828 if (mc->entry_type == ENTRYTYPE_MACv4 || 1829 mc->entry_type == ENTRYTYPE_MACv6) 1830 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1831 1832 list_for_each_entry(pgid, &ocelot->pgids, list) { 1833 /* When searching for a nonreserved multicast PGID, ignore the 1834 * dummy PGID of zero that we have for MACv4/MACv6 entries 1835 */ 1836 if (pgid->index && pgid->ports == mc->ports) { 1837 refcount_inc(&pgid->refcount); 1838 return pgid; 1839 } 1840 } 1841 1842 /* Search for a free index in the nonreserved multicast PGID area */ 1843 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1844 bool used = false; 1845 1846 list_for_each_entry(pgid, &ocelot->pgids, list) { 1847 if (pgid->index == index) { 1848 used = true; 1849 break; 1850 } 1851 } 1852 1853 if (!used) 1854 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1855 } 1856 1857 return ERR_PTR(-ENOSPC); 1858 } 1859 1860 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1861 struct ocelot_multicast *mc) 1862 { 1863 ether_addr_copy(addr, mc->addr); 1864 1865 if (mc->entry_type == ENTRYTYPE_MACv4) { 1866 addr[0] = 0; 1867 addr[1] = mc->ports >> 8; 1868 addr[2] = mc->ports & 0xff; 1869 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1870 addr[0] = mc->ports >> 8; 1871 addr[1] = mc->ports & 0xff; 1872 } 1873 } 1874 1875 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1876 const struct switchdev_obj_port_mdb *mdb, 1877 const struct net_device *bridge) 1878 { 1879 unsigned char addr[ETH_ALEN]; 1880 struct ocelot_multicast *mc; 1881 struct ocelot_pgid *pgid; 1882 u16 vid = mdb->vid; 1883 1884 if (!vid) 1885 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1886 1887 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1888 if (!mc) { 1889 /* New entry */ 1890 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1891 if (!mc) 1892 return -ENOMEM; 1893 1894 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1895 ether_addr_copy(mc->addr, mdb->addr); 1896 mc->vid = vid; 1897 1898 list_add_tail(&mc->list, &ocelot->multicast); 1899 } else { 1900 /* Existing entry. Clean up the current port mask from 1901 * hardware now, because we'll be modifying it. 1902 */ 1903 ocelot_pgid_free(ocelot, mc->pgid); 1904 ocelot_encode_ports_to_mdb(addr, mc); 1905 ocelot_mact_forget(ocelot, addr, vid); 1906 } 1907 1908 mc->ports |= BIT(port); 1909 1910 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1911 if (IS_ERR(pgid)) { 1912 dev_err(ocelot->dev, 1913 "Cannot allocate PGID for mdb %pM vid %d\n", 1914 mc->addr, mc->vid); 1915 devm_kfree(ocelot->dev, mc); 1916 return PTR_ERR(pgid); 1917 } 1918 mc->pgid = pgid; 1919 1920 ocelot_encode_ports_to_mdb(addr, mc); 1921 1922 if (mc->entry_type != ENTRYTYPE_MACv4 && 1923 mc->entry_type != ENTRYTYPE_MACv6) 1924 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1925 pgid->index); 1926 1927 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1928 mc->entry_type); 1929 } 1930 EXPORT_SYMBOL(ocelot_port_mdb_add); 1931 1932 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1933 const struct switchdev_obj_port_mdb *mdb, 1934 const struct net_device *bridge) 1935 { 1936 unsigned char addr[ETH_ALEN]; 1937 struct ocelot_multicast *mc; 1938 struct ocelot_pgid *pgid; 1939 u16 vid = mdb->vid; 1940 1941 if (!vid) 1942 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1943 1944 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1945 if (!mc) 1946 return -ENOENT; 1947 1948 ocelot_encode_ports_to_mdb(addr, mc); 1949 ocelot_mact_forget(ocelot, addr, vid); 1950 1951 ocelot_pgid_free(ocelot, mc->pgid); 1952 mc->ports &= ~BIT(port); 1953 if (!mc->ports) { 1954 list_del(&mc->list); 1955 devm_kfree(ocelot->dev, mc); 1956 return 0; 1957 } 1958 1959 /* We have a PGID with fewer ports now */ 1960 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1961 if (IS_ERR(pgid)) 1962 return PTR_ERR(pgid); 1963 mc->pgid = pgid; 1964 1965 ocelot_encode_ports_to_mdb(addr, mc); 1966 1967 if (mc->entry_type != ENTRYTYPE_MACv4 && 1968 mc->entry_type != ENTRYTYPE_MACv6) 1969 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1970 pgid->index); 1971 1972 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1973 mc->entry_type); 1974 } 1975 EXPORT_SYMBOL(ocelot_port_mdb_del); 1976 1977 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1978 struct net_device *bridge, int bridge_num, 1979 struct netlink_ext_ack *extack) 1980 { 1981 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1982 int err; 1983 1984 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 1985 if (err) 1986 return err; 1987 1988 mutex_lock(&ocelot->fwd_domain_lock); 1989 1990 ocelot_port->bridge = bridge; 1991 ocelot_port->bridge_num = bridge_num; 1992 1993 ocelot_apply_bridge_fwd_mask(ocelot, true); 1994 1995 mutex_unlock(&ocelot->fwd_domain_lock); 1996 1997 if (br_vlan_enabled(bridge)) 1998 return 0; 1999 2000 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 2001 } 2002 EXPORT_SYMBOL(ocelot_port_bridge_join); 2003 2004 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2005 struct net_device *bridge) 2006 { 2007 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2008 2009 mutex_lock(&ocelot->fwd_domain_lock); 2010 2011 if (!br_vlan_enabled(bridge)) 2012 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 2013 2014 ocelot_port->bridge = NULL; 2015 ocelot_port->bridge_num = -1; 2016 2017 ocelot_port_set_pvid(ocelot, port, NULL); 2018 ocelot_port_manage_port_tag(ocelot, port); 2019 ocelot_apply_bridge_fwd_mask(ocelot, false); 2020 2021 mutex_unlock(&ocelot->fwd_domain_lock); 2022 } 2023 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2024 2025 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2026 { 2027 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2028 int i, port, lag; 2029 2030 /* Reset destination and aggregation PGIDS */ 2031 for_each_unicast_dest_pgid(ocelot, port) 2032 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2033 2034 for_each_aggr_pgid(ocelot, i) 2035 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2036 ANA_PGID_PGID, i); 2037 2038 /* The visited ports bitmask holds the list of ports offloading any 2039 * bonding interface. Initially we mark all these ports as unvisited, 2040 * then every time we visit a port in this bitmask, we know that it is 2041 * the lowest numbered port, i.e. the one whose logical ID == physical 2042 * port ID == LAG ID. So we mark as visited all further ports in the 2043 * bitmask that are offloading the same bonding interface. This way, 2044 * we set up the aggregation PGIDs only once per bonding interface. 2045 */ 2046 for (port = 0; port < ocelot->num_phys_ports; port++) { 2047 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2048 2049 if (!ocelot_port || !ocelot_port->bond) 2050 continue; 2051 2052 visited &= ~BIT(port); 2053 } 2054 2055 /* Now, set PGIDs for each active LAG */ 2056 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2057 struct net_device *bond = ocelot->ports[lag]->bond; 2058 int num_active_ports = 0; 2059 unsigned long bond_mask; 2060 u8 aggr_idx[16]; 2061 2062 if (!bond || (visited & BIT(lag))) 2063 continue; 2064 2065 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2066 2067 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2068 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2069 2070 // Destination mask 2071 ocelot_write_rix(ocelot, bond_mask, 2072 ANA_PGID_PGID, port); 2073 2074 if (ocelot_port->lag_tx_active) 2075 aggr_idx[num_active_ports++] = port; 2076 } 2077 2078 for_each_aggr_pgid(ocelot, i) { 2079 u32 ac; 2080 2081 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2082 ac &= ~bond_mask; 2083 /* Don't do division by zero if there was no active 2084 * port. Just make all aggregation codes zero. 2085 */ 2086 if (num_active_ports) 2087 ac |= BIT(aggr_idx[i % num_active_ports]); 2088 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2089 } 2090 2091 /* Mark all ports in the same LAG as visited to avoid applying 2092 * the same config again. 2093 */ 2094 for (port = lag; port < ocelot->num_phys_ports; port++) { 2095 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2096 2097 if (!ocelot_port) 2098 continue; 2099 2100 if (ocelot_port->bond == bond) 2101 visited |= BIT(port); 2102 } 2103 } 2104 } 2105 2106 /* When offloading a bonding interface, the switch ports configured under the 2107 * same bond must have the same logical port ID, equal to the physical port ID 2108 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2109 * bridged mode, each port has a logical port ID equal to its physical port ID. 2110 */ 2111 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2112 { 2113 int port; 2114 2115 for (port = 0; port < ocelot->num_phys_ports; port++) { 2116 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2117 struct net_device *bond; 2118 2119 if (!ocelot_port) 2120 continue; 2121 2122 bond = ocelot_port->bond; 2123 if (bond) { 2124 int lag = ocelot_bond_get_id(ocelot, bond); 2125 2126 ocelot_rmw_gix(ocelot, 2127 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2128 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2129 ANA_PORT_PORT_CFG, port); 2130 } else { 2131 ocelot_rmw_gix(ocelot, 2132 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2133 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2134 ANA_PORT_PORT_CFG, port); 2135 } 2136 } 2137 } 2138 2139 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc, 2140 unsigned long from_mask, unsigned long to_mask) 2141 { 2142 unsigned char addr[ETH_ALEN]; 2143 struct ocelot_pgid *pgid; 2144 u16 vid = mc->vid; 2145 2146 dev_dbg(ocelot->dev, 2147 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n", 2148 mc->addr, mc->vid, from_mask, to_mask); 2149 2150 /* First clean up the current port mask from hardware, because 2151 * we'll be modifying it. 2152 */ 2153 ocelot_pgid_free(ocelot, mc->pgid); 2154 ocelot_encode_ports_to_mdb(addr, mc); 2155 ocelot_mact_forget(ocelot, addr, vid); 2156 2157 mc->ports &= ~from_mask; 2158 mc->ports |= to_mask; 2159 2160 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2161 if (IS_ERR(pgid)) { 2162 dev_err(ocelot->dev, 2163 "Cannot allocate PGID for mdb %pM vid %d\n", 2164 mc->addr, mc->vid); 2165 devm_kfree(ocelot->dev, mc); 2166 return PTR_ERR(pgid); 2167 } 2168 mc->pgid = pgid; 2169 2170 ocelot_encode_ports_to_mdb(addr, mc); 2171 2172 if (mc->entry_type != ENTRYTYPE_MACv4 && 2173 mc->entry_type != ENTRYTYPE_MACv6) 2174 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2175 pgid->index); 2176 2177 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2178 mc->entry_type); 2179 } 2180 2181 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 2182 unsigned long to_mask) 2183 { 2184 struct ocelot_multicast *mc; 2185 int err; 2186 2187 list_for_each_entry(mc, &ocelot->multicast, list) { 2188 if (!(mc->ports & from_mask)) 2189 continue; 2190 2191 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask); 2192 if (err) 2193 return err; 2194 } 2195 2196 return 0; 2197 } 2198 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs); 2199 2200 /* Documentation for PORTID_VAL says: 2201 * Logical port number for front port. If port is not a member of a LLAG, 2202 * then PORTID must be set to the physical port number. 2203 * If port is a member of a LLAG, then PORTID must be set to the common 2204 * PORTID_VAL used for all member ports of the LLAG. 2205 * The value must not exceed the number of physical ports on the device. 2206 * 2207 * This means we have little choice but to migrate FDB entries pointing towards 2208 * a logical port when that changes. 2209 */ 2210 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2211 struct net_device *bond, 2212 int lag) 2213 { 2214 struct ocelot_lag_fdb *fdb; 2215 int err; 2216 2217 lockdep_assert_held(&ocelot->fwd_domain_lock); 2218 2219 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2220 if (fdb->bond != bond) 2221 continue; 2222 2223 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2224 if (err) { 2225 dev_err(ocelot->dev, 2226 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2227 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2228 } 2229 2230 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2231 ENTRYTYPE_LOCKED); 2232 if (err) { 2233 dev_err(ocelot->dev, 2234 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2235 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2236 } 2237 } 2238 } 2239 2240 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2241 struct net_device *bond, 2242 struct netdev_lag_upper_info *info, 2243 struct netlink_ext_ack *extack) 2244 { 2245 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 2246 NL_SET_ERR_MSG_MOD(extack, 2247 "Can only offload LAG using hash TX type"); 2248 return -EOPNOTSUPP; 2249 } 2250 2251 mutex_lock(&ocelot->fwd_domain_lock); 2252 2253 ocelot->ports[port]->bond = bond; 2254 2255 ocelot_setup_logical_port_ids(ocelot); 2256 ocelot_apply_bridge_fwd_mask(ocelot, true); 2257 ocelot_set_aggr_pgids(ocelot); 2258 2259 mutex_unlock(&ocelot->fwd_domain_lock); 2260 2261 return 0; 2262 } 2263 EXPORT_SYMBOL(ocelot_port_lag_join); 2264 2265 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2266 struct net_device *bond) 2267 { 2268 int old_lag_id, new_lag_id; 2269 2270 mutex_lock(&ocelot->fwd_domain_lock); 2271 2272 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2273 2274 ocelot->ports[port]->bond = NULL; 2275 2276 ocelot_setup_logical_port_ids(ocelot); 2277 ocelot_apply_bridge_fwd_mask(ocelot, false); 2278 ocelot_set_aggr_pgids(ocelot); 2279 2280 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2281 2282 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2283 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2284 2285 mutex_unlock(&ocelot->fwd_domain_lock); 2286 } 2287 EXPORT_SYMBOL(ocelot_port_lag_leave); 2288 2289 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2290 { 2291 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2292 2293 mutex_lock(&ocelot->fwd_domain_lock); 2294 2295 ocelot_port->lag_tx_active = lag_tx_active; 2296 2297 /* Rebalance the LAGs */ 2298 ocelot_set_aggr_pgids(ocelot); 2299 2300 mutex_unlock(&ocelot->fwd_domain_lock); 2301 } 2302 EXPORT_SYMBOL(ocelot_port_lag_change); 2303 2304 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2305 const unsigned char *addr, u16 vid, 2306 const struct net_device *bridge) 2307 { 2308 struct ocelot_lag_fdb *fdb; 2309 int lag, err; 2310 2311 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2312 if (!fdb) 2313 return -ENOMEM; 2314 2315 mutex_lock(&ocelot->fwd_domain_lock); 2316 2317 if (!vid) 2318 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2319 2320 ether_addr_copy(fdb->addr, addr); 2321 fdb->vid = vid; 2322 fdb->bond = bond; 2323 2324 lag = ocelot_bond_get_id(ocelot, bond); 2325 2326 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2327 if (err) { 2328 mutex_unlock(&ocelot->fwd_domain_lock); 2329 kfree(fdb); 2330 return err; 2331 } 2332 2333 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2334 mutex_unlock(&ocelot->fwd_domain_lock); 2335 2336 return 0; 2337 } 2338 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2339 2340 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2341 const unsigned char *addr, u16 vid, 2342 const struct net_device *bridge) 2343 { 2344 struct ocelot_lag_fdb *fdb, *tmp; 2345 2346 mutex_lock(&ocelot->fwd_domain_lock); 2347 2348 if (!vid) 2349 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2350 2351 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2352 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2353 fdb->bond != bond) 2354 continue; 2355 2356 ocelot_mact_forget(ocelot, addr, vid); 2357 list_del(&fdb->list); 2358 mutex_unlock(&ocelot->fwd_domain_lock); 2359 kfree(fdb); 2360 2361 return 0; 2362 } 2363 2364 mutex_unlock(&ocelot->fwd_domain_lock); 2365 2366 return -ENOENT; 2367 } 2368 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2369 2370 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2371 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2372 * In the special case that it's the NPI port that we're configuring, the 2373 * length of the tag and optional prefix needs to be accounted for privately, 2374 * in order to be able to sustain communication at the requested @sdu. 2375 */ 2376 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2377 { 2378 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2379 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2380 int pause_start, pause_stop; 2381 int atop, atop_tot; 2382 2383 if (port == ocelot->npi) { 2384 maxlen += OCELOT_TAG_LEN; 2385 2386 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2387 maxlen += OCELOT_SHORT_PREFIX_LEN; 2388 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2389 maxlen += OCELOT_LONG_PREFIX_LEN; 2390 } 2391 2392 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2393 2394 /* Set Pause watermark hysteresis */ 2395 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2396 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2397 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2398 pause_start); 2399 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2400 pause_stop); 2401 2402 /* Tail dropping watermarks */ 2403 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2404 OCELOT_BUFFER_CELL_SZ; 2405 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2406 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2407 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2408 } 2409 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2410 2411 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2412 { 2413 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2414 2415 if (port == ocelot->npi) { 2416 max_mtu -= OCELOT_TAG_LEN; 2417 2418 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2419 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2420 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2421 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2422 } 2423 2424 return max_mtu; 2425 } 2426 EXPORT_SYMBOL(ocelot_get_max_mtu); 2427 2428 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2429 bool enabled) 2430 { 2431 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2432 u32 val = 0; 2433 2434 if (enabled) 2435 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2436 2437 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2438 ANA_PORT_PORT_CFG, port); 2439 2440 ocelot_port->learn_ena = enabled; 2441 } 2442 2443 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2444 bool enabled) 2445 { 2446 u32 val = 0; 2447 2448 if (enabled) 2449 val = BIT(port); 2450 2451 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2452 } 2453 2454 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2455 bool enabled) 2456 { 2457 u32 val = 0; 2458 2459 if (enabled) 2460 val = BIT(port); 2461 2462 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2463 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4); 2464 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6); 2465 } 2466 2467 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2468 bool enabled) 2469 { 2470 u32 val = 0; 2471 2472 if (enabled) 2473 val = BIT(port); 2474 2475 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2476 } 2477 2478 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2479 struct switchdev_brport_flags flags) 2480 { 2481 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2482 BR_BCAST_FLOOD)) 2483 return -EINVAL; 2484 2485 return 0; 2486 } 2487 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2488 2489 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2490 struct switchdev_brport_flags flags) 2491 { 2492 if (flags.mask & BR_LEARNING) 2493 ocelot_port_set_learning(ocelot, port, 2494 !!(flags.val & BR_LEARNING)); 2495 2496 if (flags.mask & BR_FLOOD) 2497 ocelot_port_set_ucast_flood(ocelot, port, 2498 !!(flags.val & BR_FLOOD)); 2499 2500 if (flags.mask & BR_MCAST_FLOOD) 2501 ocelot_port_set_mcast_flood(ocelot, port, 2502 !!(flags.val & BR_MCAST_FLOOD)); 2503 2504 if (flags.mask & BR_BCAST_FLOOD) 2505 ocelot_port_set_bcast_flood(ocelot, port, 2506 !!(flags.val & BR_BCAST_FLOOD)); 2507 } 2508 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2509 2510 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2511 { 2512 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2513 2514 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2515 } 2516 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2517 2518 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2519 { 2520 if (prio >= OCELOT_NUM_TC) 2521 return -ERANGE; 2522 2523 ocelot_rmw_gix(ocelot, 2524 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2525 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2526 ANA_PORT_QOS_CFG, 2527 port); 2528 2529 return 0; 2530 } 2531 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2532 2533 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2534 { 2535 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2536 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2537 2538 /* Return error if DSCP prioritization isn't enabled */ 2539 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2540 return -EOPNOTSUPP; 2541 2542 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2543 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2544 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2545 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2546 } 2547 2548 /* If the DSCP value is not trusted, the QoS classification falls back 2549 * to VLAN PCP or port-based default. 2550 */ 2551 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2552 return -EOPNOTSUPP; 2553 2554 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2555 } 2556 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2557 2558 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2559 { 2560 int mask, val; 2561 2562 if (prio >= OCELOT_NUM_TC) 2563 return -ERANGE; 2564 2565 /* There is at least one app table priority (this one), so we need to 2566 * make sure DSCP prioritization is enabled on the port. 2567 * Also make sure DSCP translation is disabled 2568 * (dcbnl doesn't support it). 2569 */ 2570 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2571 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2572 2573 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2574 ANA_PORT_QOS_CFG, port); 2575 2576 /* Trust this DSCP value and map it to the given QoS class */ 2577 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2578 2579 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2580 2581 return 0; 2582 } 2583 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2584 2585 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2586 { 2587 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2588 int mask, i; 2589 2590 /* During a "dcb app replace" command, the new app table entry will be 2591 * added first, then the old one will be deleted. But the hardware only 2592 * supports one QoS class per DSCP value (duh), so if we blindly delete 2593 * the app table entry for this DSCP value, we end up deleting the 2594 * entry with the new priority. Avoid that by checking whether user 2595 * space wants to delete the priority which is currently configured, or 2596 * something else which is no longer current. 2597 */ 2598 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2599 return 0; 2600 2601 /* Untrust this DSCP value */ 2602 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 2603 2604 for (i = 0; i < 64; i++) { 2605 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 2606 2607 /* There are still app table entries on the port, so we need to 2608 * keep DSCP enabled, nothing to do. 2609 */ 2610 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 2611 return 0; 2612 } 2613 2614 /* Disable DSCP QoS classification if there isn't any trusted 2615 * DSCP value left. 2616 */ 2617 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2618 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2619 2620 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 2621 2622 return 0; 2623 } 2624 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 2625 2626 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 2627 struct netlink_ext_ack *extack) 2628 { 2629 struct ocelot_mirror *m = ocelot->mirror; 2630 2631 if (m) { 2632 if (m->to != to) { 2633 NL_SET_ERR_MSG_MOD(extack, 2634 "Mirroring already configured towards different egress port"); 2635 return ERR_PTR(-EBUSY); 2636 } 2637 2638 refcount_inc(&m->refcount); 2639 return m; 2640 } 2641 2642 m = kzalloc(sizeof(*m), GFP_KERNEL); 2643 if (!m) 2644 return ERR_PTR(-ENOMEM); 2645 2646 m->to = to; 2647 refcount_set(&m->refcount, 1); 2648 ocelot->mirror = m; 2649 2650 /* Program the mirror port to hardware */ 2651 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 2652 2653 return m; 2654 } 2655 2656 void ocelot_mirror_put(struct ocelot *ocelot) 2657 { 2658 struct ocelot_mirror *m = ocelot->mirror; 2659 2660 if (!refcount_dec_and_test(&m->refcount)) 2661 return; 2662 2663 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 2664 ocelot->mirror = NULL; 2665 kfree(m); 2666 } 2667 2668 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 2669 bool ingress, struct netlink_ext_ack *extack) 2670 { 2671 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 2672 2673 if (IS_ERR(m)) 2674 return PTR_ERR(m); 2675 2676 if (ingress) { 2677 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2678 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2679 ANA_PORT_PORT_CFG, from); 2680 } else { 2681 ocelot_rmw(ocelot, BIT(from), BIT(from), 2682 ANA_EMIRRORPORTS); 2683 } 2684 2685 return 0; 2686 } 2687 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 2688 2689 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 2690 { 2691 if (ingress) { 2692 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2693 ANA_PORT_PORT_CFG, from); 2694 } else { 2695 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 2696 } 2697 2698 ocelot_mirror_put(ocelot); 2699 } 2700 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 2701 2702 void ocelot_init_port(struct ocelot *ocelot, int port) 2703 { 2704 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2705 2706 skb_queue_head_init(&ocelot_port->tx_skbs); 2707 2708 /* Basic L2 initialization */ 2709 2710 /* Set MAC IFG Gaps 2711 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2712 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2713 */ 2714 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2715 DEV_MAC_IFG_CFG); 2716 2717 /* Load seed (0) and set MAC HDX late collision */ 2718 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2719 DEV_MAC_HDX_CFG_SEED_LOAD, 2720 DEV_MAC_HDX_CFG); 2721 mdelay(1); 2722 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2723 DEV_MAC_HDX_CFG); 2724 2725 /* Set Max Length and maximum tags allowed */ 2726 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2727 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2728 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2729 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2730 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2731 DEV_MAC_TAGS_CFG); 2732 2733 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2734 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2735 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2736 2737 /* Enable transmission of pause frames */ 2738 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2739 2740 /* Drop frames with multicast source address */ 2741 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2742 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2743 ANA_PORT_DROP_CFG, port); 2744 2745 /* Set default VLAN and tag type to 8021Q. */ 2746 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2747 REW_PORT_VLAN_CFG_PORT_TPID_M, 2748 REW_PORT_VLAN_CFG, port); 2749 2750 /* Disable source address learning for standalone mode */ 2751 ocelot_port_set_learning(ocelot, port, false); 2752 2753 /* Set the port's initial logical port ID value, enable receiving 2754 * frames on it, and configure the MAC address learning type to 2755 * automatic. 2756 */ 2757 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2758 ANA_PORT_PORT_CFG_RECV_ENA | 2759 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2760 ANA_PORT_PORT_CFG, port); 2761 2762 /* Enable vcap lookups */ 2763 ocelot_vcap_enable(ocelot, port); 2764 } 2765 EXPORT_SYMBOL(ocelot_init_port); 2766 2767 /* Configure and enable the CPU port module, which is a set of queues 2768 * accessible through register MMIO, frame DMA or Ethernet (in case 2769 * NPI mode is used). 2770 */ 2771 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2772 { 2773 int cpu = ocelot->num_phys_ports; 2774 2775 /* The unicast destination PGID for the CPU port module is unused */ 2776 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2777 /* Instead set up a multicast destination PGID for traffic copied to 2778 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2779 * addresses will be copied to the CPU via this PGID. 2780 */ 2781 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2782 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2783 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2784 ANA_PORT_PORT_CFG, cpu); 2785 2786 /* Enable CPU port module */ 2787 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2788 /* CPU port Injection/Extraction configuration */ 2789 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2790 OCELOT_TAG_PREFIX_NONE); 2791 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2792 OCELOT_TAG_PREFIX_NONE); 2793 2794 /* Configure the CPU port to be VLAN aware */ 2795 ocelot_write_gix(ocelot, 2796 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 2797 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2798 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2799 ANA_PORT_VLAN_CFG, cpu); 2800 } 2801 2802 static void ocelot_detect_features(struct ocelot *ocelot) 2803 { 2804 int mmgt, eq_ctrl; 2805 2806 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2807 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2808 * 192 bytes as the documentation incorrectly says. 2809 */ 2810 mmgt = ocelot_read(ocelot, SYS_MMGT); 2811 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2812 2813 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2814 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2815 } 2816 2817 static int ocelot_mem_init_status(struct ocelot *ocelot) 2818 { 2819 unsigned int val; 2820 int err; 2821 2822 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 2823 &val); 2824 2825 return err ?: val; 2826 } 2827 2828 int ocelot_reset(struct ocelot *ocelot) 2829 { 2830 int err; 2831 u32 val; 2832 2833 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); 2834 if (err) 2835 return err; 2836 2837 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2838 if (err) 2839 return err; 2840 2841 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be 2842 * 100us) before enabling the switch core. 2843 */ 2844 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val, 2845 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US); 2846 if (err) 2847 return err; 2848 2849 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); 2850 if (err) 2851 return err; 2852 2853 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 2854 } 2855 EXPORT_SYMBOL(ocelot_reset); 2856 2857 int ocelot_init(struct ocelot *ocelot) 2858 { 2859 int i, ret; 2860 u32 port; 2861 2862 if (ocelot->ops->reset) { 2863 ret = ocelot->ops->reset(ocelot); 2864 if (ret) { 2865 dev_err(ocelot->dev, "Switch reset failed\n"); 2866 return ret; 2867 } 2868 } 2869 2870 mutex_init(&ocelot->ptp_lock); 2871 mutex_init(&ocelot->mact_lock); 2872 mutex_init(&ocelot->fwd_domain_lock); 2873 mutex_init(&ocelot->tas_lock); 2874 spin_lock_init(&ocelot->ptp_clock_lock); 2875 spin_lock_init(&ocelot->ts_id_lock); 2876 2877 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2878 if (!ocelot->owq) 2879 return -ENOMEM; 2880 2881 ret = ocelot_stats_init(ocelot); 2882 if (ret) 2883 goto err_stats_init; 2884 2885 INIT_LIST_HEAD(&ocelot->multicast); 2886 INIT_LIST_HEAD(&ocelot->pgids); 2887 INIT_LIST_HEAD(&ocelot->vlans); 2888 INIT_LIST_HEAD(&ocelot->lag_fdbs); 2889 ocelot_detect_features(ocelot); 2890 ocelot_mact_init(ocelot); 2891 ocelot_vlan_init(ocelot); 2892 ocelot_vcap_init(ocelot); 2893 ocelot_cpu_port_init(ocelot); 2894 2895 if (ocelot->ops->psfp_init) 2896 ocelot->ops->psfp_init(ocelot); 2897 2898 if (ocelot->mm_supported) { 2899 ret = ocelot_mm_init(ocelot); 2900 if (ret) 2901 goto err_mm_init; 2902 } 2903 2904 for (port = 0; port < ocelot->num_phys_ports; port++) { 2905 /* Clear all counters (5 groups) */ 2906 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2907 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2908 SYS_STAT_CFG); 2909 } 2910 2911 /* Only use S-Tag */ 2912 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2913 2914 /* Aggregation mode */ 2915 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2916 ANA_AGGR_CFG_AC_DMAC_ENA | 2917 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2918 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2919 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2920 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2921 ANA_AGGR_CFG); 2922 2923 /* Set MAC age time to default value. The entry is aged after 2924 * 2*AGE_PERIOD 2925 */ 2926 ocelot_write(ocelot, 2927 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2928 ANA_AUTOAGE); 2929 2930 /* Disable learning for frames discarded by VLAN ingress filtering */ 2931 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2932 2933 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2934 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2935 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2936 2937 /* Setup flooding PGIDs */ 2938 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2939 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2940 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2941 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2942 ANA_FLOODING, i); 2943 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2944 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2945 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2946 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2947 ANA_FLOODING_IPMC); 2948 2949 for (port = 0; port < ocelot->num_phys_ports; port++) { 2950 /* Transmit the frame to the local port. */ 2951 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2952 /* Do not forward BPDU frames to the front ports. */ 2953 ocelot_write_gix(ocelot, 2954 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2955 ANA_PORT_CPU_FWD_BPDU_CFG, 2956 port); 2957 /* Ensure bridging is disabled */ 2958 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2959 } 2960 2961 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2962 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2963 2964 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2965 } 2966 2967 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2968 2969 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2970 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2971 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2972 ANA_PGID_PGID, PGID_MC); 2973 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2974 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2975 ANA_PGID_PGID, PGID_BC); 2976 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2977 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2978 2979 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2980 * registers endianness. 2981 */ 2982 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2983 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2984 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2985 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2986 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2987 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2988 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2989 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2990 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2991 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2992 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2993 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2994 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2995 for (i = 0; i < 16; i++) 2996 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2997 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2998 ANA_CPUQ_8021_CFG, i); 2999 3000 return 0; 3001 3002 err_mm_init: 3003 ocelot_stats_deinit(ocelot); 3004 err_stats_init: 3005 destroy_workqueue(ocelot->owq); 3006 return ret; 3007 } 3008 EXPORT_SYMBOL(ocelot_init); 3009 3010 void ocelot_deinit(struct ocelot *ocelot) 3011 { 3012 ocelot_stats_deinit(ocelot); 3013 destroy_workqueue(ocelot->owq); 3014 } 3015 EXPORT_SYMBOL(ocelot_deinit); 3016 3017 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3018 { 3019 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3020 3021 skb_queue_purge(&ocelot_port->tx_skbs); 3022 } 3023 EXPORT_SYMBOL(ocelot_deinit_port); 3024 3025 MODULE_LICENSE("Dual MIT/GPL"); 3026