1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include "ocelot.h" 9 #include "ocelot_vcap.h" 10 11 #define TABLE_UPDATE_SLEEP_US 10 12 #define TABLE_UPDATE_TIMEOUT_US 100000 13 14 struct ocelot_mact_entry { 15 u8 mac[ETH_ALEN]; 16 u16 vid; 17 enum macaccess_entry_type type; 18 }; 19 20 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 21 { 22 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 23 } 24 25 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 26 { 27 u32 val; 28 29 return readx_poll_timeout(ocelot_mact_read_macaccess, 30 ocelot, val, 31 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 32 MACACCESS_CMD_IDLE, 33 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 34 } 35 36 static void ocelot_mact_select(struct ocelot *ocelot, 37 const unsigned char mac[ETH_ALEN], 38 unsigned int vid) 39 { 40 u32 macl = 0, mach = 0; 41 42 /* Set the MAC address to handle and the vlan associated in a format 43 * understood by the hardware. 44 */ 45 mach |= vid << 16; 46 mach |= mac[0] << 8; 47 mach |= mac[1] << 0; 48 macl |= mac[2] << 24; 49 macl |= mac[3] << 16; 50 macl |= mac[4] << 8; 51 macl |= mac[5] << 0; 52 53 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 54 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 55 56 } 57 58 int ocelot_mact_learn(struct ocelot *ocelot, int port, 59 const unsigned char mac[ETH_ALEN], 60 unsigned int vid, enum macaccess_entry_type type) 61 { 62 ocelot_mact_select(ocelot, mac, vid); 63 64 /* Issue a write command */ 65 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 69 ANA_TABLES_MACACCESS); 70 71 return ocelot_mact_wait_for_completion(ocelot); 72 } 73 EXPORT_SYMBOL(ocelot_mact_learn); 74 75 int ocelot_mact_forget(struct ocelot *ocelot, 76 const unsigned char mac[ETH_ALEN], unsigned int vid) 77 { 78 ocelot_mact_select(ocelot, mac, vid); 79 80 /* Issue a forget command */ 81 ocelot_write(ocelot, 82 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 83 ANA_TABLES_MACACCESS); 84 85 return ocelot_mact_wait_for_completion(ocelot); 86 } 87 EXPORT_SYMBOL(ocelot_mact_forget); 88 89 static void ocelot_mact_init(struct ocelot *ocelot) 90 { 91 /* Configure the learning mode entries attributes: 92 * - Do not copy the frame to the CPU extraction queues. 93 * - Use the vlan and mac_cpoy for dmac lookup. 94 */ 95 ocelot_rmw(ocelot, 0, 96 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 97 | ANA_AGENCTRL_LEARN_FWD_KILL 98 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 99 ANA_AGENCTRL); 100 101 /* Clear the MAC table */ 102 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 103 } 104 105 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 106 { 107 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 108 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 109 ANA_PORT_VCAP_S2_CFG, port); 110 } 111 112 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 113 { 114 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 115 } 116 117 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 118 { 119 u32 val; 120 121 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 122 ocelot, 123 val, 124 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 125 ANA_TABLES_VLANACCESS_CMD_IDLE, 126 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 127 } 128 129 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 130 { 131 /* Select the VID to configure */ 132 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 133 ANA_TABLES_VLANTIDX); 134 /* Set the vlan port members mask and issue a write command */ 135 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 136 ANA_TABLES_VLANACCESS_CMD_WRITE, 137 ANA_TABLES_VLANACCESS); 138 139 return ocelot_vlant_wait_for_completion(ocelot); 140 } 141 142 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 143 u16 vid) 144 { 145 struct ocelot_port *ocelot_port = ocelot->ports[port]; 146 u32 val = 0; 147 148 if (ocelot_port->vid != vid) { 149 /* Always permit deleting the native VLAN (vid = 0) */ 150 if (ocelot_port->vid && vid) { 151 dev_err(ocelot->dev, 152 "Port already has a native VLAN: %d\n", 153 ocelot_port->vid); 154 return -EBUSY; 155 } 156 ocelot_port->vid = vid; 157 } 158 159 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 160 REW_PORT_VLAN_CFG_PORT_VID_M, 161 REW_PORT_VLAN_CFG, port); 162 163 if (ocelot_port->vlan_aware && !ocelot_port->vid) 164 /* If port is vlan-aware and tagged, drop untagged and priority 165 * tagged frames. 166 */ 167 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 168 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 169 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 170 ocelot_rmw_gix(ocelot, val, 171 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 172 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 173 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 174 ANA_PORT_DROP_CFG, port); 175 176 if (ocelot_port->vlan_aware) { 177 if (ocelot_port->vid) 178 /* Tag all frames except when VID == DEFAULT_VLAN */ 179 val = REW_TAG_CFG_TAG_CFG(1); 180 else 181 /* Tag all frames */ 182 val = REW_TAG_CFG_TAG_CFG(3); 183 } else { 184 /* Port tagging disabled. */ 185 val = REW_TAG_CFG_TAG_CFG(0); 186 } 187 ocelot_rmw_gix(ocelot, val, 188 REW_TAG_CFG_TAG_CFG_M, 189 REW_TAG_CFG, port); 190 191 return 0; 192 } 193 194 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 195 bool vlan_aware) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val; 199 200 ocelot_port->vlan_aware = vlan_aware; 201 202 if (vlan_aware) 203 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 204 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 205 else 206 val = 0; 207 ocelot_rmw_gix(ocelot, val, 208 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 209 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 210 ANA_PORT_VLAN_CFG, port); 211 212 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 213 } 214 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 215 216 /* Default vlan to clasify for untagged frames (may be zero) */ 217 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 218 { 219 struct ocelot_port *ocelot_port = ocelot->ports[port]; 220 221 ocelot_rmw_gix(ocelot, 222 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 223 ANA_PORT_VLAN_CFG_VLAN_VID_M, 224 ANA_PORT_VLAN_CFG, port); 225 226 ocelot_port->pvid = pvid; 227 } 228 229 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 230 bool untagged) 231 { 232 int ret; 233 234 /* Make the port a member of the VLAN */ 235 ocelot->vlan_mask[vid] |= BIT(port); 236 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 237 if (ret) 238 return ret; 239 240 /* Default ingress vlan classification */ 241 if (pvid) 242 ocelot_port_set_pvid(ocelot, port, vid); 243 244 /* Untagged egress vlan clasification */ 245 if (untagged) { 246 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 247 if (ret) 248 return ret; 249 } 250 251 return 0; 252 } 253 EXPORT_SYMBOL(ocelot_vlan_add); 254 255 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 256 { 257 struct ocelot_port *ocelot_port = ocelot->ports[port]; 258 int ret; 259 260 /* Stop the port from being a member of the vlan */ 261 ocelot->vlan_mask[vid] &= ~BIT(port); 262 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 263 if (ret) 264 return ret; 265 266 /* Ingress */ 267 if (ocelot_port->pvid == vid) 268 ocelot_port_set_pvid(ocelot, port, 0); 269 270 /* Egress */ 271 if (ocelot_port->vid == vid) 272 ocelot_port_set_native_vlan(ocelot, port, 0); 273 274 return 0; 275 } 276 EXPORT_SYMBOL(ocelot_vlan_del); 277 278 static void ocelot_vlan_init(struct ocelot *ocelot) 279 { 280 u16 port, vid; 281 282 /* Clear VLAN table, by default all ports are members of all VLANs */ 283 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 284 ANA_TABLES_VLANACCESS); 285 ocelot_vlant_wait_for_completion(ocelot); 286 287 /* Configure the port VLAN memberships */ 288 for (vid = 1; vid < VLAN_N_VID; vid++) { 289 ocelot->vlan_mask[vid] = 0; 290 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 291 } 292 293 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 294 * traffic. It is added automatically if 8021q module is loaded, but 295 * we can't rely on it since module may be not loaded. 296 */ 297 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 298 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 299 300 /* Set vlan ingress filter mask to all ports but the CPU port by 301 * default. 302 */ 303 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 304 ANA_VLANMASK); 305 306 for (port = 0; port < ocelot->num_phys_ports; port++) { 307 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 308 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 309 } 310 } 311 312 void ocelot_adjust_link(struct ocelot *ocelot, int port, 313 struct phy_device *phydev) 314 { 315 struct ocelot_port *ocelot_port = ocelot->ports[port]; 316 int speed, mode = 0; 317 318 switch (phydev->speed) { 319 case SPEED_10: 320 speed = OCELOT_SPEED_10; 321 break; 322 case SPEED_100: 323 speed = OCELOT_SPEED_100; 324 break; 325 case SPEED_1000: 326 speed = OCELOT_SPEED_1000; 327 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 328 break; 329 case SPEED_2500: 330 speed = OCELOT_SPEED_2500; 331 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 332 break; 333 default: 334 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 335 port, phydev->speed); 336 return; 337 } 338 339 phy_print_status(phydev); 340 341 if (!phydev->link) 342 return; 343 344 /* Only full duplex supported for now */ 345 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 346 mode, DEV_MAC_MODE_CFG); 347 348 /* Disable HDX fast control */ 349 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 350 DEV_PORT_MISC); 351 352 /* SGMII only for now */ 353 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 354 PCS1G_MODE_CFG); 355 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 356 357 /* Enable PCS */ 358 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 359 360 /* No aneg on SGMII */ 361 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 362 363 /* No loopback */ 364 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 365 366 /* Enable MAC module */ 367 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 368 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 369 370 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 371 * reset */ 372 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 373 DEV_CLOCK_CFG); 374 375 /* No PFC */ 376 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 377 ANA_PFC_PFC_CFG, port); 378 379 /* Core: Enable port for frame transfer */ 380 ocelot_fields_write(ocelot, port, 381 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 382 383 /* Flow control */ 384 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 385 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 386 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 387 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 388 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 389 SYS_MAC_FC_CFG, port); 390 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 391 } 392 EXPORT_SYMBOL(ocelot_adjust_link); 393 394 void ocelot_port_enable(struct ocelot *ocelot, int port, 395 struct phy_device *phy) 396 { 397 /* Enable receiving frames on the port, and activate auto-learning of 398 * MAC addresses. 399 */ 400 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 401 ANA_PORT_PORT_CFG_RECV_ENA | 402 ANA_PORT_PORT_CFG_PORTID_VAL(port), 403 ANA_PORT_PORT_CFG, port); 404 } 405 EXPORT_SYMBOL(ocelot_port_enable); 406 407 void ocelot_port_disable(struct ocelot *ocelot, int port) 408 { 409 struct ocelot_port *ocelot_port = ocelot->ports[port]; 410 411 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 412 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 413 } 414 EXPORT_SYMBOL(ocelot_port_disable); 415 416 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 417 struct sk_buff *clone) 418 { 419 struct ocelot_port *ocelot_port = ocelot->ports[port]; 420 421 spin_lock(&ocelot_port->ts_id_lock); 422 423 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 424 /* Store timestamp ID in cb[0] of sk_buff */ 425 clone->cb[0] = ocelot_port->ts_id; 426 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 427 skb_queue_tail(&ocelot_port->tx_skbs, clone); 428 429 spin_unlock(&ocelot_port->ts_id_lock); 430 } 431 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 432 433 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 434 struct timespec64 *ts) 435 { 436 unsigned long flags; 437 u32 val; 438 439 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 440 441 /* Read current PTP time to get seconds */ 442 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 443 444 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 445 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 446 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 447 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 448 449 /* Read packet HW timestamp from FIFO */ 450 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 451 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 452 453 /* Sec has incremented since the ts was registered */ 454 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 455 ts->tv_sec--; 456 457 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 458 } 459 460 void ocelot_get_txtstamp(struct ocelot *ocelot) 461 { 462 int budget = OCELOT_PTP_QUEUE_SZ; 463 464 while (budget--) { 465 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 466 struct skb_shared_hwtstamps shhwtstamps; 467 struct ocelot_port *port; 468 struct timespec64 ts; 469 unsigned long flags; 470 u32 val, id, txport; 471 472 val = ocelot_read(ocelot, SYS_PTP_STATUS); 473 474 /* Check if a timestamp can be retrieved */ 475 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 476 break; 477 478 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 479 480 /* Retrieve the ts ID and Tx port */ 481 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 482 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 483 484 /* Retrieve its associated skb */ 485 port = ocelot->ports[txport]; 486 487 spin_lock_irqsave(&port->tx_skbs.lock, flags); 488 489 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 490 if (skb->cb[0] != id) 491 continue; 492 __skb_unlink(skb, &port->tx_skbs); 493 skb_match = skb; 494 break; 495 } 496 497 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 498 499 /* Get the h/w timestamp */ 500 ocelot_get_hwtimestamp(ocelot, &ts); 501 502 if (unlikely(!skb_match)) 503 continue; 504 505 /* Set the timestamp into the skb */ 506 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 507 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 508 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 509 510 /* Next ts */ 511 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 512 } 513 } 514 EXPORT_SYMBOL(ocelot_get_txtstamp); 515 516 int ocelot_fdb_add(struct ocelot *ocelot, int port, 517 const unsigned char *addr, u16 vid) 518 { 519 struct ocelot_port *ocelot_port = ocelot->ports[port]; 520 int pgid = port; 521 522 if (port == ocelot->npi) 523 pgid = PGID_CPU; 524 525 if (!vid) { 526 if (!ocelot_port->vlan_aware) 527 /* If the bridge is not VLAN aware and no VID was 528 * provided, set it to pvid to ensure the MAC entry 529 * matches incoming untagged packets 530 */ 531 vid = ocelot_port->pvid; 532 else 533 /* If the bridge is VLAN aware a VID must be provided as 534 * otherwise the learnt entry wouldn't match any frame. 535 */ 536 return -EINVAL; 537 } 538 539 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 540 } 541 EXPORT_SYMBOL(ocelot_fdb_add); 542 543 int ocelot_fdb_del(struct ocelot *ocelot, int port, 544 const unsigned char *addr, u16 vid) 545 { 546 return ocelot_mact_forget(ocelot, addr, vid); 547 } 548 EXPORT_SYMBOL(ocelot_fdb_del); 549 550 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 551 bool is_static, void *data) 552 { 553 struct ocelot_dump_ctx *dump = data; 554 u32 portid = NETLINK_CB(dump->cb->skb).portid; 555 u32 seq = dump->cb->nlh->nlmsg_seq; 556 struct nlmsghdr *nlh; 557 struct ndmsg *ndm; 558 559 if (dump->idx < dump->cb->args[2]) 560 goto skip; 561 562 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 563 sizeof(*ndm), NLM_F_MULTI); 564 if (!nlh) 565 return -EMSGSIZE; 566 567 ndm = nlmsg_data(nlh); 568 ndm->ndm_family = AF_BRIDGE; 569 ndm->ndm_pad1 = 0; 570 ndm->ndm_pad2 = 0; 571 ndm->ndm_flags = NTF_SELF; 572 ndm->ndm_type = 0; 573 ndm->ndm_ifindex = dump->dev->ifindex; 574 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 575 576 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 577 goto nla_put_failure; 578 579 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 580 goto nla_put_failure; 581 582 nlmsg_end(dump->skb, nlh); 583 584 skip: 585 dump->idx++; 586 return 0; 587 588 nla_put_failure: 589 nlmsg_cancel(dump->skb, nlh); 590 return -EMSGSIZE; 591 } 592 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 593 594 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 595 struct ocelot_mact_entry *entry) 596 { 597 u32 val, dst, macl, mach; 598 char mac[ETH_ALEN]; 599 600 /* Set row and column to read from */ 601 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 602 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 603 604 /* Issue a read command */ 605 ocelot_write(ocelot, 606 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 607 ANA_TABLES_MACACCESS); 608 609 if (ocelot_mact_wait_for_completion(ocelot)) 610 return -ETIMEDOUT; 611 612 /* Read the entry flags */ 613 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 614 if (!(val & ANA_TABLES_MACACCESS_VALID)) 615 return -EINVAL; 616 617 /* If the entry read has another port configured as its destination, 618 * do not report it. 619 */ 620 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 621 if (dst != port) 622 return -EINVAL; 623 624 /* Get the entry's MAC address and VLAN id */ 625 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 626 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 627 628 mac[0] = (mach >> 8) & 0xff; 629 mac[1] = (mach >> 0) & 0xff; 630 mac[2] = (macl >> 24) & 0xff; 631 mac[3] = (macl >> 16) & 0xff; 632 mac[4] = (macl >> 8) & 0xff; 633 mac[5] = (macl >> 0) & 0xff; 634 635 entry->vid = (mach >> 16) & 0xfff; 636 ether_addr_copy(entry->mac, mac); 637 638 return 0; 639 } 640 641 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 642 dsa_fdb_dump_cb_t *cb, void *data) 643 { 644 int i, j; 645 646 /* Loop through all the mac tables entries. */ 647 for (i = 0; i < ocelot->num_mact_rows; i++) { 648 for (j = 0; j < 4; j++) { 649 struct ocelot_mact_entry entry; 650 bool is_static; 651 int ret; 652 653 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 654 /* If the entry is invalid (wrong port, invalid...), 655 * skip it. 656 */ 657 if (ret == -EINVAL) 658 continue; 659 else if (ret) 660 return ret; 661 662 is_static = (entry.type == ENTRYTYPE_LOCKED); 663 664 ret = cb(entry.mac, entry.vid, is_static, data); 665 if (ret) 666 return ret; 667 } 668 } 669 670 return 0; 671 } 672 EXPORT_SYMBOL(ocelot_fdb_dump); 673 674 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 675 { 676 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 677 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 678 } 679 EXPORT_SYMBOL(ocelot_hwstamp_get); 680 681 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 682 { 683 struct ocelot_port *ocelot_port = ocelot->ports[port]; 684 struct hwtstamp_config cfg; 685 686 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 687 return -EFAULT; 688 689 /* reserved for future extensions */ 690 if (cfg.flags) 691 return -EINVAL; 692 693 /* Tx type sanity check */ 694 switch (cfg.tx_type) { 695 case HWTSTAMP_TX_ON: 696 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 697 break; 698 case HWTSTAMP_TX_ONESTEP_SYNC: 699 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 700 * need to update the origin time. 701 */ 702 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 703 break; 704 case HWTSTAMP_TX_OFF: 705 ocelot_port->ptp_cmd = 0; 706 break; 707 default: 708 return -ERANGE; 709 } 710 711 mutex_lock(&ocelot->ptp_lock); 712 713 switch (cfg.rx_filter) { 714 case HWTSTAMP_FILTER_NONE: 715 break; 716 case HWTSTAMP_FILTER_ALL: 717 case HWTSTAMP_FILTER_SOME: 718 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 719 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 720 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 721 case HWTSTAMP_FILTER_NTP_ALL: 722 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 723 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 724 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 725 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 726 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 727 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 728 case HWTSTAMP_FILTER_PTP_V2_EVENT: 729 case HWTSTAMP_FILTER_PTP_V2_SYNC: 730 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 731 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 732 break; 733 default: 734 mutex_unlock(&ocelot->ptp_lock); 735 return -ERANGE; 736 } 737 738 /* Commit back the result & save it */ 739 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 740 mutex_unlock(&ocelot->ptp_lock); 741 742 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 743 } 744 EXPORT_SYMBOL(ocelot_hwstamp_set); 745 746 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 747 { 748 int i; 749 750 if (sset != ETH_SS_STATS) 751 return; 752 753 for (i = 0; i < ocelot->num_stats; i++) 754 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 755 ETH_GSTRING_LEN); 756 } 757 EXPORT_SYMBOL(ocelot_get_strings); 758 759 static void ocelot_update_stats(struct ocelot *ocelot) 760 { 761 int i, j; 762 763 mutex_lock(&ocelot->stats_lock); 764 765 for (i = 0; i < ocelot->num_phys_ports; i++) { 766 /* Configure the port to read the stats from */ 767 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 768 769 for (j = 0; j < ocelot->num_stats; j++) { 770 u32 val; 771 unsigned int idx = i * ocelot->num_stats + j; 772 773 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 774 ocelot->stats_layout[j].offset); 775 776 if (val < (ocelot->stats[idx] & U32_MAX)) 777 ocelot->stats[idx] += (u64)1 << 32; 778 779 ocelot->stats[idx] = (ocelot->stats[idx] & 780 ~(u64)U32_MAX) + val; 781 } 782 } 783 784 mutex_unlock(&ocelot->stats_lock); 785 } 786 787 static void ocelot_check_stats_work(struct work_struct *work) 788 { 789 struct delayed_work *del_work = to_delayed_work(work); 790 struct ocelot *ocelot = container_of(del_work, struct ocelot, 791 stats_work); 792 793 ocelot_update_stats(ocelot); 794 795 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 796 OCELOT_STATS_CHECK_DELAY); 797 } 798 799 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 800 { 801 int i; 802 803 /* check and update now */ 804 ocelot_update_stats(ocelot); 805 806 /* Copy all counters */ 807 for (i = 0; i < ocelot->num_stats; i++) 808 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 809 } 810 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 811 812 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 813 { 814 if (sset != ETH_SS_STATS) 815 return -EOPNOTSUPP; 816 817 return ocelot->num_stats; 818 } 819 EXPORT_SYMBOL(ocelot_get_sset_count); 820 821 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 822 struct ethtool_ts_info *info) 823 { 824 info->phc_index = ocelot->ptp_clock ? 825 ptp_clock_index(ocelot->ptp_clock) : -1; 826 if (info->phc_index == -1) { 827 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 828 SOF_TIMESTAMPING_RX_SOFTWARE | 829 SOF_TIMESTAMPING_SOFTWARE; 830 return 0; 831 } 832 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 833 SOF_TIMESTAMPING_RX_SOFTWARE | 834 SOF_TIMESTAMPING_SOFTWARE | 835 SOF_TIMESTAMPING_TX_HARDWARE | 836 SOF_TIMESTAMPING_RX_HARDWARE | 837 SOF_TIMESTAMPING_RAW_HARDWARE; 838 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 839 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 840 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 841 842 return 0; 843 } 844 EXPORT_SYMBOL(ocelot_get_ts_info); 845 846 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 847 { 848 u32 port_cfg; 849 int p, i; 850 851 if (!(BIT(port) & ocelot->bridge_mask)) 852 return; 853 854 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 855 856 switch (state) { 857 case BR_STATE_FORWARDING: 858 ocelot->bridge_fwd_mask |= BIT(port); 859 fallthrough; 860 case BR_STATE_LEARNING: 861 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 862 break; 863 864 default: 865 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 866 ocelot->bridge_fwd_mask &= ~BIT(port); 867 break; 868 } 869 870 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 871 872 /* Apply FWD mask. The loop is needed to add/remove the current port as 873 * a source for the other ports. 874 */ 875 for (p = 0; p < ocelot->num_phys_ports; p++) { 876 if (ocelot->bridge_fwd_mask & BIT(p)) { 877 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 878 879 for (i = 0; i < ocelot->num_phys_ports; i++) { 880 unsigned long bond_mask = ocelot->lags[i]; 881 882 if (!bond_mask) 883 continue; 884 885 if (bond_mask & BIT(p)) { 886 mask &= ~bond_mask; 887 break; 888 } 889 } 890 891 ocelot_write_rix(ocelot, mask, 892 ANA_PGID_PGID, PGID_SRC + p); 893 } else { 894 ocelot_write_rix(ocelot, 0, 895 ANA_PGID_PGID, PGID_SRC + p); 896 } 897 } 898 } 899 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 900 901 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 902 { 903 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 904 905 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 906 * which is clearly not what our intention is. So avoid that. 907 */ 908 if (!age_period) 909 age_period = 1; 910 911 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 912 } 913 EXPORT_SYMBOL(ocelot_set_ageing_time); 914 915 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 916 const unsigned char *addr, 917 u16 vid) 918 { 919 struct ocelot_multicast *mc; 920 921 list_for_each_entry(mc, &ocelot->multicast, list) { 922 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 923 return mc; 924 } 925 926 return NULL; 927 } 928 929 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 930 { 931 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 932 return ENTRYTYPE_MACv4; 933 if (addr[0] == 0x33 && addr[1] == 0x33) 934 return ENTRYTYPE_MACv6; 935 return ENTRYTYPE_NORMAL; 936 } 937 938 static int ocelot_mdb_get_pgid(struct ocelot *ocelot, 939 enum macaccess_entry_type entry_type) 940 { 941 int pgid; 942 943 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 944 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 945 * destination mask table (PGID), the destination set is programmed as 946 * part of the entry MAC address.", and the DEST_IDX is set to 0. 947 */ 948 if (entry_type == ENTRYTYPE_MACv4 || 949 entry_type == ENTRYTYPE_MACv6) 950 return 0; 951 952 for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) { 953 struct ocelot_multicast *mc; 954 bool used = false; 955 956 list_for_each_entry(mc, &ocelot->multicast, list) { 957 if (mc->pgid == pgid) { 958 used = true; 959 break; 960 } 961 } 962 963 if (!used) 964 return pgid; 965 } 966 967 return -1; 968 } 969 970 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 971 struct ocelot_multicast *mc, 972 enum macaccess_entry_type entry_type) 973 { 974 memcpy(addr, mc->addr, ETH_ALEN); 975 976 if (entry_type == ENTRYTYPE_MACv4) { 977 addr[0] = 0; 978 addr[1] = mc->ports >> 8; 979 addr[2] = mc->ports & 0xff; 980 } else if (entry_type == ENTRYTYPE_MACv6) { 981 addr[0] = mc->ports >> 8; 982 addr[1] = mc->ports & 0xff; 983 } 984 } 985 986 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 987 const struct switchdev_obj_port_mdb *mdb) 988 { 989 struct ocelot_port *ocelot_port = ocelot->ports[port]; 990 enum macaccess_entry_type entry_type; 991 unsigned char addr[ETH_ALEN]; 992 struct ocelot_multicast *mc; 993 u16 vid = mdb->vid; 994 bool new = false; 995 996 if (port == ocelot->npi) 997 port = ocelot->num_phys_ports; 998 999 if (!vid) 1000 vid = ocelot_port->pvid; 1001 1002 entry_type = ocelot_classify_mdb(mdb->addr); 1003 1004 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1005 if (!mc) { 1006 int pgid = ocelot_mdb_get_pgid(ocelot, entry_type); 1007 1008 if (pgid < 0) { 1009 dev_err(ocelot->dev, 1010 "No more PGIDs available for mdb %pM vid %d\n", 1011 mdb->addr, vid); 1012 return -ENOSPC; 1013 } 1014 1015 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1016 if (!mc) 1017 return -ENOMEM; 1018 1019 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1020 mc->vid = vid; 1021 mc->pgid = pgid; 1022 1023 list_add_tail(&mc->list, &ocelot->multicast); 1024 new = true; 1025 } 1026 1027 if (!new) { 1028 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1029 ocelot_mact_forget(ocelot, addr, vid); 1030 } 1031 1032 mc->ports |= BIT(port); 1033 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1034 1035 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1036 } 1037 EXPORT_SYMBOL(ocelot_port_mdb_add); 1038 1039 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1040 const struct switchdev_obj_port_mdb *mdb) 1041 { 1042 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1043 enum macaccess_entry_type entry_type; 1044 unsigned char addr[ETH_ALEN]; 1045 struct ocelot_multicast *mc; 1046 u16 vid = mdb->vid; 1047 1048 if (port == ocelot->npi) 1049 port = ocelot->num_phys_ports; 1050 1051 if (!vid) 1052 vid = ocelot_port->pvid; 1053 1054 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1055 if (!mc) 1056 return -ENOENT; 1057 1058 entry_type = ocelot_classify_mdb(mdb->addr); 1059 1060 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1061 ocelot_mact_forget(ocelot, addr, vid); 1062 1063 mc->ports &= ~BIT(port); 1064 if (!mc->ports) { 1065 list_del(&mc->list); 1066 devm_kfree(ocelot->dev, mc); 1067 return 0; 1068 } 1069 1070 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1071 1072 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1073 } 1074 EXPORT_SYMBOL(ocelot_port_mdb_del); 1075 1076 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1077 struct net_device *bridge) 1078 { 1079 if (!ocelot->bridge_mask) { 1080 ocelot->hw_bridge_dev = bridge; 1081 } else { 1082 if (ocelot->hw_bridge_dev != bridge) 1083 /* This is adding the port to a second bridge, this is 1084 * unsupported */ 1085 return -ENODEV; 1086 } 1087 1088 ocelot->bridge_mask |= BIT(port); 1089 1090 return 0; 1091 } 1092 EXPORT_SYMBOL(ocelot_port_bridge_join); 1093 1094 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1095 struct net_device *bridge) 1096 { 1097 ocelot->bridge_mask &= ~BIT(port); 1098 1099 if (!ocelot->bridge_mask) 1100 ocelot->hw_bridge_dev = NULL; 1101 1102 ocelot_port_vlan_filtering(ocelot, port, 0); 1103 ocelot_port_set_pvid(ocelot, port, 0); 1104 return ocelot_port_set_native_vlan(ocelot, port, 0); 1105 } 1106 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1107 1108 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1109 { 1110 int i, port, lag; 1111 1112 /* Reset destination and aggregation PGIDS */ 1113 for_each_unicast_dest_pgid(ocelot, port) 1114 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1115 1116 for_each_aggr_pgid(ocelot, i) 1117 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1118 ANA_PGID_PGID, i); 1119 1120 /* Now, set PGIDs for each LAG */ 1121 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1122 unsigned long bond_mask; 1123 int aggr_count = 0; 1124 u8 aggr_idx[16]; 1125 1126 bond_mask = ocelot->lags[lag]; 1127 if (!bond_mask) 1128 continue; 1129 1130 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1131 // Destination mask 1132 ocelot_write_rix(ocelot, bond_mask, 1133 ANA_PGID_PGID, port); 1134 aggr_idx[aggr_count] = port; 1135 aggr_count++; 1136 } 1137 1138 for_each_aggr_pgid(ocelot, i) { 1139 u32 ac; 1140 1141 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1142 ac &= ~bond_mask; 1143 ac |= BIT(aggr_idx[i % aggr_count]); 1144 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1145 } 1146 } 1147 } 1148 1149 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1150 { 1151 unsigned long bond_mask = ocelot->lags[lag]; 1152 unsigned int p; 1153 1154 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1155 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1156 1157 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1158 1159 /* Use lag port as logical port for port i */ 1160 ocelot_write_gix(ocelot, port_cfg | 1161 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1162 ANA_PORT_PORT_CFG, p); 1163 } 1164 } 1165 1166 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1167 struct net_device *bond) 1168 { 1169 struct net_device *ndev; 1170 u32 bond_mask = 0; 1171 int lag, lp; 1172 1173 rcu_read_lock(); 1174 for_each_netdev_in_bond_rcu(bond, ndev) { 1175 struct ocelot_port_private *priv = netdev_priv(ndev); 1176 1177 bond_mask |= BIT(priv->chip_port); 1178 } 1179 rcu_read_unlock(); 1180 1181 lp = __ffs(bond_mask); 1182 1183 /* If the new port is the lowest one, use it as the logical port from 1184 * now on 1185 */ 1186 if (port == lp) { 1187 lag = port; 1188 ocelot->lags[port] = bond_mask; 1189 bond_mask &= ~BIT(port); 1190 if (bond_mask) { 1191 lp = __ffs(bond_mask); 1192 ocelot->lags[lp] = 0; 1193 } 1194 } else { 1195 lag = lp; 1196 ocelot->lags[lp] |= BIT(port); 1197 } 1198 1199 ocelot_setup_lag(ocelot, lag); 1200 ocelot_set_aggr_pgids(ocelot); 1201 1202 return 0; 1203 } 1204 EXPORT_SYMBOL(ocelot_port_lag_join); 1205 1206 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1207 struct net_device *bond) 1208 { 1209 u32 port_cfg; 1210 int i; 1211 1212 /* Remove port from any lag */ 1213 for (i = 0; i < ocelot->num_phys_ports; i++) 1214 ocelot->lags[i] &= ~BIT(port); 1215 1216 /* if it was the logical port of the lag, move the lag config to the 1217 * next port 1218 */ 1219 if (ocelot->lags[port]) { 1220 int n = __ffs(ocelot->lags[port]); 1221 1222 ocelot->lags[n] = ocelot->lags[port]; 1223 ocelot->lags[port] = 0; 1224 1225 ocelot_setup_lag(ocelot, n); 1226 } 1227 1228 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1229 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1230 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1231 ANA_PORT_PORT_CFG, port); 1232 1233 ocelot_set_aggr_pgids(ocelot); 1234 } 1235 EXPORT_SYMBOL(ocelot_port_lag_leave); 1236 1237 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1238 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1239 * In the special case that it's the NPI port that we're configuring, the 1240 * length of the tag and optional prefix needs to be accounted for privately, 1241 * in order to be able to sustain communication at the requested @sdu. 1242 */ 1243 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1244 { 1245 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1246 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1247 int pause_start, pause_stop; 1248 int atop_wm; 1249 1250 if (port == ocelot->npi) { 1251 maxlen += OCELOT_TAG_LEN; 1252 1253 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1254 maxlen += OCELOT_SHORT_PREFIX_LEN; 1255 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1256 maxlen += OCELOT_LONG_PREFIX_LEN; 1257 } 1258 1259 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1260 1261 /* Set Pause watermark hysteresis */ 1262 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1263 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1264 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1265 pause_start); 1266 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1267 pause_stop); 1268 1269 /* Tail dropping watermark */ 1270 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) / 1271 OCELOT_BUFFER_CELL_SZ; 1272 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(9 * maxlen), 1273 SYS_ATOP, port); 1274 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 1275 } 1276 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1277 1278 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1279 { 1280 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1281 1282 if (port == ocelot->npi) { 1283 max_mtu -= OCELOT_TAG_LEN; 1284 1285 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1286 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1287 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1288 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1289 } 1290 1291 return max_mtu; 1292 } 1293 EXPORT_SYMBOL(ocelot_get_max_mtu); 1294 1295 void ocelot_init_port(struct ocelot *ocelot, int port) 1296 { 1297 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1298 1299 skb_queue_head_init(&ocelot_port->tx_skbs); 1300 spin_lock_init(&ocelot_port->ts_id_lock); 1301 1302 /* Basic L2 initialization */ 1303 1304 /* Set MAC IFG Gaps 1305 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1306 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1307 */ 1308 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1309 DEV_MAC_IFG_CFG); 1310 1311 /* Load seed (0) and set MAC HDX late collision */ 1312 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1313 DEV_MAC_HDX_CFG_SEED_LOAD, 1314 DEV_MAC_HDX_CFG); 1315 mdelay(1); 1316 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1317 DEV_MAC_HDX_CFG); 1318 1319 /* Set Max Length and maximum tags allowed */ 1320 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1321 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1322 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1323 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1324 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1325 DEV_MAC_TAGS_CFG); 1326 1327 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1328 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1329 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1330 1331 /* Enable transmission of pause frames */ 1332 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1333 1334 /* Drop frames with multicast source address */ 1335 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1336 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1337 ANA_PORT_DROP_CFG, port); 1338 1339 /* Set default VLAN and tag type to 8021Q. */ 1340 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1341 REW_PORT_VLAN_CFG_PORT_TPID_M, 1342 REW_PORT_VLAN_CFG, port); 1343 1344 /* Enable vcap lookups */ 1345 ocelot_vcap_enable(ocelot, port); 1346 } 1347 EXPORT_SYMBOL(ocelot_init_port); 1348 1349 /* Configure and enable the CPU port module, which is a set of queues 1350 * accessible through register MMIO, frame DMA or Ethernet (in case 1351 * NPI mode is used). 1352 */ 1353 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1354 { 1355 int cpu = ocelot->num_phys_ports; 1356 1357 /* The unicast destination PGID for the CPU port module is unused */ 1358 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1359 /* Instead set up a multicast destination PGID for traffic copied to 1360 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1361 * addresses will be copied to the CPU via this PGID. 1362 */ 1363 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1364 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1365 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1366 ANA_PORT_PORT_CFG, cpu); 1367 1368 /* Enable CPU port module */ 1369 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1370 /* CPU port Injection/Extraction configuration */ 1371 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1372 ocelot->xtr_prefix); 1373 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1374 ocelot->inj_prefix); 1375 1376 /* Configure the CPU port to be VLAN aware */ 1377 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1378 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1379 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1380 ANA_PORT_VLAN_CFG, cpu); 1381 } 1382 1383 int ocelot_init(struct ocelot *ocelot) 1384 { 1385 char queue_name[32]; 1386 int i, ret; 1387 u32 port; 1388 1389 if (ocelot->ops->reset) { 1390 ret = ocelot->ops->reset(ocelot); 1391 if (ret) { 1392 dev_err(ocelot->dev, "Switch reset failed\n"); 1393 return ret; 1394 } 1395 } 1396 1397 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1398 sizeof(u32), GFP_KERNEL); 1399 if (!ocelot->lags) 1400 return -ENOMEM; 1401 1402 ocelot->stats = devm_kcalloc(ocelot->dev, 1403 ocelot->num_phys_ports * ocelot->num_stats, 1404 sizeof(u64), GFP_KERNEL); 1405 if (!ocelot->stats) 1406 return -ENOMEM; 1407 1408 mutex_init(&ocelot->stats_lock); 1409 mutex_init(&ocelot->ptp_lock); 1410 spin_lock_init(&ocelot->ptp_clock_lock); 1411 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1412 dev_name(ocelot->dev)); 1413 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1414 if (!ocelot->stats_queue) 1415 return -ENOMEM; 1416 1417 INIT_LIST_HEAD(&ocelot->multicast); 1418 ocelot_mact_init(ocelot); 1419 ocelot_vlan_init(ocelot); 1420 ocelot_vcap_init(ocelot); 1421 ocelot_cpu_port_init(ocelot); 1422 1423 for (port = 0; port < ocelot->num_phys_ports; port++) { 1424 /* Clear all counters (5 groups) */ 1425 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1426 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1427 SYS_STAT_CFG); 1428 } 1429 1430 /* Only use S-Tag */ 1431 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1432 1433 /* Aggregation mode */ 1434 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1435 ANA_AGGR_CFG_AC_DMAC_ENA | 1436 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1437 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1438 1439 /* Set MAC age time to default value. The entry is aged after 1440 * 2*AGE_PERIOD 1441 */ 1442 ocelot_write(ocelot, 1443 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1444 ANA_AUTOAGE); 1445 1446 /* Disable learning for frames discarded by VLAN ingress filtering */ 1447 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1448 1449 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1450 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1451 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1452 1453 /* Setup flooding PGIDs */ 1454 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1455 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1456 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1457 ANA_FLOODING, 0); 1458 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1459 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1460 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1461 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1462 ANA_FLOODING_IPMC); 1463 1464 for (port = 0; port < ocelot->num_phys_ports; port++) { 1465 /* Transmit the frame to the local port. */ 1466 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1467 /* Do not forward BPDU frames to the front ports. */ 1468 ocelot_write_gix(ocelot, 1469 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1470 ANA_PORT_CPU_FWD_BPDU_CFG, 1471 port); 1472 /* Ensure bridging is disabled */ 1473 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1474 } 1475 1476 /* Allow broadcast MAC frames. */ 1477 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1478 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1479 1480 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1481 } 1482 ocelot_write_rix(ocelot, 1483 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1484 ANA_PGID_PGID, PGID_MC); 1485 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1486 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1487 1488 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1489 * registers endianness. 1490 */ 1491 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1492 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1493 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1494 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1495 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1496 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1497 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1498 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1499 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1500 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1501 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1502 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1503 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1504 for (i = 0; i < 16; i++) 1505 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1506 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1507 ANA_CPUQ_8021_CFG, i); 1508 1509 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1510 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1511 OCELOT_STATS_CHECK_DELAY); 1512 1513 return 0; 1514 } 1515 EXPORT_SYMBOL(ocelot_init); 1516 1517 void ocelot_deinit(struct ocelot *ocelot) 1518 { 1519 cancel_delayed_work(&ocelot->stats_work); 1520 destroy_workqueue(ocelot->stats_queue); 1521 mutex_destroy(&ocelot->stats_lock); 1522 } 1523 EXPORT_SYMBOL(ocelot_deinit); 1524 1525 void ocelot_deinit_port(struct ocelot *ocelot, int port) 1526 { 1527 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1528 1529 skb_queue_purge(&ocelot_port->tx_skbs); 1530 } 1531 EXPORT_SYMBOL(ocelot_deinit_port); 1532 1533 MODULE_LICENSE("Dual MIT/GPL"); 1534