1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <linux/iopoll.h> 19 #include <net/arp.h> 20 #include <net/netevent.h> 21 #include <net/rtnetlink.h> 22 #include <net/switchdev.h> 23 24 #include "ocelot.h" 25 26 #define TABLE_UPDATE_SLEEP_US 10 27 #define TABLE_UPDATE_TIMEOUT_US 100000 28 29 /* MAC table entry types. 30 * ENTRYTYPE_NORMAL is subject to aging. 31 * ENTRYTYPE_LOCKED is not subject to aging. 32 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 33 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 34 */ 35 enum macaccess_entry_type { 36 ENTRYTYPE_NORMAL = 0, 37 ENTRYTYPE_LOCKED, 38 ENTRYTYPE_MACv4, 39 ENTRYTYPE_MACv6, 40 }; 41 42 struct ocelot_mact_entry { 43 u8 mac[ETH_ALEN]; 44 u16 vid; 45 enum macaccess_entry_type type; 46 }; 47 48 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 49 { 50 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 51 } 52 53 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 54 { 55 u32 val; 56 57 return readx_poll_timeout(ocelot_mact_read_macaccess, 58 ocelot, val, 59 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 60 MACACCESS_CMD_IDLE, 61 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 62 } 63 64 static void ocelot_mact_select(struct ocelot *ocelot, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid) 67 { 68 u32 macl = 0, mach = 0; 69 70 /* Set the MAC address to handle and the vlan associated in a format 71 * understood by the hardware. 72 */ 73 mach |= vid << 16; 74 mach |= mac[0] << 8; 75 mach |= mac[1] << 0; 76 macl |= mac[2] << 24; 77 macl |= mac[3] << 16; 78 macl |= mac[4] << 8; 79 macl |= mac[5] << 0; 80 81 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 82 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 83 84 } 85 86 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 87 const unsigned char mac[ETH_ALEN], 88 unsigned int vid, 89 enum macaccess_entry_type type) 90 { 91 ocelot_mact_select(ocelot, mac, vid); 92 93 /* Issue a write command */ 94 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 95 ANA_TABLES_MACACCESS_DEST_IDX(port) | 96 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 97 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 98 ANA_TABLES_MACACCESS); 99 100 return ocelot_mact_wait_for_completion(ocelot); 101 } 102 103 static int ocelot_mact_forget(struct ocelot *ocelot, 104 const unsigned char mac[ETH_ALEN], 105 unsigned int vid) 106 { 107 ocelot_mact_select(ocelot, mac, vid); 108 109 /* Issue a forget command */ 110 ocelot_write(ocelot, 111 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 112 ANA_TABLES_MACACCESS); 113 114 return ocelot_mact_wait_for_completion(ocelot); 115 } 116 117 static void ocelot_mact_init(struct ocelot *ocelot) 118 { 119 /* Configure the learning mode entries attributes: 120 * - Do not copy the frame to the CPU extraction queues. 121 * - Use the vlan and mac_cpoy for dmac lookup. 122 */ 123 ocelot_rmw(ocelot, 0, 124 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 125 | ANA_AGENCTRL_LEARN_FWD_KILL 126 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 127 ANA_AGENCTRL); 128 129 /* Clear the MAC table */ 130 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 131 } 132 133 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 134 { 135 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 136 } 137 138 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 139 { 140 u32 val; 141 142 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 143 ocelot, 144 val, 145 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 146 ANA_TABLES_VLANACCESS_CMD_IDLE, 147 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 148 } 149 150 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 151 { 152 /* Select the VID to configure */ 153 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 154 ANA_TABLES_VLANTIDX); 155 /* Set the vlan port members mask and issue a write command */ 156 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 157 ANA_TABLES_VLANACCESS_CMD_WRITE, 158 ANA_TABLES_VLANACCESS); 159 160 return ocelot_vlant_wait_for_completion(ocelot); 161 } 162 163 static void ocelot_vlan_mode(struct ocelot_port *port, 164 netdev_features_t features) 165 { 166 struct ocelot *ocelot = port->ocelot; 167 u8 p = port->chip_port; 168 u32 val; 169 170 /* Filtering */ 171 val = ocelot_read(ocelot, ANA_VLANMASK); 172 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 173 val |= BIT(p); 174 else 175 val &= ~BIT(p); 176 ocelot_write(ocelot, val, ANA_VLANMASK); 177 } 178 179 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 180 struct ocelot_port *port) 181 { 182 u32 val; 183 184 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 185 /* Default vlan to clasify for untagged frames (may be zero) */ 186 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 187 if (port->vlan_aware) 188 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 189 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 190 191 ocelot_rmw_gix(ocelot, val, 192 ANA_PORT_VLAN_CFG_VLAN_VID_M | 193 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 194 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 195 ANA_PORT_VLAN_CFG, port->chip_port); 196 197 /* Drop frames with multicast source address */ 198 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 199 if (port->vlan_aware && !port->vid) 200 /* If port is vlan-aware and tagged, drop untagged and priority 201 * tagged frames. 202 */ 203 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 204 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 205 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 206 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 207 208 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 209 val = REW_TAG_CFG_TAG_TPID_CFG(0); 210 211 if (port->vlan_aware) { 212 if (port->vid) 213 /* Tag all frames except when VID == DEFAULT_VLAN */ 214 val |= REW_TAG_CFG_TAG_CFG(1); 215 else 216 /* Tag all frames */ 217 val |= REW_TAG_CFG_TAG_CFG(3); 218 } 219 ocelot_rmw_gix(ocelot, val, 220 REW_TAG_CFG_TAG_TPID_CFG_M | 221 REW_TAG_CFG_TAG_CFG_M, 222 REW_TAG_CFG, port->chip_port); 223 224 /* Set default VLAN and tag type to 8021Q. */ 225 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 226 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 227 ocelot_rmw_gix(ocelot, val, 228 REW_PORT_VLAN_CFG_PORT_TPID_M | 229 REW_PORT_VLAN_CFG_PORT_VID_M, 230 REW_PORT_VLAN_CFG, port->chip_port); 231 } 232 233 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 234 bool untagged) 235 { 236 struct ocelot_port *port = netdev_priv(dev); 237 struct ocelot *ocelot = port->ocelot; 238 int ret; 239 240 /* Add the port MAC address to with the right VLAN information */ 241 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 242 ENTRYTYPE_LOCKED); 243 244 /* Make the port a member of the VLAN */ 245 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 246 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 247 if (ret) 248 return ret; 249 250 /* Default ingress vlan classification */ 251 if (pvid) 252 port->pvid = vid; 253 254 /* Untagged egress vlan clasification */ 255 if (untagged) 256 port->vid = vid; 257 258 ocelot_vlan_port_apply(ocelot, port); 259 260 return 0; 261 } 262 263 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 264 { 265 struct ocelot_port *port = netdev_priv(dev); 266 struct ocelot *ocelot = port->ocelot; 267 int ret; 268 269 /* 8021q removes VID 0 on module unload for all interfaces 270 * with VLAN filtering feature. We need to keep it to receive 271 * untagged traffic. 272 */ 273 if (vid == 0) 274 return 0; 275 276 /* Del the port MAC address to with the right VLAN information */ 277 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 278 279 /* Stop the port from being a member of the vlan */ 280 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 281 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 282 if (ret) 283 return ret; 284 285 /* Ingress */ 286 if (port->pvid == vid) 287 port->pvid = 0; 288 289 /* Egress */ 290 if (port->vid == vid) 291 port->vid = 0; 292 293 ocelot_vlan_port_apply(ocelot, port); 294 295 return 0; 296 } 297 298 static void ocelot_vlan_init(struct ocelot *ocelot) 299 { 300 u16 port, vid; 301 302 /* Clear VLAN table, by default all ports are members of all VLANs */ 303 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 304 ANA_TABLES_VLANACCESS); 305 ocelot_vlant_wait_for_completion(ocelot); 306 307 /* Configure the port VLAN memberships */ 308 for (vid = 1; vid < VLAN_N_VID; vid++) { 309 ocelot->vlan_mask[vid] = 0; 310 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 311 } 312 313 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 314 * traffic. It is added automatically if 8021q module is loaded, but 315 * we can't rely on it since module may be not loaded. 316 */ 317 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 318 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 319 320 /* Configure the CPU port to be VLAN aware */ 321 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 322 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 323 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 324 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 325 326 /* Set vlan ingress filter mask to all ports but the CPU port by 327 * default. 328 */ 329 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 330 331 for (port = 0; port < ocelot->num_phys_ports; port++) { 332 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 333 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 334 } 335 } 336 337 /* Watermark encode 338 * Bit 8: Unit; 0:1, 1:16 339 * Bit 7-0: Value to be multiplied with unit 340 */ 341 static u16 ocelot_wm_enc(u16 value) 342 { 343 if (value >= BIT(8)) 344 return BIT(8) | (value / 16); 345 346 return value; 347 } 348 349 static void ocelot_port_adjust_link(struct net_device *dev) 350 { 351 struct ocelot_port *port = netdev_priv(dev); 352 struct ocelot *ocelot = port->ocelot; 353 u8 p = port->chip_port; 354 int speed, atop_wm, mode = 0; 355 356 switch (dev->phydev->speed) { 357 case SPEED_10: 358 speed = OCELOT_SPEED_10; 359 break; 360 case SPEED_100: 361 speed = OCELOT_SPEED_100; 362 break; 363 case SPEED_1000: 364 speed = OCELOT_SPEED_1000; 365 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 366 break; 367 case SPEED_2500: 368 speed = OCELOT_SPEED_2500; 369 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 370 break; 371 default: 372 netdev_err(dev, "Unsupported PHY speed: %d\n", 373 dev->phydev->speed); 374 return; 375 } 376 377 phy_print_status(dev->phydev); 378 379 if (!dev->phydev->link) 380 return; 381 382 /* Only full duplex supported for now */ 383 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 384 mode, DEV_MAC_MODE_CFG); 385 386 /* Set MAC IFG Gaps 387 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 388 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 389 */ 390 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 391 392 /* Load seed (0) and set MAC HDX late collision */ 393 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 394 DEV_MAC_HDX_CFG_SEED_LOAD, 395 DEV_MAC_HDX_CFG); 396 mdelay(1); 397 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 398 DEV_MAC_HDX_CFG); 399 400 /* Disable HDX fast control */ 401 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 402 403 /* SGMII only for now */ 404 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 405 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 406 407 /* Enable PCS */ 408 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 409 410 /* No aneg on SGMII */ 411 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 412 413 /* No loopback */ 414 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 415 416 /* Set Max Length and maximum tags allowed */ 417 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 418 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 419 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 420 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 421 DEV_MAC_TAGS_CFG); 422 423 /* Enable MAC module */ 424 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 425 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 426 427 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 428 * reset */ 429 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 430 DEV_CLOCK_CFG); 431 432 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 433 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 435 436 /* No PFC */ 437 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 438 ANA_PFC_PFC_CFG, p); 439 440 /* Set Pause WM hysteresis 441 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 442 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 443 */ 444 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 445 SYS_PAUSE_CFG_PAUSE_STOP(101) | 446 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 447 448 /* Core: Enable port for frame transfer */ 449 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 450 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 451 QSYS_SWITCH_PORT_MODE_PORT_ENA, 452 QSYS_SWITCH_PORT_MODE, p); 453 454 /* Flow control */ 455 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 456 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 457 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 458 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 459 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 460 SYS_MAC_FC_CFG, p); 461 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 462 463 /* Tail dropping watermark */ 464 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 465 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 466 SYS_ATOP, p); 467 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 468 } 469 470 static int ocelot_port_open(struct net_device *dev) 471 { 472 struct ocelot_port *port = netdev_priv(dev); 473 struct ocelot *ocelot = port->ocelot; 474 int err; 475 476 /* Enable receiving frames on the port, and activate auto-learning of 477 * MAC addresses. 478 */ 479 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 480 ANA_PORT_PORT_CFG_RECV_ENA | 481 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 482 ANA_PORT_PORT_CFG, port->chip_port); 483 484 if (port->serdes) { 485 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 486 port->phy_mode); 487 if (err) { 488 netdev_err(dev, "Could not set mode of SerDes\n"); 489 return err; 490 } 491 } 492 493 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 494 port->phy_mode); 495 if (err) { 496 netdev_err(dev, "Could not attach to PHY\n"); 497 return err; 498 } 499 500 dev->phydev = port->phy; 501 502 phy_attached_info(port->phy); 503 phy_start(port->phy); 504 return 0; 505 } 506 507 static int ocelot_port_stop(struct net_device *dev) 508 { 509 struct ocelot_port *port = netdev_priv(dev); 510 511 phy_disconnect(port->phy); 512 513 dev->phydev = NULL; 514 515 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 516 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 517 QSYS_SWITCH_PORT_MODE, port->chip_port); 518 return 0; 519 } 520 521 /* Generate the IFH for frame injection 522 * 523 * The IFH is a 128bit-value 524 * bit 127: bypass the analyzer processing 525 * bit 56-67: destination mask 526 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 527 * bit 20-27: cpu extraction queue mask 528 * bit 16: tag type 0: C-tag, 1: S-tag 529 * bit 0-11: VID 530 */ 531 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 532 { 533 ifh[0] = IFH_INJ_BYPASS; 534 ifh[1] = (0xf00 & info->port) >> 8; 535 ifh[2] = (0xff & info->port) << 24; 536 ifh[3] = (info->tag_type << 16) | info->vid; 537 538 return 0; 539 } 540 541 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 542 { 543 struct ocelot_port *port = netdev_priv(dev); 544 struct ocelot *ocelot = port->ocelot; 545 u32 val, ifh[IFH_LEN]; 546 struct frame_info info = {}; 547 u8 grp = 0; /* Send everything on CPU group 0 */ 548 unsigned int i, count, last; 549 550 val = ocelot_read(ocelot, QS_INJ_STATUS); 551 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 552 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 553 return NETDEV_TX_BUSY; 554 555 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 556 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 557 558 info.port = BIT(port->chip_port); 559 info.tag_type = IFH_TAG_TYPE_C; 560 info.vid = skb_vlan_tag_get(skb); 561 ocelot_gen_ifh(ifh, &info); 562 563 for (i = 0; i < IFH_LEN; i++) 564 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 565 QS_INJ_WR, grp); 566 567 count = (skb->len + 3) / 4; 568 last = skb->len % 4; 569 for (i = 0; i < count; i++) { 570 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 571 } 572 573 /* Add padding */ 574 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 575 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 576 i++; 577 } 578 579 /* Indicate EOF and valid bytes in last word */ 580 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 581 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 582 QS_INJ_CTRL_EOF, 583 QS_INJ_CTRL, grp); 584 585 /* Add dummy CRC */ 586 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 587 skb_tx_timestamp(skb); 588 589 dev->stats.tx_packets++; 590 dev->stats.tx_bytes += skb->len; 591 dev_kfree_skb_any(skb); 592 593 return NETDEV_TX_OK; 594 } 595 596 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 597 { 598 struct ocelot_port *port = netdev_priv(dev); 599 600 return ocelot_mact_forget(port->ocelot, addr, port->pvid); 601 } 602 603 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 604 { 605 struct ocelot_port *port = netdev_priv(dev); 606 607 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid, 608 ENTRYTYPE_LOCKED); 609 } 610 611 static void ocelot_set_rx_mode(struct net_device *dev) 612 { 613 struct ocelot_port *port = netdev_priv(dev); 614 struct ocelot *ocelot = port->ocelot; 615 int i; 616 u32 val; 617 618 /* This doesn't handle promiscuous mode because the bridge core is 619 * setting IFF_PROMISC on all slave interfaces and all frames would be 620 * forwarded to the CPU port. 621 */ 622 val = GENMASK(ocelot->num_phys_ports - 1, 0); 623 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 624 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 625 626 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 627 } 628 629 static int ocelot_port_get_phys_port_name(struct net_device *dev, 630 char *buf, size_t len) 631 { 632 struct ocelot_port *port = netdev_priv(dev); 633 int ret; 634 635 ret = snprintf(buf, len, "p%d", port->chip_port); 636 if (ret >= len) 637 return -EINVAL; 638 639 return 0; 640 } 641 642 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 643 { 644 struct ocelot_port *port = netdev_priv(dev); 645 struct ocelot *ocelot = port->ocelot; 646 const struct sockaddr *addr = p; 647 648 /* Learn the new net device MAC address in the mac table. */ 649 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 650 ENTRYTYPE_LOCKED); 651 /* Then forget the previous one. */ 652 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 653 654 ether_addr_copy(dev->dev_addr, addr->sa_data); 655 return 0; 656 } 657 658 static void ocelot_get_stats64(struct net_device *dev, 659 struct rtnl_link_stats64 *stats) 660 { 661 struct ocelot_port *port = netdev_priv(dev); 662 struct ocelot *ocelot = port->ocelot; 663 664 /* Configure the port to read the stats from */ 665 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 666 SYS_STAT_CFG); 667 668 /* Get Rx stats */ 669 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 670 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 671 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 672 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 673 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 674 ocelot_read(ocelot, SYS_COUNT_RX_64) + 675 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 676 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 677 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 678 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 679 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 680 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 681 stats->rx_dropped = dev->stats.rx_dropped; 682 683 /* Get Tx stats */ 684 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 685 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 686 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 687 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 688 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 689 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 690 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 691 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 692 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 693 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 694 } 695 696 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 697 struct net_device *dev, const unsigned char *addr, 698 u16 vid, u16 flags, 699 struct netlink_ext_ack *extack) 700 { 701 struct ocelot_port *port = netdev_priv(dev); 702 struct ocelot *ocelot = port->ocelot; 703 704 if (!vid) { 705 if (!port->vlan_aware) 706 /* If the bridge is not VLAN aware and no VID was 707 * provided, set it to pvid to ensure the MAC entry 708 * matches incoming untagged packets 709 */ 710 vid = port->pvid; 711 else 712 /* If the bridge is VLAN aware a VID must be provided as 713 * otherwise the learnt entry wouldn't match any frame. 714 */ 715 return -EINVAL; 716 } 717 718 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 719 ENTRYTYPE_LOCKED); 720 } 721 722 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 723 struct net_device *dev, 724 const unsigned char *addr, u16 vid) 725 { 726 struct ocelot_port *port = netdev_priv(dev); 727 struct ocelot *ocelot = port->ocelot; 728 729 return ocelot_mact_forget(ocelot, addr, vid); 730 } 731 732 struct ocelot_dump_ctx { 733 struct net_device *dev; 734 struct sk_buff *skb; 735 struct netlink_callback *cb; 736 int idx; 737 }; 738 739 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 740 struct ocelot_dump_ctx *dump) 741 { 742 u32 portid = NETLINK_CB(dump->cb->skb).portid; 743 u32 seq = dump->cb->nlh->nlmsg_seq; 744 struct nlmsghdr *nlh; 745 struct ndmsg *ndm; 746 747 if (dump->idx < dump->cb->args[2]) 748 goto skip; 749 750 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 751 sizeof(*ndm), NLM_F_MULTI); 752 if (!nlh) 753 return -EMSGSIZE; 754 755 ndm = nlmsg_data(nlh); 756 ndm->ndm_family = AF_BRIDGE; 757 ndm->ndm_pad1 = 0; 758 ndm->ndm_pad2 = 0; 759 ndm->ndm_flags = NTF_SELF; 760 ndm->ndm_type = 0; 761 ndm->ndm_ifindex = dump->dev->ifindex; 762 ndm->ndm_state = NUD_REACHABLE; 763 764 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 765 goto nla_put_failure; 766 767 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 768 goto nla_put_failure; 769 770 nlmsg_end(dump->skb, nlh); 771 772 skip: 773 dump->idx++; 774 return 0; 775 776 nla_put_failure: 777 nlmsg_cancel(dump->skb, nlh); 778 return -EMSGSIZE; 779 } 780 781 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 782 struct ocelot_mact_entry *entry) 783 { 784 struct ocelot *ocelot = port->ocelot; 785 char mac[ETH_ALEN]; 786 u32 val, dst, macl, mach; 787 788 /* Set row and column to read from */ 789 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 790 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 791 792 /* Issue a read command */ 793 ocelot_write(ocelot, 794 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 795 ANA_TABLES_MACACCESS); 796 797 if (ocelot_mact_wait_for_completion(ocelot)) 798 return -ETIMEDOUT; 799 800 /* Read the entry flags */ 801 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 802 if (!(val & ANA_TABLES_MACACCESS_VALID)) 803 return -EINVAL; 804 805 /* If the entry read has another port configured as its destination, 806 * do not report it. 807 */ 808 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 809 if (dst != port->chip_port) 810 return -EINVAL; 811 812 /* Get the entry's MAC address and VLAN id */ 813 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 814 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 815 816 mac[0] = (mach >> 8) & 0xff; 817 mac[1] = (mach >> 0) & 0xff; 818 mac[2] = (macl >> 24) & 0xff; 819 mac[3] = (macl >> 16) & 0xff; 820 mac[4] = (macl >> 8) & 0xff; 821 mac[5] = (macl >> 0) & 0xff; 822 823 entry->vid = (mach >> 16) & 0xfff; 824 ether_addr_copy(entry->mac, mac); 825 826 return 0; 827 } 828 829 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 830 struct net_device *dev, 831 struct net_device *filter_dev, int *idx) 832 { 833 struct ocelot_port *port = netdev_priv(dev); 834 int i, j, ret = 0; 835 struct ocelot_dump_ctx dump = { 836 .dev = dev, 837 .skb = skb, 838 .cb = cb, 839 .idx = *idx, 840 }; 841 842 struct ocelot_mact_entry entry; 843 844 /* Loop through all the mac tables entries. There are 1024 rows of 4 845 * entries. 846 */ 847 for (i = 0; i < 1024; i++) { 848 for (j = 0; j < 4; j++) { 849 ret = ocelot_mact_read(port, i, j, &entry); 850 /* If the entry is invalid (wrong port, invalid...), 851 * skip it. 852 */ 853 if (ret == -EINVAL) 854 continue; 855 else if (ret) 856 goto end; 857 858 ret = ocelot_fdb_do_dump(&entry, &dump); 859 if (ret) 860 goto end; 861 } 862 } 863 864 end: 865 *idx = dump.idx; 866 return ret; 867 } 868 869 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 870 u16 vid) 871 { 872 return ocelot_vlan_vid_add(dev, vid, false, true); 873 } 874 875 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 876 u16 vid) 877 { 878 return ocelot_vlan_vid_del(dev, vid); 879 } 880 881 static int ocelot_set_features(struct net_device *dev, 882 netdev_features_t features) 883 { 884 struct ocelot_port *port = netdev_priv(dev); 885 netdev_features_t changed = dev->features ^ features; 886 887 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 888 ocelot_vlan_mode(port, features); 889 890 return 0; 891 } 892 893 static int ocelot_get_port_parent_id(struct net_device *dev, 894 struct netdev_phys_item_id *ppid) 895 { 896 struct ocelot_port *ocelot_port = netdev_priv(dev); 897 struct ocelot *ocelot = ocelot_port->ocelot; 898 899 ppid->id_len = sizeof(ocelot->base_mac); 900 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 901 902 return 0; 903 } 904 905 static const struct net_device_ops ocelot_port_netdev_ops = { 906 .ndo_open = ocelot_port_open, 907 .ndo_stop = ocelot_port_stop, 908 .ndo_start_xmit = ocelot_port_xmit, 909 .ndo_set_rx_mode = ocelot_set_rx_mode, 910 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 911 .ndo_set_mac_address = ocelot_port_set_mac_address, 912 .ndo_get_stats64 = ocelot_get_stats64, 913 .ndo_fdb_add = ocelot_fdb_add, 914 .ndo_fdb_del = ocelot_fdb_del, 915 .ndo_fdb_dump = ocelot_fdb_dump, 916 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 917 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 918 .ndo_set_features = ocelot_set_features, 919 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 920 }; 921 922 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 923 { 924 struct ocelot_port *port = netdev_priv(netdev); 925 struct ocelot *ocelot = port->ocelot; 926 int i; 927 928 if (sset != ETH_SS_STATS) 929 return; 930 931 for (i = 0; i < ocelot->num_stats; i++) 932 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 933 ETH_GSTRING_LEN); 934 } 935 936 static void ocelot_update_stats(struct ocelot *ocelot) 937 { 938 int i, j; 939 940 mutex_lock(&ocelot->stats_lock); 941 942 for (i = 0; i < ocelot->num_phys_ports; i++) { 943 /* Configure the port to read the stats from */ 944 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 945 946 for (j = 0; j < ocelot->num_stats; j++) { 947 u32 val; 948 unsigned int idx = i * ocelot->num_stats + j; 949 950 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 951 ocelot->stats_layout[j].offset); 952 953 if (val < (ocelot->stats[idx] & U32_MAX)) 954 ocelot->stats[idx] += (u64)1 << 32; 955 956 ocelot->stats[idx] = (ocelot->stats[idx] & 957 ~(u64)U32_MAX) + val; 958 } 959 } 960 961 mutex_unlock(&ocelot->stats_lock); 962 } 963 964 static void ocelot_check_stats_work(struct work_struct *work) 965 { 966 struct delayed_work *del_work = to_delayed_work(work); 967 struct ocelot *ocelot = container_of(del_work, struct ocelot, 968 stats_work); 969 970 ocelot_update_stats(ocelot); 971 972 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 973 OCELOT_STATS_CHECK_DELAY); 974 } 975 976 static void ocelot_get_ethtool_stats(struct net_device *dev, 977 struct ethtool_stats *stats, u64 *data) 978 { 979 struct ocelot_port *port = netdev_priv(dev); 980 struct ocelot *ocelot = port->ocelot; 981 int i; 982 983 /* check and update now */ 984 ocelot_update_stats(ocelot); 985 986 /* Copy all counters */ 987 for (i = 0; i < ocelot->num_stats; i++) 988 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 989 } 990 991 static int ocelot_get_sset_count(struct net_device *dev, int sset) 992 { 993 struct ocelot_port *port = netdev_priv(dev); 994 struct ocelot *ocelot = port->ocelot; 995 996 if (sset != ETH_SS_STATS) 997 return -EOPNOTSUPP; 998 return ocelot->num_stats; 999 } 1000 1001 static const struct ethtool_ops ocelot_ethtool_ops = { 1002 .get_strings = ocelot_get_strings, 1003 .get_ethtool_stats = ocelot_get_ethtool_stats, 1004 .get_sset_count = ocelot_get_sset_count, 1005 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1006 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1007 }; 1008 1009 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1010 struct switchdev_trans *trans, 1011 u8 state) 1012 { 1013 struct ocelot *ocelot = ocelot_port->ocelot; 1014 u32 port_cfg; 1015 int port, i; 1016 1017 if (switchdev_trans_ph_prepare(trans)) 1018 return 0; 1019 1020 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1021 return 0; 1022 1023 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1024 ocelot_port->chip_port); 1025 1026 switch (state) { 1027 case BR_STATE_FORWARDING: 1028 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1029 /* Fallthrough */ 1030 case BR_STATE_LEARNING: 1031 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1032 break; 1033 1034 default: 1035 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1036 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1037 break; 1038 } 1039 1040 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1041 ocelot_port->chip_port); 1042 1043 /* Apply FWD mask. The loop is needed to add/remove the current port as 1044 * a source for the other ports. 1045 */ 1046 for (port = 0; port < ocelot->num_phys_ports; port++) { 1047 if (ocelot->bridge_fwd_mask & BIT(port)) { 1048 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1049 1050 for (i = 0; i < ocelot->num_phys_ports; i++) { 1051 unsigned long bond_mask = ocelot->lags[i]; 1052 1053 if (!bond_mask) 1054 continue; 1055 1056 if (bond_mask & BIT(port)) { 1057 mask &= ~bond_mask; 1058 break; 1059 } 1060 } 1061 1062 ocelot_write_rix(ocelot, 1063 BIT(ocelot->num_phys_ports) | mask, 1064 ANA_PGID_PGID, PGID_SRC + port); 1065 } else { 1066 /* Only the CPU port, this is compatible with link 1067 * aggregation. 1068 */ 1069 ocelot_write_rix(ocelot, 1070 BIT(ocelot->num_phys_ports), 1071 ANA_PGID_PGID, PGID_SRC + port); 1072 } 1073 } 1074 1075 return 0; 1076 } 1077 1078 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1079 unsigned long ageing_clock_t) 1080 { 1081 struct ocelot *ocelot = ocelot_port->ocelot; 1082 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1083 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1084 1085 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1086 ANA_AUTOAGE); 1087 } 1088 1089 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1090 { 1091 struct ocelot *ocelot = port->ocelot; 1092 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1093 port->chip_port); 1094 1095 if (mc) 1096 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1097 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1098 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1099 else 1100 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1101 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1102 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1103 1104 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1105 } 1106 1107 static int ocelot_port_attr_set(struct net_device *dev, 1108 const struct switchdev_attr *attr, 1109 struct switchdev_trans *trans) 1110 { 1111 struct ocelot_port *ocelot_port = netdev_priv(dev); 1112 int err = 0; 1113 1114 switch (attr->id) { 1115 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1116 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1117 attr->u.stp_state); 1118 break; 1119 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1120 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1121 break; 1122 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1123 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1124 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1125 break; 1126 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1127 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1128 break; 1129 default: 1130 err = -EOPNOTSUPP; 1131 break; 1132 } 1133 1134 return err; 1135 } 1136 1137 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1138 const struct switchdev_obj_port_vlan *vlan, 1139 struct switchdev_trans *trans) 1140 { 1141 int ret; 1142 u16 vid; 1143 1144 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1145 ret = ocelot_vlan_vid_add(dev, vid, 1146 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1147 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1148 if (ret) 1149 return ret; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1156 const struct switchdev_obj_port_vlan *vlan) 1157 { 1158 int ret; 1159 u16 vid; 1160 1161 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1162 ret = ocelot_vlan_vid_del(dev, vid); 1163 1164 if (ret) 1165 return ret; 1166 } 1167 1168 return 0; 1169 } 1170 1171 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1172 const unsigned char *addr, 1173 u16 vid) 1174 { 1175 struct ocelot_multicast *mc; 1176 1177 list_for_each_entry(mc, &ocelot->multicast, list) { 1178 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1179 return mc; 1180 } 1181 1182 return NULL; 1183 } 1184 1185 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1186 const struct switchdev_obj_port_mdb *mdb, 1187 struct switchdev_trans *trans) 1188 { 1189 struct ocelot_port *port = netdev_priv(dev); 1190 struct ocelot *ocelot = port->ocelot; 1191 struct ocelot_multicast *mc; 1192 unsigned char addr[ETH_ALEN]; 1193 u16 vid = mdb->vid; 1194 bool new = false; 1195 1196 if (!vid) 1197 vid = port->pvid; 1198 1199 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1200 if (!mc) { 1201 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1202 if (!mc) 1203 return -ENOMEM; 1204 1205 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1206 mc->vid = vid; 1207 1208 list_add_tail(&mc->list, &ocelot->multicast); 1209 new = true; 1210 } 1211 1212 memcpy(addr, mc->addr, ETH_ALEN); 1213 addr[0] = 0; 1214 1215 if (!new) { 1216 addr[2] = mc->ports << 0; 1217 addr[1] = mc->ports << 8; 1218 ocelot_mact_forget(ocelot, addr, vid); 1219 } 1220 1221 mc->ports |= BIT(port->chip_port); 1222 addr[2] = mc->ports << 0; 1223 addr[1] = mc->ports << 8; 1224 1225 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1226 } 1227 1228 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1229 const struct switchdev_obj_port_mdb *mdb) 1230 { 1231 struct ocelot_port *port = netdev_priv(dev); 1232 struct ocelot *ocelot = port->ocelot; 1233 struct ocelot_multicast *mc; 1234 unsigned char addr[ETH_ALEN]; 1235 u16 vid = mdb->vid; 1236 1237 if (!vid) 1238 vid = port->pvid; 1239 1240 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1241 if (!mc) 1242 return -ENOENT; 1243 1244 memcpy(addr, mc->addr, ETH_ALEN); 1245 addr[2] = mc->ports << 0; 1246 addr[1] = mc->ports << 8; 1247 addr[0] = 0; 1248 ocelot_mact_forget(ocelot, addr, vid); 1249 1250 mc->ports &= ~BIT(port->chip_port); 1251 if (!mc->ports) { 1252 list_del(&mc->list); 1253 devm_kfree(ocelot->dev, mc); 1254 return 0; 1255 } 1256 1257 addr[2] = mc->ports << 0; 1258 addr[1] = mc->ports << 8; 1259 1260 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1261 } 1262 1263 static int ocelot_port_obj_add(struct net_device *dev, 1264 const struct switchdev_obj *obj, 1265 struct switchdev_trans *trans, 1266 struct netlink_ext_ack *extack) 1267 { 1268 int ret = 0; 1269 1270 switch (obj->id) { 1271 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1272 ret = ocelot_port_obj_add_vlan(dev, 1273 SWITCHDEV_OBJ_PORT_VLAN(obj), 1274 trans); 1275 break; 1276 case SWITCHDEV_OBJ_ID_PORT_MDB: 1277 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1278 trans); 1279 break; 1280 default: 1281 return -EOPNOTSUPP; 1282 } 1283 1284 return ret; 1285 } 1286 1287 static int ocelot_port_obj_del(struct net_device *dev, 1288 const struct switchdev_obj *obj) 1289 { 1290 int ret = 0; 1291 1292 switch (obj->id) { 1293 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1294 ret = ocelot_port_vlan_del_vlan(dev, 1295 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1296 break; 1297 case SWITCHDEV_OBJ_ID_PORT_MDB: 1298 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1299 break; 1300 default: 1301 return -EOPNOTSUPP; 1302 } 1303 1304 return ret; 1305 } 1306 1307 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1308 struct net_device *bridge) 1309 { 1310 struct ocelot *ocelot = ocelot_port->ocelot; 1311 1312 if (!ocelot->bridge_mask) { 1313 ocelot->hw_bridge_dev = bridge; 1314 } else { 1315 if (ocelot->hw_bridge_dev != bridge) 1316 /* This is adding the port to a second bridge, this is 1317 * unsupported */ 1318 return -ENODEV; 1319 } 1320 1321 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1322 1323 return 0; 1324 } 1325 1326 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1327 struct net_device *bridge) 1328 { 1329 struct ocelot *ocelot = ocelot_port->ocelot; 1330 1331 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1332 1333 if (!ocelot->bridge_mask) 1334 ocelot->hw_bridge_dev = NULL; 1335 1336 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1337 ocelot_port->vlan_aware = 0; 1338 ocelot_port->pvid = 0; 1339 ocelot_port->vid = 0; 1340 } 1341 1342 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1343 { 1344 int i, port, lag; 1345 1346 /* Reset destination and aggregation PGIDS */ 1347 for (port = 0; port < ocelot->num_phys_ports; port++) 1348 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1349 1350 for (i = PGID_AGGR; i < PGID_SRC; i++) 1351 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1352 ANA_PGID_PGID, i); 1353 1354 /* Now, set PGIDs for each LAG */ 1355 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1356 unsigned long bond_mask; 1357 int aggr_count = 0; 1358 u8 aggr_idx[16]; 1359 1360 bond_mask = ocelot->lags[lag]; 1361 if (!bond_mask) 1362 continue; 1363 1364 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1365 // Destination mask 1366 ocelot_write_rix(ocelot, bond_mask, 1367 ANA_PGID_PGID, port); 1368 aggr_idx[aggr_count] = port; 1369 aggr_count++; 1370 } 1371 1372 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1373 u32 ac; 1374 1375 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1376 ac &= ~bond_mask; 1377 ac |= BIT(aggr_idx[i % aggr_count]); 1378 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1379 } 1380 } 1381 } 1382 1383 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1384 { 1385 unsigned long bond_mask = ocelot->lags[lag]; 1386 unsigned int p; 1387 1388 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1389 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1390 1391 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1392 1393 /* Use lag port as logical port for port i */ 1394 ocelot_write_gix(ocelot, port_cfg | 1395 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1396 ANA_PORT_PORT_CFG, p); 1397 } 1398 } 1399 1400 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1401 struct net_device *bond) 1402 { 1403 struct ocelot *ocelot = ocelot_port->ocelot; 1404 int p = ocelot_port->chip_port; 1405 int lag, lp; 1406 struct net_device *ndev; 1407 u32 bond_mask = 0; 1408 1409 rcu_read_lock(); 1410 for_each_netdev_in_bond_rcu(bond, ndev) { 1411 struct ocelot_port *port = netdev_priv(ndev); 1412 1413 bond_mask |= BIT(port->chip_port); 1414 } 1415 rcu_read_unlock(); 1416 1417 lp = __ffs(bond_mask); 1418 1419 /* If the new port is the lowest one, use it as the logical port from 1420 * now on 1421 */ 1422 if (p == lp) { 1423 lag = p; 1424 ocelot->lags[p] = bond_mask; 1425 bond_mask &= ~BIT(p); 1426 if (bond_mask) { 1427 lp = __ffs(bond_mask); 1428 ocelot->lags[lp] = 0; 1429 } 1430 } else { 1431 lag = lp; 1432 ocelot->lags[lp] |= BIT(p); 1433 } 1434 1435 ocelot_setup_lag(ocelot, lag); 1436 ocelot_set_aggr_pgids(ocelot); 1437 1438 return 0; 1439 } 1440 1441 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1442 struct net_device *bond) 1443 { 1444 struct ocelot *ocelot = ocelot_port->ocelot; 1445 int p = ocelot_port->chip_port; 1446 u32 port_cfg; 1447 int i; 1448 1449 /* Remove port from any lag */ 1450 for (i = 0; i < ocelot->num_phys_ports; i++) 1451 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1452 1453 /* if it was the logical port of the lag, move the lag config to the 1454 * next port 1455 */ 1456 if (ocelot->lags[p]) { 1457 int n = __ffs(ocelot->lags[p]); 1458 1459 ocelot->lags[n] = ocelot->lags[p]; 1460 ocelot->lags[p] = 0; 1461 1462 ocelot_setup_lag(ocelot, n); 1463 } 1464 1465 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1466 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1467 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1468 ANA_PORT_PORT_CFG, p); 1469 1470 ocelot_set_aggr_pgids(ocelot); 1471 } 1472 1473 /* Checks if the net_device instance given to us originate from our driver. */ 1474 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1475 { 1476 return dev->netdev_ops == &ocelot_port_netdev_ops; 1477 } 1478 1479 static int ocelot_netdevice_port_event(struct net_device *dev, 1480 unsigned long event, 1481 struct netdev_notifier_changeupper_info *info) 1482 { 1483 struct ocelot_port *ocelot_port = netdev_priv(dev); 1484 int err = 0; 1485 1486 if (!ocelot_netdevice_dev_check(dev)) 1487 return 0; 1488 1489 switch (event) { 1490 case NETDEV_CHANGEUPPER: 1491 if (netif_is_bridge_master(info->upper_dev)) { 1492 if (info->linking) 1493 err = ocelot_port_bridge_join(ocelot_port, 1494 info->upper_dev); 1495 else 1496 ocelot_port_bridge_leave(ocelot_port, 1497 info->upper_dev); 1498 1499 ocelot_vlan_port_apply(ocelot_port->ocelot, 1500 ocelot_port); 1501 } 1502 if (netif_is_lag_master(info->upper_dev)) { 1503 if (info->linking) 1504 err = ocelot_port_lag_join(ocelot_port, 1505 info->upper_dev); 1506 else 1507 ocelot_port_lag_leave(ocelot_port, 1508 info->upper_dev); 1509 } 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 return err; 1516 } 1517 1518 static int ocelot_netdevice_event(struct notifier_block *unused, 1519 unsigned long event, void *ptr) 1520 { 1521 struct netdev_notifier_changeupper_info *info = ptr; 1522 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1523 int ret = 0; 1524 1525 if (event == NETDEV_PRECHANGEUPPER && 1526 netif_is_lag_master(info->upper_dev)) { 1527 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1528 struct netlink_ext_ack *extack; 1529 1530 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1531 extack = netdev_notifier_info_to_extack(&info->info); 1532 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1533 1534 ret = -EINVAL; 1535 goto notify; 1536 } 1537 } 1538 1539 if (netif_is_lag_master(dev)) { 1540 struct net_device *slave; 1541 struct list_head *iter; 1542 1543 netdev_for_each_lower_dev(dev, slave, iter) { 1544 ret = ocelot_netdevice_port_event(slave, event, info); 1545 if (ret) 1546 goto notify; 1547 } 1548 } else { 1549 ret = ocelot_netdevice_port_event(dev, event, info); 1550 } 1551 1552 notify: 1553 return notifier_from_errno(ret); 1554 } 1555 1556 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1557 .notifier_call = ocelot_netdevice_event, 1558 }; 1559 EXPORT_SYMBOL(ocelot_netdevice_nb); 1560 1561 static int ocelot_switchdev_event(struct notifier_block *unused, 1562 unsigned long event, void *ptr) 1563 { 1564 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1565 int err; 1566 1567 switch (event) { 1568 case SWITCHDEV_PORT_ATTR_SET: 1569 err = switchdev_handle_port_attr_set(dev, ptr, 1570 ocelot_netdevice_dev_check, 1571 ocelot_port_attr_set); 1572 return notifier_from_errno(err); 1573 } 1574 1575 return NOTIFY_DONE; 1576 } 1577 1578 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1579 .notifier_call = ocelot_switchdev_event, 1580 }; 1581 EXPORT_SYMBOL(ocelot_switchdev_nb); 1582 1583 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1584 unsigned long event, void *ptr) 1585 { 1586 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1587 int err; 1588 1589 switch (event) { 1590 /* Blocking events. */ 1591 case SWITCHDEV_PORT_OBJ_ADD: 1592 err = switchdev_handle_port_obj_add(dev, ptr, 1593 ocelot_netdevice_dev_check, 1594 ocelot_port_obj_add); 1595 return notifier_from_errno(err); 1596 case SWITCHDEV_PORT_OBJ_DEL: 1597 err = switchdev_handle_port_obj_del(dev, ptr, 1598 ocelot_netdevice_dev_check, 1599 ocelot_port_obj_del); 1600 return notifier_from_errno(err); 1601 case SWITCHDEV_PORT_ATTR_SET: 1602 err = switchdev_handle_port_attr_set(dev, ptr, 1603 ocelot_netdevice_dev_check, 1604 ocelot_port_attr_set); 1605 return notifier_from_errno(err); 1606 } 1607 1608 return NOTIFY_DONE; 1609 } 1610 1611 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1612 .notifier_call = ocelot_switchdev_blocking_event, 1613 }; 1614 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1615 1616 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1617 void __iomem *regs, 1618 struct phy_device *phy) 1619 { 1620 struct ocelot_port *ocelot_port; 1621 struct net_device *dev; 1622 int err; 1623 1624 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1625 if (!dev) 1626 return -ENOMEM; 1627 SET_NETDEV_DEV(dev, ocelot->dev); 1628 ocelot_port = netdev_priv(dev); 1629 ocelot_port->dev = dev; 1630 ocelot_port->ocelot = ocelot; 1631 ocelot_port->regs = regs; 1632 ocelot_port->chip_port = port; 1633 ocelot_port->phy = phy; 1634 ocelot->ports[port] = ocelot_port; 1635 1636 dev->netdev_ops = &ocelot_port_netdev_ops; 1637 dev->ethtool_ops = &ocelot_ethtool_ops; 1638 1639 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS; 1640 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1641 1642 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1643 dev->dev_addr[ETH_ALEN - 1] += port; 1644 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1645 ENTRYTYPE_LOCKED); 1646 1647 err = register_netdev(dev); 1648 if (err) { 1649 dev_err(ocelot->dev, "register_netdev failed\n"); 1650 goto err_register_netdev; 1651 } 1652 1653 /* Basic L2 initialization */ 1654 ocelot_vlan_port_apply(ocelot, ocelot_port); 1655 1656 return 0; 1657 1658 err_register_netdev: 1659 free_netdev(dev); 1660 return err; 1661 } 1662 EXPORT_SYMBOL(ocelot_probe_port); 1663 1664 int ocelot_init(struct ocelot *ocelot) 1665 { 1666 u32 port; 1667 int i, cpu = ocelot->num_phys_ports; 1668 char queue_name[32]; 1669 1670 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1671 sizeof(u32), GFP_KERNEL); 1672 if (!ocelot->lags) 1673 return -ENOMEM; 1674 1675 ocelot->stats = devm_kcalloc(ocelot->dev, 1676 ocelot->num_phys_ports * ocelot->num_stats, 1677 sizeof(u64), GFP_KERNEL); 1678 if (!ocelot->stats) 1679 return -ENOMEM; 1680 1681 mutex_init(&ocelot->stats_lock); 1682 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1683 dev_name(ocelot->dev)); 1684 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1685 if (!ocelot->stats_queue) 1686 return -ENOMEM; 1687 1688 ocelot_mact_init(ocelot); 1689 ocelot_vlan_init(ocelot); 1690 1691 for (port = 0; port < ocelot->num_phys_ports; port++) { 1692 /* Clear all counters (5 groups) */ 1693 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1694 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1695 SYS_STAT_CFG); 1696 } 1697 1698 /* Only use S-Tag */ 1699 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1700 1701 /* Aggregation mode */ 1702 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1703 ANA_AGGR_CFG_AC_DMAC_ENA | 1704 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1705 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1706 1707 /* Set MAC age time to default value. The entry is aged after 1708 * 2*AGE_PERIOD 1709 */ 1710 ocelot_write(ocelot, 1711 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1712 ANA_AUTOAGE); 1713 1714 /* Disable learning for frames discarded by VLAN ingress filtering */ 1715 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1716 1717 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1718 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1719 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1720 1721 /* Setup flooding PGIDs */ 1722 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1723 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1724 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1725 ANA_FLOODING, 0); 1726 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1727 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1728 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1729 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1730 ANA_FLOODING_IPMC); 1731 1732 for (port = 0; port < ocelot->num_phys_ports; port++) { 1733 /* Transmit the frame to the local port. */ 1734 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1735 /* Do not forward BPDU frames to the front ports. */ 1736 ocelot_write_gix(ocelot, 1737 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1738 ANA_PORT_CPU_FWD_BPDU_CFG, 1739 port); 1740 /* Ensure bridging is disabled */ 1741 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1742 } 1743 1744 /* Configure and enable the CPU port. */ 1745 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1746 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1747 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1748 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1749 ANA_PORT_PORT_CFG, cpu); 1750 1751 /* Allow broadcast MAC frames. */ 1752 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1753 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1754 1755 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1756 } 1757 ocelot_write_rix(ocelot, 1758 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1759 ANA_PGID_PGID, PGID_MC); 1760 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1761 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1762 1763 /* CPU port Injection/Extraction configuration */ 1764 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1765 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1766 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1767 QSYS_SWITCH_PORT_MODE, cpu); 1768 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1769 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1770 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1771 * registers endianness. 1772 */ 1773 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1774 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1775 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1776 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1777 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1778 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1779 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1780 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1781 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1782 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1783 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1784 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1785 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1786 for (i = 0; i < 16; i++) 1787 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1788 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1789 ANA_CPUQ_8021_CFG, i); 1790 1791 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1792 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1793 OCELOT_STATS_CHECK_DELAY); 1794 return 0; 1795 } 1796 EXPORT_SYMBOL(ocelot_init); 1797 1798 void ocelot_deinit(struct ocelot *ocelot) 1799 { 1800 destroy_workqueue(ocelot->stats_queue); 1801 mutex_destroy(&ocelot->stats_lock); 1802 } 1803 EXPORT_SYMBOL(ocelot_deinit); 1804 1805 MODULE_LICENSE("Dual MIT/GPL"); 1806