1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <linux/iopoll.h> 19 #include <net/arp.h> 20 #include <net/netevent.h> 21 #include <net/rtnetlink.h> 22 #include <net/switchdev.h> 23 24 #include "ocelot.h" 25 #include "ocelot_ace.h" 26 27 #define TABLE_UPDATE_SLEEP_US 10 28 #define TABLE_UPDATE_TIMEOUT_US 100000 29 30 /* MAC table entry types. 31 * ENTRYTYPE_NORMAL is subject to aging. 32 * ENTRYTYPE_LOCKED is not subject to aging. 33 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 34 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 35 */ 36 enum macaccess_entry_type { 37 ENTRYTYPE_NORMAL = 0, 38 ENTRYTYPE_LOCKED, 39 ENTRYTYPE_MACv4, 40 ENTRYTYPE_MACv6, 41 }; 42 43 struct ocelot_mact_entry { 44 u8 mac[ETH_ALEN]; 45 u16 vid; 46 enum macaccess_entry_type type; 47 }; 48 49 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 50 { 51 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 52 } 53 54 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 55 { 56 u32 val; 57 58 return readx_poll_timeout(ocelot_mact_read_macaccess, 59 ocelot, val, 60 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 61 MACACCESS_CMD_IDLE, 62 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 63 } 64 65 static void ocelot_mact_select(struct ocelot *ocelot, 66 const unsigned char mac[ETH_ALEN], 67 unsigned int vid) 68 { 69 u32 macl = 0, mach = 0; 70 71 /* Set the MAC address to handle and the vlan associated in a format 72 * understood by the hardware. 73 */ 74 mach |= vid << 16; 75 mach |= mac[0] << 8; 76 mach |= mac[1] << 0; 77 macl |= mac[2] << 24; 78 macl |= mac[3] << 16; 79 macl |= mac[4] << 8; 80 macl |= mac[5] << 0; 81 82 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 83 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 84 85 } 86 87 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 88 const unsigned char mac[ETH_ALEN], 89 unsigned int vid, 90 enum macaccess_entry_type type) 91 { 92 ocelot_mact_select(ocelot, mac, vid); 93 94 /* Issue a write command */ 95 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 96 ANA_TABLES_MACACCESS_DEST_IDX(port) | 97 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 104 static int ocelot_mact_forget(struct ocelot *ocelot, 105 const unsigned char mac[ETH_ALEN], 106 unsigned int vid) 107 { 108 ocelot_mact_select(ocelot, mac, vid); 109 110 /* Issue a forget command */ 111 ocelot_write(ocelot, 112 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 113 ANA_TABLES_MACACCESS); 114 115 return ocelot_mact_wait_for_completion(ocelot); 116 } 117 118 static void ocelot_mact_init(struct ocelot *ocelot) 119 { 120 /* Configure the learning mode entries attributes: 121 * - Do not copy the frame to the CPU extraction queues. 122 * - Use the vlan and mac_cpoy for dmac lookup. 123 */ 124 ocelot_rmw(ocelot, 0, 125 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 126 | ANA_AGENCTRL_LEARN_FWD_KILL 127 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 128 ANA_AGENCTRL); 129 130 /* Clear the MAC table */ 131 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 132 } 133 134 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 135 { 136 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 137 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 138 ANA_PORT_VCAP_S2_CFG, port); 139 } 140 141 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 142 { 143 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 144 } 145 146 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 147 { 148 u32 val; 149 150 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 151 ocelot, 152 val, 153 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 154 ANA_TABLES_VLANACCESS_CMD_IDLE, 155 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 156 } 157 158 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 159 { 160 /* Select the VID to configure */ 161 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 162 ANA_TABLES_VLANTIDX); 163 /* Set the vlan port members mask and issue a write command */ 164 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 165 ANA_TABLES_VLANACCESS_CMD_WRITE, 166 ANA_TABLES_VLANACCESS); 167 168 return ocelot_vlant_wait_for_completion(ocelot); 169 } 170 171 static void ocelot_vlan_mode(struct ocelot *ocelot, int port, 172 netdev_features_t features) 173 { 174 u32 val; 175 176 /* Filtering */ 177 val = ocelot_read(ocelot, ANA_VLANMASK); 178 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 179 val |= BIT(port); 180 else 181 val &= ~BIT(port); 182 ocelot_write(ocelot, val, ANA_VLANMASK); 183 } 184 185 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 186 u16 vid) 187 { 188 struct ocelot_port *ocelot_port = ocelot->ports[port]; 189 u32 val = 0; 190 191 if (ocelot_port->vid != vid) { 192 /* Always permit deleting the native VLAN (vid = 0) */ 193 if (ocelot_port->vid && vid) { 194 dev_err(ocelot->dev, 195 "Port already has a native VLAN: %d\n", 196 ocelot_port->vid); 197 return -EBUSY; 198 } 199 ocelot_port->vid = vid; 200 } 201 202 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 203 REW_PORT_VLAN_CFG_PORT_VID_M, 204 REW_PORT_VLAN_CFG, port); 205 206 if (ocelot_port->vlan_aware && !ocelot_port->vid) 207 /* If port is vlan-aware and tagged, drop untagged and priority 208 * tagged frames. 209 */ 210 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 211 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 212 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 213 ocelot_rmw_gix(ocelot, val, 214 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 215 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 216 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 217 ANA_PORT_DROP_CFG, port); 218 219 if (ocelot_port->vlan_aware) { 220 if (ocelot_port->vid) 221 /* Tag all frames except when VID == DEFAULT_VLAN */ 222 val = REW_TAG_CFG_TAG_CFG(1); 223 else 224 /* Tag all frames */ 225 val = REW_TAG_CFG_TAG_CFG(3); 226 } else { 227 /* Port tagging disabled. */ 228 val = REW_TAG_CFG_TAG_CFG(0); 229 } 230 ocelot_rmw_gix(ocelot, val, 231 REW_TAG_CFG_TAG_CFG_M, 232 REW_TAG_CFG, port); 233 234 return 0; 235 } 236 237 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 238 bool vlan_aware) 239 { 240 struct ocelot_port *ocelot_port = ocelot->ports[port]; 241 u32 val; 242 243 ocelot_port->vlan_aware = vlan_aware; 244 245 if (vlan_aware) 246 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 247 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 248 else 249 val = 0; 250 ocelot_rmw_gix(ocelot, val, 251 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 252 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 253 ANA_PORT_VLAN_CFG, port); 254 255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 256 } 257 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 258 259 /* Default vlan to clasify for untagged frames (may be zero) */ 260 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 261 { 262 struct ocelot_port *ocelot_port = ocelot->ports[port]; 263 264 ocelot_rmw_gix(ocelot, 265 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 266 ANA_PORT_VLAN_CFG_VLAN_VID_M, 267 ANA_PORT_VLAN_CFG, port); 268 269 ocelot_port->pvid = pvid; 270 } 271 272 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 273 bool untagged) 274 { 275 int ret; 276 277 /* Make the port a member of the VLAN */ 278 ocelot->vlan_mask[vid] |= BIT(port); 279 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 280 if (ret) 281 return ret; 282 283 /* Default ingress vlan classification */ 284 if (pvid) 285 ocelot_port_set_pvid(ocelot, port, vid); 286 287 /* Untagged egress vlan clasification */ 288 if (untagged) { 289 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 290 if (ret) 291 return ret; 292 } 293 294 return 0; 295 } 296 EXPORT_SYMBOL(ocelot_vlan_add); 297 298 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 299 bool untagged) 300 { 301 struct ocelot_port_private *priv = netdev_priv(dev); 302 struct ocelot_port *ocelot_port = &priv->port; 303 struct ocelot *ocelot = ocelot_port->ocelot; 304 int port = priv->chip_port; 305 int ret; 306 307 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged); 308 if (ret) 309 return ret; 310 311 /* Add the port MAC address to with the right VLAN information */ 312 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 313 ENTRYTYPE_LOCKED); 314 315 return 0; 316 } 317 318 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 319 { 320 struct ocelot_port *ocelot_port = ocelot->ports[port]; 321 int ret; 322 323 /* Stop the port from being a member of the vlan */ 324 ocelot->vlan_mask[vid] &= ~BIT(port); 325 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 326 if (ret) 327 return ret; 328 329 /* Ingress */ 330 if (ocelot_port->pvid == vid) 331 ocelot_port_set_pvid(ocelot, port, 0); 332 333 /* Egress */ 334 if (ocelot_port->vid == vid) 335 ocelot_port_set_native_vlan(ocelot, port, 0); 336 337 return 0; 338 } 339 EXPORT_SYMBOL(ocelot_vlan_del); 340 341 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 342 { 343 struct ocelot_port_private *priv = netdev_priv(dev); 344 struct ocelot *ocelot = priv->port.ocelot; 345 int port = priv->chip_port; 346 int ret; 347 348 /* 8021q removes VID 0 on module unload for all interfaces 349 * with VLAN filtering feature. We need to keep it to receive 350 * untagged traffic. 351 */ 352 if (vid == 0) 353 return 0; 354 355 ret = ocelot_vlan_del(ocelot, port, vid); 356 if (ret) 357 return ret; 358 359 /* Del the port MAC address to with the right VLAN information */ 360 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 361 362 return 0; 363 } 364 365 static void ocelot_vlan_init(struct ocelot *ocelot) 366 { 367 u16 port, vid; 368 369 /* Clear VLAN table, by default all ports are members of all VLANs */ 370 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 371 ANA_TABLES_VLANACCESS); 372 ocelot_vlant_wait_for_completion(ocelot); 373 374 /* Configure the port VLAN memberships */ 375 for (vid = 1; vid < VLAN_N_VID; vid++) { 376 ocelot->vlan_mask[vid] = 0; 377 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 378 } 379 380 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 381 * traffic. It is added automatically if 8021q module is loaded, but 382 * we can't rely on it since module may be not loaded. 383 */ 384 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 385 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 386 387 /* Set vlan ingress filter mask to all ports but the CPU port by 388 * default. 389 */ 390 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 391 ANA_VLANMASK); 392 393 for (port = 0; port < ocelot->num_phys_ports; port++) { 394 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 395 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 396 } 397 } 398 399 /* Watermark encode 400 * Bit 8: Unit; 0:1, 1:16 401 * Bit 7-0: Value to be multiplied with unit 402 */ 403 static u16 ocelot_wm_enc(u16 value) 404 { 405 if (value >= BIT(8)) 406 return BIT(8) | (value / 16); 407 408 return value; 409 } 410 411 void ocelot_adjust_link(struct ocelot *ocelot, int port, 412 struct phy_device *phydev) 413 { 414 struct ocelot_port *ocelot_port = ocelot->ports[port]; 415 int speed, mode = 0; 416 417 switch (phydev->speed) { 418 case SPEED_10: 419 speed = OCELOT_SPEED_10; 420 break; 421 case SPEED_100: 422 speed = OCELOT_SPEED_100; 423 break; 424 case SPEED_1000: 425 speed = OCELOT_SPEED_1000; 426 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 427 break; 428 case SPEED_2500: 429 speed = OCELOT_SPEED_2500; 430 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 431 break; 432 default: 433 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 434 port, phydev->speed); 435 return; 436 } 437 438 phy_print_status(phydev); 439 440 if (!phydev->link) 441 return; 442 443 /* Only full duplex supported for now */ 444 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 445 mode, DEV_MAC_MODE_CFG); 446 447 /* Disable HDX fast control */ 448 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 449 DEV_PORT_MISC); 450 451 /* SGMII only for now */ 452 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 453 PCS1G_MODE_CFG); 454 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 455 456 /* Enable PCS */ 457 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 458 459 /* No aneg on SGMII */ 460 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 461 462 /* No loopback */ 463 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 464 465 /* Enable MAC module */ 466 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 467 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 468 469 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 470 * reset */ 471 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 472 DEV_CLOCK_CFG); 473 474 /* No PFC */ 475 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 476 ANA_PFC_PFC_CFG, port); 477 478 /* Core: Enable port for frame transfer */ 479 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 480 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 481 QSYS_SWITCH_PORT_MODE_PORT_ENA, 482 QSYS_SWITCH_PORT_MODE, port); 483 484 /* Flow control */ 485 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 486 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 487 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 488 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 489 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 490 SYS_MAC_FC_CFG, port); 491 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 492 } 493 EXPORT_SYMBOL(ocelot_adjust_link); 494 495 static void ocelot_port_adjust_link(struct net_device *dev) 496 { 497 struct ocelot_port_private *priv = netdev_priv(dev); 498 struct ocelot *ocelot = priv->port.ocelot; 499 int port = priv->chip_port; 500 501 ocelot_adjust_link(ocelot, port, dev->phydev); 502 } 503 504 void ocelot_port_enable(struct ocelot *ocelot, int port, 505 struct phy_device *phy) 506 { 507 /* Enable receiving frames on the port, and activate auto-learning of 508 * MAC addresses. 509 */ 510 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 511 ANA_PORT_PORT_CFG_RECV_ENA | 512 ANA_PORT_PORT_CFG_PORTID_VAL(port), 513 ANA_PORT_PORT_CFG, port); 514 } 515 EXPORT_SYMBOL(ocelot_port_enable); 516 517 static int ocelot_port_open(struct net_device *dev) 518 { 519 struct ocelot_port_private *priv = netdev_priv(dev); 520 struct ocelot_port *ocelot_port = &priv->port; 521 struct ocelot *ocelot = ocelot_port->ocelot; 522 int port = priv->chip_port; 523 int err; 524 525 if (priv->serdes) { 526 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET, 527 ocelot_port->phy_mode); 528 if (err) { 529 netdev_err(dev, "Could not set mode of SerDes\n"); 530 return err; 531 } 532 } 533 534 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link, 535 ocelot_port->phy_mode); 536 if (err) { 537 netdev_err(dev, "Could not attach to PHY\n"); 538 return err; 539 } 540 541 dev->phydev = priv->phy; 542 543 phy_attached_info(priv->phy); 544 phy_start(priv->phy); 545 546 ocelot_port_enable(ocelot, port, priv->phy); 547 548 return 0; 549 } 550 551 void ocelot_port_disable(struct ocelot *ocelot, int port) 552 { 553 struct ocelot_port *ocelot_port = ocelot->ports[port]; 554 555 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 556 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 557 QSYS_SWITCH_PORT_MODE, port); 558 } 559 EXPORT_SYMBOL(ocelot_port_disable); 560 561 static int ocelot_port_stop(struct net_device *dev) 562 { 563 struct ocelot_port_private *priv = netdev_priv(dev); 564 struct ocelot *ocelot = priv->port.ocelot; 565 int port = priv->chip_port; 566 567 phy_disconnect(priv->phy); 568 569 dev->phydev = NULL; 570 571 ocelot_port_disable(ocelot, port); 572 573 return 0; 574 } 575 576 /* Generate the IFH for frame injection 577 * 578 * The IFH is a 128bit-value 579 * bit 127: bypass the analyzer processing 580 * bit 56-67: destination mask 581 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 582 * bit 20-27: cpu extraction queue mask 583 * bit 16: tag type 0: C-tag, 1: S-tag 584 * bit 0-11: VID 585 */ 586 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 587 { 588 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 589 ifh[1] = (0xf00 & info->port) >> 8; 590 ifh[2] = (0xff & info->port) << 24; 591 ifh[3] = (info->tag_type << 16) | info->vid; 592 593 return 0; 594 } 595 596 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 597 struct sk_buff *skb) 598 { 599 struct skb_shared_info *shinfo = skb_shinfo(skb); 600 struct ocelot *ocelot = ocelot_port->ocelot; 601 602 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 603 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 604 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 605 /* Store timestamp ID in cb[0] of sk_buff */ 606 skb->cb[0] = ocelot_port->ts_id % 4; 607 skb_queue_tail(&ocelot_port->tx_skbs, skb); 608 return 0; 609 } 610 return -ENODATA; 611 } 612 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 613 614 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 615 { 616 struct ocelot_port_private *priv = netdev_priv(dev); 617 struct skb_shared_info *shinfo = skb_shinfo(skb); 618 struct ocelot_port *ocelot_port = &priv->port; 619 struct ocelot *ocelot = ocelot_port->ocelot; 620 u32 val, ifh[OCELOT_TAG_LEN / 4]; 621 struct frame_info info = {}; 622 u8 grp = 0; /* Send everything on CPU group 0 */ 623 unsigned int i, count, last; 624 int port = priv->chip_port; 625 626 val = ocelot_read(ocelot, QS_INJ_STATUS); 627 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 628 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 629 return NETDEV_TX_BUSY; 630 631 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 632 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 633 634 info.port = BIT(port); 635 info.tag_type = IFH_TAG_TYPE_C; 636 info.vid = skb_vlan_tag_get(skb); 637 638 /* Check if timestamping is needed */ 639 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 640 info.rew_op = ocelot_port->ptp_cmd; 641 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 642 info.rew_op |= (ocelot_port->ts_id % 4) << 3; 643 } 644 645 ocelot_gen_ifh(ifh, &info); 646 647 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 648 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 649 QS_INJ_WR, grp); 650 651 count = (skb->len + 3) / 4; 652 last = skb->len % 4; 653 for (i = 0; i < count; i++) { 654 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 655 } 656 657 /* Add padding */ 658 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 659 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 660 i++; 661 } 662 663 /* Indicate EOF and valid bytes in last word */ 664 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 665 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 666 QS_INJ_CTRL_EOF, 667 QS_INJ_CTRL, grp); 668 669 /* Add dummy CRC */ 670 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 671 skb_tx_timestamp(skb); 672 673 dev->stats.tx_packets++; 674 dev->stats.tx_bytes += skb->len; 675 676 if (!ocelot_port_add_txtstamp_skb(ocelot_port, skb)) { 677 ocelot_port->ts_id++; 678 return NETDEV_TX_OK; 679 } 680 681 dev_kfree_skb_any(skb); 682 return NETDEV_TX_OK; 683 } 684 685 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 686 struct timespec64 *ts) 687 { 688 unsigned long flags; 689 u32 val; 690 691 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 692 693 /* Read current PTP time to get seconds */ 694 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 695 696 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 697 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 698 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 699 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 700 701 /* Read packet HW timestamp from FIFO */ 702 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 703 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 704 705 /* Sec has incremented since the ts was registered */ 706 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 707 ts->tv_sec--; 708 709 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 710 } 711 712 void ocelot_get_txtstamp(struct ocelot *ocelot) 713 { 714 int budget = OCELOT_PTP_QUEUE_SZ; 715 716 while (budget--) { 717 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 718 struct skb_shared_hwtstamps shhwtstamps; 719 struct ocelot_port *port; 720 struct timespec64 ts; 721 unsigned long flags; 722 u32 val, id, txport; 723 724 val = ocelot_read(ocelot, SYS_PTP_STATUS); 725 726 /* Check if a timestamp can be retrieved */ 727 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 728 break; 729 730 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 731 732 /* Retrieve the ts ID and Tx port */ 733 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 734 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 735 736 /* Retrieve its associated skb */ 737 port = ocelot->ports[txport]; 738 739 spin_lock_irqsave(&port->tx_skbs.lock, flags); 740 741 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 742 if (skb->cb[0] != id) 743 continue; 744 __skb_unlink(skb, &port->tx_skbs); 745 skb_match = skb; 746 break; 747 } 748 749 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 750 751 /* Next ts */ 752 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 753 754 if (unlikely(!skb_match)) 755 continue; 756 757 /* Get the h/w timestamp */ 758 ocelot_get_hwtimestamp(ocelot, &ts); 759 760 /* Set the timestamp into the skb */ 761 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 762 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 763 skb_tstamp_tx(skb_match, &shhwtstamps); 764 765 dev_kfree_skb_any(skb_match); 766 } 767 } 768 EXPORT_SYMBOL(ocelot_get_txtstamp); 769 770 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 771 { 772 struct ocelot_port_private *priv = netdev_priv(dev); 773 struct ocelot_port *ocelot_port = &priv->port; 774 struct ocelot *ocelot = ocelot_port->ocelot; 775 776 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid); 777 } 778 779 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 780 { 781 struct ocelot_port_private *priv = netdev_priv(dev); 782 struct ocelot_port *ocelot_port = &priv->port; 783 struct ocelot *ocelot = ocelot_port->ocelot; 784 785 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid, 786 ENTRYTYPE_LOCKED); 787 } 788 789 static void ocelot_set_rx_mode(struct net_device *dev) 790 { 791 struct ocelot_port_private *priv = netdev_priv(dev); 792 struct ocelot *ocelot = priv->port.ocelot; 793 u32 val; 794 int i; 795 796 /* This doesn't handle promiscuous mode because the bridge core is 797 * setting IFF_PROMISC on all slave interfaces and all frames would be 798 * forwarded to the CPU port. 799 */ 800 val = GENMASK(ocelot->num_phys_ports - 1, 0); 801 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 802 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 803 804 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 805 } 806 807 static int ocelot_port_get_phys_port_name(struct net_device *dev, 808 char *buf, size_t len) 809 { 810 struct ocelot_port_private *priv = netdev_priv(dev); 811 int port = priv->chip_port; 812 int ret; 813 814 ret = snprintf(buf, len, "p%d", port); 815 if (ret >= len) 816 return -EINVAL; 817 818 return 0; 819 } 820 821 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 822 { 823 struct ocelot_port_private *priv = netdev_priv(dev); 824 struct ocelot_port *ocelot_port = &priv->port; 825 struct ocelot *ocelot = ocelot_port->ocelot; 826 const struct sockaddr *addr = p; 827 828 /* Learn the new net device MAC address in the mac table. */ 829 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid, 830 ENTRYTYPE_LOCKED); 831 /* Then forget the previous one. */ 832 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid); 833 834 ether_addr_copy(dev->dev_addr, addr->sa_data); 835 return 0; 836 } 837 838 static void ocelot_get_stats64(struct net_device *dev, 839 struct rtnl_link_stats64 *stats) 840 { 841 struct ocelot_port_private *priv = netdev_priv(dev); 842 struct ocelot *ocelot = priv->port.ocelot; 843 int port = priv->chip_port; 844 845 /* Configure the port to read the stats from */ 846 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), 847 SYS_STAT_CFG); 848 849 /* Get Rx stats */ 850 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 851 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 852 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 853 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 854 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 855 ocelot_read(ocelot, SYS_COUNT_RX_64) + 856 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 857 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 858 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 859 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 860 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 861 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 862 stats->rx_dropped = dev->stats.rx_dropped; 863 864 /* Get Tx stats */ 865 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 866 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 867 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 868 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 869 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 870 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 871 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 872 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 873 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 874 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 875 } 876 877 int ocelot_fdb_add(struct ocelot *ocelot, int port, 878 const unsigned char *addr, u16 vid) 879 { 880 struct ocelot_port *ocelot_port = ocelot->ports[port]; 881 882 if (!vid) { 883 if (!ocelot_port->vlan_aware) 884 /* If the bridge is not VLAN aware and no VID was 885 * provided, set it to pvid to ensure the MAC entry 886 * matches incoming untagged packets 887 */ 888 vid = ocelot_port->pvid; 889 else 890 /* If the bridge is VLAN aware a VID must be provided as 891 * otherwise the learnt entry wouldn't match any frame. 892 */ 893 return -EINVAL; 894 } 895 896 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 897 } 898 EXPORT_SYMBOL(ocelot_fdb_add); 899 900 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 901 struct net_device *dev, 902 const unsigned char *addr, 903 u16 vid, u16 flags, 904 struct netlink_ext_ack *extack) 905 { 906 struct ocelot_port_private *priv = netdev_priv(dev); 907 struct ocelot *ocelot = priv->port.ocelot; 908 int port = priv->chip_port; 909 910 return ocelot_fdb_add(ocelot, port, addr, vid); 911 } 912 913 int ocelot_fdb_del(struct ocelot *ocelot, int port, 914 const unsigned char *addr, u16 vid) 915 { 916 return ocelot_mact_forget(ocelot, addr, vid); 917 } 918 EXPORT_SYMBOL(ocelot_fdb_del); 919 920 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 921 struct net_device *dev, 922 const unsigned char *addr, u16 vid) 923 { 924 struct ocelot_port_private *priv = netdev_priv(dev); 925 struct ocelot *ocelot = priv->port.ocelot; 926 int port = priv->chip_port; 927 928 return ocelot_fdb_del(ocelot, port, addr, vid); 929 } 930 931 struct ocelot_dump_ctx { 932 struct net_device *dev; 933 struct sk_buff *skb; 934 struct netlink_callback *cb; 935 int idx; 936 }; 937 938 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 939 bool is_static, void *data) 940 { 941 struct ocelot_dump_ctx *dump = data; 942 u32 portid = NETLINK_CB(dump->cb->skb).portid; 943 u32 seq = dump->cb->nlh->nlmsg_seq; 944 struct nlmsghdr *nlh; 945 struct ndmsg *ndm; 946 947 if (dump->idx < dump->cb->args[2]) 948 goto skip; 949 950 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 951 sizeof(*ndm), NLM_F_MULTI); 952 if (!nlh) 953 return -EMSGSIZE; 954 955 ndm = nlmsg_data(nlh); 956 ndm->ndm_family = AF_BRIDGE; 957 ndm->ndm_pad1 = 0; 958 ndm->ndm_pad2 = 0; 959 ndm->ndm_flags = NTF_SELF; 960 ndm->ndm_type = 0; 961 ndm->ndm_ifindex = dump->dev->ifindex; 962 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 963 964 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 965 goto nla_put_failure; 966 967 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 968 goto nla_put_failure; 969 970 nlmsg_end(dump->skb, nlh); 971 972 skip: 973 dump->idx++; 974 return 0; 975 976 nla_put_failure: 977 nlmsg_cancel(dump->skb, nlh); 978 return -EMSGSIZE; 979 } 980 981 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 982 struct ocelot_mact_entry *entry) 983 { 984 u32 val, dst, macl, mach; 985 char mac[ETH_ALEN]; 986 987 /* Set row and column to read from */ 988 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 989 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 990 991 /* Issue a read command */ 992 ocelot_write(ocelot, 993 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 994 ANA_TABLES_MACACCESS); 995 996 if (ocelot_mact_wait_for_completion(ocelot)) 997 return -ETIMEDOUT; 998 999 /* Read the entry flags */ 1000 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1001 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1002 return -EINVAL; 1003 1004 /* If the entry read has another port configured as its destination, 1005 * do not report it. 1006 */ 1007 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1008 if (dst != port) 1009 return -EINVAL; 1010 1011 /* Get the entry's MAC address and VLAN id */ 1012 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1013 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1014 1015 mac[0] = (mach >> 8) & 0xff; 1016 mac[1] = (mach >> 0) & 0xff; 1017 mac[2] = (macl >> 24) & 0xff; 1018 mac[3] = (macl >> 16) & 0xff; 1019 mac[4] = (macl >> 8) & 0xff; 1020 mac[5] = (macl >> 0) & 0xff; 1021 1022 entry->vid = (mach >> 16) & 0xfff; 1023 ether_addr_copy(entry->mac, mac); 1024 1025 return 0; 1026 } 1027 1028 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1029 dsa_fdb_dump_cb_t *cb, void *data) 1030 { 1031 int i, j; 1032 1033 /* Loop through all the mac tables entries. */ 1034 for (i = 0; i < ocelot->num_mact_rows; i++) { 1035 for (j = 0; j < 4; j++) { 1036 struct ocelot_mact_entry entry; 1037 bool is_static; 1038 int ret; 1039 1040 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1041 /* If the entry is invalid (wrong port, invalid...), 1042 * skip it. 1043 */ 1044 if (ret == -EINVAL) 1045 continue; 1046 else if (ret) 1047 return ret; 1048 1049 is_static = (entry.type == ENTRYTYPE_LOCKED); 1050 1051 ret = cb(entry.mac, entry.vid, is_static, data); 1052 if (ret) 1053 return ret; 1054 } 1055 } 1056 1057 return 0; 1058 } 1059 EXPORT_SYMBOL(ocelot_fdb_dump); 1060 1061 static int ocelot_port_fdb_dump(struct sk_buff *skb, 1062 struct netlink_callback *cb, 1063 struct net_device *dev, 1064 struct net_device *filter_dev, int *idx) 1065 { 1066 struct ocelot_port_private *priv = netdev_priv(dev); 1067 struct ocelot *ocelot = priv->port.ocelot; 1068 struct ocelot_dump_ctx dump = { 1069 .dev = dev, 1070 .skb = skb, 1071 .cb = cb, 1072 .idx = *idx, 1073 }; 1074 int port = priv->chip_port; 1075 int ret; 1076 1077 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump); 1078 1079 *idx = dump.idx; 1080 1081 return ret; 1082 } 1083 1084 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 1085 u16 vid) 1086 { 1087 return ocelot_vlan_vid_add(dev, vid, false, false); 1088 } 1089 1090 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 1091 u16 vid) 1092 { 1093 return ocelot_vlan_vid_del(dev, vid); 1094 } 1095 1096 static int ocelot_set_features(struct net_device *dev, 1097 netdev_features_t features) 1098 { 1099 netdev_features_t changed = dev->features ^ features; 1100 struct ocelot_port_private *priv = netdev_priv(dev); 1101 struct ocelot *ocelot = priv->port.ocelot; 1102 int port = priv->chip_port; 1103 1104 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1105 priv->tc.offload_cnt) { 1106 netdev_err(dev, 1107 "Cannot disable HW TC offload while offloads active\n"); 1108 return -EBUSY; 1109 } 1110 1111 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 1112 ocelot_vlan_mode(ocelot, port, features); 1113 1114 return 0; 1115 } 1116 1117 static int ocelot_get_port_parent_id(struct net_device *dev, 1118 struct netdev_phys_item_id *ppid) 1119 { 1120 struct ocelot_port_private *priv = netdev_priv(dev); 1121 struct ocelot *ocelot = priv->port.ocelot; 1122 1123 ppid->id_len = sizeof(ocelot->base_mac); 1124 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 1125 1126 return 0; 1127 } 1128 1129 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1130 { 1131 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1132 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1133 } 1134 EXPORT_SYMBOL(ocelot_hwstamp_get); 1135 1136 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1137 { 1138 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1139 struct hwtstamp_config cfg; 1140 1141 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1142 return -EFAULT; 1143 1144 /* reserved for future extensions */ 1145 if (cfg.flags) 1146 return -EINVAL; 1147 1148 /* Tx type sanity check */ 1149 switch (cfg.tx_type) { 1150 case HWTSTAMP_TX_ON: 1151 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1152 break; 1153 case HWTSTAMP_TX_ONESTEP_SYNC: 1154 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1155 * need to update the origin time. 1156 */ 1157 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1158 break; 1159 case HWTSTAMP_TX_OFF: 1160 ocelot_port->ptp_cmd = 0; 1161 break; 1162 default: 1163 return -ERANGE; 1164 } 1165 1166 mutex_lock(&ocelot->ptp_lock); 1167 1168 switch (cfg.rx_filter) { 1169 case HWTSTAMP_FILTER_NONE: 1170 break; 1171 case HWTSTAMP_FILTER_ALL: 1172 case HWTSTAMP_FILTER_SOME: 1173 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1174 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1175 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1176 case HWTSTAMP_FILTER_NTP_ALL: 1177 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1178 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1179 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1180 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1181 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1182 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1183 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1184 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1185 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1186 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1187 break; 1188 default: 1189 mutex_unlock(&ocelot->ptp_lock); 1190 return -ERANGE; 1191 } 1192 1193 /* Commit back the result & save it */ 1194 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1195 mutex_unlock(&ocelot->ptp_lock); 1196 1197 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1198 } 1199 EXPORT_SYMBOL(ocelot_hwstamp_set); 1200 1201 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1202 { 1203 struct ocelot_port_private *priv = netdev_priv(dev); 1204 struct ocelot *ocelot = priv->port.ocelot; 1205 int port = priv->chip_port; 1206 1207 /* If the attached PHY device isn't capable of timestamping operations, 1208 * use our own (when possible). 1209 */ 1210 if (!phy_has_hwtstamp(dev->phydev) && ocelot->ptp) { 1211 switch (cmd) { 1212 case SIOCSHWTSTAMP: 1213 return ocelot_hwstamp_set(ocelot, port, ifr); 1214 case SIOCGHWTSTAMP: 1215 return ocelot_hwstamp_get(ocelot, port, ifr); 1216 } 1217 } 1218 1219 return phy_mii_ioctl(dev->phydev, ifr, cmd); 1220 } 1221 1222 static const struct net_device_ops ocelot_port_netdev_ops = { 1223 .ndo_open = ocelot_port_open, 1224 .ndo_stop = ocelot_port_stop, 1225 .ndo_start_xmit = ocelot_port_xmit, 1226 .ndo_set_rx_mode = ocelot_set_rx_mode, 1227 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1228 .ndo_set_mac_address = ocelot_port_set_mac_address, 1229 .ndo_get_stats64 = ocelot_get_stats64, 1230 .ndo_fdb_add = ocelot_port_fdb_add, 1231 .ndo_fdb_del = ocelot_port_fdb_del, 1232 .ndo_fdb_dump = ocelot_port_fdb_dump, 1233 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1234 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1235 .ndo_set_features = ocelot_set_features, 1236 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1237 .ndo_setup_tc = ocelot_setup_tc, 1238 .ndo_do_ioctl = ocelot_ioctl, 1239 }; 1240 1241 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1242 { 1243 int i; 1244 1245 if (sset != ETH_SS_STATS) 1246 return; 1247 1248 for (i = 0; i < ocelot->num_stats; i++) 1249 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1250 ETH_GSTRING_LEN); 1251 } 1252 EXPORT_SYMBOL(ocelot_get_strings); 1253 1254 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset, 1255 u8 *data) 1256 { 1257 struct ocelot_port_private *priv = netdev_priv(netdev); 1258 struct ocelot *ocelot = priv->port.ocelot; 1259 int port = priv->chip_port; 1260 1261 ocelot_get_strings(ocelot, port, sset, data); 1262 } 1263 1264 static void ocelot_update_stats(struct ocelot *ocelot) 1265 { 1266 int i, j; 1267 1268 mutex_lock(&ocelot->stats_lock); 1269 1270 for (i = 0; i < ocelot->num_phys_ports; i++) { 1271 /* Configure the port to read the stats from */ 1272 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1273 1274 for (j = 0; j < ocelot->num_stats; j++) { 1275 u32 val; 1276 unsigned int idx = i * ocelot->num_stats + j; 1277 1278 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1279 ocelot->stats_layout[j].offset); 1280 1281 if (val < (ocelot->stats[idx] & U32_MAX)) 1282 ocelot->stats[idx] += (u64)1 << 32; 1283 1284 ocelot->stats[idx] = (ocelot->stats[idx] & 1285 ~(u64)U32_MAX) + val; 1286 } 1287 } 1288 1289 mutex_unlock(&ocelot->stats_lock); 1290 } 1291 1292 static void ocelot_check_stats_work(struct work_struct *work) 1293 { 1294 struct delayed_work *del_work = to_delayed_work(work); 1295 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1296 stats_work); 1297 1298 ocelot_update_stats(ocelot); 1299 1300 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1301 OCELOT_STATS_CHECK_DELAY); 1302 } 1303 1304 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1305 { 1306 int i; 1307 1308 /* check and update now */ 1309 ocelot_update_stats(ocelot); 1310 1311 /* Copy all counters */ 1312 for (i = 0; i < ocelot->num_stats; i++) 1313 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1314 } 1315 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1316 1317 static void ocelot_port_get_ethtool_stats(struct net_device *dev, 1318 struct ethtool_stats *stats, 1319 u64 *data) 1320 { 1321 struct ocelot_port_private *priv = netdev_priv(dev); 1322 struct ocelot *ocelot = priv->port.ocelot; 1323 int port = priv->chip_port; 1324 1325 ocelot_get_ethtool_stats(ocelot, port, data); 1326 } 1327 1328 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1329 { 1330 if (sset != ETH_SS_STATS) 1331 return -EOPNOTSUPP; 1332 1333 return ocelot->num_stats; 1334 } 1335 EXPORT_SYMBOL(ocelot_get_sset_count); 1336 1337 static int ocelot_port_get_sset_count(struct net_device *dev, int sset) 1338 { 1339 struct ocelot_port_private *priv = netdev_priv(dev); 1340 struct ocelot *ocelot = priv->port.ocelot; 1341 int port = priv->chip_port; 1342 1343 return ocelot_get_sset_count(ocelot, port, sset); 1344 } 1345 1346 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1347 struct ethtool_ts_info *info) 1348 { 1349 info->phc_index = ocelot->ptp_clock ? 1350 ptp_clock_index(ocelot->ptp_clock) : -1; 1351 if (info->phc_index == -1) { 1352 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1353 SOF_TIMESTAMPING_RX_SOFTWARE | 1354 SOF_TIMESTAMPING_SOFTWARE; 1355 return 0; 1356 } 1357 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1358 SOF_TIMESTAMPING_RX_SOFTWARE | 1359 SOF_TIMESTAMPING_SOFTWARE | 1360 SOF_TIMESTAMPING_TX_HARDWARE | 1361 SOF_TIMESTAMPING_RX_HARDWARE | 1362 SOF_TIMESTAMPING_RAW_HARDWARE; 1363 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1364 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1365 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1366 1367 return 0; 1368 } 1369 EXPORT_SYMBOL(ocelot_get_ts_info); 1370 1371 static int ocelot_port_get_ts_info(struct net_device *dev, 1372 struct ethtool_ts_info *info) 1373 { 1374 struct ocelot_port_private *priv = netdev_priv(dev); 1375 struct ocelot *ocelot = priv->port.ocelot; 1376 int port = priv->chip_port; 1377 1378 if (!ocelot->ptp) 1379 return ethtool_op_get_ts_info(dev, info); 1380 1381 return ocelot_get_ts_info(ocelot, port, info); 1382 } 1383 1384 static const struct ethtool_ops ocelot_ethtool_ops = { 1385 .get_strings = ocelot_port_get_strings, 1386 .get_ethtool_stats = ocelot_port_get_ethtool_stats, 1387 .get_sset_count = ocelot_port_get_sset_count, 1388 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1389 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1390 .get_ts_info = ocelot_port_get_ts_info, 1391 }; 1392 1393 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1394 { 1395 u32 port_cfg; 1396 int p, i; 1397 1398 if (!(BIT(port) & ocelot->bridge_mask)) 1399 return; 1400 1401 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1402 1403 switch (state) { 1404 case BR_STATE_FORWARDING: 1405 ocelot->bridge_fwd_mask |= BIT(port); 1406 /* Fallthrough */ 1407 case BR_STATE_LEARNING: 1408 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1409 break; 1410 1411 default: 1412 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1413 ocelot->bridge_fwd_mask &= ~BIT(port); 1414 break; 1415 } 1416 1417 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 1418 1419 /* Apply FWD mask. The loop is needed to add/remove the current port as 1420 * a source for the other ports. 1421 */ 1422 for (p = 0; p < ocelot->num_phys_ports; p++) { 1423 if (ocelot->bridge_fwd_mask & BIT(p)) { 1424 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 1425 1426 for (i = 0; i < ocelot->num_phys_ports; i++) { 1427 unsigned long bond_mask = ocelot->lags[i]; 1428 1429 if (!bond_mask) 1430 continue; 1431 1432 if (bond_mask & BIT(p)) { 1433 mask &= ~bond_mask; 1434 break; 1435 } 1436 } 1437 1438 ocelot_write_rix(ocelot, mask, 1439 ANA_PGID_PGID, PGID_SRC + p); 1440 } else { 1441 ocelot_write_rix(ocelot, 0, 1442 ANA_PGID_PGID, PGID_SRC + p); 1443 } 1444 } 1445 } 1446 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1447 1448 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port, 1449 struct switchdev_trans *trans, 1450 u8 state) 1451 { 1452 if (switchdev_trans_ph_prepare(trans)) 1453 return; 1454 1455 ocelot_bridge_stp_state_set(ocelot, port, state); 1456 } 1457 1458 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1459 { 1460 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1461 1462 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1463 * which is clearly not what our intention is. So avoid that. 1464 */ 1465 if (!age_period) 1466 age_period = 1; 1467 1468 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1469 } 1470 EXPORT_SYMBOL(ocelot_set_ageing_time); 1471 1472 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port, 1473 unsigned long ageing_clock_t) 1474 { 1475 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1476 u32 ageing_time = jiffies_to_msecs(ageing_jiffies); 1477 1478 ocelot_set_ageing_time(ocelot, ageing_time); 1479 } 1480 1481 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc) 1482 { 1483 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1484 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1485 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1486 u32 val = 0; 1487 1488 if (mc) 1489 val = cpu_fwd_mcast; 1490 1491 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast, 1492 ANA_PORT_CPU_FWD_CFG, port); 1493 } 1494 1495 static int ocelot_port_attr_set(struct net_device *dev, 1496 const struct switchdev_attr *attr, 1497 struct switchdev_trans *trans) 1498 { 1499 struct ocelot_port_private *priv = netdev_priv(dev); 1500 struct ocelot *ocelot = priv->port.ocelot; 1501 int port = priv->chip_port; 1502 int err = 0; 1503 1504 switch (attr->id) { 1505 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1506 ocelot_port_attr_stp_state_set(ocelot, port, trans, 1507 attr->u.stp_state); 1508 break; 1509 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1510 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time); 1511 break; 1512 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1513 ocelot_port_vlan_filtering(ocelot, port, 1514 attr->u.vlan_filtering); 1515 break; 1516 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1517 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled); 1518 break; 1519 default: 1520 err = -EOPNOTSUPP; 1521 break; 1522 } 1523 1524 return err; 1525 } 1526 1527 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1528 const struct switchdev_obj_port_vlan *vlan, 1529 struct switchdev_trans *trans) 1530 { 1531 int ret; 1532 u16 vid; 1533 1534 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1535 ret = ocelot_vlan_vid_add(dev, vid, 1536 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1537 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1538 if (ret) 1539 return ret; 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1546 const struct switchdev_obj_port_vlan *vlan) 1547 { 1548 int ret; 1549 u16 vid; 1550 1551 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1552 ret = ocelot_vlan_vid_del(dev, vid); 1553 1554 if (ret) 1555 return ret; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1562 const unsigned char *addr, 1563 u16 vid) 1564 { 1565 struct ocelot_multicast *mc; 1566 1567 list_for_each_entry(mc, &ocelot->multicast, list) { 1568 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1569 return mc; 1570 } 1571 1572 return NULL; 1573 } 1574 1575 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1576 const struct switchdev_obj_port_mdb *mdb, 1577 struct switchdev_trans *trans) 1578 { 1579 struct ocelot_port_private *priv = netdev_priv(dev); 1580 struct ocelot_port *ocelot_port = &priv->port; 1581 struct ocelot *ocelot = ocelot_port->ocelot; 1582 unsigned char addr[ETH_ALEN]; 1583 struct ocelot_multicast *mc; 1584 int port = priv->chip_port; 1585 u16 vid = mdb->vid; 1586 bool new = false; 1587 1588 if (!vid) 1589 vid = ocelot_port->pvid; 1590 1591 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1592 if (!mc) { 1593 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1594 if (!mc) 1595 return -ENOMEM; 1596 1597 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1598 mc->vid = vid; 1599 1600 list_add_tail(&mc->list, &ocelot->multicast); 1601 new = true; 1602 } 1603 1604 memcpy(addr, mc->addr, ETH_ALEN); 1605 addr[0] = 0; 1606 1607 if (!new) { 1608 addr[2] = mc->ports << 0; 1609 addr[1] = mc->ports << 8; 1610 ocelot_mact_forget(ocelot, addr, vid); 1611 } 1612 1613 mc->ports |= BIT(port); 1614 addr[2] = mc->ports << 0; 1615 addr[1] = mc->ports << 8; 1616 1617 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1618 } 1619 1620 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1621 const struct switchdev_obj_port_mdb *mdb) 1622 { 1623 struct ocelot_port_private *priv = netdev_priv(dev); 1624 struct ocelot_port *ocelot_port = &priv->port; 1625 struct ocelot *ocelot = ocelot_port->ocelot; 1626 unsigned char addr[ETH_ALEN]; 1627 struct ocelot_multicast *mc; 1628 int port = priv->chip_port; 1629 u16 vid = mdb->vid; 1630 1631 if (!vid) 1632 vid = ocelot_port->pvid; 1633 1634 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1635 if (!mc) 1636 return -ENOENT; 1637 1638 memcpy(addr, mc->addr, ETH_ALEN); 1639 addr[2] = mc->ports << 0; 1640 addr[1] = mc->ports << 8; 1641 addr[0] = 0; 1642 ocelot_mact_forget(ocelot, addr, vid); 1643 1644 mc->ports &= ~BIT(port); 1645 if (!mc->ports) { 1646 list_del(&mc->list); 1647 devm_kfree(ocelot->dev, mc); 1648 return 0; 1649 } 1650 1651 addr[2] = mc->ports << 0; 1652 addr[1] = mc->ports << 8; 1653 1654 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1655 } 1656 1657 static int ocelot_port_obj_add(struct net_device *dev, 1658 const struct switchdev_obj *obj, 1659 struct switchdev_trans *trans, 1660 struct netlink_ext_ack *extack) 1661 { 1662 int ret = 0; 1663 1664 switch (obj->id) { 1665 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1666 ret = ocelot_port_obj_add_vlan(dev, 1667 SWITCHDEV_OBJ_PORT_VLAN(obj), 1668 trans); 1669 break; 1670 case SWITCHDEV_OBJ_ID_PORT_MDB: 1671 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1672 trans); 1673 break; 1674 default: 1675 return -EOPNOTSUPP; 1676 } 1677 1678 return ret; 1679 } 1680 1681 static int ocelot_port_obj_del(struct net_device *dev, 1682 const struct switchdev_obj *obj) 1683 { 1684 int ret = 0; 1685 1686 switch (obj->id) { 1687 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1688 ret = ocelot_port_vlan_del_vlan(dev, 1689 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1690 break; 1691 case SWITCHDEV_OBJ_ID_PORT_MDB: 1692 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1693 break; 1694 default: 1695 return -EOPNOTSUPP; 1696 } 1697 1698 return ret; 1699 } 1700 1701 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1702 struct net_device *bridge) 1703 { 1704 if (!ocelot->bridge_mask) { 1705 ocelot->hw_bridge_dev = bridge; 1706 } else { 1707 if (ocelot->hw_bridge_dev != bridge) 1708 /* This is adding the port to a second bridge, this is 1709 * unsupported */ 1710 return -ENODEV; 1711 } 1712 1713 ocelot->bridge_mask |= BIT(port); 1714 1715 return 0; 1716 } 1717 EXPORT_SYMBOL(ocelot_port_bridge_join); 1718 1719 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1720 struct net_device *bridge) 1721 { 1722 ocelot->bridge_mask &= ~BIT(port); 1723 1724 if (!ocelot->bridge_mask) 1725 ocelot->hw_bridge_dev = NULL; 1726 1727 ocelot_port_vlan_filtering(ocelot, port, 0); 1728 ocelot_port_set_pvid(ocelot, port, 0); 1729 return ocelot_port_set_native_vlan(ocelot, port, 0); 1730 } 1731 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1732 1733 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1734 { 1735 int i, port, lag; 1736 1737 /* Reset destination and aggregation PGIDS */ 1738 for (port = 0; port < ocelot->num_phys_ports; port++) 1739 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1740 1741 for (i = PGID_AGGR; i < PGID_SRC; i++) 1742 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1743 ANA_PGID_PGID, i); 1744 1745 /* Now, set PGIDs for each LAG */ 1746 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1747 unsigned long bond_mask; 1748 int aggr_count = 0; 1749 u8 aggr_idx[16]; 1750 1751 bond_mask = ocelot->lags[lag]; 1752 if (!bond_mask) 1753 continue; 1754 1755 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1756 // Destination mask 1757 ocelot_write_rix(ocelot, bond_mask, 1758 ANA_PGID_PGID, port); 1759 aggr_idx[aggr_count] = port; 1760 aggr_count++; 1761 } 1762 1763 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1764 u32 ac; 1765 1766 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1767 ac &= ~bond_mask; 1768 ac |= BIT(aggr_idx[i % aggr_count]); 1769 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1770 } 1771 } 1772 } 1773 1774 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1775 { 1776 unsigned long bond_mask = ocelot->lags[lag]; 1777 unsigned int p; 1778 1779 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1780 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1781 1782 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1783 1784 /* Use lag port as logical port for port i */ 1785 ocelot_write_gix(ocelot, port_cfg | 1786 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1787 ANA_PORT_PORT_CFG, p); 1788 } 1789 } 1790 1791 static int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1792 struct net_device *bond) 1793 { 1794 struct net_device *ndev; 1795 u32 bond_mask = 0; 1796 int lag, lp; 1797 1798 rcu_read_lock(); 1799 for_each_netdev_in_bond_rcu(bond, ndev) { 1800 struct ocelot_port_private *priv = netdev_priv(ndev); 1801 1802 bond_mask |= BIT(priv->chip_port); 1803 } 1804 rcu_read_unlock(); 1805 1806 lp = __ffs(bond_mask); 1807 1808 /* If the new port is the lowest one, use it as the logical port from 1809 * now on 1810 */ 1811 if (port == lp) { 1812 lag = port; 1813 ocelot->lags[port] = bond_mask; 1814 bond_mask &= ~BIT(port); 1815 if (bond_mask) { 1816 lp = __ffs(bond_mask); 1817 ocelot->lags[lp] = 0; 1818 } 1819 } else { 1820 lag = lp; 1821 ocelot->lags[lp] |= BIT(port); 1822 } 1823 1824 ocelot_setup_lag(ocelot, lag); 1825 ocelot_set_aggr_pgids(ocelot); 1826 1827 return 0; 1828 } 1829 1830 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1831 struct net_device *bond) 1832 { 1833 u32 port_cfg; 1834 int i; 1835 1836 /* Remove port from any lag */ 1837 for (i = 0; i < ocelot->num_phys_ports; i++) 1838 ocelot->lags[i] &= ~BIT(port); 1839 1840 /* if it was the logical port of the lag, move the lag config to the 1841 * next port 1842 */ 1843 if (ocelot->lags[port]) { 1844 int n = __ffs(ocelot->lags[port]); 1845 1846 ocelot->lags[n] = ocelot->lags[port]; 1847 ocelot->lags[port] = 0; 1848 1849 ocelot_setup_lag(ocelot, n); 1850 } 1851 1852 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1853 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1854 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1855 ANA_PORT_PORT_CFG, port); 1856 1857 ocelot_set_aggr_pgids(ocelot); 1858 } 1859 1860 /* Checks if the net_device instance given to us originate from our driver. */ 1861 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1862 { 1863 return dev->netdev_ops == &ocelot_port_netdev_ops; 1864 } 1865 1866 static int ocelot_netdevice_port_event(struct net_device *dev, 1867 unsigned long event, 1868 struct netdev_notifier_changeupper_info *info) 1869 { 1870 struct ocelot_port_private *priv = netdev_priv(dev); 1871 struct ocelot_port *ocelot_port = &priv->port; 1872 struct ocelot *ocelot = ocelot_port->ocelot; 1873 int port = priv->chip_port; 1874 int err = 0; 1875 1876 switch (event) { 1877 case NETDEV_CHANGEUPPER: 1878 if (netif_is_bridge_master(info->upper_dev)) { 1879 if (info->linking) { 1880 err = ocelot_port_bridge_join(ocelot, port, 1881 info->upper_dev); 1882 } else { 1883 err = ocelot_port_bridge_leave(ocelot, port, 1884 info->upper_dev); 1885 } 1886 } 1887 if (netif_is_lag_master(info->upper_dev)) { 1888 if (info->linking) 1889 err = ocelot_port_lag_join(ocelot, port, 1890 info->upper_dev); 1891 else 1892 ocelot_port_lag_leave(ocelot, port, 1893 info->upper_dev); 1894 } 1895 break; 1896 default: 1897 break; 1898 } 1899 1900 return err; 1901 } 1902 1903 static int ocelot_netdevice_event(struct notifier_block *unused, 1904 unsigned long event, void *ptr) 1905 { 1906 struct netdev_notifier_changeupper_info *info = ptr; 1907 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1908 int ret = 0; 1909 1910 if (!ocelot_netdevice_dev_check(dev)) 1911 return 0; 1912 1913 if (event == NETDEV_PRECHANGEUPPER && 1914 netif_is_lag_master(info->upper_dev)) { 1915 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1916 struct netlink_ext_ack *extack; 1917 1918 if (lag_upper_info && 1919 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1920 extack = netdev_notifier_info_to_extack(&info->info); 1921 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1922 1923 ret = -EINVAL; 1924 goto notify; 1925 } 1926 } 1927 1928 if (netif_is_lag_master(dev)) { 1929 struct net_device *slave; 1930 struct list_head *iter; 1931 1932 netdev_for_each_lower_dev(dev, slave, iter) { 1933 ret = ocelot_netdevice_port_event(slave, event, info); 1934 if (ret) 1935 goto notify; 1936 } 1937 } else { 1938 ret = ocelot_netdevice_port_event(dev, event, info); 1939 } 1940 1941 notify: 1942 return notifier_from_errno(ret); 1943 } 1944 1945 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1946 .notifier_call = ocelot_netdevice_event, 1947 }; 1948 EXPORT_SYMBOL(ocelot_netdevice_nb); 1949 1950 static int ocelot_switchdev_event(struct notifier_block *unused, 1951 unsigned long event, void *ptr) 1952 { 1953 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1954 int err; 1955 1956 switch (event) { 1957 case SWITCHDEV_PORT_ATTR_SET: 1958 err = switchdev_handle_port_attr_set(dev, ptr, 1959 ocelot_netdevice_dev_check, 1960 ocelot_port_attr_set); 1961 return notifier_from_errno(err); 1962 } 1963 1964 return NOTIFY_DONE; 1965 } 1966 1967 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1968 .notifier_call = ocelot_switchdev_event, 1969 }; 1970 EXPORT_SYMBOL(ocelot_switchdev_nb); 1971 1972 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1973 unsigned long event, void *ptr) 1974 { 1975 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1976 int err; 1977 1978 switch (event) { 1979 /* Blocking events. */ 1980 case SWITCHDEV_PORT_OBJ_ADD: 1981 err = switchdev_handle_port_obj_add(dev, ptr, 1982 ocelot_netdevice_dev_check, 1983 ocelot_port_obj_add); 1984 return notifier_from_errno(err); 1985 case SWITCHDEV_PORT_OBJ_DEL: 1986 err = switchdev_handle_port_obj_del(dev, ptr, 1987 ocelot_netdevice_dev_check, 1988 ocelot_port_obj_del); 1989 return notifier_from_errno(err); 1990 case SWITCHDEV_PORT_ATTR_SET: 1991 err = switchdev_handle_port_attr_set(dev, ptr, 1992 ocelot_netdevice_dev_check, 1993 ocelot_port_attr_set); 1994 return notifier_from_errno(err); 1995 } 1996 1997 return NOTIFY_DONE; 1998 } 1999 2000 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 2001 .notifier_call = ocelot_switchdev_blocking_event, 2002 }; 2003 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 2004 2005 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2006 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2007 * In the special case that it's the NPI port that we're configuring, the 2008 * length of the tag and optional prefix needs to be accounted for privately, 2009 * in order to be able to sustain communication at the requested @sdu. 2010 */ 2011 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2012 { 2013 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2014 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2015 int atop_wm; 2016 2017 if (port == ocelot->npi) { 2018 maxlen += OCELOT_TAG_LEN; 2019 2020 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2021 maxlen += OCELOT_SHORT_PREFIX_LEN; 2022 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 2023 maxlen += OCELOT_LONG_PREFIX_LEN; 2024 } 2025 2026 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2027 2028 /* Set Pause WM hysteresis 2029 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ 2030 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ 2031 */ 2032 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 2033 SYS_PAUSE_CFG_PAUSE_STOP(101) | 2034 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); 2035 2036 /* Tail dropping watermark */ 2037 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) / 2038 OCELOT_BUFFER_CELL_SZ; 2039 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * maxlen), 2040 SYS_ATOP, port); 2041 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 2042 } 2043 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2044 2045 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2046 { 2047 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2048 2049 if (port == ocelot->npi) { 2050 max_mtu -= OCELOT_TAG_LEN; 2051 2052 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2053 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2054 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 2055 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2056 } 2057 2058 return max_mtu; 2059 } 2060 EXPORT_SYMBOL(ocelot_get_max_mtu); 2061 2062 void ocelot_init_port(struct ocelot *ocelot, int port) 2063 { 2064 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2065 2066 skb_queue_head_init(&ocelot_port->tx_skbs); 2067 2068 /* Basic L2 initialization */ 2069 2070 /* Set MAC IFG Gaps 2071 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2072 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2073 */ 2074 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2075 DEV_MAC_IFG_CFG); 2076 2077 /* Load seed (0) and set MAC HDX late collision */ 2078 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2079 DEV_MAC_HDX_CFG_SEED_LOAD, 2080 DEV_MAC_HDX_CFG); 2081 mdelay(1); 2082 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2083 DEV_MAC_HDX_CFG); 2084 2085 /* Set Max Length and maximum tags allowed */ 2086 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2087 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2088 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2089 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2090 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2091 DEV_MAC_TAGS_CFG); 2092 2093 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2094 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2095 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2096 2097 /* Drop frames with multicast source address */ 2098 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2099 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2100 ANA_PORT_DROP_CFG, port); 2101 2102 /* Set default VLAN and tag type to 8021Q. */ 2103 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2104 REW_PORT_VLAN_CFG_PORT_TPID_M, 2105 REW_PORT_VLAN_CFG, port); 2106 2107 /* Enable vcap lookups */ 2108 ocelot_vcap_enable(ocelot, port); 2109 } 2110 EXPORT_SYMBOL(ocelot_init_port); 2111 2112 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 2113 void __iomem *regs, 2114 struct phy_device *phy) 2115 { 2116 struct ocelot_port_private *priv; 2117 struct ocelot_port *ocelot_port; 2118 struct net_device *dev; 2119 int err; 2120 2121 dev = alloc_etherdev(sizeof(struct ocelot_port_private)); 2122 if (!dev) 2123 return -ENOMEM; 2124 SET_NETDEV_DEV(dev, ocelot->dev); 2125 priv = netdev_priv(dev); 2126 priv->dev = dev; 2127 priv->phy = phy; 2128 priv->chip_port = port; 2129 ocelot_port = &priv->port; 2130 ocelot_port->ocelot = ocelot; 2131 ocelot_port->regs = regs; 2132 ocelot->ports[port] = ocelot_port; 2133 2134 dev->netdev_ops = &ocelot_port_netdev_ops; 2135 dev->ethtool_ops = &ocelot_ethtool_ops; 2136 2137 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2138 NETIF_F_HW_TC; 2139 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2140 2141 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2142 dev->dev_addr[ETH_ALEN - 1] += port; 2143 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2144 ENTRYTYPE_LOCKED); 2145 2146 ocelot_init_port(ocelot, port); 2147 2148 err = register_netdev(dev); 2149 if (err) { 2150 dev_err(ocelot->dev, "register_netdev failed\n"); 2151 free_netdev(dev); 2152 } 2153 2154 return err; 2155 } 2156 EXPORT_SYMBOL(ocelot_probe_port); 2157 2158 /* Configure and enable the CPU port module, which is a set of queues. 2159 * If @npi contains a valid port index, the CPU port module is connected 2160 * to the Node Processor Interface (NPI). This is the mode through which 2161 * frames can be injected from and extracted to an external CPU, 2162 * over Ethernet. 2163 */ 2164 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 2165 enum ocelot_tag_prefix injection, 2166 enum ocelot_tag_prefix extraction) 2167 { 2168 int cpu = ocelot->num_phys_ports; 2169 2170 ocelot->npi = npi; 2171 ocelot->inj_prefix = injection; 2172 ocelot->xtr_prefix = extraction; 2173 2174 /* The unicast destination PGID for the CPU port module is unused */ 2175 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2176 /* Instead set up a multicast destination PGID for traffic copied to 2177 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2178 * addresses will be copied to the CPU via this PGID. 2179 */ 2180 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2181 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2182 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2183 ANA_PORT_PORT_CFG, cpu); 2184 2185 if (npi >= 0 && npi < ocelot->num_phys_ports) { 2186 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 2187 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi), 2188 QSYS_EXT_CPU_CFG); 2189 2190 /* Enable NPI port */ 2191 ocelot_write_rix(ocelot, 2192 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2193 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2194 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2195 QSYS_SWITCH_PORT_MODE, npi); 2196 /* NPI port Injection/Extraction configuration */ 2197 ocelot_write_rix(ocelot, 2198 SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2199 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2200 SYS_PORT_MODE, npi); 2201 } 2202 2203 /* Enable CPU port module */ 2204 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2205 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2206 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2207 QSYS_SWITCH_PORT_MODE, cpu); 2208 /* CPU port Injection/Extraction configuration */ 2209 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2210 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2211 SYS_PORT_MODE, cpu); 2212 2213 /* Configure the CPU port to be VLAN aware */ 2214 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2215 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2216 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2217 ANA_PORT_VLAN_CFG, cpu); 2218 } 2219 EXPORT_SYMBOL(ocelot_configure_cpu); 2220 2221 int ocelot_init(struct ocelot *ocelot) 2222 { 2223 char queue_name[32]; 2224 int i, ret; 2225 u32 port; 2226 2227 if (ocelot->ops->reset) { 2228 ret = ocelot->ops->reset(ocelot); 2229 if (ret) { 2230 dev_err(ocelot->dev, "Switch reset failed\n"); 2231 return ret; 2232 } 2233 } 2234 2235 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2236 sizeof(u32), GFP_KERNEL); 2237 if (!ocelot->lags) 2238 return -ENOMEM; 2239 2240 ocelot->stats = devm_kcalloc(ocelot->dev, 2241 ocelot->num_phys_ports * ocelot->num_stats, 2242 sizeof(u64), GFP_KERNEL); 2243 if (!ocelot->stats) 2244 return -ENOMEM; 2245 2246 mutex_init(&ocelot->stats_lock); 2247 mutex_init(&ocelot->ptp_lock); 2248 spin_lock_init(&ocelot->ptp_clock_lock); 2249 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2250 dev_name(ocelot->dev)); 2251 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2252 if (!ocelot->stats_queue) 2253 return -ENOMEM; 2254 2255 INIT_LIST_HEAD(&ocelot->multicast); 2256 ocelot_mact_init(ocelot); 2257 ocelot_vlan_init(ocelot); 2258 ocelot_ace_init(ocelot); 2259 2260 for (port = 0; port < ocelot->num_phys_ports; port++) { 2261 /* Clear all counters (5 groups) */ 2262 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2263 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2264 SYS_STAT_CFG); 2265 } 2266 2267 /* Only use S-Tag */ 2268 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2269 2270 /* Aggregation mode */ 2271 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2272 ANA_AGGR_CFG_AC_DMAC_ENA | 2273 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2274 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2275 2276 /* Set MAC age time to default value. The entry is aged after 2277 * 2*AGE_PERIOD 2278 */ 2279 ocelot_write(ocelot, 2280 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2281 ANA_AUTOAGE); 2282 2283 /* Disable learning for frames discarded by VLAN ingress filtering */ 2284 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2285 2286 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2287 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2288 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2289 2290 /* Setup flooding PGIDs */ 2291 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2292 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2293 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2294 ANA_FLOODING, 0); 2295 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2296 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2297 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2298 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2299 ANA_FLOODING_IPMC); 2300 2301 for (port = 0; port < ocelot->num_phys_ports; port++) { 2302 /* Transmit the frame to the local port. */ 2303 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2304 /* Do not forward BPDU frames to the front ports. */ 2305 ocelot_write_gix(ocelot, 2306 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2307 ANA_PORT_CPU_FWD_BPDU_CFG, 2308 port); 2309 /* Ensure bridging is disabled */ 2310 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2311 } 2312 2313 /* Allow broadcast MAC frames. */ 2314 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2315 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2316 2317 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2318 } 2319 ocelot_write_rix(ocelot, 2320 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2321 ANA_PGID_PGID, PGID_MC); 2322 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2323 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2324 2325 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2326 * registers endianness. 2327 */ 2328 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2329 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2330 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2331 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2332 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2333 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2334 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2335 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2336 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2337 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2338 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2339 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2340 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2341 for (i = 0; i < 16; i++) 2342 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2343 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2344 ANA_CPUQ_8021_CFG, i); 2345 2346 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2347 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2348 OCELOT_STATS_CHECK_DELAY); 2349 2350 return 0; 2351 } 2352 EXPORT_SYMBOL(ocelot_init); 2353 2354 void ocelot_deinit(struct ocelot *ocelot) 2355 { 2356 struct ocelot_port *port; 2357 int i; 2358 2359 cancel_delayed_work(&ocelot->stats_work); 2360 destroy_workqueue(ocelot->stats_queue); 2361 mutex_destroy(&ocelot->stats_lock); 2362 2363 for (i = 0; i < ocelot->num_phys_ports; i++) { 2364 port = ocelot->ports[i]; 2365 skb_queue_purge(&port->tx_skbs); 2366 } 2367 } 2368 EXPORT_SYMBOL(ocelot_deinit); 2369 2370 MODULE_LICENSE("Dual MIT/GPL"); 2371