1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <linux/iopoll.h> 19 #include <net/arp.h> 20 #include <net/netevent.h> 21 #include <net/rtnetlink.h> 22 #include <net/switchdev.h> 23 24 #include "ocelot.h" 25 26 #define TABLE_UPDATE_SLEEP_US 10 27 #define TABLE_UPDATE_TIMEOUT_US 100000 28 29 /* MAC table entry types. 30 * ENTRYTYPE_NORMAL is subject to aging. 31 * ENTRYTYPE_LOCKED is not subject to aging. 32 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 33 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 34 */ 35 enum macaccess_entry_type { 36 ENTRYTYPE_NORMAL = 0, 37 ENTRYTYPE_LOCKED, 38 ENTRYTYPE_MACv4, 39 ENTRYTYPE_MACv6, 40 }; 41 42 struct ocelot_mact_entry { 43 u8 mac[ETH_ALEN]; 44 u16 vid; 45 enum macaccess_entry_type type; 46 }; 47 48 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 49 { 50 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 51 } 52 53 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 54 { 55 u32 val; 56 57 return readx_poll_timeout(ocelot_mact_read_macaccess, 58 ocelot, val, 59 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 60 MACACCESS_CMD_IDLE, 61 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 62 } 63 64 static void ocelot_mact_select(struct ocelot *ocelot, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid) 67 { 68 u32 macl = 0, mach = 0; 69 70 /* Set the MAC address to handle and the vlan associated in a format 71 * understood by the hardware. 72 */ 73 mach |= vid << 16; 74 mach |= mac[0] << 8; 75 mach |= mac[1] << 0; 76 macl |= mac[2] << 24; 77 macl |= mac[3] << 16; 78 macl |= mac[4] << 8; 79 macl |= mac[5] << 0; 80 81 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 82 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 83 84 } 85 86 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 87 const unsigned char mac[ETH_ALEN], 88 unsigned int vid, 89 enum macaccess_entry_type type) 90 { 91 ocelot_mact_select(ocelot, mac, vid); 92 93 /* Issue a write command */ 94 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 95 ANA_TABLES_MACACCESS_DEST_IDX(port) | 96 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 97 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 98 ANA_TABLES_MACACCESS); 99 100 return ocelot_mact_wait_for_completion(ocelot); 101 } 102 103 static int ocelot_mact_forget(struct ocelot *ocelot, 104 const unsigned char mac[ETH_ALEN], 105 unsigned int vid) 106 { 107 ocelot_mact_select(ocelot, mac, vid); 108 109 /* Issue a forget command */ 110 ocelot_write(ocelot, 111 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 112 ANA_TABLES_MACACCESS); 113 114 return ocelot_mact_wait_for_completion(ocelot); 115 } 116 117 static void ocelot_mact_init(struct ocelot *ocelot) 118 { 119 /* Configure the learning mode entries attributes: 120 * - Do not copy the frame to the CPU extraction queues. 121 * - Use the vlan and mac_cpoy for dmac lookup. 122 */ 123 ocelot_rmw(ocelot, 0, 124 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 125 | ANA_AGENCTRL_LEARN_FWD_KILL 126 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 127 ANA_AGENCTRL); 128 129 /* Clear the MAC table */ 130 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 131 } 132 133 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 134 { 135 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 136 } 137 138 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 139 { 140 u32 val; 141 142 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 143 ocelot, 144 val, 145 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 146 ANA_TABLES_VLANACCESS_CMD_IDLE, 147 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 148 } 149 150 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 151 { 152 /* Select the VID to configure */ 153 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 154 ANA_TABLES_VLANTIDX); 155 /* Set the vlan port members mask and issue a write command */ 156 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 157 ANA_TABLES_VLANACCESS_CMD_WRITE, 158 ANA_TABLES_VLANACCESS); 159 160 return ocelot_vlant_wait_for_completion(ocelot); 161 } 162 163 static void ocelot_vlan_mode(struct ocelot_port *port, 164 netdev_features_t features) 165 { 166 struct ocelot *ocelot = port->ocelot; 167 u8 p = port->chip_port; 168 u32 val; 169 170 /* Filtering */ 171 val = ocelot_read(ocelot, ANA_VLANMASK); 172 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 173 val |= BIT(p); 174 else 175 val &= ~BIT(p); 176 ocelot_write(ocelot, val, ANA_VLANMASK); 177 } 178 179 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 180 struct ocelot_port *port) 181 { 182 u32 val; 183 184 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 185 /* Default vlan to clasify for untagged frames (may be zero) */ 186 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 187 if (port->vlan_aware) 188 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 189 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 190 191 ocelot_rmw_gix(ocelot, val, 192 ANA_PORT_VLAN_CFG_VLAN_VID_M | 193 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 194 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 195 ANA_PORT_VLAN_CFG, port->chip_port); 196 197 /* Drop frames with multicast source address */ 198 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 199 if (port->vlan_aware && !port->vid) 200 /* If port is vlan-aware and tagged, drop untagged and priority 201 * tagged frames. 202 */ 203 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 204 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 205 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 206 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 207 208 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 209 val = REW_TAG_CFG_TAG_TPID_CFG(0); 210 211 if (port->vlan_aware) { 212 if (port->vid) 213 /* Tag all frames except when VID == DEFAULT_VLAN */ 214 val |= REW_TAG_CFG_TAG_CFG(1); 215 else 216 /* Tag all frames */ 217 val |= REW_TAG_CFG_TAG_CFG(3); 218 } 219 ocelot_rmw_gix(ocelot, val, 220 REW_TAG_CFG_TAG_TPID_CFG_M | 221 REW_TAG_CFG_TAG_CFG_M, 222 REW_TAG_CFG, port->chip_port); 223 224 /* Set default VLAN and tag type to 8021Q. */ 225 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 226 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 227 ocelot_rmw_gix(ocelot, val, 228 REW_PORT_VLAN_CFG_PORT_TPID_M | 229 REW_PORT_VLAN_CFG_PORT_VID_M, 230 REW_PORT_VLAN_CFG, port->chip_port); 231 } 232 233 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 234 bool untagged) 235 { 236 struct ocelot_port *port = netdev_priv(dev); 237 struct ocelot *ocelot = port->ocelot; 238 int ret; 239 240 /* Add the port MAC address to with the right VLAN information */ 241 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 242 ENTRYTYPE_LOCKED); 243 244 /* Make the port a member of the VLAN */ 245 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 246 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 247 if (ret) 248 return ret; 249 250 /* Default ingress vlan classification */ 251 if (pvid) 252 port->pvid = vid; 253 254 /* Untagged egress vlan clasification */ 255 if (untagged) 256 port->vid = vid; 257 258 ocelot_vlan_port_apply(ocelot, port); 259 260 return 0; 261 } 262 263 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 264 { 265 struct ocelot_port *port = netdev_priv(dev); 266 struct ocelot *ocelot = port->ocelot; 267 int ret; 268 269 /* 8021q removes VID 0 on module unload for all interfaces 270 * with VLAN filtering feature. We need to keep it to receive 271 * untagged traffic. 272 */ 273 if (vid == 0) 274 return 0; 275 276 /* Del the port MAC address to with the right VLAN information */ 277 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 278 279 /* Stop the port from being a member of the vlan */ 280 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 281 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 282 if (ret) 283 return ret; 284 285 /* Ingress */ 286 if (port->pvid == vid) 287 port->pvid = 0; 288 289 /* Egress */ 290 if (port->vid == vid) 291 port->vid = 0; 292 293 ocelot_vlan_port_apply(ocelot, port); 294 295 return 0; 296 } 297 298 static void ocelot_vlan_init(struct ocelot *ocelot) 299 { 300 u16 port, vid; 301 302 /* Clear VLAN table, by default all ports are members of all VLANs */ 303 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 304 ANA_TABLES_VLANACCESS); 305 ocelot_vlant_wait_for_completion(ocelot); 306 307 /* Configure the port VLAN memberships */ 308 for (vid = 1; vid < VLAN_N_VID; vid++) { 309 ocelot->vlan_mask[vid] = 0; 310 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 311 } 312 313 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 314 * traffic. It is added automatically if 8021q module is loaded, but 315 * we can't rely on it since module may be not loaded. 316 */ 317 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 318 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 319 320 /* Configure the CPU port to be VLAN aware */ 321 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 322 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 323 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 324 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 325 326 /* Set vlan ingress filter mask to all ports but the CPU port by 327 * default. 328 */ 329 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 330 331 for (port = 0; port < ocelot->num_phys_ports; port++) { 332 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 333 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 334 } 335 } 336 337 /* Watermark encode 338 * Bit 8: Unit; 0:1, 1:16 339 * Bit 7-0: Value to be multiplied with unit 340 */ 341 static u16 ocelot_wm_enc(u16 value) 342 { 343 if (value >= BIT(8)) 344 return BIT(8) | (value / 16); 345 346 return value; 347 } 348 349 static void ocelot_port_adjust_link(struct net_device *dev) 350 { 351 struct ocelot_port *port = netdev_priv(dev); 352 struct ocelot *ocelot = port->ocelot; 353 u8 p = port->chip_port; 354 int speed, atop_wm, mode = 0; 355 356 switch (dev->phydev->speed) { 357 case SPEED_10: 358 speed = OCELOT_SPEED_10; 359 break; 360 case SPEED_100: 361 speed = OCELOT_SPEED_100; 362 break; 363 case SPEED_1000: 364 speed = OCELOT_SPEED_1000; 365 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 366 break; 367 case SPEED_2500: 368 speed = OCELOT_SPEED_2500; 369 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 370 break; 371 default: 372 netdev_err(dev, "Unsupported PHY speed: %d\n", 373 dev->phydev->speed); 374 return; 375 } 376 377 phy_print_status(dev->phydev); 378 379 if (!dev->phydev->link) 380 return; 381 382 /* Only full duplex supported for now */ 383 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 384 mode, DEV_MAC_MODE_CFG); 385 386 /* Set MAC IFG Gaps 387 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 388 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 389 */ 390 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 391 392 /* Load seed (0) and set MAC HDX late collision */ 393 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 394 DEV_MAC_HDX_CFG_SEED_LOAD, 395 DEV_MAC_HDX_CFG); 396 mdelay(1); 397 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 398 DEV_MAC_HDX_CFG); 399 400 /* Disable HDX fast control */ 401 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 402 403 /* SGMII only for now */ 404 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 405 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 406 407 /* Enable PCS */ 408 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 409 410 /* No aneg on SGMII */ 411 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 412 413 /* No loopback */ 414 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 415 416 /* Set Max Length and maximum tags allowed */ 417 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 418 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 419 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 420 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 421 DEV_MAC_TAGS_CFG); 422 423 /* Enable MAC module */ 424 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 425 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 426 427 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 428 * reset */ 429 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 430 DEV_CLOCK_CFG); 431 432 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 433 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 435 436 /* No PFC */ 437 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 438 ANA_PFC_PFC_CFG, p); 439 440 /* Set Pause WM hysteresis 441 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 442 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 443 */ 444 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 445 SYS_PAUSE_CFG_PAUSE_STOP(101) | 446 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 447 448 /* Core: Enable port for frame transfer */ 449 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 450 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 451 QSYS_SWITCH_PORT_MODE_PORT_ENA, 452 QSYS_SWITCH_PORT_MODE, p); 453 454 /* Flow control */ 455 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 456 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 457 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 458 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 459 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 460 SYS_MAC_FC_CFG, p); 461 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 462 463 /* Tail dropping watermark */ 464 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 465 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 466 SYS_ATOP, p); 467 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 468 } 469 470 static int ocelot_port_open(struct net_device *dev) 471 { 472 struct ocelot_port *port = netdev_priv(dev); 473 struct ocelot *ocelot = port->ocelot; 474 int err; 475 476 /* Enable receiving frames on the port, and activate auto-learning of 477 * MAC addresses. 478 */ 479 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 480 ANA_PORT_PORT_CFG_RECV_ENA | 481 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 482 ANA_PORT_PORT_CFG, port->chip_port); 483 484 if (port->serdes) { 485 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 486 port->phy_mode); 487 if (err) { 488 netdev_err(dev, "Could not set mode of SerDes\n"); 489 return err; 490 } 491 } 492 493 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 494 port->phy_mode); 495 if (err) { 496 netdev_err(dev, "Could not attach to PHY\n"); 497 return err; 498 } 499 500 dev->phydev = port->phy; 501 502 phy_attached_info(port->phy); 503 phy_start(port->phy); 504 return 0; 505 } 506 507 static int ocelot_port_stop(struct net_device *dev) 508 { 509 struct ocelot_port *port = netdev_priv(dev); 510 511 phy_disconnect(port->phy); 512 513 dev->phydev = NULL; 514 515 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 516 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 517 QSYS_SWITCH_PORT_MODE, port->chip_port); 518 return 0; 519 } 520 521 /* Generate the IFH for frame injection 522 * 523 * The IFH is a 128bit-value 524 * bit 127: bypass the analyzer processing 525 * bit 56-67: destination mask 526 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 527 * bit 20-27: cpu extraction queue mask 528 * bit 16: tag type 0: C-tag, 1: S-tag 529 * bit 0-11: VID 530 */ 531 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 532 { 533 ifh[0] = IFH_INJ_BYPASS; 534 ifh[1] = (0xf00 & info->port) >> 8; 535 ifh[2] = (0xff & info->port) << 24; 536 ifh[3] = (info->tag_type << 16) | info->vid; 537 538 return 0; 539 } 540 541 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 542 { 543 struct ocelot_port *port = netdev_priv(dev); 544 struct ocelot *ocelot = port->ocelot; 545 u32 val, ifh[IFH_LEN]; 546 struct frame_info info = {}; 547 u8 grp = 0; /* Send everything on CPU group 0 */ 548 unsigned int i, count, last; 549 550 val = ocelot_read(ocelot, QS_INJ_STATUS); 551 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 552 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 553 return NETDEV_TX_BUSY; 554 555 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 556 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 557 558 info.port = BIT(port->chip_port); 559 info.tag_type = IFH_TAG_TYPE_C; 560 info.vid = skb_vlan_tag_get(skb); 561 ocelot_gen_ifh(ifh, &info); 562 563 for (i = 0; i < IFH_LEN; i++) 564 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 565 QS_INJ_WR, grp); 566 567 count = (skb->len + 3) / 4; 568 last = skb->len % 4; 569 for (i = 0; i < count; i++) { 570 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 571 } 572 573 /* Add padding */ 574 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 575 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 576 i++; 577 } 578 579 /* Indicate EOF and valid bytes in last word */ 580 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 581 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 582 QS_INJ_CTRL_EOF, 583 QS_INJ_CTRL, grp); 584 585 /* Add dummy CRC */ 586 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 587 skb_tx_timestamp(skb); 588 589 dev->stats.tx_packets++; 590 dev->stats.tx_bytes += skb->len; 591 dev_kfree_skb_any(skb); 592 593 return NETDEV_TX_OK; 594 } 595 596 static void ocelot_mact_mc_reset(struct ocelot_port *port) 597 { 598 struct ocelot *ocelot = port->ocelot; 599 struct netdev_hw_addr *ha, *n; 600 601 /* Free and forget all the MAC addresses stored in the port private mc 602 * list. These are mc addresses that were previously added by calling 603 * ocelot_mact_mc_add(). 604 */ 605 list_for_each_entry_safe(ha, n, &port->mc, list) { 606 ocelot_mact_forget(ocelot, ha->addr, port->pvid); 607 list_del(&ha->list); 608 kfree(ha); 609 } 610 } 611 612 static int ocelot_mact_mc_add(struct ocelot_port *port, 613 struct netdev_hw_addr *hw_addr) 614 { 615 struct ocelot *ocelot = port->ocelot; 616 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL); 617 618 if (!ha) 619 return -ENOMEM; 620 621 memcpy(ha, hw_addr, sizeof(*ha)); 622 list_add_tail(&ha->list, &port->mc); 623 624 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid, 625 ENTRYTYPE_LOCKED); 626 627 return 0; 628 } 629 630 static void ocelot_set_rx_mode(struct net_device *dev) 631 { 632 struct ocelot_port *port = netdev_priv(dev); 633 struct ocelot *ocelot = port->ocelot; 634 struct netdev_hw_addr *ha; 635 int i; 636 u32 val; 637 638 /* This doesn't handle promiscuous mode because the bridge core is 639 * setting IFF_PROMISC on all slave interfaces and all frames would be 640 * forwarded to the CPU port. 641 */ 642 val = GENMASK(ocelot->num_phys_ports - 1, 0); 643 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 644 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 645 646 /* Handle the device multicast addresses. First remove all the 647 * previously installed addresses and then add the latest ones to the 648 * mac table. 649 */ 650 ocelot_mact_mc_reset(port); 651 netdev_for_each_mc_addr(ha, dev) 652 ocelot_mact_mc_add(port, ha); 653 } 654 655 static int ocelot_port_get_phys_port_name(struct net_device *dev, 656 char *buf, size_t len) 657 { 658 struct ocelot_port *port = netdev_priv(dev); 659 int ret; 660 661 ret = snprintf(buf, len, "p%d", port->chip_port); 662 if (ret >= len) 663 return -EINVAL; 664 665 return 0; 666 } 667 668 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 669 { 670 struct ocelot_port *port = netdev_priv(dev); 671 struct ocelot *ocelot = port->ocelot; 672 const struct sockaddr *addr = p; 673 674 /* Learn the new net device MAC address in the mac table. */ 675 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 676 ENTRYTYPE_LOCKED); 677 /* Then forget the previous one. */ 678 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 679 680 ether_addr_copy(dev->dev_addr, addr->sa_data); 681 return 0; 682 } 683 684 static void ocelot_get_stats64(struct net_device *dev, 685 struct rtnl_link_stats64 *stats) 686 { 687 struct ocelot_port *port = netdev_priv(dev); 688 struct ocelot *ocelot = port->ocelot; 689 690 /* Configure the port to read the stats from */ 691 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 692 SYS_STAT_CFG); 693 694 /* Get Rx stats */ 695 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 696 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 697 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 698 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 699 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 700 ocelot_read(ocelot, SYS_COUNT_RX_64) + 701 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 702 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 703 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 704 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 705 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 706 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 707 stats->rx_dropped = dev->stats.rx_dropped; 708 709 /* Get Tx stats */ 710 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 711 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 712 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 713 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 714 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 715 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 716 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 717 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 718 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 719 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 720 } 721 722 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 723 struct net_device *dev, const unsigned char *addr, 724 u16 vid, u16 flags) 725 { 726 struct ocelot_port *port = netdev_priv(dev); 727 struct ocelot *ocelot = port->ocelot; 728 729 if (!vid) { 730 if (!port->vlan_aware) 731 /* If the bridge is not VLAN aware and no VID was 732 * provided, set it to pvid to ensure the MAC entry 733 * matches incoming untagged packets 734 */ 735 vid = port->pvid; 736 else 737 /* If the bridge is VLAN aware a VID must be provided as 738 * otherwise the learnt entry wouldn't match any frame. 739 */ 740 return -EINVAL; 741 } 742 743 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 744 ENTRYTYPE_LOCKED); 745 } 746 747 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 748 struct net_device *dev, 749 const unsigned char *addr, u16 vid) 750 { 751 struct ocelot_port *port = netdev_priv(dev); 752 struct ocelot *ocelot = port->ocelot; 753 754 return ocelot_mact_forget(ocelot, addr, vid); 755 } 756 757 struct ocelot_dump_ctx { 758 struct net_device *dev; 759 struct sk_buff *skb; 760 struct netlink_callback *cb; 761 int idx; 762 }; 763 764 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 765 struct ocelot_dump_ctx *dump) 766 { 767 u32 portid = NETLINK_CB(dump->cb->skb).portid; 768 u32 seq = dump->cb->nlh->nlmsg_seq; 769 struct nlmsghdr *nlh; 770 struct ndmsg *ndm; 771 772 if (dump->idx < dump->cb->args[2]) 773 goto skip; 774 775 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 776 sizeof(*ndm), NLM_F_MULTI); 777 if (!nlh) 778 return -EMSGSIZE; 779 780 ndm = nlmsg_data(nlh); 781 ndm->ndm_family = AF_BRIDGE; 782 ndm->ndm_pad1 = 0; 783 ndm->ndm_pad2 = 0; 784 ndm->ndm_flags = NTF_SELF; 785 ndm->ndm_type = 0; 786 ndm->ndm_ifindex = dump->dev->ifindex; 787 ndm->ndm_state = NUD_REACHABLE; 788 789 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 790 goto nla_put_failure; 791 792 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 793 goto nla_put_failure; 794 795 nlmsg_end(dump->skb, nlh); 796 797 skip: 798 dump->idx++; 799 return 0; 800 801 nla_put_failure: 802 nlmsg_cancel(dump->skb, nlh); 803 return -EMSGSIZE; 804 } 805 806 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 807 struct ocelot_mact_entry *entry) 808 { 809 struct ocelot *ocelot = port->ocelot; 810 char mac[ETH_ALEN]; 811 u32 val, dst, macl, mach; 812 813 /* Set row and column to read from */ 814 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 815 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 816 817 /* Issue a read command */ 818 ocelot_write(ocelot, 819 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 820 ANA_TABLES_MACACCESS); 821 822 if (ocelot_mact_wait_for_completion(ocelot)) 823 return -ETIMEDOUT; 824 825 /* Read the entry flags */ 826 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 827 if (!(val & ANA_TABLES_MACACCESS_VALID)) 828 return -EINVAL; 829 830 /* If the entry read has another port configured as its destination, 831 * do not report it. 832 */ 833 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 834 if (dst != port->chip_port) 835 return -EINVAL; 836 837 /* Get the entry's MAC address and VLAN id */ 838 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 839 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 840 841 mac[0] = (mach >> 8) & 0xff; 842 mac[1] = (mach >> 0) & 0xff; 843 mac[2] = (macl >> 24) & 0xff; 844 mac[3] = (macl >> 16) & 0xff; 845 mac[4] = (macl >> 8) & 0xff; 846 mac[5] = (macl >> 0) & 0xff; 847 848 entry->vid = (mach >> 16) & 0xfff; 849 ether_addr_copy(entry->mac, mac); 850 851 return 0; 852 } 853 854 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 855 struct net_device *dev, 856 struct net_device *filter_dev, int *idx) 857 { 858 struct ocelot_port *port = netdev_priv(dev); 859 int i, j, ret = 0; 860 struct ocelot_dump_ctx dump = { 861 .dev = dev, 862 .skb = skb, 863 .cb = cb, 864 .idx = *idx, 865 }; 866 867 struct ocelot_mact_entry entry; 868 869 /* Loop through all the mac tables entries. There are 1024 rows of 4 870 * entries. 871 */ 872 for (i = 0; i < 1024; i++) { 873 for (j = 0; j < 4; j++) { 874 ret = ocelot_mact_read(port, i, j, &entry); 875 /* If the entry is invalid (wrong port, invalid...), 876 * skip it. 877 */ 878 if (ret == -EINVAL) 879 continue; 880 else if (ret) 881 goto end; 882 883 ret = ocelot_fdb_do_dump(&entry, &dump); 884 if (ret) 885 goto end; 886 } 887 } 888 889 end: 890 *idx = dump.idx; 891 return ret; 892 } 893 894 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 895 u16 vid) 896 { 897 return ocelot_vlan_vid_add(dev, vid, false, true); 898 } 899 900 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 901 u16 vid) 902 { 903 return ocelot_vlan_vid_del(dev, vid); 904 } 905 906 static int ocelot_set_features(struct net_device *dev, 907 netdev_features_t features) 908 { 909 struct ocelot_port *port = netdev_priv(dev); 910 netdev_features_t changed = dev->features ^ features; 911 912 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 913 ocelot_vlan_mode(port, features); 914 915 return 0; 916 } 917 918 static const struct net_device_ops ocelot_port_netdev_ops = { 919 .ndo_open = ocelot_port_open, 920 .ndo_stop = ocelot_port_stop, 921 .ndo_start_xmit = ocelot_port_xmit, 922 .ndo_set_rx_mode = ocelot_set_rx_mode, 923 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 924 .ndo_set_mac_address = ocelot_port_set_mac_address, 925 .ndo_get_stats64 = ocelot_get_stats64, 926 .ndo_fdb_add = ocelot_fdb_add, 927 .ndo_fdb_del = ocelot_fdb_del, 928 .ndo_fdb_dump = ocelot_fdb_dump, 929 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 930 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 931 .ndo_set_features = ocelot_set_features, 932 }; 933 934 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 935 { 936 struct ocelot_port *port = netdev_priv(netdev); 937 struct ocelot *ocelot = port->ocelot; 938 int i; 939 940 if (sset != ETH_SS_STATS) 941 return; 942 943 for (i = 0; i < ocelot->num_stats; i++) 944 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 945 ETH_GSTRING_LEN); 946 } 947 948 static void ocelot_check_stats(struct work_struct *work) 949 { 950 struct delayed_work *del_work = to_delayed_work(work); 951 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work); 952 int i, j; 953 954 mutex_lock(&ocelot->stats_lock); 955 956 for (i = 0; i < ocelot->num_phys_ports; i++) { 957 /* Configure the port to read the stats from */ 958 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 959 960 for (j = 0; j < ocelot->num_stats; j++) { 961 u32 val; 962 unsigned int idx = i * ocelot->num_stats + j; 963 964 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 965 ocelot->stats_layout[j].offset); 966 967 if (val < (ocelot->stats[idx] & U32_MAX)) 968 ocelot->stats[idx] += (u64)1 << 32; 969 970 ocelot->stats[idx] = (ocelot->stats[idx] & 971 ~(u64)U32_MAX) + val; 972 } 973 } 974 975 cancel_delayed_work(&ocelot->stats_work); 976 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 977 OCELOT_STATS_CHECK_DELAY); 978 979 mutex_unlock(&ocelot->stats_lock); 980 } 981 982 static void ocelot_get_ethtool_stats(struct net_device *dev, 983 struct ethtool_stats *stats, u64 *data) 984 { 985 struct ocelot_port *port = netdev_priv(dev); 986 struct ocelot *ocelot = port->ocelot; 987 int i; 988 989 /* check and update now */ 990 ocelot_check_stats(&ocelot->stats_work.work); 991 992 /* Copy all counters */ 993 for (i = 0; i < ocelot->num_stats; i++) 994 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 995 } 996 997 static int ocelot_get_sset_count(struct net_device *dev, int sset) 998 { 999 struct ocelot_port *port = netdev_priv(dev); 1000 struct ocelot *ocelot = port->ocelot; 1001 1002 if (sset != ETH_SS_STATS) 1003 return -EOPNOTSUPP; 1004 return ocelot->num_stats; 1005 } 1006 1007 static const struct ethtool_ops ocelot_ethtool_ops = { 1008 .get_strings = ocelot_get_strings, 1009 .get_ethtool_stats = ocelot_get_ethtool_stats, 1010 .get_sset_count = ocelot_get_sset_count, 1011 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1012 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1013 }; 1014 1015 static int ocelot_port_attr_get(struct net_device *dev, 1016 struct switchdev_attr *attr) 1017 { 1018 struct ocelot_port *ocelot_port = netdev_priv(dev); 1019 struct ocelot *ocelot = ocelot_port->ocelot; 1020 1021 switch (attr->id) { 1022 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 1023 attr->u.ppid.id_len = sizeof(ocelot->base_mac); 1024 memcpy(&attr->u.ppid.id, &ocelot->base_mac, 1025 attr->u.ppid.id_len); 1026 break; 1027 default: 1028 return -EOPNOTSUPP; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1035 struct switchdev_trans *trans, 1036 u8 state) 1037 { 1038 struct ocelot *ocelot = ocelot_port->ocelot; 1039 u32 port_cfg; 1040 int port, i; 1041 1042 if (switchdev_trans_ph_prepare(trans)) 1043 return 0; 1044 1045 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1046 return 0; 1047 1048 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1049 ocelot_port->chip_port); 1050 1051 switch (state) { 1052 case BR_STATE_FORWARDING: 1053 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1054 /* Fallthrough */ 1055 case BR_STATE_LEARNING: 1056 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1057 break; 1058 1059 default: 1060 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1061 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1062 break; 1063 } 1064 1065 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1066 ocelot_port->chip_port); 1067 1068 /* Apply FWD mask. The loop is needed to add/remove the current port as 1069 * a source for the other ports. 1070 */ 1071 for (port = 0; port < ocelot->num_phys_ports; port++) { 1072 if (ocelot->bridge_fwd_mask & BIT(port)) { 1073 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1074 1075 for (i = 0; i < ocelot->num_phys_ports; i++) { 1076 unsigned long bond_mask = ocelot->lags[i]; 1077 1078 if (!bond_mask) 1079 continue; 1080 1081 if (bond_mask & BIT(port)) { 1082 mask &= ~bond_mask; 1083 break; 1084 } 1085 } 1086 1087 ocelot_write_rix(ocelot, 1088 BIT(ocelot->num_phys_ports) | mask, 1089 ANA_PGID_PGID, PGID_SRC + port); 1090 } else { 1091 /* Only the CPU port, this is compatible with link 1092 * aggregation. 1093 */ 1094 ocelot_write_rix(ocelot, 1095 BIT(ocelot->num_phys_ports), 1096 ANA_PGID_PGID, PGID_SRC + port); 1097 } 1098 } 1099 1100 return 0; 1101 } 1102 1103 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1104 unsigned long ageing_clock_t) 1105 { 1106 struct ocelot *ocelot = ocelot_port->ocelot; 1107 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1108 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1109 1110 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1111 ANA_AUTOAGE); 1112 } 1113 1114 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1115 { 1116 struct ocelot *ocelot = port->ocelot; 1117 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1118 port->chip_port); 1119 1120 if (mc) 1121 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1122 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1123 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1124 else 1125 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1126 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1127 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1128 1129 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1130 } 1131 1132 static int ocelot_port_attr_set(struct net_device *dev, 1133 const struct switchdev_attr *attr, 1134 struct switchdev_trans *trans) 1135 { 1136 struct ocelot_port *ocelot_port = netdev_priv(dev); 1137 int err = 0; 1138 1139 switch (attr->id) { 1140 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1141 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1142 attr->u.stp_state); 1143 break; 1144 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1145 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1146 break; 1147 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1148 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1149 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1150 break; 1151 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1152 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1153 break; 1154 default: 1155 err = -EOPNOTSUPP; 1156 break; 1157 } 1158 1159 return err; 1160 } 1161 1162 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1163 const struct switchdev_obj_port_vlan *vlan, 1164 struct switchdev_trans *trans) 1165 { 1166 int ret; 1167 u16 vid; 1168 1169 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1170 ret = ocelot_vlan_vid_add(dev, vid, 1171 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1172 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1173 if (ret) 1174 return ret; 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1181 const struct switchdev_obj_port_vlan *vlan) 1182 { 1183 int ret; 1184 u16 vid; 1185 1186 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1187 ret = ocelot_vlan_vid_del(dev, vid); 1188 1189 if (ret) 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1197 const unsigned char *addr, 1198 u16 vid) 1199 { 1200 struct ocelot_multicast *mc; 1201 1202 list_for_each_entry(mc, &ocelot->multicast, list) { 1203 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1204 return mc; 1205 } 1206 1207 return NULL; 1208 } 1209 1210 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1211 const struct switchdev_obj_port_mdb *mdb, 1212 struct switchdev_trans *trans) 1213 { 1214 struct ocelot_port *port = netdev_priv(dev); 1215 struct ocelot *ocelot = port->ocelot; 1216 struct ocelot_multicast *mc; 1217 unsigned char addr[ETH_ALEN]; 1218 u16 vid = mdb->vid; 1219 bool new = false; 1220 1221 if (!vid) 1222 vid = port->pvid; 1223 1224 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1225 if (!mc) { 1226 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1227 if (!mc) 1228 return -ENOMEM; 1229 1230 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1231 mc->vid = vid; 1232 1233 list_add_tail(&mc->list, &ocelot->multicast); 1234 new = true; 1235 } 1236 1237 memcpy(addr, mc->addr, ETH_ALEN); 1238 addr[0] = 0; 1239 1240 if (!new) { 1241 addr[2] = mc->ports << 0; 1242 addr[1] = mc->ports << 8; 1243 ocelot_mact_forget(ocelot, addr, vid); 1244 } 1245 1246 mc->ports |= BIT(port->chip_port); 1247 addr[2] = mc->ports << 0; 1248 addr[1] = mc->ports << 8; 1249 1250 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1251 } 1252 1253 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1254 const struct switchdev_obj_port_mdb *mdb) 1255 { 1256 struct ocelot_port *port = netdev_priv(dev); 1257 struct ocelot *ocelot = port->ocelot; 1258 struct ocelot_multicast *mc; 1259 unsigned char addr[ETH_ALEN]; 1260 u16 vid = mdb->vid; 1261 1262 if (!vid) 1263 vid = port->pvid; 1264 1265 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1266 if (!mc) 1267 return -ENOENT; 1268 1269 memcpy(addr, mc->addr, ETH_ALEN); 1270 addr[2] = mc->ports << 0; 1271 addr[1] = mc->ports << 8; 1272 addr[0] = 0; 1273 ocelot_mact_forget(ocelot, addr, vid); 1274 1275 mc->ports &= ~BIT(port->chip_port); 1276 if (!mc->ports) { 1277 list_del(&mc->list); 1278 devm_kfree(ocelot->dev, mc); 1279 return 0; 1280 } 1281 1282 addr[2] = mc->ports << 0; 1283 addr[1] = mc->ports << 8; 1284 1285 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1286 } 1287 1288 static int ocelot_port_obj_add(struct net_device *dev, 1289 const struct switchdev_obj *obj, 1290 struct switchdev_trans *trans, 1291 struct netlink_ext_ack *extack) 1292 { 1293 int ret = 0; 1294 1295 switch (obj->id) { 1296 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1297 ret = ocelot_port_obj_add_vlan(dev, 1298 SWITCHDEV_OBJ_PORT_VLAN(obj), 1299 trans); 1300 break; 1301 case SWITCHDEV_OBJ_ID_PORT_MDB: 1302 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1303 trans); 1304 break; 1305 default: 1306 return -EOPNOTSUPP; 1307 } 1308 1309 return ret; 1310 } 1311 1312 static int ocelot_port_obj_del(struct net_device *dev, 1313 const struct switchdev_obj *obj) 1314 { 1315 int ret = 0; 1316 1317 switch (obj->id) { 1318 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1319 ret = ocelot_port_vlan_del_vlan(dev, 1320 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1321 break; 1322 case SWITCHDEV_OBJ_ID_PORT_MDB: 1323 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1324 break; 1325 default: 1326 return -EOPNOTSUPP; 1327 } 1328 1329 return ret; 1330 } 1331 1332 static const struct switchdev_ops ocelot_port_switchdev_ops = { 1333 .switchdev_port_attr_get = ocelot_port_attr_get, 1334 .switchdev_port_attr_set = ocelot_port_attr_set, 1335 }; 1336 1337 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1338 struct net_device *bridge) 1339 { 1340 struct ocelot *ocelot = ocelot_port->ocelot; 1341 1342 if (!ocelot->bridge_mask) { 1343 ocelot->hw_bridge_dev = bridge; 1344 } else { 1345 if (ocelot->hw_bridge_dev != bridge) 1346 /* This is adding the port to a second bridge, this is 1347 * unsupported */ 1348 return -ENODEV; 1349 } 1350 1351 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1352 1353 return 0; 1354 } 1355 1356 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1357 struct net_device *bridge) 1358 { 1359 struct ocelot *ocelot = ocelot_port->ocelot; 1360 1361 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1362 1363 if (!ocelot->bridge_mask) 1364 ocelot->hw_bridge_dev = NULL; 1365 1366 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1367 ocelot_port->vlan_aware = 0; 1368 ocelot_port->pvid = 0; 1369 ocelot_port->vid = 0; 1370 } 1371 1372 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1373 { 1374 int i, port, lag; 1375 1376 /* Reset destination and aggregation PGIDS */ 1377 for (port = 0; port < ocelot->num_phys_ports; port++) 1378 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1379 1380 for (i = PGID_AGGR; i < PGID_SRC; i++) 1381 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1382 ANA_PGID_PGID, i); 1383 1384 /* Now, set PGIDs for each LAG */ 1385 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1386 unsigned long bond_mask; 1387 int aggr_count = 0; 1388 u8 aggr_idx[16]; 1389 1390 bond_mask = ocelot->lags[lag]; 1391 if (!bond_mask) 1392 continue; 1393 1394 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1395 // Destination mask 1396 ocelot_write_rix(ocelot, bond_mask, 1397 ANA_PGID_PGID, port); 1398 aggr_idx[aggr_count] = port; 1399 aggr_count++; 1400 } 1401 1402 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1403 u32 ac; 1404 1405 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1406 ac &= ~bond_mask; 1407 ac |= BIT(aggr_idx[i % aggr_count]); 1408 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1409 } 1410 } 1411 } 1412 1413 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1414 { 1415 unsigned long bond_mask = ocelot->lags[lag]; 1416 unsigned int p; 1417 1418 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1419 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1420 1421 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1422 1423 /* Use lag port as logical port for port i */ 1424 ocelot_write_gix(ocelot, port_cfg | 1425 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1426 ANA_PORT_PORT_CFG, p); 1427 } 1428 } 1429 1430 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1431 struct net_device *bond) 1432 { 1433 struct ocelot *ocelot = ocelot_port->ocelot; 1434 int p = ocelot_port->chip_port; 1435 int lag, lp; 1436 struct net_device *ndev; 1437 u32 bond_mask = 0; 1438 1439 rcu_read_lock(); 1440 for_each_netdev_in_bond_rcu(bond, ndev) { 1441 struct ocelot_port *port = netdev_priv(ndev); 1442 1443 bond_mask |= BIT(port->chip_port); 1444 } 1445 rcu_read_unlock(); 1446 1447 lp = __ffs(bond_mask); 1448 1449 /* If the new port is the lowest one, use it as the logical port from 1450 * now on 1451 */ 1452 if (p == lp) { 1453 lag = p; 1454 ocelot->lags[p] = bond_mask; 1455 bond_mask &= ~BIT(p); 1456 if (bond_mask) { 1457 lp = __ffs(bond_mask); 1458 ocelot->lags[lp] = 0; 1459 } 1460 } else { 1461 lag = lp; 1462 ocelot->lags[lp] |= BIT(p); 1463 } 1464 1465 ocelot_setup_lag(ocelot, lag); 1466 ocelot_set_aggr_pgids(ocelot); 1467 1468 return 0; 1469 } 1470 1471 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1472 struct net_device *bond) 1473 { 1474 struct ocelot *ocelot = ocelot_port->ocelot; 1475 int p = ocelot_port->chip_port; 1476 u32 port_cfg; 1477 int i; 1478 1479 /* Remove port from any lag */ 1480 for (i = 0; i < ocelot->num_phys_ports; i++) 1481 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1482 1483 /* if it was the logical port of the lag, move the lag config to the 1484 * next port 1485 */ 1486 if (ocelot->lags[p]) { 1487 int n = __ffs(ocelot->lags[p]); 1488 1489 ocelot->lags[n] = ocelot->lags[p]; 1490 ocelot->lags[p] = 0; 1491 1492 ocelot_setup_lag(ocelot, n); 1493 } 1494 1495 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1496 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1497 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1498 ANA_PORT_PORT_CFG, p); 1499 1500 ocelot_set_aggr_pgids(ocelot); 1501 } 1502 1503 /* Checks if the net_device instance given to us originate from our driver. */ 1504 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1505 { 1506 return dev->netdev_ops == &ocelot_port_netdev_ops; 1507 } 1508 1509 static int ocelot_netdevice_port_event(struct net_device *dev, 1510 unsigned long event, 1511 struct netdev_notifier_changeupper_info *info) 1512 { 1513 struct ocelot_port *ocelot_port = netdev_priv(dev); 1514 int err = 0; 1515 1516 if (!ocelot_netdevice_dev_check(dev)) 1517 return 0; 1518 1519 switch (event) { 1520 case NETDEV_CHANGEUPPER: 1521 if (netif_is_bridge_master(info->upper_dev)) { 1522 if (info->linking) 1523 err = ocelot_port_bridge_join(ocelot_port, 1524 info->upper_dev); 1525 else 1526 ocelot_port_bridge_leave(ocelot_port, 1527 info->upper_dev); 1528 1529 ocelot_vlan_port_apply(ocelot_port->ocelot, 1530 ocelot_port); 1531 } 1532 if (netif_is_lag_master(info->upper_dev)) { 1533 if (info->linking) 1534 err = ocelot_port_lag_join(ocelot_port, 1535 info->upper_dev); 1536 else 1537 ocelot_port_lag_leave(ocelot_port, 1538 info->upper_dev); 1539 } 1540 break; 1541 default: 1542 break; 1543 } 1544 1545 return err; 1546 } 1547 1548 static int ocelot_netdevice_event(struct notifier_block *unused, 1549 unsigned long event, void *ptr) 1550 { 1551 struct netdev_notifier_changeupper_info *info = ptr; 1552 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1553 int ret = 0; 1554 1555 if (event == NETDEV_PRECHANGEUPPER && 1556 netif_is_lag_master(info->upper_dev)) { 1557 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1558 struct netlink_ext_ack *extack; 1559 1560 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1561 extack = netdev_notifier_info_to_extack(&info->info); 1562 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1563 1564 ret = -EINVAL; 1565 goto notify; 1566 } 1567 } 1568 1569 if (netif_is_lag_master(dev)) { 1570 struct net_device *slave; 1571 struct list_head *iter; 1572 1573 netdev_for_each_lower_dev(dev, slave, iter) { 1574 ret = ocelot_netdevice_port_event(slave, event, info); 1575 if (ret) 1576 goto notify; 1577 } 1578 } else { 1579 ret = ocelot_netdevice_port_event(dev, event, info); 1580 } 1581 1582 notify: 1583 return notifier_from_errno(ret); 1584 } 1585 1586 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1587 .notifier_call = ocelot_netdevice_event, 1588 }; 1589 EXPORT_SYMBOL(ocelot_netdevice_nb); 1590 1591 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1592 unsigned long event, void *ptr) 1593 { 1594 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1595 int err; 1596 1597 switch (event) { 1598 /* Blocking events. */ 1599 case SWITCHDEV_PORT_OBJ_ADD: 1600 err = switchdev_handle_port_obj_add(dev, ptr, 1601 ocelot_netdevice_dev_check, 1602 ocelot_port_obj_add); 1603 return notifier_from_errno(err); 1604 case SWITCHDEV_PORT_OBJ_DEL: 1605 err = switchdev_handle_port_obj_del(dev, ptr, 1606 ocelot_netdevice_dev_check, 1607 ocelot_port_obj_del); 1608 return notifier_from_errno(err); 1609 } 1610 1611 return NOTIFY_DONE; 1612 } 1613 1614 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1615 .notifier_call = ocelot_switchdev_blocking_event, 1616 }; 1617 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1618 1619 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1620 void __iomem *regs, 1621 struct phy_device *phy) 1622 { 1623 struct ocelot_port *ocelot_port; 1624 struct net_device *dev; 1625 int err; 1626 1627 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1628 if (!dev) 1629 return -ENOMEM; 1630 SET_NETDEV_DEV(dev, ocelot->dev); 1631 ocelot_port = netdev_priv(dev); 1632 ocelot_port->dev = dev; 1633 ocelot_port->ocelot = ocelot; 1634 ocelot_port->regs = regs; 1635 ocelot_port->chip_port = port; 1636 ocelot_port->phy = phy; 1637 INIT_LIST_HEAD(&ocelot_port->mc); 1638 ocelot->ports[port] = ocelot_port; 1639 1640 dev->netdev_ops = &ocelot_port_netdev_ops; 1641 dev->ethtool_ops = &ocelot_ethtool_ops; 1642 dev->switchdev_ops = &ocelot_port_switchdev_ops; 1643 1644 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS; 1645 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1646 1647 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1648 dev->dev_addr[ETH_ALEN - 1] += port; 1649 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1650 ENTRYTYPE_LOCKED); 1651 1652 err = register_netdev(dev); 1653 if (err) { 1654 dev_err(ocelot->dev, "register_netdev failed\n"); 1655 goto err_register_netdev; 1656 } 1657 1658 /* Basic L2 initialization */ 1659 ocelot_vlan_port_apply(ocelot, ocelot_port); 1660 1661 return 0; 1662 1663 err_register_netdev: 1664 free_netdev(dev); 1665 return err; 1666 } 1667 EXPORT_SYMBOL(ocelot_probe_port); 1668 1669 int ocelot_init(struct ocelot *ocelot) 1670 { 1671 u32 port; 1672 int i, cpu = ocelot->num_phys_ports; 1673 char queue_name[32]; 1674 1675 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1676 sizeof(u32), GFP_KERNEL); 1677 if (!ocelot->lags) 1678 return -ENOMEM; 1679 1680 ocelot->stats = devm_kcalloc(ocelot->dev, 1681 ocelot->num_phys_ports * ocelot->num_stats, 1682 sizeof(u64), GFP_KERNEL); 1683 if (!ocelot->stats) 1684 return -ENOMEM; 1685 1686 mutex_init(&ocelot->stats_lock); 1687 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1688 dev_name(ocelot->dev)); 1689 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1690 if (!ocelot->stats_queue) 1691 return -ENOMEM; 1692 1693 ocelot_mact_init(ocelot); 1694 ocelot_vlan_init(ocelot); 1695 1696 for (port = 0; port < ocelot->num_phys_ports; port++) { 1697 /* Clear all counters (5 groups) */ 1698 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1699 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1700 SYS_STAT_CFG); 1701 } 1702 1703 /* Only use S-Tag */ 1704 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1705 1706 /* Aggregation mode */ 1707 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1708 ANA_AGGR_CFG_AC_DMAC_ENA | 1709 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1710 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1711 1712 /* Set MAC age time to default value. The entry is aged after 1713 * 2*AGE_PERIOD 1714 */ 1715 ocelot_write(ocelot, 1716 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1717 ANA_AUTOAGE); 1718 1719 /* Disable learning for frames discarded by VLAN ingress filtering */ 1720 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1721 1722 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1723 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1724 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1725 1726 /* Setup flooding PGIDs */ 1727 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1728 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1729 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1730 ANA_FLOODING, 0); 1731 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1732 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1733 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1734 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1735 ANA_FLOODING_IPMC); 1736 1737 for (port = 0; port < ocelot->num_phys_ports; port++) { 1738 /* Transmit the frame to the local port. */ 1739 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1740 /* Do not forward BPDU frames to the front ports. */ 1741 ocelot_write_gix(ocelot, 1742 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1743 ANA_PORT_CPU_FWD_BPDU_CFG, 1744 port); 1745 /* Ensure bridging is disabled */ 1746 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1747 } 1748 1749 /* Configure and enable the CPU port. */ 1750 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1751 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1752 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1753 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1754 ANA_PORT_PORT_CFG, cpu); 1755 1756 /* Allow broadcast MAC frames. */ 1757 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1758 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1759 1760 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1761 } 1762 ocelot_write_rix(ocelot, 1763 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1764 ANA_PGID_PGID, PGID_MC); 1765 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1766 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1767 1768 /* CPU port Injection/Extraction configuration */ 1769 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1770 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1771 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1772 QSYS_SWITCH_PORT_MODE, cpu); 1773 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1774 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1775 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1776 * registers endianness. 1777 */ 1778 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1779 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1780 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1781 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1782 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1783 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1784 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1785 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1786 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1787 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1788 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1789 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1790 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1791 for (i = 0; i < 16; i++) 1792 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1793 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1794 ANA_CPUQ_8021_CFG, i); 1795 1796 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats); 1797 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1798 OCELOT_STATS_CHECK_DELAY); 1799 return 0; 1800 } 1801 EXPORT_SYMBOL(ocelot_init); 1802 1803 void ocelot_deinit(struct ocelot *ocelot) 1804 { 1805 destroy_workqueue(ocelot->stats_queue); 1806 mutex_destroy(&ocelot->stats_lock); 1807 } 1808 EXPORT_SYMBOL(ocelot_deinit); 1809 1810 MODULE_LICENSE("Dual MIT/GPL"); 1811