1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 226 bool vlan_aware) 227 { 228 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 229 struct ocelot_port *ocelot_port = ocelot->ports[port]; 230 struct ocelot_vcap_filter *filter; 231 u32 val; 232 233 list_for_each_entry(filter, &block->rules, list) { 234 if (filter->ingress_port_mask & BIT(port) && 235 filter->action.vid_replace_ena) { 236 dev_err(ocelot->dev, 237 "Cannot change VLAN state with vlan modify rules active\n"); 238 return -EBUSY; 239 } 240 } 241 242 ocelot_port->vlan_aware = vlan_aware; 243 244 if (vlan_aware) 245 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 246 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 247 else 248 val = 0; 249 ocelot_rmw_gix(ocelot, val, 250 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 251 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 252 ANA_PORT_VLAN_CFG, port); 253 254 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 256 257 return 0; 258 } 259 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 260 261 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 262 bool untagged) 263 { 264 struct ocelot_port *ocelot_port = ocelot->ports[port]; 265 266 /* Deny changing the native VLAN, but always permit deleting it */ 267 if (untagged && ocelot_port->native_vlan.vid != vid && 268 ocelot_port->native_vlan.valid) { 269 dev_err(ocelot->dev, 270 "Port already has a native VLAN: %d\n", 271 ocelot_port->native_vlan.vid); 272 return -EBUSY; 273 } 274 275 return 0; 276 } 277 EXPORT_SYMBOL(ocelot_vlan_prepare); 278 279 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 280 bool untagged) 281 { 282 int ret; 283 284 /* Make the port a member of the VLAN */ 285 ocelot->vlan_mask[vid] |= BIT(port); 286 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 287 if (ret) 288 return ret; 289 290 /* Default ingress vlan classification */ 291 if (pvid) { 292 struct ocelot_vlan pvid_vlan; 293 294 pvid_vlan.vid = vid; 295 pvid_vlan.valid = true; 296 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 297 } 298 299 /* Untagged egress vlan clasification */ 300 if (untagged) { 301 struct ocelot_vlan native_vlan; 302 303 native_vlan.vid = vid; 304 native_vlan.valid = true; 305 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 306 } 307 308 return 0; 309 } 310 EXPORT_SYMBOL(ocelot_vlan_add); 311 312 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 313 { 314 struct ocelot_port *ocelot_port = ocelot->ports[port]; 315 int ret; 316 317 /* Stop the port from being a member of the vlan */ 318 ocelot->vlan_mask[vid] &= ~BIT(port); 319 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 320 if (ret) 321 return ret; 322 323 /* Ingress */ 324 if (ocelot_port->pvid_vlan.vid == vid) { 325 struct ocelot_vlan pvid_vlan = {0}; 326 327 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 328 } 329 330 /* Egress */ 331 if (ocelot_port->native_vlan.vid == vid) { 332 struct ocelot_vlan native_vlan = {0}; 333 334 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 335 } 336 337 return 0; 338 } 339 EXPORT_SYMBOL(ocelot_vlan_del); 340 341 static void ocelot_vlan_init(struct ocelot *ocelot) 342 { 343 u16 port, vid; 344 345 /* Clear VLAN table, by default all ports are members of all VLANs */ 346 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 347 ANA_TABLES_VLANACCESS); 348 ocelot_vlant_wait_for_completion(ocelot); 349 350 /* Configure the port VLAN memberships */ 351 for (vid = 1; vid < VLAN_N_VID; vid++) { 352 ocelot->vlan_mask[vid] = 0; 353 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 354 } 355 356 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 357 * traffic. It is added automatically if 8021q module is loaded, but 358 * we can't rely on it since module may be not loaded. 359 */ 360 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 361 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 362 363 /* Set vlan ingress filter mask to all ports but the CPU port by 364 * default. 365 */ 366 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 367 ANA_VLANMASK); 368 369 for (port = 0; port < ocelot->num_phys_ports; port++) { 370 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 371 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 372 } 373 } 374 375 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 376 { 377 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 378 } 379 380 int ocelot_port_flush(struct ocelot *ocelot, int port) 381 { 382 int err, val; 383 384 /* Disable dequeuing from the egress queues */ 385 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 386 QSYS_PORT_MODE_DEQUEUE_DIS, 387 QSYS_PORT_MODE, port); 388 389 /* Disable flow control */ 390 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 391 392 /* Disable priority flow control */ 393 ocelot_fields_write(ocelot, port, 394 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 395 396 /* Wait at least the time it takes to receive a frame of maximum length 397 * at the port. 398 * Worst-case delays for 10 kilobyte jumbo frames are: 399 * 8 ms on a 10M port 400 * 800 μs on a 100M port 401 * 80 μs on a 1G port 402 * 32 μs on a 2.5G port 403 */ 404 usleep_range(8000, 10000); 405 406 /* Disable half duplex backpressure. */ 407 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 408 SYS_FRONT_PORT_MODE, port); 409 410 /* Flush the queues associated with the port. */ 411 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 412 REW_PORT_CFG, port); 413 414 /* Enable dequeuing from the egress queues. */ 415 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 416 port); 417 418 /* Wait until flushing is complete. */ 419 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 420 100, 2000000, false, ocelot, port); 421 422 /* Clear flushing again. */ 423 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 424 425 return err; 426 } 427 EXPORT_SYMBOL(ocelot_port_flush); 428 429 void ocelot_adjust_link(struct ocelot *ocelot, int port, 430 struct phy_device *phydev) 431 { 432 struct ocelot_port *ocelot_port = ocelot->ports[port]; 433 int speed, mode = 0; 434 435 switch (phydev->speed) { 436 case SPEED_10: 437 speed = OCELOT_SPEED_10; 438 break; 439 case SPEED_100: 440 speed = OCELOT_SPEED_100; 441 break; 442 case SPEED_1000: 443 speed = OCELOT_SPEED_1000; 444 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 445 break; 446 case SPEED_2500: 447 speed = OCELOT_SPEED_2500; 448 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 449 break; 450 default: 451 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 452 port, phydev->speed); 453 return; 454 } 455 456 phy_print_status(phydev); 457 458 if (!phydev->link) 459 return; 460 461 /* Only full duplex supported for now */ 462 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 463 mode, DEV_MAC_MODE_CFG); 464 465 /* Disable HDX fast control */ 466 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 467 DEV_PORT_MISC); 468 469 /* SGMII only for now */ 470 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 471 PCS1G_MODE_CFG); 472 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 473 474 /* Enable PCS */ 475 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 476 477 /* No aneg on SGMII */ 478 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 479 480 /* No loopback */ 481 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 482 483 /* Enable MAC module */ 484 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 485 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 486 487 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 488 * reset 489 */ 490 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 491 DEV_CLOCK_CFG); 492 493 /* No PFC */ 494 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 495 ANA_PFC_PFC_CFG, port); 496 497 /* Core: Enable port for frame transfer */ 498 ocelot_fields_write(ocelot, port, 499 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 500 501 /* Flow control */ 502 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 503 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 504 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 505 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 506 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 507 SYS_MAC_FC_CFG, port); 508 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 509 } 510 EXPORT_SYMBOL(ocelot_adjust_link); 511 512 void ocelot_port_enable(struct ocelot *ocelot, int port, 513 struct phy_device *phy) 514 { 515 /* Enable receiving frames on the port, and activate auto-learning of 516 * MAC addresses. 517 */ 518 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 519 ANA_PORT_PORT_CFG_RECV_ENA | 520 ANA_PORT_PORT_CFG_PORTID_VAL(port), 521 ANA_PORT_PORT_CFG, port); 522 } 523 EXPORT_SYMBOL(ocelot_port_enable); 524 525 void ocelot_port_disable(struct ocelot *ocelot, int port) 526 { 527 struct ocelot_port *ocelot_port = ocelot->ports[port]; 528 529 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 530 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 531 } 532 EXPORT_SYMBOL(ocelot_port_disable); 533 534 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 535 struct sk_buff *clone) 536 { 537 struct ocelot_port *ocelot_port = ocelot->ports[port]; 538 539 spin_lock(&ocelot_port->ts_id_lock); 540 541 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 542 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 543 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 544 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 545 skb_queue_tail(&ocelot_port->tx_skbs, clone); 546 547 spin_unlock(&ocelot_port->ts_id_lock); 548 } 549 550 u32 ocelot_ptp_rew_op(struct sk_buff *skb) 551 { 552 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 553 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd; 554 u32 rew_op = 0; 555 556 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) { 557 rew_op = ptp_cmd; 558 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3; 559 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 560 rew_op = ptp_cmd; 561 } 562 563 return rew_op; 564 } 565 EXPORT_SYMBOL(ocelot_ptp_rew_op); 566 567 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb) 568 { 569 struct ptp_header *hdr; 570 unsigned int ptp_class; 571 u8 msgtype, twostep; 572 573 ptp_class = ptp_classify_raw(skb); 574 if (ptp_class == PTP_CLASS_NONE) 575 return false; 576 577 hdr = ptp_parse_header(skb, ptp_class); 578 if (!hdr) 579 return false; 580 581 msgtype = ptp_get_msgtype(hdr, ptp_class); 582 twostep = hdr->flag_field[0] & 0x2; 583 584 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 585 return true; 586 587 return false; 588 } 589 590 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 591 struct sk_buff *skb, 592 struct sk_buff **clone) 593 { 594 struct ocelot_port *ocelot_port = ocelot->ports[port]; 595 u8 ptp_cmd = ocelot_port->ptp_cmd; 596 597 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 598 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 599 if (ocelot_ptp_is_onestep_sync(skb)) { 600 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 601 return 0; 602 } 603 604 /* Fall back to two-step timestamping */ 605 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 606 } 607 608 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 609 *clone = skb_clone_sk(skb); 610 if (!(*clone)) 611 return -ENOMEM; 612 613 ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 614 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 615 } 616 617 return 0; 618 } 619 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 620 621 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 622 struct timespec64 *ts) 623 { 624 unsigned long flags; 625 u32 val; 626 627 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 628 629 /* Read current PTP time to get seconds */ 630 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 631 632 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 633 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 634 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 635 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 636 637 /* Read packet HW timestamp from FIFO */ 638 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 639 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 640 641 /* Sec has incremented since the ts was registered */ 642 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 643 ts->tv_sec--; 644 645 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 646 } 647 648 void ocelot_get_txtstamp(struct ocelot *ocelot) 649 { 650 int budget = OCELOT_PTP_QUEUE_SZ; 651 652 while (budget--) { 653 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 654 struct skb_shared_hwtstamps shhwtstamps; 655 struct ocelot_port *port; 656 struct timespec64 ts; 657 unsigned long flags; 658 u32 val, id, txport; 659 660 val = ocelot_read(ocelot, SYS_PTP_STATUS); 661 662 /* Check if a timestamp can be retrieved */ 663 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 664 break; 665 666 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 667 668 /* Retrieve the ts ID and Tx port */ 669 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 670 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 671 672 /* Retrieve its associated skb */ 673 port = ocelot->ports[txport]; 674 675 spin_lock_irqsave(&port->tx_skbs.lock, flags); 676 677 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 678 if (OCELOT_SKB_CB(skb)->ts_id != id) 679 continue; 680 __skb_unlink(skb, &port->tx_skbs); 681 skb_match = skb; 682 break; 683 } 684 685 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 686 687 /* Get the h/w timestamp */ 688 ocelot_get_hwtimestamp(ocelot, &ts); 689 690 if (unlikely(!skb_match)) 691 continue; 692 693 /* Set the timestamp into the skb */ 694 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 695 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 696 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 697 698 /* Next ts */ 699 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 700 } 701 } 702 EXPORT_SYMBOL(ocelot_get_txtstamp); 703 704 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 705 u32 *rval) 706 { 707 u32 bytes_valid, val; 708 709 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 710 if (val == XTR_NOT_READY) { 711 if (ifh) 712 return -EIO; 713 714 do { 715 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 716 } while (val == XTR_NOT_READY); 717 } 718 719 switch (val) { 720 case XTR_ABORT: 721 return -EIO; 722 case XTR_EOF_0: 723 case XTR_EOF_1: 724 case XTR_EOF_2: 725 case XTR_EOF_3: 726 case XTR_PRUNED: 727 bytes_valid = XTR_VALID_BYTES(val); 728 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 729 if (val == XTR_ESCAPE) 730 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 731 else 732 *rval = val; 733 734 return bytes_valid; 735 case XTR_ESCAPE: 736 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 737 738 return 4; 739 default: 740 *rval = val; 741 742 return 4; 743 } 744 } 745 746 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 747 { 748 int i, err = 0; 749 750 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 751 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 752 if (err != 4) 753 return (err < 0) ? err : -EIO; 754 } 755 756 return 0; 757 } 758 759 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 760 { 761 struct skb_shared_hwtstamps *shhwtstamps; 762 u64 tod_in_ns, full_ts_in_ns; 763 u64 timestamp, src_port, len; 764 u32 xfh[OCELOT_TAG_LEN / 4]; 765 struct net_device *dev; 766 struct timespec64 ts; 767 struct sk_buff *skb; 768 int sz, buf_len; 769 u32 val, *buf; 770 int err; 771 772 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 773 if (err) 774 return err; 775 776 ocelot_xfh_get_src_port(xfh, &src_port); 777 ocelot_xfh_get_len(xfh, &len); 778 ocelot_xfh_get_rew_val(xfh, ×tamp); 779 780 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 781 return -EINVAL; 782 783 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 784 if (!dev) 785 return -EINVAL; 786 787 skb = netdev_alloc_skb(dev, len); 788 if (unlikely(!skb)) { 789 netdev_err(dev, "Unable to allocate sk_buff\n"); 790 return -ENOMEM; 791 } 792 793 buf_len = len - ETH_FCS_LEN; 794 buf = (u32 *)skb_put(skb, buf_len); 795 796 len = 0; 797 do { 798 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 799 if (sz < 0) { 800 err = sz; 801 goto out_free_skb; 802 } 803 *buf++ = val; 804 len += sz; 805 } while (len < buf_len); 806 807 /* Read the FCS */ 808 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 809 if (sz < 0) { 810 err = sz; 811 goto out_free_skb; 812 } 813 814 /* Update the statistics if part of the FCS was read before */ 815 len -= ETH_FCS_LEN - sz; 816 817 if (unlikely(dev->features & NETIF_F_RXFCS)) { 818 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 819 *buf = val; 820 } 821 822 if (ocelot->ptp) { 823 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 824 825 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 826 if ((tod_in_ns & 0xffffffff) < timestamp) 827 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 828 timestamp; 829 else 830 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 831 timestamp; 832 833 shhwtstamps = skb_hwtstamps(skb); 834 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 835 shhwtstamps->hwtstamp = full_ts_in_ns; 836 } 837 838 /* Everything we see on an interface that is in the HW bridge 839 * has already been forwarded. 840 */ 841 if (ocelot->ports[src_port]->bridge) 842 skb->offload_fwd_mark = 1; 843 844 skb->protocol = eth_type_trans(skb, dev); 845 846 *nskb = skb; 847 848 return 0; 849 850 out_free_skb: 851 kfree_skb(skb); 852 return err; 853 } 854 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 855 856 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 857 { 858 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 859 860 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 861 return false; 862 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 863 return false; 864 865 return true; 866 } 867 EXPORT_SYMBOL(ocelot_can_inject); 868 869 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 870 u32 rew_op, struct sk_buff *skb) 871 { 872 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 873 unsigned int i, count, last; 874 875 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 876 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 877 878 ocelot_ifh_set_bypass(ifh, 1); 879 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 880 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 881 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 882 ocelot_ifh_set_rew_op(ifh, rew_op); 883 884 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 885 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 886 887 count = DIV_ROUND_UP(skb->len, 4); 888 last = skb->len % 4; 889 for (i = 0; i < count; i++) 890 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 891 892 /* Add padding */ 893 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 894 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 895 i++; 896 } 897 898 /* Indicate EOF and valid bytes in last word */ 899 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 900 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 901 QS_INJ_CTRL_EOF, 902 QS_INJ_CTRL, grp); 903 904 /* Add dummy CRC */ 905 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 906 skb_tx_timestamp(skb); 907 908 skb->dev->stats.tx_packets++; 909 skb->dev->stats.tx_bytes += skb->len; 910 } 911 EXPORT_SYMBOL(ocelot_port_inject_frame); 912 913 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 914 { 915 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 916 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 917 } 918 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 919 920 int ocelot_fdb_add(struct ocelot *ocelot, int port, 921 const unsigned char *addr, u16 vid) 922 { 923 int pgid = port; 924 925 if (port == ocelot->npi) 926 pgid = PGID_CPU; 927 928 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 929 } 930 EXPORT_SYMBOL(ocelot_fdb_add); 931 932 int ocelot_fdb_del(struct ocelot *ocelot, int port, 933 const unsigned char *addr, u16 vid) 934 { 935 return ocelot_mact_forget(ocelot, addr, vid); 936 } 937 EXPORT_SYMBOL(ocelot_fdb_del); 938 939 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 940 bool is_static, void *data) 941 { 942 struct ocelot_dump_ctx *dump = data; 943 u32 portid = NETLINK_CB(dump->cb->skb).portid; 944 u32 seq = dump->cb->nlh->nlmsg_seq; 945 struct nlmsghdr *nlh; 946 struct ndmsg *ndm; 947 948 if (dump->idx < dump->cb->args[2]) 949 goto skip; 950 951 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 952 sizeof(*ndm), NLM_F_MULTI); 953 if (!nlh) 954 return -EMSGSIZE; 955 956 ndm = nlmsg_data(nlh); 957 ndm->ndm_family = AF_BRIDGE; 958 ndm->ndm_pad1 = 0; 959 ndm->ndm_pad2 = 0; 960 ndm->ndm_flags = NTF_SELF; 961 ndm->ndm_type = 0; 962 ndm->ndm_ifindex = dump->dev->ifindex; 963 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 964 965 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 966 goto nla_put_failure; 967 968 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 969 goto nla_put_failure; 970 971 nlmsg_end(dump->skb, nlh); 972 973 skip: 974 dump->idx++; 975 return 0; 976 977 nla_put_failure: 978 nlmsg_cancel(dump->skb, nlh); 979 return -EMSGSIZE; 980 } 981 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 982 983 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 984 struct ocelot_mact_entry *entry) 985 { 986 u32 val, dst, macl, mach; 987 char mac[ETH_ALEN]; 988 989 /* Set row and column to read from */ 990 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 991 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 992 993 /* Issue a read command */ 994 ocelot_write(ocelot, 995 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 996 ANA_TABLES_MACACCESS); 997 998 if (ocelot_mact_wait_for_completion(ocelot)) 999 return -ETIMEDOUT; 1000 1001 /* Read the entry flags */ 1002 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1003 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1004 return -EINVAL; 1005 1006 /* If the entry read has another port configured as its destination, 1007 * do not report it. 1008 */ 1009 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1010 if (dst != port) 1011 return -EINVAL; 1012 1013 /* Get the entry's MAC address and VLAN id */ 1014 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1015 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1016 1017 mac[0] = (mach >> 8) & 0xff; 1018 mac[1] = (mach >> 0) & 0xff; 1019 mac[2] = (macl >> 24) & 0xff; 1020 mac[3] = (macl >> 16) & 0xff; 1021 mac[4] = (macl >> 8) & 0xff; 1022 mac[5] = (macl >> 0) & 0xff; 1023 1024 entry->vid = (mach >> 16) & 0xfff; 1025 ether_addr_copy(entry->mac, mac); 1026 1027 return 0; 1028 } 1029 1030 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1031 dsa_fdb_dump_cb_t *cb, void *data) 1032 { 1033 int i, j; 1034 1035 /* Loop through all the mac tables entries. */ 1036 for (i = 0; i < ocelot->num_mact_rows; i++) { 1037 for (j = 0; j < 4; j++) { 1038 struct ocelot_mact_entry entry; 1039 bool is_static; 1040 int ret; 1041 1042 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1043 /* If the entry is invalid (wrong port, invalid...), 1044 * skip it. 1045 */ 1046 if (ret == -EINVAL) 1047 continue; 1048 else if (ret) 1049 return ret; 1050 1051 is_static = (entry.type == ENTRYTYPE_LOCKED); 1052 1053 ret = cb(entry.mac, entry.vid, is_static, data); 1054 if (ret) 1055 return ret; 1056 } 1057 } 1058 1059 return 0; 1060 } 1061 EXPORT_SYMBOL(ocelot_fdb_dump); 1062 1063 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1064 { 1065 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1066 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1067 } 1068 EXPORT_SYMBOL(ocelot_hwstamp_get); 1069 1070 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1071 { 1072 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1073 struct hwtstamp_config cfg; 1074 1075 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1076 return -EFAULT; 1077 1078 /* reserved for future extensions */ 1079 if (cfg.flags) 1080 return -EINVAL; 1081 1082 /* Tx type sanity check */ 1083 switch (cfg.tx_type) { 1084 case HWTSTAMP_TX_ON: 1085 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1086 break; 1087 case HWTSTAMP_TX_ONESTEP_SYNC: 1088 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1089 * need to update the origin time. 1090 */ 1091 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1092 break; 1093 case HWTSTAMP_TX_OFF: 1094 ocelot_port->ptp_cmd = 0; 1095 break; 1096 default: 1097 return -ERANGE; 1098 } 1099 1100 mutex_lock(&ocelot->ptp_lock); 1101 1102 switch (cfg.rx_filter) { 1103 case HWTSTAMP_FILTER_NONE: 1104 break; 1105 case HWTSTAMP_FILTER_ALL: 1106 case HWTSTAMP_FILTER_SOME: 1107 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1108 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1109 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1110 case HWTSTAMP_FILTER_NTP_ALL: 1111 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1112 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1113 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1114 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1115 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1116 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1117 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1118 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1119 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1120 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1121 break; 1122 default: 1123 mutex_unlock(&ocelot->ptp_lock); 1124 return -ERANGE; 1125 } 1126 1127 /* Commit back the result & save it */ 1128 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1129 mutex_unlock(&ocelot->ptp_lock); 1130 1131 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1132 } 1133 EXPORT_SYMBOL(ocelot_hwstamp_set); 1134 1135 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1136 { 1137 int i; 1138 1139 if (sset != ETH_SS_STATS) 1140 return; 1141 1142 for (i = 0; i < ocelot->num_stats; i++) 1143 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1144 ETH_GSTRING_LEN); 1145 } 1146 EXPORT_SYMBOL(ocelot_get_strings); 1147 1148 static void ocelot_update_stats(struct ocelot *ocelot) 1149 { 1150 int i, j; 1151 1152 mutex_lock(&ocelot->stats_lock); 1153 1154 for (i = 0; i < ocelot->num_phys_ports; i++) { 1155 /* Configure the port to read the stats from */ 1156 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1157 1158 for (j = 0; j < ocelot->num_stats; j++) { 1159 u32 val; 1160 unsigned int idx = i * ocelot->num_stats + j; 1161 1162 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1163 ocelot->stats_layout[j].offset); 1164 1165 if (val < (ocelot->stats[idx] & U32_MAX)) 1166 ocelot->stats[idx] += (u64)1 << 32; 1167 1168 ocelot->stats[idx] = (ocelot->stats[idx] & 1169 ~(u64)U32_MAX) + val; 1170 } 1171 } 1172 1173 mutex_unlock(&ocelot->stats_lock); 1174 } 1175 1176 static void ocelot_check_stats_work(struct work_struct *work) 1177 { 1178 struct delayed_work *del_work = to_delayed_work(work); 1179 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1180 stats_work); 1181 1182 ocelot_update_stats(ocelot); 1183 1184 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1185 OCELOT_STATS_CHECK_DELAY); 1186 } 1187 1188 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1189 { 1190 int i; 1191 1192 /* check and update now */ 1193 ocelot_update_stats(ocelot); 1194 1195 /* Copy all counters */ 1196 for (i = 0; i < ocelot->num_stats; i++) 1197 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1198 } 1199 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1200 1201 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1202 { 1203 if (sset != ETH_SS_STATS) 1204 return -EOPNOTSUPP; 1205 1206 return ocelot->num_stats; 1207 } 1208 EXPORT_SYMBOL(ocelot_get_sset_count); 1209 1210 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1211 struct ethtool_ts_info *info) 1212 { 1213 info->phc_index = ocelot->ptp_clock ? 1214 ptp_clock_index(ocelot->ptp_clock) : -1; 1215 if (info->phc_index == -1) { 1216 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1217 SOF_TIMESTAMPING_RX_SOFTWARE | 1218 SOF_TIMESTAMPING_SOFTWARE; 1219 return 0; 1220 } 1221 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1222 SOF_TIMESTAMPING_RX_SOFTWARE | 1223 SOF_TIMESTAMPING_SOFTWARE | 1224 SOF_TIMESTAMPING_TX_HARDWARE | 1225 SOF_TIMESTAMPING_RX_HARDWARE | 1226 SOF_TIMESTAMPING_RAW_HARDWARE; 1227 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1228 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1229 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1230 1231 return 0; 1232 } 1233 EXPORT_SYMBOL(ocelot_get_ts_info); 1234 1235 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1236 bool only_active_ports) 1237 { 1238 u32 mask = 0; 1239 int port; 1240 1241 for (port = 0; port < ocelot->num_phys_ports; port++) { 1242 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1243 1244 if (!ocelot_port) 1245 continue; 1246 1247 if (ocelot_port->bond == bond) { 1248 if (only_active_ports && !ocelot_port->lag_tx_active) 1249 continue; 1250 1251 mask |= BIT(port); 1252 } 1253 } 1254 1255 return mask; 1256 } 1257 1258 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, 1259 struct net_device *bridge) 1260 { 1261 u32 mask = 0; 1262 int port; 1263 1264 for (port = 0; port < ocelot->num_phys_ports; port++) { 1265 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1266 1267 if (!ocelot_port) 1268 continue; 1269 1270 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1271 ocelot_port->bridge == bridge) 1272 mask |= BIT(port); 1273 } 1274 1275 return mask; 1276 } 1277 1278 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1279 { 1280 u32 mask = 0; 1281 int port; 1282 1283 for (port = 0; port < ocelot->num_phys_ports; port++) { 1284 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1285 1286 if (!ocelot_port) 1287 continue; 1288 1289 if (ocelot_port->is_dsa_8021q_cpu) 1290 mask |= BIT(port); 1291 } 1292 1293 return mask; 1294 } 1295 1296 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1297 { 1298 unsigned long cpu_fwd_mask; 1299 int port; 1300 1301 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1302 * regular forwarding path of the front ports regardless of whether 1303 * those are bridged or standalone. 1304 * If DSA tag_8021q is not used, this returns 0, which is fine because 1305 * the hardware-based CPU port module can be a destination for packets 1306 * even if it isn't part of PGID_SRC. 1307 */ 1308 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1309 1310 /* Apply FWD mask. The loop is needed to add/remove the current port as 1311 * a source for the other ports. 1312 */ 1313 for (port = 0; port < ocelot->num_phys_ports; port++) { 1314 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1315 unsigned long mask; 1316 1317 if (!ocelot_port) { 1318 /* Unused ports can't send anywhere */ 1319 mask = 0; 1320 } else if (ocelot_port->is_dsa_8021q_cpu) { 1321 /* The DSA tag_8021q CPU ports need to be able to 1322 * forward packets to all other ports except for 1323 * themselves 1324 */ 1325 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1326 mask &= ~cpu_fwd_mask; 1327 } else if (ocelot_port->bridge) { 1328 struct net_device *bridge = ocelot_port->bridge; 1329 struct net_device *bond = ocelot_port->bond; 1330 1331 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge); 1332 mask &= ~BIT(port); 1333 if (bond) { 1334 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1335 false); 1336 } 1337 } else { 1338 /* Standalone ports forward only to DSA tag_8021q CPU 1339 * ports (if those exist), or to the hardware CPU port 1340 * module otherwise. 1341 */ 1342 mask = cpu_fwd_mask; 1343 } 1344 1345 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1346 } 1347 } 1348 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1349 1350 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1351 { 1352 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1353 u32 learn_ena = 0; 1354 1355 ocelot_port->stp_state = state; 1356 1357 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1358 ocelot_port->learn_ena) 1359 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1360 1361 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1362 ANA_PORT_PORT_CFG, port); 1363 1364 ocelot_apply_bridge_fwd_mask(ocelot); 1365 } 1366 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1367 1368 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1369 { 1370 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1371 1372 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1373 * which is clearly not what our intention is. So avoid that. 1374 */ 1375 if (!age_period) 1376 age_period = 1; 1377 1378 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1379 } 1380 EXPORT_SYMBOL(ocelot_set_ageing_time); 1381 1382 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1383 const unsigned char *addr, 1384 u16 vid) 1385 { 1386 struct ocelot_multicast *mc; 1387 1388 list_for_each_entry(mc, &ocelot->multicast, list) { 1389 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1390 return mc; 1391 } 1392 1393 return NULL; 1394 } 1395 1396 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1397 { 1398 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1399 return ENTRYTYPE_MACv4; 1400 if (addr[0] == 0x33 && addr[1] == 0x33) 1401 return ENTRYTYPE_MACv6; 1402 return ENTRYTYPE_LOCKED; 1403 } 1404 1405 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1406 unsigned long ports) 1407 { 1408 struct ocelot_pgid *pgid; 1409 1410 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1411 if (!pgid) 1412 return ERR_PTR(-ENOMEM); 1413 1414 pgid->ports = ports; 1415 pgid->index = index; 1416 refcount_set(&pgid->refcount, 1); 1417 list_add_tail(&pgid->list, &ocelot->pgids); 1418 1419 return pgid; 1420 } 1421 1422 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1423 { 1424 if (!refcount_dec_and_test(&pgid->refcount)) 1425 return; 1426 1427 list_del(&pgid->list); 1428 kfree(pgid); 1429 } 1430 1431 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1432 const struct ocelot_multicast *mc) 1433 { 1434 struct ocelot_pgid *pgid; 1435 int index; 1436 1437 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1438 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1439 * destination mask table (PGID), the destination set is programmed as 1440 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1441 */ 1442 if (mc->entry_type == ENTRYTYPE_MACv4 || 1443 mc->entry_type == ENTRYTYPE_MACv6) 1444 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1445 1446 list_for_each_entry(pgid, &ocelot->pgids, list) { 1447 /* When searching for a nonreserved multicast PGID, ignore the 1448 * dummy PGID of zero that we have for MACv4/MACv6 entries 1449 */ 1450 if (pgid->index && pgid->ports == mc->ports) { 1451 refcount_inc(&pgid->refcount); 1452 return pgid; 1453 } 1454 } 1455 1456 /* Search for a free index in the nonreserved multicast PGID area */ 1457 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1458 bool used = false; 1459 1460 list_for_each_entry(pgid, &ocelot->pgids, list) { 1461 if (pgid->index == index) { 1462 used = true; 1463 break; 1464 } 1465 } 1466 1467 if (!used) 1468 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1469 } 1470 1471 return ERR_PTR(-ENOSPC); 1472 } 1473 1474 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1475 struct ocelot_multicast *mc) 1476 { 1477 ether_addr_copy(addr, mc->addr); 1478 1479 if (mc->entry_type == ENTRYTYPE_MACv4) { 1480 addr[0] = 0; 1481 addr[1] = mc->ports >> 8; 1482 addr[2] = mc->ports & 0xff; 1483 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1484 addr[0] = mc->ports >> 8; 1485 addr[1] = mc->ports & 0xff; 1486 } 1487 } 1488 1489 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1490 const struct switchdev_obj_port_mdb *mdb) 1491 { 1492 unsigned char addr[ETH_ALEN]; 1493 struct ocelot_multicast *mc; 1494 struct ocelot_pgid *pgid; 1495 u16 vid = mdb->vid; 1496 1497 if (port == ocelot->npi) 1498 port = ocelot->num_phys_ports; 1499 1500 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1501 if (!mc) { 1502 /* New entry */ 1503 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1504 if (!mc) 1505 return -ENOMEM; 1506 1507 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1508 ether_addr_copy(mc->addr, mdb->addr); 1509 mc->vid = vid; 1510 1511 list_add_tail(&mc->list, &ocelot->multicast); 1512 } else { 1513 /* Existing entry. Clean up the current port mask from 1514 * hardware now, because we'll be modifying it. 1515 */ 1516 ocelot_pgid_free(ocelot, mc->pgid); 1517 ocelot_encode_ports_to_mdb(addr, mc); 1518 ocelot_mact_forget(ocelot, addr, vid); 1519 } 1520 1521 mc->ports |= BIT(port); 1522 1523 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1524 if (IS_ERR(pgid)) { 1525 dev_err(ocelot->dev, 1526 "Cannot allocate PGID for mdb %pM vid %d\n", 1527 mc->addr, mc->vid); 1528 devm_kfree(ocelot->dev, mc); 1529 return PTR_ERR(pgid); 1530 } 1531 mc->pgid = pgid; 1532 1533 ocelot_encode_ports_to_mdb(addr, mc); 1534 1535 if (mc->entry_type != ENTRYTYPE_MACv4 && 1536 mc->entry_type != ENTRYTYPE_MACv6) 1537 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1538 pgid->index); 1539 1540 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1541 mc->entry_type); 1542 } 1543 EXPORT_SYMBOL(ocelot_port_mdb_add); 1544 1545 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1546 const struct switchdev_obj_port_mdb *mdb) 1547 { 1548 unsigned char addr[ETH_ALEN]; 1549 struct ocelot_multicast *mc; 1550 struct ocelot_pgid *pgid; 1551 u16 vid = mdb->vid; 1552 1553 if (port == ocelot->npi) 1554 port = ocelot->num_phys_ports; 1555 1556 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1557 if (!mc) 1558 return -ENOENT; 1559 1560 ocelot_encode_ports_to_mdb(addr, mc); 1561 ocelot_mact_forget(ocelot, addr, vid); 1562 1563 ocelot_pgid_free(ocelot, mc->pgid); 1564 mc->ports &= ~BIT(port); 1565 if (!mc->ports) { 1566 list_del(&mc->list); 1567 devm_kfree(ocelot->dev, mc); 1568 return 0; 1569 } 1570 1571 /* We have a PGID with fewer ports now */ 1572 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1573 if (IS_ERR(pgid)) 1574 return PTR_ERR(pgid); 1575 mc->pgid = pgid; 1576 1577 ocelot_encode_ports_to_mdb(addr, mc); 1578 1579 if (mc->entry_type != ENTRYTYPE_MACv4 && 1580 mc->entry_type != ENTRYTYPE_MACv6) 1581 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1582 pgid->index); 1583 1584 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1585 mc->entry_type); 1586 } 1587 EXPORT_SYMBOL(ocelot_port_mdb_del); 1588 1589 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1590 struct net_device *bridge) 1591 { 1592 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1593 1594 ocelot_port->bridge = bridge; 1595 1596 ocelot_apply_bridge_fwd_mask(ocelot); 1597 } 1598 EXPORT_SYMBOL(ocelot_port_bridge_join); 1599 1600 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1601 struct net_device *bridge) 1602 { 1603 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1604 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1605 1606 ocelot_port->bridge = NULL; 1607 1608 ocelot_port_set_pvid(ocelot, port, pvid); 1609 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1610 ocelot_apply_bridge_fwd_mask(ocelot); 1611 } 1612 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1613 1614 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1615 { 1616 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1617 int i, port, lag; 1618 1619 /* Reset destination and aggregation PGIDS */ 1620 for_each_unicast_dest_pgid(ocelot, port) 1621 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1622 1623 for_each_aggr_pgid(ocelot, i) 1624 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1625 ANA_PGID_PGID, i); 1626 1627 /* The visited ports bitmask holds the list of ports offloading any 1628 * bonding interface. Initially we mark all these ports as unvisited, 1629 * then every time we visit a port in this bitmask, we know that it is 1630 * the lowest numbered port, i.e. the one whose logical ID == physical 1631 * port ID == LAG ID. So we mark as visited all further ports in the 1632 * bitmask that are offloading the same bonding interface. This way, 1633 * we set up the aggregation PGIDs only once per bonding interface. 1634 */ 1635 for (port = 0; port < ocelot->num_phys_ports; port++) { 1636 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1637 1638 if (!ocelot_port || !ocelot_port->bond) 1639 continue; 1640 1641 visited &= ~BIT(port); 1642 } 1643 1644 /* Now, set PGIDs for each active LAG */ 1645 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1646 struct net_device *bond = ocelot->ports[lag]->bond; 1647 int num_active_ports = 0; 1648 unsigned long bond_mask; 1649 u8 aggr_idx[16]; 1650 1651 if (!bond || (visited & BIT(lag))) 1652 continue; 1653 1654 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1655 1656 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1657 // Destination mask 1658 ocelot_write_rix(ocelot, bond_mask, 1659 ANA_PGID_PGID, port); 1660 aggr_idx[num_active_ports++] = port; 1661 } 1662 1663 for_each_aggr_pgid(ocelot, i) { 1664 u32 ac; 1665 1666 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1667 ac &= ~bond_mask; 1668 /* Don't do division by zero if there was no active 1669 * port. Just make all aggregation codes zero. 1670 */ 1671 if (num_active_ports) 1672 ac |= BIT(aggr_idx[i % num_active_ports]); 1673 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1674 } 1675 1676 /* Mark all ports in the same LAG as visited to avoid applying 1677 * the same config again. 1678 */ 1679 for (port = lag; port < ocelot->num_phys_ports; port++) { 1680 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1681 1682 if (!ocelot_port) 1683 continue; 1684 1685 if (ocelot_port->bond == bond) 1686 visited |= BIT(port); 1687 } 1688 } 1689 } 1690 1691 /* When offloading a bonding interface, the switch ports configured under the 1692 * same bond must have the same logical port ID, equal to the physical port ID 1693 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1694 * bridged mode, each port has a logical port ID equal to its physical port ID. 1695 */ 1696 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1697 { 1698 int port; 1699 1700 for (port = 0; port < ocelot->num_phys_ports; port++) { 1701 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1702 struct net_device *bond; 1703 1704 if (!ocelot_port) 1705 continue; 1706 1707 bond = ocelot_port->bond; 1708 if (bond) { 1709 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1710 false)); 1711 1712 ocelot_rmw_gix(ocelot, 1713 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1714 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1715 ANA_PORT_PORT_CFG, port); 1716 } else { 1717 ocelot_rmw_gix(ocelot, 1718 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1719 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1720 ANA_PORT_PORT_CFG, port); 1721 } 1722 } 1723 } 1724 1725 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1726 struct net_device *bond, 1727 struct netdev_lag_upper_info *info) 1728 { 1729 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1730 return -EOPNOTSUPP; 1731 1732 ocelot->ports[port]->bond = bond; 1733 1734 ocelot_setup_logical_port_ids(ocelot); 1735 ocelot_apply_bridge_fwd_mask(ocelot); 1736 ocelot_set_aggr_pgids(ocelot); 1737 1738 return 0; 1739 } 1740 EXPORT_SYMBOL(ocelot_port_lag_join); 1741 1742 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1743 struct net_device *bond) 1744 { 1745 ocelot->ports[port]->bond = NULL; 1746 1747 ocelot_setup_logical_port_ids(ocelot); 1748 ocelot_apply_bridge_fwd_mask(ocelot); 1749 ocelot_set_aggr_pgids(ocelot); 1750 } 1751 EXPORT_SYMBOL(ocelot_port_lag_leave); 1752 1753 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1754 { 1755 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1756 1757 ocelot_port->lag_tx_active = lag_tx_active; 1758 1759 /* Rebalance the LAGs */ 1760 ocelot_set_aggr_pgids(ocelot); 1761 } 1762 EXPORT_SYMBOL(ocelot_port_lag_change); 1763 1764 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1765 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1766 * In the special case that it's the NPI port that we're configuring, the 1767 * length of the tag and optional prefix needs to be accounted for privately, 1768 * in order to be able to sustain communication at the requested @sdu. 1769 */ 1770 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1771 { 1772 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1773 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1774 int pause_start, pause_stop; 1775 int atop, atop_tot; 1776 1777 if (port == ocelot->npi) { 1778 maxlen += OCELOT_TAG_LEN; 1779 1780 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1781 maxlen += OCELOT_SHORT_PREFIX_LEN; 1782 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1783 maxlen += OCELOT_LONG_PREFIX_LEN; 1784 } 1785 1786 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1787 1788 /* Set Pause watermark hysteresis */ 1789 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1790 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1791 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1792 pause_start); 1793 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1794 pause_stop); 1795 1796 /* Tail dropping watermarks */ 1797 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1798 OCELOT_BUFFER_CELL_SZ; 1799 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1800 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1801 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1802 } 1803 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1804 1805 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1806 { 1807 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1808 1809 if (port == ocelot->npi) { 1810 max_mtu -= OCELOT_TAG_LEN; 1811 1812 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1813 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1814 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1815 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1816 } 1817 1818 return max_mtu; 1819 } 1820 EXPORT_SYMBOL(ocelot_get_max_mtu); 1821 1822 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1823 bool enabled) 1824 { 1825 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1826 u32 val = 0; 1827 1828 if (enabled) 1829 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1830 1831 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1832 ANA_PORT_PORT_CFG, port); 1833 1834 ocelot_port->learn_ena = enabled; 1835 } 1836 1837 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1838 bool enabled) 1839 { 1840 u32 val = 0; 1841 1842 if (enabled) 1843 val = BIT(port); 1844 1845 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1846 } 1847 1848 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1849 bool enabled) 1850 { 1851 u32 val = 0; 1852 1853 if (enabled) 1854 val = BIT(port); 1855 1856 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1857 } 1858 1859 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1860 bool enabled) 1861 { 1862 u32 val = 0; 1863 1864 if (enabled) 1865 val = BIT(port); 1866 1867 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1868 } 1869 1870 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1871 struct switchdev_brport_flags flags) 1872 { 1873 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1874 BR_BCAST_FLOOD)) 1875 return -EINVAL; 1876 1877 return 0; 1878 } 1879 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1880 1881 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1882 struct switchdev_brport_flags flags) 1883 { 1884 if (flags.mask & BR_LEARNING) 1885 ocelot_port_set_learning(ocelot, port, 1886 !!(flags.val & BR_LEARNING)); 1887 1888 if (flags.mask & BR_FLOOD) 1889 ocelot_port_set_ucast_flood(ocelot, port, 1890 !!(flags.val & BR_FLOOD)); 1891 1892 if (flags.mask & BR_MCAST_FLOOD) 1893 ocelot_port_set_mcast_flood(ocelot, port, 1894 !!(flags.val & BR_MCAST_FLOOD)); 1895 1896 if (flags.mask & BR_BCAST_FLOOD) 1897 ocelot_port_set_bcast_flood(ocelot, port, 1898 !!(flags.val & BR_BCAST_FLOOD)); 1899 } 1900 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1901 1902 void ocelot_init_port(struct ocelot *ocelot, int port) 1903 { 1904 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1905 1906 skb_queue_head_init(&ocelot_port->tx_skbs); 1907 spin_lock_init(&ocelot_port->ts_id_lock); 1908 1909 /* Basic L2 initialization */ 1910 1911 /* Set MAC IFG Gaps 1912 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1913 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1914 */ 1915 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1916 DEV_MAC_IFG_CFG); 1917 1918 /* Load seed (0) and set MAC HDX late collision */ 1919 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1920 DEV_MAC_HDX_CFG_SEED_LOAD, 1921 DEV_MAC_HDX_CFG); 1922 mdelay(1); 1923 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1924 DEV_MAC_HDX_CFG); 1925 1926 /* Set Max Length and maximum tags allowed */ 1927 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1928 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1929 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1930 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1931 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1932 DEV_MAC_TAGS_CFG); 1933 1934 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1935 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1936 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1937 1938 /* Enable transmission of pause frames */ 1939 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1940 1941 /* Drop frames with multicast source address */ 1942 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1943 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1944 ANA_PORT_DROP_CFG, port); 1945 1946 /* Set default VLAN and tag type to 8021Q. */ 1947 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1948 REW_PORT_VLAN_CFG_PORT_TPID_M, 1949 REW_PORT_VLAN_CFG, port); 1950 1951 /* Disable source address learning for standalone mode */ 1952 ocelot_port_set_learning(ocelot, port, false); 1953 1954 /* Enable vcap lookups */ 1955 ocelot_vcap_enable(ocelot, port); 1956 } 1957 EXPORT_SYMBOL(ocelot_init_port); 1958 1959 /* Configure and enable the CPU port module, which is a set of queues 1960 * accessible through register MMIO, frame DMA or Ethernet (in case 1961 * NPI mode is used). 1962 */ 1963 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1964 { 1965 int cpu = ocelot->num_phys_ports; 1966 1967 /* The unicast destination PGID for the CPU port module is unused */ 1968 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1969 /* Instead set up a multicast destination PGID for traffic copied to 1970 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1971 * addresses will be copied to the CPU via this PGID. 1972 */ 1973 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1974 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1975 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1976 ANA_PORT_PORT_CFG, cpu); 1977 1978 /* Enable CPU port module */ 1979 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1980 /* CPU port Injection/Extraction configuration */ 1981 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1982 OCELOT_TAG_PREFIX_NONE); 1983 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1984 OCELOT_TAG_PREFIX_NONE); 1985 1986 /* Configure the CPU port to be VLAN aware */ 1987 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1988 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1989 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1990 ANA_PORT_VLAN_CFG, cpu); 1991 } 1992 1993 static void ocelot_detect_features(struct ocelot *ocelot) 1994 { 1995 int mmgt, eq_ctrl; 1996 1997 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 1998 * the number of 240-byte free memory words (aka 4-cell chunks) and not 1999 * 192 bytes as the documentation incorrectly says. 2000 */ 2001 mmgt = ocelot_read(ocelot, SYS_MMGT); 2002 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2003 2004 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2005 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2006 } 2007 2008 int ocelot_init(struct ocelot *ocelot) 2009 { 2010 char queue_name[32]; 2011 int i, ret; 2012 u32 port; 2013 2014 if (ocelot->ops->reset) { 2015 ret = ocelot->ops->reset(ocelot); 2016 if (ret) { 2017 dev_err(ocelot->dev, "Switch reset failed\n"); 2018 return ret; 2019 } 2020 } 2021 2022 ocelot->stats = devm_kcalloc(ocelot->dev, 2023 ocelot->num_phys_ports * ocelot->num_stats, 2024 sizeof(u64), GFP_KERNEL); 2025 if (!ocelot->stats) 2026 return -ENOMEM; 2027 2028 mutex_init(&ocelot->stats_lock); 2029 mutex_init(&ocelot->ptp_lock); 2030 spin_lock_init(&ocelot->ptp_clock_lock); 2031 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2032 dev_name(ocelot->dev)); 2033 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2034 if (!ocelot->stats_queue) 2035 return -ENOMEM; 2036 2037 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2038 if (!ocelot->owq) { 2039 destroy_workqueue(ocelot->stats_queue); 2040 return -ENOMEM; 2041 } 2042 2043 INIT_LIST_HEAD(&ocelot->multicast); 2044 INIT_LIST_HEAD(&ocelot->pgids); 2045 ocelot_detect_features(ocelot); 2046 ocelot_mact_init(ocelot); 2047 ocelot_vlan_init(ocelot); 2048 ocelot_vcap_init(ocelot); 2049 ocelot_cpu_port_init(ocelot); 2050 2051 for (port = 0; port < ocelot->num_phys_ports; port++) { 2052 /* Clear all counters (5 groups) */ 2053 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2054 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2055 SYS_STAT_CFG); 2056 } 2057 2058 /* Only use S-Tag */ 2059 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2060 2061 /* Aggregation mode */ 2062 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2063 ANA_AGGR_CFG_AC_DMAC_ENA | 2064 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2065 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2066 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2067 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2068 ANA_AGGR_CFG); 2069 2070 /* Set MAC age time to default value. The entry is aged after 2071 * 2*AGE_PERIOD 2072 */ 2073 ocelot_write(ocelot, 2074 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2075 ANA_AUTOAGE); 2076 2077 /* Disable learning for frames discarded by VLAN ingress filtering */ 2078 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2079 2080 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2081 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2082 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2083 2084 /* Setup flooding PGIDs */ 2085 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2086 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2087 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2088 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2089 ANA_FLOODING, i); 2090 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2091 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2092 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2093 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2094 ANA_FLOODING_IPMC); 2095 2096 for (port = 0; port < ocelot->num_phys_ports; port++) { 2097 /* Transmit the frame to the local port. */ 2098 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2099 /* Do not forward BPDU frames to the front ports. */ 2100 ocelot_write_gix(ocelot, 2101 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2102 ANA_PORT_CPU_FWD_BPDU_CFG, 2103 port); 2104 /* Ensure bridging is disabled */ 2105 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2106 } 2107 2108 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2109 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2110 2111 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2112 } 2113 2114 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2115 2116 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2117 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2118 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2119 ANA_PGID_PGID, PGID_MC); 2120 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2121 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2122 ANA_PGID_PGID, PGID_BC); 2123 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2124 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2125 2126 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2127 * registers endianness. 2128 */ 2129 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2130 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2131 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2132 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2133 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2134 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2135 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2136 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2137 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2138 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2139 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2140 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2141 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2142 for (i = 0; i < 16; i++) 2143 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2144 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2145 ANA_CPUQ_8021_CFG, i); 2146 2147 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2148 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2149 OCELOT_STATS_CHECK_DELAY); 2150 2151 return 0; 2152 } 2153 EXPORT_SYMBOL(ocelot_init); 2154 2155 void ocelot_deinit(struct ocelot *ocelot) 2156 { 2157 cancel_delayed_work(&ocelot->stats_work); 2158 destroy_workqueue(ocelot->stats_queue); 2159 destroy_workqueue(ocelot->owq); 2160 mutex_destroy(&ocelot->stats_lock); 2161 } 2162 EXPORT_SYMBOL(ocelot_deinit); 2163 2164 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2165 { 2166 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2167 2168 skb_queue_purge(&ocelot_port->tx_skbs); 2169 } 2170 EXPORT_SYMBOL(ocelot_deinit_port); 2171 2172 MODULE_LICENSE("Dual MIT/GPL"); 2173