1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <linux/iopoll.h> 19 #include <net/arp.h> 20 #include <net/netevent.h> 21 #include <net/rtnetlink.h> 22 #include <net/switchdev.h> 23 24 #include "ocelot.h" 25 #include "ocelot_ace.h" 26 27 #define TABLE_UPDATE_SLEEP_US 10 28 #define TABLE_UPDATE_TIMEOUT_US 100000 29 30 /* MAC table entry types. 31 * ENTRYTYPE_NORMAL is subject to aging. 32 * ENTRYTYPE_LOCKED is not subject to aging. 33 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 34 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 35 */ 36 enum macaccess_entry_type { 37 ENTRYTYPE_NORMAL = 0, 38 ENTRYTYPE_LOCKED, 39 ENTRYTYPE_MACv4, 40 ENTRYTYPE_MACv6, 41 }; 42 43 struct ocelot_mact_entry { 44 u8 mac[ETH_ALEN]; 45 u16 vid; 46 enum macaccess_entry_type type; 47 }; 48 49 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 50 { 51 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 52 } 53 54 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 55 { 56 u32 val; 57 58 return readx_poll_timeout(ocelot_mact_read_macaccess, 59 ocelot, val, 60 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 61 MACACCESS_CMD_IDLE, 62 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 63 } 64 65 static void ocelot_mact_select(struct ocelot *ocelot, 66 const unsigned char mac[ETH_ALEN], 67 unsigned int vid) 68 { 69 u32 macl = 0, mach = 0; 70 71 /* Set the MAC address to handle and the vlan associated in a format 72 * understood by the hardware. 73 */ 74 mach |= vid << 16; 75 mach |= mac[0] << 8; 76 mach |= mac[1] << 0; 77 macl |= mac[2] << 24; 78 macl |= mac[3] << 16; 79 macl |= mac[4] << 8; 80 macl |= mac[5] << 0; 81 82 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 83 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 84 85 } 86 87 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 88 const unsigned char mac[ETH_ALEN], 89 unsigned int vid, 90 enum macaccess_entry_type type) 91 { 92 ocelot_mact_select(ocelot, mac, vid); 93 94 /* Issue a write command */ 95 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 96 ANA_TABLES_MACACCESS_DEST_IDX(port) | 97 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 104 static int ocelot_mact_forget(struct ocelot *ocelot, 105 const unsigned char mac[ETH_ALEN], 106 unsigned int vid) 107 { 108 ocelot_mact_select(ocelot, mac, vid); 109 110 /* Issue a forget command */ 111 ocelot_write(ocelot, 112 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 113 ANA_TABLES_MACACCESS); 114 115 return ocelot_mact_wait_for_completion(ocelot); 116 } 117 118 static void ocelot_mact_init(struct ocelot *ocelot) 119 { 120 /* Configure the learning mode entries attributes: 121 * - Do not copy the frame to the CPU extraction queues. 122 * - Use the vlan and mac_cpoy for dmac lookup. 123 */ 124 ocelot_rmw(ocelot, 0, 125 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 126 | ANA_AGENCTRL_LEARN_FWD_KILL 127 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 128 ANA_AGENCTRL); 129 130 /* Clear the MAC table */ 131 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 132 } 133 134 static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port) 135 { 136 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 137 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 138 ANA_PORT_VCAP_S2_CFG, port->chip_port); 139 } 140 141 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 142 { 143 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 144 } 145 146 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 147 { 148 u32 val; 149 150 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 151 ocelot, 152 val, 153 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 154 ANA_TABLES_VLANACCESS_CMD_IDLE, 155 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 156 } 157 158 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 159 { 160 /* Select the VID to configure */ 161 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 162 ANA_TABLES_VLANTIDX); 163 /* Set the vlan port members mask and issue a write command */ 164 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 165 ANA_TABLES_VLANACCESS_CMD_WRITE, 166 ANA_TABLES_VLANACCESS); 167 168 return ocelot_vlant_wait_for_completion(ocelot); 169 } 170 171 static void ocelot_vlan_mode(struct ocelot_port *port, 172 netdev_features_t features) 173 { 174 struct ocelot *ocelot = port->ocelot; 175 u8 p = port->chip_port; 176 u32 val; 177 178 /* Filtering */ 179 val = ocelot_read(ocelot, ANA_VLANMASK); 180 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 181 val |= BIT(p); 182 else 183 val &= ~BIT(p); 184 ocelot_write(ocelot, val, ANA_VLANMASK); 185 } 186 187 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 188 struct ocelot_port *port) 189 { 190 u32 val; 191 192 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 195 if (port->vlan_aware) 196 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 197 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 198 199 ocelot_rmw_gix(ocelot, val, 200 ANA_PORT_VLAN_CFG_VLAN_VID_M | 201 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 202 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 203 ANA_PORT_VLAN_CFG, port->chip_port); 204 205 /* Drop frames with multicast source address */ 206 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 207 if (port->vlan_aware && !port->vid) 208 /* If port is vlan-aware and tagged, drop untagged and priority 209 * tagged frames. 210 */ 211 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 212 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 213 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 214 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 215 216 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 217 val = REW_TAG_CFG_TAG_TPID_CFG(0); 218 219 if (port->vlan_aware) { 220 if (port->vid) 221 /* Tag all frames except when VID == DEFAULT_VLAN */ 222 val |= REW_TAG_CFG_TAG_CFG(1); 223 else 224 /* Tag all frames */ 225 val |= REW_TAG_CFG_TAG_CFG(3); 226 } 227 ocelot_rmw_gix(ocelot, val, 228 REW_TAG_CFG_TAG_TPID_CFG_M | 229 REW_TAG_CFG_TAG_CFG_M, 230 REW_TAG_CFG, port->chip_port); 231 232 /* Set default VLAN and tag type to 8021Q. */ 233 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 234 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 235 ocelot_rmw_gix(ocelot, val, 236 REW_PORT_VLAN_CFG_PORT_TPID_M | 237 REW_PORT_VLAN_CFG_PORT_VID_M, 238 REW_PORT_VLAN_CFG, port->chip_port); 239 } 240 241 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 242 bool untagged) 243 { 244 struct ocelot_port *port = netdev_priv(dev); 245 struct ocelot *ocelot = port->ocelot; 246 int ret; 247 248 /* Add the port MAC address to with the right VLAN information */ 249 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 250 ENTRYTYPE_LOCKED); 251 252 /* Make the port a member of the VLAN */ 253 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 254 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 255 if (ret) 256 return ret; 257 258 /* Default ingress vlan classification */ 259 if (pvid) 260 port->pvid = vid; 261 262 /* Untagged egress vlan clasification */ 263 if (untagged) 264 port->vid = vid; 265 266 ocelot_vlan_port_apply(ocelot, port); 267 268 return 0; 269 } 270 271 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 272 { 273 struct ocelot_port *port = netdev_priv(dev); 274 struct ocelot *ocelot = port->ocelot; 275 int ret; 276 277 /* 8021q removes VID 0 on module unload for all interfaces 278 * with VLAN filtering feature. We need to keep it to receive 279 * untagged traffic. 280 */ 281 if (vid == 0) 282 return 0; 283 284 /* Del the port MAC address to with the right VLAN information */ 285 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 286 287 /* Stop the port from being a member of the vlan */ 288 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 289 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 290 if (ret) 291 return ret; 292 293 /* Ingress */ 294 if (port->pvid == vid) 295 port->pvid = 0; 296 297 /* Egress */ 298 if (port->vid == vid) 299 port->vid = 0; 300 301 ocelot_vlan_port_apply(ocelot, port); 302 303 return 0; 304 } 305 306 static void ocelot_vlan_init(struct ocelot *ocelot) 307 { 308 u16 port, vid; 309 310 /* Clear VLAN table, by default all ports are members of all VLANs */ 311 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 312 ANA_TABLES_VLANACCESS); 313 ocelot_vlant_wait_for_completion(ocelot); 314 315 /* Configure the port VLAN memberships */ 316 for (vid = 1; vid < VLAN_N_VID; vid++) { 317 ocelot->vlan_mask[vid] = 0; 318 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 319 } 320 321 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 322 * traffic. It is added automatically if 8021q module is loaded, but 323 * we can't rely on it since module may be not loaded. 324 */ 325 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 326 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 327 328 /* Configure the CPU port to be VLAN aware */ 329 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 330 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 331 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 332 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 333 334 /* Set vlan ingress filter mask to all ports but the CPU port by 335 * default. 336 */ 337 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 338 339 for (port = 0; port < ocelot->num_phys_ports; port++) { 340 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 341 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 342 } 343 } 344 345 /* Watermark encode 346 * Bit 8: Unit; 0:1, 1:16 347 * Bit 7-0: Value to be multiplied with unit 348 */ 349 static u16 ocelot_wm_enc(u16 value) 350 { 351 if (value >= BIT(8)) 352 return BIT(8) | (value / 16); 353 354 return value; 355 } 356 357 static void ocelot_port_adjust_link(struct net_device *dev) 358 { 359 struct ocelot_port *port = netdev_priv(dev); 360 struct ocelot *ocelot = port->ocelot; 361 u8 p = port->chip_port; 362 int speed, atop_wm, mode = 0; 363 364 switch (dev->phydev->speed) { 365 case SPEED_10: 366 speed = OCELOT_SPEED_10; 367 break; 368 case SPEED_100: 369 speed = OCELOT_SPEED_100; 370 break; 371 case SPEED_1000: 372 speed = OCELOT_SPEED_1000; 373 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 374 break; 375 case SPEED_2500: 376 speed = OCELOT_SPEED_2500; 377 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 378 break; 379 default: 380 netdev_err(dev, "Unsupported PHY speed: %d\n", 381 dev->phydev->speed); 382 return; 383 } 384 385 phy_print_status(dev->phydev); 386 387 if (!dev->phydev->link) 388 return; 389 390 /* Only full duplex supported for now */ 391 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 392 mode, DEV_MAC_MODE_CFG); 393 394 /* Set MAC IFG Gaps 395 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 396 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 397 */ 398 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 399 400 /* Load seed (0) and set MAC HDX late collision */ 401 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 402 DEV_MAC_HDX_CFG_SEED_LOAD, 403 DEV_MAC_HDX_CFG); 404 mdelay(1); 405 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 406 DEV_MAC_HDX_CFG); 407 408 /* Disable HDX fast control */ 409 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 410 411 /* SGMII only for now */ 412 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 413 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 414 415 /* Enable PCS */ 416 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 417 418 /* No aneg on SGMII */ 419 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 420 421 /* No loopback */ 422 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 423 424 /* Set Max Length and maximum tags allowed */ 425 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 426 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 427 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 428 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 429 DEV_MAC_TAGS_CFG); 430 431 /* Enable MAC module */ 432 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 433 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 434 435 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 436 * reset */ 437 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 438 DEV_CLOCK_CFG); 439 440 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 441 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 442 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 443 444 /* No PFC */ 445 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 446 ANA_PFC_PFC_CFG, p); 447 448 /* Set Pause WM hysteresis 449 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 450 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 451 */ 452 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 453 SYS_PAUSE_CFG_PAUSE_STOP(101) | 454 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 455 456 /* Core: Enable port for frame transfer */ 457 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 458 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 459 QSYS_SWITCH_PORT_MODE_PORT_ENA, 460 QSYS_SWITCH_PORT_MODE, p); 461 462 /* Flow control */ 463 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 464 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 465 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 466 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 467 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 468 SYS_MAC_FC_CFG, p); 469 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 470 471 /* Tail dropping watermark */ 472 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 473 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 474 SYS_ATOP, p); 475 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 476 } 477 478 static int ocelot_port_open(struct net_device *dev) 479 { 480 struct ocelot_port *port = netdev_priv(dev); 481 struct ocelot *ocelot = port->ocelot; 482 int err; 483 484 /* Enable receiving frames on the port, and activate auto-learning of 485 * MAC addresses. 486 */ 487 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 488 ANA_PORT_PORT_CFG_RECV_ENA | 489 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 490 ANA_PORT_PORT_CFG, port->chip_port); 491 492 if (port->serdes) { 493 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, 494 port->phy_mode); 495 if (err) { 496 netdev_err(dev, "Could not set mode of SerDes\n"); 497 return err; 498 } 499 } 500 501 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 502 port->phy_mode); 503 if (err) { 504 netdev_err(dev, "Could not attach to PHY\n"); 505 return err; 506 } 507 508 dev->phydev = port->phy; 509 510 phy_attached_info(port->phy); 511 phy_start(port->phy); 512 return 0; 513 } 514 515 static int ocelot_port_stop(struct net_device *dev) 516 { 517 struct ocelot_port *port = netdev_priv(dev); 518 519 phy_disconnect(port->phy); 520 521 dev->phydev = NULL; 522 523 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 524 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 525 QSYS_SWITCH_PORT_MODE, port->chip_port); 526 return 0; 527 } 528 529 /* Generate the IFH for frame injection 530 * 531 * The IFH is a 128bit-value 532 * bit 127: bypass the analyzer processing 533 * bit 56-67: destination mask 534 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 535 * bit 20-27: cpu extraction queue mask 536 * bit 16: tag type 0: C-tag, 1: S-tag 537 * bit 0-11: VID 538 */ 539 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 540 { 541 ifh[0] = IFH_INJ_BYPASS; 542 ifh[1] = (0xf00 & info->port) >> 8; 543 ifh[2] = (0xff & info->port) << 24; 544 ifh[3] = (info->tag_type << 16) | info->vid; 545 546 return 0; 547 } 548 549 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 550 { 551 struct ocelot_port *port = netdev_priv(dev); 552 struct ocelot *ocelot = port->ocelot; 553 u32 val, ifh[IFH_LEN]; 554 struct frame_info info = {}; 555 u8 grp = 0; /* Send everything on CPU group 0 */ 556 unsigned int i, count, last; 557 558 val = ocelot_read(ocelot, QS_INJ_STATUS); 559 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 560 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 561 return NETDEV_TX_BUSY; 562 563 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 564 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 565 566 info.port = BIT(port->chip_port); 567 info.tag_type = IFH_TAG_TYPE_C; 568 info.vid = skb_vlan_tag_get(skb); 569 ocelot_gen_ifh(ifh, &info); 570 571 for (i = 0; i < IFH_LEN; i++) 572 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 573 QS_INJ_WR, grp); 574 575 count = (skb->len + 3) / 4; 576 last = skb->len % 4; 577 for (i = 0; i < count; i++) { 578 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 579 } 580 581 /* Add padding */ 582 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 583 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 584 i++; 585 } 586 587 /* Indicate EOF and valid bytes in last word */ 588 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 589 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 590 QS_INJ_CTRL_EOF, 591 QS_INJ_CTRL, grp); 592 593 /* Add dummy CRC */ 594 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 595 skb_tx_timestamp(skb); 596 597 dev->stats.tx_packets++; 598 dev->stats.tx_bytes += skb->len; 599 dev_kfree_skb_any(skb); 600 601 return NETDEV_TX_OK; 602 } 603 604 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 605 { 606 struct ocelot_port *port = netdev_priv(dev); 607 608 return ocelot_mact_forget(port->ocelot, addr, port->pvid); 609 } 610 611 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 612 { 613 struct ocelot_port *port = netdev_priv(dev); 614 615 return ocelot_mact_learn(port->ocelot, PGID_CPU, addr, port->pvid, 616 ENTRYTYPE_LOCKED); 617 } 618 619 static void ocelot_set_rx_mode(struct net_device *dev) 620 { 621 struct ocelot_port *port = netdev_priv(dev); 622 struct ocelot *ocelot = port->ocelot; 623 int i; 624 u32 val; 625 626 /* This doesn't handle promiscuous mode because the bridge core is 627 * setting IFF_PROMISC on all slave interfaces and all frames would be 628 * forwarded to the CPU port. 629 */ 630 val = GENMASK(ocelot->num_phys_ports - 1, 0); 631 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 632 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 633 634 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 635 } 636 637 static int ocelot_port_get_phys_port_name(struct net_device *dev, 638 char *buf, size_t len) 639 { 640 struct ocelot_port *port = netdev_priv(dev); 641 int ret; 642 643 ret = snprintf(buf, len, "p%d", port->chip_port); 644 if (ret >= len) 645 return -EINVAL; 646 647 return 0; 648 } 649 650 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 651 { 652 struct ocelot_port *port = netdev_priv(dev); 653 struct ocelot *ocelot = port->ocelot; 654 const struct sockaddr *addr = p; 655 656 /* Learn the new net device MAC address in the mac table. */ 657 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 658 ENTRYTYPE_LOCKED); 659 /* Then forget the previous one. */ 660 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 661 662 ether_addr_copy(dev->dev_addr, addr->sa_data); 663 return 0; 664 } 665 666 static void ocelot_get_stats64(struct net_device *dev, 667 struct rtnl_link_stats64 *stats) 668 { 669 struct ocelot_port *port = netdev_priv(dev); 670 struct ocelot *ocelot = port->ocelot; 671 672 /* Configure the port to read the stats from */ 673 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 674 SYS_STAT_CFG); 675 676 /* Get Rx stats */ 677 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 678 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 679 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 680 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 681 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 682 ocelot_read(ocelot, SYS_COUNT_RX_64) + 683 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 684 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 685 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 686 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 687 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 688 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 689 stats->rx_dropped = dev->stats.rx_dropped; 690 691 /* Get Tx stats */ 692 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 693 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 694 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 695 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 696 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 697 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 698 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 699 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 700 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 701 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 702 } 703 704 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 705 struct net_device *dev, const unsigned char *addr, 706 u16 vid, u16 flags, 707 struct netlink_ext_ack *extack) 708 { 709 struct ocelot_port *port = netdev_priv(dev); 710 struct ocelot *ocelot = port->ocelot; 711 712 if (!vid) { 713 if (!port->vlan_aware) 714 /* If the bridge is not VLAN aware and no VID was 715 * provided, set it to pvid to ensure the MAC entry 716 * matches incoming untagged packets 717 */ 718 vid = port->pvid; 719 else 720 /* If the bridge is VLAN aware a VID must be provided as 721 * otherwise the learnt entry wouldn't match any frame. 722 */ 723 return -EINVAL; 724 } 725 726 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 727 ENTRYTYPE_LOCKED); 728 } 729 730 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 731 struct net_device *dev, 732 const unsigned char *addr, u16 vid) 733 { 734 struct ocelot_port *port = netdev_priv(dev); 735 struct ocelot *ocelot = port->ocelot; 736 737 return ocelot_mact_forget(ocelot, addr, vid); 738 } 739 740 struct ocelot_dump_ctx { 741 struct net_device *dev; 742 struct sk_buff *skb; 743 struct netlink_callback *cb; 744 int idx; 745 }; 746 747 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 748 struct ocelot_dump_ctx *dump) 749 { 750 u32 portid = NETLINK_CB(dump->cb->skb).portid; 751 u32 seq = dump->cb->nlh->nlmsg_seq; 752 struct nlmsghdr *nlh; 753 struct ndmsg *ndm; 754 755 if (dump->idx < dump->cb->args[2]) 756 goto skip; 757 758 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 759 sizeof(*ndm), NLM_F_MULTI); 760 if (!nlh) 761 return -EMSGSIZE; 762 763 ndm = nlmsg_data(nlh); 764 ndm->ndm_family = AF_BRIDGE; 765 ndm->ndm_pad1 = 0; 766 ndm->ndm_pad2 = 0; 767 ndm->ndm_flags = NTF_SELF; 768 ndm->ndm_type = 0; 769 ndm->ndm_ifindex = dump->dev->ifindex; 770 ndm->ndm_state = NUD_REACHABLE; 771 772 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 773 goto nla_put_failure; 774 775 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 776 goto nla_put_failure; 777 778 nlmsg_end(dump->skb, nlh); 779 780 skip: 781 dump->idx++; 782 return 0; 783 784 nla_put_failure: 785 nlmsg_cancel(dump->skb, nlh); 786 return -EMSGSIZE; 787 } 788 789 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 790 struct ocelot_mact_entry *entry) 791 { 792 struct ocelot *ocelot = port->ocelot; 793 char mac[ETH_ALEN]; 794 u32 val, dst, macl, mach; 795 796 /* Set row and column to read from */ 797 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 798 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 799 800 /* Issue a read command */ 801 ocelot_write(ocelot, 802 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 803 ANA_TABLES_MACACCESS); 804 805 if (ocelot_mact_wait_for_completion(ocelot)) 806 return -ETIMEDOUT; 807 808 /* Read the entry flags */ 809 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 810 if (!(val & ANA_TABLES_MACACCESS_VALID)) 811 return -EINVAL; 812 813 /* If the entry read has another port configured as its destination, 814 * do not report it. 815 */ 816 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 817 if (dst != port->chip_port) 818 return -EINVAL; 819 820 /* Get the entry's MAC address and VLAN id */ 821 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 822 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 823 824 mac[0] = (mach >> 8) & 0xff; 825 mac[1] = (mach >> 0) & 0xff; 826 mac[2] = (macl >> 24) & 0xff; 827 mac[3] = (macl >> 16) & 0xff; 828 mac[4] = (macl >> 8) & 0xff; 829 mac[5] = (macl >> 0) & 0xff; 830 831 entry->vid = (mach >> 16) & 0xfff; 832 ether_addr_copy(entry->mac, mac); 833 834 return 0; 835 } 836 837 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 838 struct net_device *dev, 839 struct net_device *filter_dev, int *idx) 840 { 841 struct ocelot_port *port = netdev_priv(dev); 842 int i, j, ret = 0; 843 struct ocelot_dump_ctx dump = { 844 .dev = dev, 845 .skb = skb, 846 .cb = cb, 847 .idx = *idx, 848 }; 849 850 struct ocelot_mact_entry entry; 851 852 /* Loop through all the mac tables entries. There are 1024 rows of 4 853 * entries. 854 */ 855 for (i = 0; i < 1024; i++) { 856 for (j = 0; j < 4; j++) { 857 ret = ocelot_mact_read(port, i, j, &entry); 858 /* If the entry is invalid (wrong port, invalid...), 859 * skip it. 860 */ 861 if (ret == -EINVAL) 862 continue; 863 else if (ret) 864 goto end; 865 866 ret = ocelot_fdb_do_dump(&entry, &dump); 867 if (ret) 868 goto end; 869 } 870 } 871 872 end: 873 *idx = dump.idx; 874 return ret; 875 } 876 877 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 878 u16 vid) 879 { 880 return ocelot_vlan_vid_add(dev, vid, false, true); 881 } 882 883 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 884 u16 vid) 885 { 886 return ocelot_vlan_vid_del(dev, vid); 887 } 888 889 static int ocelot_set_features(struct net_device *dev, 890 netdev_features_t features) 891 { 892 struct ocelot_port *port = netdev_priv(dev); 893 netdev_features_t changed = dev->features ^ features; 894 895 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 896 port->tc.offload_cnt) { 897 netdev_err(dev, 898 "Cannot disable HW TC offload while offloads active\n"); 899 return -EBUSY; 900 } 901 902 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 903 ocelot_vlan_mode(port, features); 904 905 return 0; 906 } 907 908 static int ocelot_get_port_parent_id(struct net_device *dev, 909 struct netdev_phys_item_id *ppid) 910 { 911 struct ocelot_port *ocelot_port = netdev_priv(dev); 912 struct ocelot *ocelot = ocelot_port->ocelot; 913 914 ppid->id_len = sizeof(ocelot->base_mac); 915 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 916 917 return 0; 918 } 919 920 static const struct net_device_ops ocelot_port_netdev_ops = { 921 .ndo_open = ocelot_port_open, 922 .ndo_stop = ocelot_port_stop, 923 .ndo_start_xmit = ocelot_port_xmit, 924 .ndo_set_rx_mode = ocelot_set_rx_mode, 925 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 926 .ndo_set_mac_address = ocelot_port_set_mac_address, 927 .ndo_get_stats64 = ocelot_get_stats64, 928 .ndo_fdb_add = ocelot_fdb_add, 929 .ndo_fdb_del = ocelot_fdb_del, 930 .ndo_fdb_dump = ocelot_fdb_dump, 931 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 932 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 933 .ndo_set_features = ocelot_set_features, 934 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 935 .ndo_setup_tc = ocelot_setup_tc, 936 }; 937 938 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 939 { 940 struct ocelot_port *port = netdev_priv(netdev); 941 struct ocelot *ocelot = port->ocelot; 942 int i; 943 944 if (sset != ETH_SS_STATS) 945 return; 946 947 for (i = 0; i < ocelot->num_stats; i++) 948 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 949 ETH_GSTRING_LEN); 950 } 951 952 static void ocelot_update_stats(struct ocelot *ocelot) 953 { 954 int i, j; 955 956 mutex_lock(&ocelot->stats_lock); 957 958 for (i = 0; i < ocelot->num_phys_ports; i++) { 959 /* Configure the port to read the stats from */ 960 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 961 962 for (j = 0; j < ocelot->num_stats; j++) { 963 u32 val; 964 unsigned int idx = i * ocelot->num_stats + j; 965 966 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 967 ocelot->stats_layout[j].offset); 968 969 if (val < (ocelot->stats[idx] & U32_MAX)) 970 ocelot->stats[idx] += (u64)1 << 32; 971 972 ocelot->stats[idx] = (ocelot->stats[idx] & 973 ~(u64)U32_MAX) + val; 974 } 975 } 976 977 mutex_unlock(&ocelot->stats_lock); 978 } 979 980 static void ocelot_check_stats_work(struct work_struct *work) 981 { 982 struct delayed_work *del_work = to_delayed_work(work); 983 struct ocelot *ocelot = container_of(del_work, struct ocelot, 984 stats_work); 985 986 ocelot_update_stats(ocelot); 987 988 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 989 OCELOT_STATS_CHECK_DELAY); 990 } 991 992 static void ocelot_get_ethtool_stats(struct net_device *dev, 993 struct ethtool_stats *stats, u64 *data) 994 { 995 struct ocelot_port *port = netdev_priv(dev); 996 struct ocelot *ocelot = port->ocelot; 997 int i; 998 999 /* check and update now */ 1000 ocelot_update_stats(ocelot); 1001 1002 /* Copy all counters */ 1003 for (i = 0; i < ocelot->num_stats; i++) 1004 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 1005 } 1006 1007 static int ocelot_get_sset_count(struct net_device *dev, int sset) 1008 { 1009 struct ocelot_port *port = netdev_priv(dev); 1010 struct ocelot *ocelot = port->ocelot; 1011 1012 if (sset != ETH_SS_STATS) 1013 return -EOPNOTSUPP; 1014 return ocelot->num_stats; 1015 } 1016 1017 static const struct ethtool_ops ocelot_ethtool_ops = { 1018 .get_strings = ocelot_get_strings, 1019 .get_ethtool_stats = ocelot_get_ethtool_stats, 1020 .get_sset_count = ocelot_get_sset_count, 1021 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1022 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1023 }; 1024 1025 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1026 struct switchdev_trans *trans, 1027 u8 state) 1028 { 1029 struct ocelot *ocelot = ocelot_port->ocelot; 1030 u32 port_cfg; 1031 int port, i; 1032 1033 if (switchdev_trans_ph_prepare(trans)) 1034 return 0; 1035 1036 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1037 return 0; 1038 1039 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1040 ocelot_port->chip_port); 1041 1042 switch (state) { 1043 case BR_STATE_FORWARDING: 1044 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1045 /* Fallthrough */ 1046 case BR_STATE_LEARNING: 1047 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1048 break; 1049 1050 default: 1051 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1052 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1053 break; 1054 } 1055 1056 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1057 ocelot_port->chip_port); 1058 1059 /* Apply FWD mask. The loop is needed to add/remove the current port as 1060 * a source for the other ports. 1061 */ 1062 for (port = 0; port < ocelot->num_phys_ports; port++) { 1063 if (ocelot->bridge_fwd_mask & BIT(port)) { 1064 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1065 1066 for (i = 0; i < ocelot->num_phys_ports; i++) { 1067 unsigned long bond_mask = ocelot->lags[i]; 1068 1069 if (!bond_mask) 1070 continue; 1071 1072 if (bond_mask & BIT(port)) { 1073 mask &= ~bond_mask; 1074 break; 1075 } 1076 } 1077 1078 ocelot_write_rix(ocelot, 1079 BIT(ocelot->num_phys_ports) | mask, 1080 ANA_PGID_PGID, PGID_SRC + port); 1081 } else { 1082 /* Only the CPU port, this is compatible with link 1083 * aggregation. 1084 */ 1085 ocelot_write_rix(ocelot, 1086 BIT(ocelot->num_phys_ports), 1087 ANA_PGID_PGID, PGID_SRC + port); 1088 } 1089 } 1090 1091 return 0; 1092 } 1093 1094 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1095 unsigned long ageing_clock_t) 1096 { 1097 struct ocelot *ocelot = ocelot_port->ocelot; 1098 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1099 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1100 1101 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1102 ANA_AUTOAGE); 1103 } 1104 1105 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1106 { 1107 struct ocelot *ocelot = port->ocelot; 1108 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1109 port->chip_port); 1110 1111 if (mc) 1112 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1113 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1114 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1115 else 1116 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1117 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1118 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1119 1120 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1121 } 1122 1123 static int ocelot_port_attr_set(struct net_device *dev, 1124 const struct switchdev_attr *attr, 1125 struct switchdev_trans *trans) 1126 { 1127 struct ocelot_port *ocelot_port = netdev_priv(dev); 1128 int err = 0; 1129 1130 switch (attr->id) { 1131 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1132 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1133 attr->u.stp_state); 1134 break; 1135 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1136 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1137 break; 1138 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1139 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1140 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1141 break; 1142 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1143 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1144 break; 1145 default: 1146 err = -EOPNOTSUPP; 1147 break; 1148 } 1149 1150 return err; 1151 } 1152 1153 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1154 const struct switchdev_obj_port_vlan *vlan, 1155 struct switchdev_trans *trans) 1156 { 1157 int ret; 1158 u16 vid; 1159 1160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1161 ret = ocelot_vlan_vid_add(dev, vid, 1162 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1163 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1164 if (ret) 1165 return ret; 1166 } 1167 1168 return 0; 1169 } 1170 1171 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1172 const struct switchdev_obj_port_vlan *vlan) 1173 { 1174 int ret; 1175 u16 vid; 1176 1177 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1178 ret = ocelot_vlan_vid_del(dev, vid); 1179 1180 if (ret) 1181 return ret; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1188 const unsigned char *addr, 1189 u16 vid) 1190 { 1191 struct ocelot_multicast *mc; 1192 1193 list_for_each_entry(mc, &ocelot->multicast, list) { 1194 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1195 return mc; 1196 } 1197 1198 return NULL; 1199 } 1200 1201 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1202 const struct switchdev_obj_port_mdb *mdb, 1203 struct switchdev_trans *trans) 1204 { 1205 struct ocelot_port *port = netdev_priv(dev); 1206 struct ocelot *ocelot = port->ocelot; 1207 struct ocelot_multicast *mc; 1208 unsigned char addr[ETH_ALEN]; 1209 u16 vid = mdb->vid; 1210 bool new = false; 1211 1212 if (!vid) 1213 vid = port->pvid; 1214 1215 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1216 if (!mc) { 1217 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1218 if (!mc) 1219 return -ENOMEM; 1220 1221 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1222 mc->vid = vid; 1223 1224 list_add_tail(&mc->list, &ocelot->multicast); 1225 new = true; 1226 } 1227 1228 memcpy(addr, mc->addr, ETH_ALEN); 1229 addr[0] = 0; 1230 1231 if (!new) { 1232 addr[2] = mc->ports << 0; 1233 addr[1] = mc->ports << 8; 1234 ocelot_mact_forget(ocelot, addr, vid); 1235 } 1236 1237 mc->ports |= BIT(port->chip_port); 1238 addr[2] = mc->ports << 0; 1239 addr[1] = mc->ports << 8; 1240 1241 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1242 } 1243 1244 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1245 const struct switchdev_obj_port_mdb *mdb) 1246 { 1247 struct ocelot_port *port = netdev_priv(dev); 1248 struct ocelot *ocelot = port->ocelot; 1249 struct ocelot_multicast *mc; 1250 unsigned char addr[ETH_ALEN]; 1251 u16 vid = mdb->vid; 1252 1253 if (!vid) 1254 vid = port->pvid; 1255 1256 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1257 if (!mc) 1258 return -ENOENT; 1259 1260 memcpy(addr, mc->addr, ETH_ALEN); 1261 addr[2] = mc->ports << 0; 1262 addr[1] = mc->ports << 8; 1263 addr[0] = 0; 1264 ocelot_mact_forget(ocelot, addr, vid); 1265 1266 mc->ports &= ~BIT(port->chip_port); 1267 if (!mc->ports) { 1268 list_del(&mc->list); 1269 devm_kfree(ocelot->dev, mc); 1270 return 0; 1271 } 1272 1273 addr[2] = mc->ports << 0; 1274 addr[1] = mc->ports << 8; 1275 1276 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1277 } 1278 1279 static int ocelot_port_obj_add(struct net_device *dev, 1280 const struct switchdev_obj *obj, 1281 struct switchdev_trans *trans, 1282 struct netlink_ext_ack *extack) 1283 { 1284 int ret = 0; 1285 1286 switch (obj->id) { 1287 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1288 ret = ocelot_port_obj_add_vlan(dev, 1289 SWITCHDEV_OBJ_PORT_VLAN(obj), 1290 trans); 1291 break; 1292 case SWITCHDEV_OBJ_ID_PORT_MDB: 1293 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1294 trans); 1295 break; 1296 default: 1297 return -EOPNOTSUPP; 1298 } 1299 1300 return ret; 1301 } 1302 1303 static int ocelot_port_obj_del(struct net_device *dev, 1304 const struct switchdev_obj *obj) 1305 { 1306 int ret = 0; 1307 1308 switch (obj->id) { 1309 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1310 ret = ocelot_port_vlan_del_vlan(dev, 1311 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1312 break; 1313 case SWITCHDEV_OBJ_ID_PORT_MDB: 1314 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1315 break; 1316 default: 1317 return -EOPNOTSUPP; 1318 } 1319 1320 return ret; 1321 } 1322 1323 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1324 struct net_device *bridge) 1325 { 1326 struct ocelot *ocelot = ocelot_port->ocelot; 1327 1328 if (!ocelot->bridge_mask) { 1329 ocelot->hw_bridge_dev = bridge; 1330 } else { 1331 if (ocelot->hw_bridge_dev != bridge) 1332 /* This is adding the port to a second bridge, this is 1333 * unsupported */ 1334 return -ENODEV; 1335 } 1336 1337 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1338 1339 return 0; 1340 } 1341 1342 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1343 struct net_device *bridge) 1344 { 1345 struct ocelot *ocelot = ocelot_port->ocelot; 1346 1347 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1348 1349 if (!ocelot->bridge_mask) 1350 ocelot->hw_bridge_dev = NULL; 1351 1352 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1353 ocelot_port->vlan_aware = 0; 1354 ocelot_port->pvid = 0; 1355 ocelot_port->vid = 0; 1356 } 1357 1358 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1359 { 1360 int i, port, lag; 1361 1362 /* Reset destination and aggregation PGIDS */ 1363 for (port = 0; port < ocelot->num_phys_ports; port++) 1364 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1365 1366 for (i = PGID_AGGR; i < PGID_SRC; i++) 1367 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1368 ANA_PGID_PGID, i); 1369 1370 /* Now, set PGIDs for each LAG */ 1371 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1372 unsigned long bond_mask; 1373 int aggr_count = 0; 1374 u8 aggr_idx[16]; 1375 1376 bond_mask = ocelot->lags[lag]; 1377 if (!bond_mask) 1378 continue; 1379 1380 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1381 // Destination mask 1382 ocelot_write_rix(ocelot, bond_mask, 1383 ANA_PGID_PGID, port); 1384 aggr_idx[aggr_count] = port; 1385 aggr_count++; 1386 } 1387 1388 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1389 u32 ac; 1390 1391 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1392 ac &= ~bond_mask; 1393 ac |= BIT(aggr_idx[i % aggr_count]); 1394 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1395 } 1396 } 1397 } 1398 1399 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1400 { 1401 unsigned long bond_mask = ocelot->lags[lag]; 1402 unsigned int p; 1403 1404 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1405 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1406 1407 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1408 1409 /* Use lag port as logical port for port i */ 1410 ocelot_write_gix(ocelot, port_cfg | 1411 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1412 ANA_PORT_PORT_CFG, p); 1413 } 1414 } 1415 1416 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1417 struct net_device *bond) 1418 { 1419 struct ocelot *ocelot = ocelot_port->ocelot; 1420 int p = ocelot_port->chip_port; 1421 int lag, lp; 1422 struct net_device *ndev; 1423 u32 bond_mask = 0; 1424 1425 rcu_read_lock(); 1426 for_each_netdev_in_bond_rcu(bond, ndev) { 1427 struct ocelot_port *port = netdev_priv(ndev); 1428 1429 bond_mask |= BIT(port->chip_port); 1430 } 1431 rcu_read_unlock(); 1432 1433 lp = __ffs(bond_mask); 1434 1435 /* If the new port is the lowest one, use it as the logical port from 1436 * now on 1437 */ 1438 if (p == lp) { 1439 lag = p; 1440 ocelot->lags[p] = bond_mask; 1441 bond_mask &= ~BIT(p); 1442 if (bond_mask) { 1443 lp = __ffs(bond_mask); 1444 ocelot->lags[lp] = 0; 1445 } 1446 } else { 1447 lag = lp; 1448 ocelot->lags[lp] |= BIT(p); 1449 } 1450 1451 ocelot_setup_lag(ocelot, lag); 1452 ocelot_set_aggr_pgids(ocelot); 1453 1454 return 0; 1455 } 1456 1457 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1458 struct net_device *bond) 1459 { 1460 struct ocelot *ocelot = ocelot_port->ocelot; 1461 int p = ocelot_port->chip_port; 1462 u32 port_cfg; 1463 int i; 1464 1465 /* Remove port from any lag */ 1466 for (i = 0; i < ocelot->num_phys_ports; i++) 1467 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1468 1469 /* if it was the logical port of the lag, move the lag config to the 1470 * next port 1471 */ 1472 if (ocelot->lags[p]) { 1473 int n = __ffs(ocelot->lags[p]); 1474 1475 ocelot->lags[n] = ocelot->lags[p]; 1476 ocelot->lags[p] = 0; 1477 1478 ocelot_setup_lag(ocelot, n); 1479 } 1480 1481 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1482 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1483 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1484 ANA_PORT_PORT_CFG, p); 1485 1486 ocelot_set_aggr_pgids(ocelot); 1487 } 1488 1489 /* Checks if the net_device instance given to us originate from our driver. */ 1490 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1491 { 1492 return dev->netdev_ops == &ocelot_port_netdev_ops; 1493 } 1494 1495 static int ocelot_netdevice_port_event(struct net_device *dev, 1496 unsigned long event, 1497 struct netdev_notifier_changeupper_info *info) 1498 { 1499 struct ocelot_port *ocelot_port = netdev_priv(dev); 1500 int err = 0; 1501 1502 if (!ocelot_netdevice_dev_check(dev)) 1503 return 0; 1504 1505 switch (event) { 1506 case NETDEV_CHANGEUPPER: 1507 if (netif_is_bridge_master(info->upper_dev)) { 1508 if (info->linking) 1509 err = ocelot_port_bridge_join(ocelot_port, 1510 info->upper_dev); 1511 else 1512 ocelot_port_bridge_leave(ocelot_port, 1513 info->upper_dev); 1514 1515 ocelot_vlan_port_apply(ocelot_port->ocelot, 1516 ocelot_port); 1517 } 1518 if (netif_is_lag_master(info->upper_dev)) { 1519 if (info->linking) 1520 err = ocelot_port_lag_join(ocelot_port, 1521 info->upper_dev); 1522 else 1523 ocelot_port_lag_leave(ocelot_port, 1524 info->upper_dev); 1525 } 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 return err; 1532 } 1533 1534 static int ocelot_netdevice_event(struct notifier_block *unused, 1535 unsigned long event, void *ptr) 1536 { 1537 struct netdev_notifier_changeupper_info *info = ptr; 1538 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1539 int ret = 0; 1540 1541 if (event == NETDEV_PRECHANGEUPPER && 1542 netif_is_lag_master(info->upper_dev)) { 1543 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1544 struct netlink_ext_ack *extack; 1545 1546 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1547 extack = netdev_notifier_info_to_extack(&info->info); 1548 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1549 1550 ret = -EINVAL; 1551 goto notify; 1552 } 1553 } 1554 1555 if (netif_is_lag_master(dev)) { 1556 struct net_device *slave; 1557 struct list_head *iter; 1558 1559 netdev_for_each_lower_dev(dev, slave, iter) { 1560 ret = ocelot_netdevice_port_event(slave, event, info); 1561 if (ret) 1562 goto notify; 1563 } 1564 } else { 1565 ret = ocelot_netdevice_port_event(dev, event, info); 1566 } 1567 1568 notify: 1569 return notifier_from_errno(ret); 1570 } 1571 1572 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1573 .notifier_call = ocelot_netdevice_event, 1574 }; 1575 EXPORT_SYMBOL(ocelot_netdevice_nb); 1576 1577 static int ocelot_switchdev_event(struct notifier_block *unused, 1578 unsigned long event, void *ptr) 1579 { 1580 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1581 int err; 1582 1583 switch (event) { 1584 case SWITCHDEV_PORT_ATTR_SET: 1585 err = switchdev_handle_port_attr_set(dev, ptr, 1586 ocelot_netdevice_dev_check, 1587 ocelot_port_attr_set); 1588 return notifier_from_errno(err); 1589 } 1590 1591 return NOTIFY_DONE; 1592 } 1593 1594 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1595 .notifier_call = ocelot_switchdev_event, 1596 }; 1597 EXPORT_SYMBOL(ocelot_switchdev_nb); 1598 1599 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1600 unsigned long event, void *ptr) 1601 { 1602 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1603 int err; 1604 1605 switch (event) { 1606 /* Blocking events. */ 1607 case SWITCHDEV_PORT_OBJ_ADD: 1608 err = switchdev_handle_port_obj_add(dev, ptr, 1609 ocelot_netdevice_dev_check, 1610 ocelot_port_obj_add); 1611 return notifier_from_errno(err); 1612 case SWITCHDEV_PORT_OBJ_DEL: 1613 err = switchdev_handle_port_obj_del(dev, ptr, 1614 ocelot_netdevice_dev_check, 1615 ocelot_port_obj_del); 1616 return notifier_from_errno(err); 1617 case SWITCHDEV_PORT_ATTR_SET: 1618 err = switchdev_handle_port_attr_set(dev, ptr, 1619 ocelot_netdevice_dev_check, 1620 ocelot_port_attr_set); 1621 return notifier_from_errno(err); 1622 } 1623 1624 return NOTIFY_DONE; 1625 } 1626 1627 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1628 .notifier_call = ocelot_switchdev_blocking_event, 1629 }; 1630 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1631 1632 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1633 void __iomem *regs, 1634 struct phy_device *phy) 1635 { 1636 struct ocelot_port *ocelot_port; 1637 struct net_device *dev; 1638 int err; 1639 1640 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1641 if (!dev) 1642 return -ENOMEM; 1643 SET_NETDEV_DEV(dev, ocelot->dev); 1644 ocelot_port = netdev_priv(dev); 1645 ocelot_port->dev = dev; 1646 ocelot_port->ocelot = ocelot; 1647 ocelot_port->regs = regs; 1648 ocelot_port->chip_port = port; 1649 ocelot_port->phy = phy; 1650 ocelot->ports[port] = ocelot_port; 1651 1652 dev->netdev_ops = &ocelot_port_netdev_ops; 1653 dev->ethtool_ops = &ocelot_ethtool_ops; 1654 1655 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 1656 NETIF_F_HW_TC; 1657 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 1658 1659 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1660 dev->dev_addr[ETH_ALEN - 1] += port; 1661 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1662 ENTRYTYPE_LOCKED); 1663 1664 err = register_netdev(dev); 1665 if (err) { 1666 dev_err(ocelot->dev, "register_netdev failed\n"); 1667 goto err_register_netdev; 1668 } 1669 1670 /* Basic L2 initialization */ 1671 ocelot_vlan_port_apply(ocelot, ocelot_port); 1672 1673 /* Enable vcap lookups */ 1674 ocelot_vcap_enable(ocelot, ocelot_port); 1675 1676 return 0; 1677 1678 err_register_netdev: 1679 free_netdev(dev); 1680 return err; 1681 } 1682 EXPORT_SYMBOL(ocelot_probe_port); 1683 1684 int ocelot_init(struct ocelot *ocelot) 1685 { 1686 u32 port; 1687 int i, cpu = ocelot->num_phys_ports; 1688 char queue_name[32]; 1689 1690 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1691 sizeof(u32), GFP_KERNEL); 1692 if (!ocelot->lags) 1693 return -ENOMEM; 1694 1695 ocelot->stats = devm_kcalloc(ocelot->dev, 1696 ocelot->num_phys_ports * ocelot->num_stats, 1697 sizeof(u64), GFP_KERNEL); 1698 if (!ocelot->stats) 1699 return -ENOMEM; 1700 1701 mutex_init(&ocelot->stats_lock); 1702 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1703 dev_name(ocelot->dev)); 1704 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1705 if (!ocelot->stats_queue) 1706 return -ENOMEM; 1707 1708 ocelot_mact_init(ocelot); 1709 ocelot_vlan_init(ocelot); 1710 ocelot_ace_init(ocelot); 1711 1712 for (port = 0; port < ocelot->num_phys_ports; port++) { 1713 /* Clear all counters (5 groups) */ 1714 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1715 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1716 SYS_STAT_CFG); 1717 } 1718 1719 /* Only use S-Tag */ 1720 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1721 1722 /* Aggregation mode */ 1723 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1724 ANA_AGGR_CFG_AC_DMAC_ENA | 1725 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1726 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1727 1728 /* Set MAC age time to default value. The entry is aged after 1729 * 2*AGE_PERIOD 1730 */ 1731 ocelot_write(ocelot, 1732 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1733 ANA_AUTOAGE); 1734 1735 /* Disable learning for frames discarded by VLAN ingress filtering */ 1736 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1737 1738 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1739 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1740 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1741 1742 /* Setup flooding PGIDs */ 1743 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1744 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1745 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1746 ANA_FLOODING, 0); 1747 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1748 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1749 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1750 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1751 ANA_FLOODING_IPMC); 1752 1753 for (port = 0; port < ocelot->num_phys_ports; port++) { 1754 /* Transmit the frame to the local port. */ 1755 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1756 /* Do not forward BPDU frames to the front ports. */ 1757 ocelot_write_gix(ocelot, 1758 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1759 ANA_PORT_CPU_FWD_BPDU_CFG, 1760 port); 1761 /* Ensure bridging is disabled */ 1762 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1763 } 1764 1765 /* Configure and enable the CPU port. */ 1766 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1767 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1768 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1769 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1770 ANA_PORT_PORT_CFG, cpu); 1771 1772 /* Allow broadcast MAC frames. */ 1773 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1774 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1775 1776 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1777 } 1778 ocelot_write_rix(ocelot, 1779 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1780 ANA_PGID_PGID, PGID_MC); 1781 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1782 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1783 1784 /* CPU port Injection/Extraction configuration */ 1785 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1786 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1787 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1788 QSYS_SWITCH_PORT_MODE, cpu); 1789 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1790 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1791 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1792 * registers endianness. 1793 */ 1794 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1795 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1796 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1797 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1798 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1799 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1800 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1801 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1802 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1803 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1804 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1805 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1806 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1807 for (i = 0; i < 16; i++) 1808 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1809 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1810 ANA_CPUQ_8021_CFG, i); 1811 1812 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1813 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1814 OCELOT_STATS_CHECK_DELAY); 1815 return 0; 1816 } 1817 EXPORT_SYMBOL(ocelot_init); 1818 1819 void ocelot_deinit(struct ocelot *ocelot) 1820 { 1821 destroy_workqueue(ocelot->stats_queue); 1822 mutex_destroy(&ocelot->stats_lock); 1823 ocelot_ace_deinit(); 1824 } 1825 EXPORT_SYMBOL(ocelot_deinit); 1826 1827 MODULE_LICENSE("Dual MIT/GPL"); 1828