1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 #define OCELOT_RSV_VLAN_RANGE_START 4000 17 18 struct ocelot_mact_entry { 19 u8 mac[ETH_ALEN]; 20 u16 vid; 21 enum macaccess_entry_type type; 22 }; 23 24 /* Caller must hold &ocelot->mact_lock */ 25 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 26 { 27 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 28 } 29 30 /* Caller must hold &ocelot->mact_lock */ 31 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 32 { 33 u32 val; 34 35 return readx_poll_timeout(ocelot_mact_read_macaccess, 36 ocelot, val, 37 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 38 MACACCESS_CMD_IDLE, 39 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 40 } 41 42 /* Caller must hold &ocelot->mact_lock */ 43 static void ocelot_mact_select(struct ocelot *ocelot, 44 const unsigned char mac[ETH_ALEN], 45 unsigned int vid) 46 { 47 u32 macl = 0, mach = 0; 48 49 /* Set the MAC address to handle and the vlan associated in a format 50 * understood by the hardware. 51 */ 52 mach |= vid << 16; 53 mach |= mac[0] << 8; 54 mach |= mac[1] << 0; 55 macl |= mac[2] << 24; 56 macl |= mac[3] << 16; 57 macl |= mac[4] << 8; 58 macl |= mac[5] << 0; 59 60 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 61 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 62 63 } 64 65 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 66 const unsigned char mac[ETH_ALEN], 67 unsigned int vid, enum macaccess_entry_type type) 68 { 69 u32 cmd = ANA_TABLES_MACACCESS_VALID | 70 ANA_TABLES_MACACCESS_DEST_IDX(port) | 71 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 72 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 73 unsigned int mc_ports; 74 int err; 75 76 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 77 if (type == ENTRYTYPE_MACv4) 78 mc_ports = (mac[1] << 8) | mac[2]; 79 else if (type == ENTRYTYPE_MACv6) 80 mc_ports = (mac[0] << 8) | mac[1]; 81 else 82 mc_ports = 0; 83 84 if (mc_ports & BIT(ocelot->num_phys_ports)) 85 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 86 87 ocelot_mact_select(ocelot, mac, vid); 88 89 /* Issue a write command */ 90 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 91 92 err = ocelot_mact_wait_for_completion(ocelot); 93 94 return err; 95 } 96 97 int ocelot_mact_learn(struct ocelot *ocelot, int port, 98 const unsigned char mac[ETH_ALEN], 99 unsigned int vid, enum macaccess_entry_type type) 100 { 101 int ret; 102 103 mutex_lock(&ocelot->mact_lock); 104 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 105 mutex_unlock(&ocelot->mact_lock); 106 107 return ret; 108 } 109 EXPORT_SYMBOL(ocelot_mact_learn); 110 111 int ocelot_mact_forget(struct ocelot *ocelot, 112 const unsigned char mac[ETH_ALEN], unsigned int vid) 113 { 114 int err; 115 116 mutex_lock(&ocelot->mact_lock); 117 118 ocelot_mact_select(ocelot, mac, vid); 119 120 /* Issue a forget command */ 121 ocelot_write(ocelot, 122 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 123 ANA_TABLES_MACACCESS); 124 125 err = ocelot_mact_wait_for_completion(ocelot); 126 127 mutex_unlock(&ocelot->mact_lock); 128 129 return err; 130 } 131 EXPORT_SYMBOL(ocelot_mact_forget); 132 133 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 134 const unsigned char mac[ETH_ALEN], 135 unsigned int vid, enum macaccess_entry_type *type) 136 { 137 int val; 138 139 mutex_lock(&ocelot->mact_lock); 140 141 ocelot_mact_select(ocelot, mac, vid); 142 143 /* Issue a read command with MACACCESS_VALID=1. */ 144 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 145 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 146 ANA_TABLES_MACACCESS); 147 148 if (ocelot_mact_wait_for_completion(ocelot)) { 149 mutex_unlock(&ocelot->mact_lock); 150 return -ETIMEDOUT; 151 } 152 153 /* Read back the entry flags */ 154 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 155 156 mutex_unlock(&ocelot->mact_lock); 157 158 if (!(val & ANA_TABLES_MACACCESS_VALID)) 159 return -ENOENT; 160 161 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 162 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 163 164 return 0; 165 } 166 EXPORT_SYMBOL(ocelot_mact_lookup); 167 168 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 169 const unsigned char mac[ETH_ALEN], 170 unsigned int vid, 171 enum macaccess_entry_type type, 172 int sfid, int ssid) 173 { 174 int ret; 175 176 mutex_lock(&ocelot->mact_lock); 177 178 ocelot_write(ocelot, 179 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 180 ANA_TABLES_STREAMDATA_SFID(sfid) | 181 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 182 ANA_TABLES_STREAMDATA_SSID(ssid), 183 ANA_TABLES_STREAMDATA); 184 185 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 186 187 mutex_unlock(&ocelot->mact_lock); 188 189 return ret; 190 } 191 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 192 193 static void ocelot_mact_init(struct ocelot *ocelot) 194 { 195 /* Configure the learning mode entries attributes: 196 * - Do not copy the frame to the CPU extraction queues. 197 * - Use the vlan and mac_cpoy for dmac lookup. 198 */ 199 ocelot_rmw(ocelot, 0, 200 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 201 | ANA_AGENCTRL_LEARN_FWD_KILL 202 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 203 ANA_AGENCTRL); 204 205 /* Clear the MAC table. We are not concurrent with anyone, so 206 * holding &ocelot->mact_lock is pointless. 207 */ 208 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 209 } 210 211 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 212 { 213 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 214 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 215 ANA_PORT_VCAP_S2_CFG, port); 216 217 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 218 ANA_PORT_VCAP_CFG, port); 219 220 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG_ES0_EN, 222 REW_PORT_CFG, port); 223 } 224 225 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 226 struct netlink_ext_ack *extack) 227 { 228 struct net_device *bridge = NULL; 229 int port; 230 231 for (port = 0; port < ocelot->num_phys_ports; port++) { 232 struct ocelot_port *ocelot_port = ocelot->ports[port]; 233 234 if (!ocelot_port || !ocelot_port->bridge || 235 !br_vlan_enabled(ocelot_port->bridge)) 236 continue; 237 238 if (!bridge) { 239 bridge = ocelot_port->bridge; 240 continue; 241 } 242 243 if (bridge == ocelot_port->bridge) 244 continue; 245 246 NL_SET_ERR_MSG_MOD(extack, 247 "Only one VLAN-aware bridge is supported"); 248 return -EBUSY; 249 } 250 251 return 0; 252 } 253 254 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 255 { 256 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 257 } 258 259 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 260 { 261 u32 val; 262 263 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 264 ocelot, 265 val, 266 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 267 ANA_TABLES_VLANACCESS_CMD_IDLE, 268 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 269 } 270 271 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 272 { 273 /* Select the VID to configure */ 274 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 275 ANA_TABLES_VLANTIDX); 276 /* Set the vlan port members mask and issue a write command */ 277 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 278 ANA_TABLES_VLANACCESS_CMD_WRITE, 279 ANA_TABLES_VLANACCESS); 280 281 return ocelot_vlant_wait_for_completion(ocelot); 282 } 283 284 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 285 { 286 struct ocelot_bridge_vlan *vlan; 287 int num_untagged = 0; 288 289 list_for_each_entry(vlan, &ocelot->vlans, list) { 290 if (!(vlan->portmask & BIT(port))) 291 continue; 292 293 if (vlan->untagged & BIT(port)) 294 num_untagged++; 295 } 296 297 return num_untagged; 298 } 299 300 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 301 { 302 struct ocelot_bridge_vlan *vlan; 303 int num_tagged = 0; 304 305 list_for_each_entry(vlan, &ocelot->vlans, list) { 306 if (!(vlan->portmask & BIT(port))) 307 continue; 308 309 if (!(vlan->untagged & BIT(port))) 310 num_tagged++; 311 } 312 313 return num_tagged; 314 } 315 316 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 317 * _one_ egress-untagged VLAN (_the_ native VLAN) 318 */ 319 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 320 { 321 return ocelot_port_num_tagged_vlans(ocelot, port) && 322 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 323 } 324 325 static struct ocelot_bridge_vlan * 326 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 327 { 328 struct ocelot_bridge_vlan *vlan; 329 330 list_for_each_entry(vlan, &ocelot->vlans, list) 331 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 332 return vlan; 333 334 return NULL; 335 } 336 337 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 338 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 339 * state of the port. 340 */ 341 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 342 { 343 struct ocelot_port *ocelot_port = ocelot->ports[port]; 344 enum ocelot_port_tag_config tag_cfg; 345 bool uses_native_vlan = false; 346 347 if (ocelot_port->vlan_aware) { 348 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 349 350 if (uses_native_vlan) 351 tag_cfg = OCELOT_PORT_TAG_NATIVE; 352 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 353 tag_cfg = OCELOT_PORT_TAG_DISABLED; 354 else 355 tag_cfg = OCELOT_PORT_TAG_TRUNK; 356 } else { 357 tag_cfg = OCELOT_PORT_TAG_DISABLED; 358 } 359 360 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 361 REW_TAG_CFG_TAG_CFG_M, 362 REW_TAG_CFG, port); 363 364 if (uses_native_vlan) { 365 struct ocelot_bridge_vlan *native_vlan; 366 367 /* Not having a native VLAN is impossible, because 368 * ocelot_port_num_untagged_vlans has returned 1. 369 * So there is no use in checking for NULL here. 370 */ 371 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 372 373 ocelot_rmw_gix(ocelot, 374 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 375 REW_PORT_VLAN_CFG_PORT_VID_M, 376 REW_PORT_VLAN_CFG, port); 377 } 378 } 379 380 int ocelot_bridge_num_find(struct ocelot *ocelot, 381 const struct net_device *bridge) 382 { 383 int port; 384 385 for (port = 0; port < ocelot->num_phys_ports; port++) { 386 struct ocelot_port *ocelot_port = ocelot->ports[port]; 387 388 if (ocelot_port && ocelot_port->bridge == bridge) 389 return ocelot_port->bridge_num; 390 } 391 392 return -1; 393 } 394 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 395 396 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 397 const struct net_device *bridge) 398 { 399 int bridge_num; 400 401 /* Standalone ports use VID 0 */ 402 if (!bridge) 403 return 0; 404 405 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 406 if (WARN_ON(bridge_num < 0)) 407 return 0; 408 409 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 410 return VLAN_N_VID - bridge_num - 1; 411 } 412 413 /* Default vlan to clasify for untagged frames (may be zero) */ 414 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 415 const struct ocelot_bridge_vlan *pvid_vlan) 416 { 417 struct ocelot_port *ocelot_port = ocelot->ports[port]; 418 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 419 u32 val = 0; 420 421 ocelot_port->pvid_vlan = pvid_vlan; 422 423 if (ocelot_port->vlan_aware && pvid_vlan) 424 pvid = pvid_vlan->vid; 425 426 ocelot_rmw_gix(ocelot, 427 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 428 ANA_PORT_VLAN_CFG_VLAN_VID_M, 429 ANA_PORT_VLAN_CFG, port); 430 431 /* If there's no pvid, we should drop not only untagged traffic (which 432 * happens automatically), but also 802.1p traffic which gets 433 * classified to VLAN 0, but that is always in our RX filter, so it 434 * would get accepted were it not for this setting. 435 */ 436 if (!pvid_vlan && ocelot_port->vlan_aware) 437 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 438 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 439 440 ocelot_rmw_gix(ocelot, val, 441 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 442 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 443 ANA_PORT_DROP_CFG, port); 444 } 445 446 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 447 u16 vid) 448 { 449 struct ocelot_bridge_vlan *vlan; 450 451 list_for_each_entry(vlan, &ocelot->vlans, list) 452 if (vlan->vid == vid) 453 return vlan; 454 455 return NULL; 456 } 457 458 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 459 bool untagged) 460 { 461 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 462 unsigned long portmask; 463 int err; 464 465 if (vlan) { 466 portmask = vlan->portmask | BIT(port); 467 468 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 469 if (err) 470 return err; 471 472 vlan->portmask = portmask; 473 /* Bridge VLANs can be overwritten with a different 474 * egress-tagging setting, so make sure to override an untagged 475 * with a tagged VID if that's going on. 476 */ 477 if (untagged) 478 vlan->untagged |= BIT(port); 479 else 480 vlan->untagged &= ~BIT(port); 481 482 return 0; 483 } 484 485 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 486 if (!vlan) 487 return -ENOMEM; 488 489 portmask = BIT(port); 490 491 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 492 if (err) { 493 kfree(vlan); 494 return err; 495 } 496 497 vlan->vid = vid; 498 vlan->portmask = portmask; 499 if (untagged) 500 vlan->untagged = BIT(port); 501 INIT_LIST_HEAD(&vlan->list); 502 list_add_tail(&vlan->list, &ocelot->vlans); 503 504 return 0; 505 } 506 507 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 508 { 509 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 510 unsigned long portmask; 511 int err; 512 513 if (!vlan) 514 return 0; 515 516 portmask = vlan->portmask & ~BIT(port); 517 518 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 519 if (err) 520 return err; 521 522 vlan->portmask = portmask; 523 if (vlan->portmask) 524 return 0; 525 526 list_del(&vlan->list); 527 kfree(vlan); 528 529 return 0; 530 } 531 532 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 533 const struct net_device *bridge) 534 { 535 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 536 537 return ocelot_vlan_member_add(ocelot, port, vid, true); 538 } 539 540 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 541 const struct net_device *bridge) 542 { 543 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 544 545 return ocelot_vlan_member_del(ocelot, port, vid); 546 } 547 548 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 549 bool vlan_aware, struct netlink_ext_ack *extack) 550 { 551 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 552 struct ocelot_port *ocelot_port = ocelot->ports[port]; 553 struct ocelot_vcap_filter *filter; 554 int err; 555 u32 val; 556 557 list_for_each_entry(filter, &block->rules, list) { 558 if (filter->ingress_port_mask & BIT(port) && 559 filter->action.vid_replace_ena) { 560 NL_SET_ERR_MSG_MOD(extack, 561 "Cannot change VLAN state with vlan modify rules active"); 562 return -EBUSY; 563 } 564 } 565 566 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 567 if (err) 568 return err; 569 570 if (vlan_aware) 571 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 572 ocelot_port->bridge); 573 else 574 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 575 ocelot_port->bridge); 576 if (err) 577 return err; 578 579 ocelot_port->vlan_aware = vlan_aware; 580 581 if (vlan_aware) 582 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 583 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 584 else 585 val = 0; 586 ocelot_rmw_gix(ocelot, val, 587 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 588 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 589 ANA_PORT_VLAN_CFG, port); 590 591 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 592 ocelot_port_manage_port_tag(ocelot, port); 593 594 return 0; 595 } 596 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 597 598 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 599 bool untagged, struct netlink_ext_ack *extack) 600 { 601 if (untagged) { 602 /* We are adding an egress-tagged VLAN */ 603 if (ocelot_port_uses_native_vlan(ocelot, port)) { 604 NL_SET_ERR_MSG_MOD(extack, 605 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 606 return -EBUSY; 607 } 608 } else { 609 /* We are adding an egress-tagged VLAN */ 610 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 611 NL_SET_ERR_MSG_MOD(extack, 612 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 613 return -EBUSY; 614 } 615 } 616 617 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 618 NL_SET_ERR_MSG_MOD(extack, 619 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 620 return -EBUSY; 621 } 622 623 return 0; 624 } 625 EXPORT_SYMBOL(ocelot_vlan_prepare); 626 627 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 628 bool untagged) 629 { 630 int err; 631 632 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 633 if (err) 634 return err; 635 636 /* Default ingress vlan classification */ 637 if (pvid) 638 ocelot_port_set_pvid(ocelot, port, 639 ocelot_bridge_vlan_find(ocelot, vid)); 640 641 /* Untagged egress vlan clasification */ 642 ocelot_port_manage_port_tag(ocelot, port); 643 644 return 0; 645 } 646 EXPORT_SYMBOL(ocelot_vlan_add); 647 648 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 649 { 650 struct ocelot_port *ocelot_port = ocelot->ports[port]; 651 bool del_pvid = false; 652 int err; 653 654 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 655 del_pvid = true; 656 657 err = ocelot_vlan_member_del(ocelot, port, vid); 658 if (err) 659 return err; 660 661 /* Ingress */ 662 if (del_pvid) 663 ocelot_port_set_pvid(ocelot, port, NULL); 664 665 /* Egress */ 666 ocelot_port_manage_port_tag(ocelot, port); 667 668 return 0; 669 } 670 EXPORT_SYMBOL(ocelot_vlan_del); 671 672 static void ocelot_vlan_init(struct ocelot *ocelot) 673 { 674 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 675 u16 port, vid; 676 677 /* Clear VLAN table, by default all ports are members of all VLANs */ 678 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 679 ANA_TABLES_VLANACCESS); 680 ocelot_vlant_wait_for_completion(ocelot); 681 682 /* Configure the port VLAN memberships */ 683 for (vid = 1; vid < VLAN_N_VID; vid++) 684 ocelot_vlant_set_mask(ocelot, vid, 0); 685 686 /* We need VID 0 to get traffic on standalone ports. 687 * It is added automatically if the 8021q module is loaded, but we 688 * can't rely on that since it might not be. 689 */ 690 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 691 692 /* Set vlan ingress filter mask to all ports but the CPU port by 693 * default. 694 */ 695 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 696 697 for (port = 0; port < ocelot->num_phys_ports; port++) { 698 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 699 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 700 } 701 } 702 703 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 704 { 705 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 706 } 707 708 static int ocelot_port_flush(struct ocelot *ocelot, int port) 709 { 710 unsigned int pause_ena; 711 int err, val; 712 713 /* Disable dequeuing from the egress queues */ 714 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 715 QSYS_PORT_MODE_DEQUEUE_DIS, 716 QSYS_PORT_MODE, port); 717 718 /* Disable flow control */ 719 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 720 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 721 722 /* Disable priority flow control */ 723 ocelot_fields_write(ocelot, port, 724 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 725 726 /* Wait at least the time it takes to receive a frame of maximum length 727 * at the port. 728 * Worst-case delays for 10 kilobyte jumbo frames are: 729 * 8 ms on a 10M port 730 * 800 μs on a 100M port 731 * 80 μs on a 1G port 732 * 32 μs on a 2.5G port 733 */ 734 usleep_range(8000, 10000); 735 736 /* Disable half duplex backpressure. */ 737 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 738 SYS_FRONT_PORT_MODE, port); 739 740 /* Flush the queues associated with the port. */ 741 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 742 REW_PORT_CFG, port); 743 744 /* Enable dequeuing from the egress queues. */ 745 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 746 port); 747 748 /* Wait until flushing is complete. */ 749 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 750 100, 2000000, false, ocelot, port); 751 752 /* Clear flushing again. */ 753 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 754 755 /* Re-enable flow control */ 756 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 757 758 return err; 759 } 760 761 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 762 unsigned int link_an_mode, 763 phy_interface_t interface, 764 unsigned long quirks) 765 { 766 struct ocelot_port *ocelot_port = ocelot->ports[port]; 767 int err; 768 769 ocelot_port->speed = SPEED_UNKNOWN; 770 771 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 772 DEV_MAC_ENA_CFG); 773 774 if (ocelot->ops->cut_through_fwd) { 775 mutex_lock(&ocelot->fwd_domain_lock); 776 ocelot->ops->cut_through_fwd(ocelot); 777 mutex_unlock(&ocelot->fwd_domain_lock); 778 } 779 780 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 781 782 err = ocelot_port_flush(ocelot, port); 783 if (err) 784 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 785 port, err); 786 787 /* Put the port in reset. */ 788 if (interface != PHY_INTERFACE_MODE_QSGMII || 789 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 790 ocelot_port_rmwl(ocelot_port, 791 DEV_CLOCK_CFG_MAC_TX_RST | 792 DEV_CLOCK_CFG_MAC_RX_RST, 793 DEV_CLOCK_CFG_MAC_TX_RST | 794 DEV_CLOCK_CFG_MAC_RX_RST, 795 DEV_CLOCK_CFG); 796 } 797 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 798 799 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 800 struct phy_device *phydev, 801 unsigned int link_an_mode, 802 phy_interface_t interface, 803 int speed, int duplex, 804 bool tx_pause, bool rx_pause, 805 unsigned long quirks) 806 { 807 struct ocelot_port *ocelot_port = ocelot->ports[port]; 808 int mac_speed, mode = 0; 809 u32 mac_fc_cfg; 810 811 ocelot_port->speed = speed; 812 813 /* The MAC might be integrated in systems where the MAC speed is fixed 814 * and it's the PCS who is performing the rate adaptation, so we have 815 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 816 * (which is also its default value). 817 */ 818 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 819 speed == SPEED_1000) { 820 mac_speed = OCELOT_SPEED_1000; 821 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 822 } else if (speed == SPEED_2500) { 823 mac_speed = OCELOT_SPEED_2500; 824 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 825 } else if (speed == SPEED_100) { 826 mac_speed = OCELOT_SPEED_100; 827 } else { 828 mac_speed = OCELOT_SPEED_10; 829 } 830 831 if (duplex == DUPLEX_FULL) 832 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 833 834 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 835 836 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 837 * PORT_RST bits in DEV_CLOCK_CFG. 838 */ 839 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 840 DEV_CLOCK_CFG); 841 842 switch (speed) { 843 case SPEED_10: 844 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 845 break; 846 case SPEED_100: 847 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 848 break; 849 case SPEED_1000: 850 case SPEED_2500: 851 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 852 break; 853 default: 854 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 855 port, speed); 856 return; 857 } 858 859 /* Handle RX pause in all cases, with 2500base-X this is used for rate 860 * adaptation. 861 */ 862 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 863 864 if (tx_pause) 865 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 866 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 867 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 868 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 869 870 /* Flow control. Link speed is only used here to evaluate the time 871 * specification in incoming pause frames. 872 */ 873 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 874 875 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 876 877 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 878 if (port != ocelot->npi) 879 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 880 tx_pause); 881 882 /* Undo the effects of ocelot_phylink_mac_link_down: 883 * enable MAC module 884 */ 885 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 886 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 887 888 /* If the port supports cut-through forwarding, update the masks before 889 * enabling forwarding on the port. 890 */ 891 if (ocelot->ops->cut_through_fwd) { 892 mutex_lock(&ocelot->fwd_domain_lock); 893 ocelot->ops->cut_through_fwd(ocelot); 894 mutex_unlock(&ocelot->fwd_domain_lock); 895 } 896 897 /* Core: Enable port for frame transfer */ 898 ocelot_fields_write(ocelot, port, 899 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 900 } 901 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 902 903 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 904 struct sk_buff *clone) 905 { 906 struct ocelot_port *ocelot_port = ocelot->ports[port]; 907 unsigned long flags; 908 909 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 910 911 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 912 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 913 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 914 return -EBUSY; 915 } 916 917 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 918 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 919 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 920 921 ocelot_port->ts_id++; 922 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 923 ocelot_port->ts_id = 0; 924 925 ocelot_port->ptp_skbs_in_flight++; 926 ocelot->ptp_skbs_in_flight++; 927 928 skb_queue_tail(&ocelot_port->tx_skbs, clone); 929 930 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 931 932 return 0; 933 } 934 935 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 936 unsigned int ptp_class) 937 { 938 struct ptp_header *hdr; 939 u8 msgtype, twostep; 940 941 hdr = ptp_parse_header(skb, ptp_class); 942 if (!hdr) 943 return false; 944 945 msgtype = ptp_get_msgtype(hdr, ptp_class); 946 twostep = hdr->flag_field[0] & 0x2; 947 948 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 949 return true; 950 951 return false; 952 } 953 954 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 955 struct sk_buff *skb, 956 struct sk_buff **clone) 957 { 958 struct ocelot_port *ocelot_port = ocelot->ports[port]; 959 u8 ptp_cmd = ocelot_port->ptp_cmd; 960 unsigned int ptp_class; 961 int err; 962 963 /* Don't do anything if PTP timestamping not enabled */ 964 if (!ptp_cmd) 965 return 0; 966 967 ptp_class = ptp_classify_raw(skb); 968 if (ptp_class == PTP_CLASS_NONE) 969 return -EINVAL; 970 971 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 972 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 973 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 974 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 975 return 0; 976 } 977 978 /* Fall back to two-step timestamping */ 979 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 980 } 981 982 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 983 *clone = skb_clone_sk(skb); 984 if (!(*clone)) 985 return -ENOMEM; 986 987 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 988 if (err) 989 return err; 990 991 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 992 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 993 } 994 995 return 0; 996 } 997 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 998 999 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 1000 struct timespec64 *ts) 1001 { 1002 unsigned long flags; 1003 u32 val; 1004 1005 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1006 1007 /* Read current PTP time to get seconds */ 1008 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1009 1010 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1011 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 1012 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1013 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1014 1015 /* Read packet HW timestamp from FIFO */ 1016 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 1017 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 1018 1019 /* Sec has incremented since the ts was registered */ 1020 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 1021 ts->tv_sec--; 1022 1023 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1024 } 1025 1026 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 1027 { 1028 struct ptp_header *hdr; 1029 1030 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 1031 if (WARN_ON(!hdr)) 1032 return false; 1033 1034 return seqid == ntohs(hdr->sequence_id); 1035 } 1036 1037 void ocelot_get_txtstamp(struct ocelot *ocelot) 1038 { 1039 int budget = OCELOT_PTP_QUEUE_SZ; 1040 1041 while (budget--) { 1042 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 1043 struct skb_shared_hwtstamps shhwtstamps; 1044 u32 val, id, seqid, txport; 1045 struct ocelot_port *port; 1046 struct timespec64 ts; 1047 unsigned long flags; 1048 1049 val = ocelot_read(ocelot, SYS_PTP_STATUS); 1050 1051 /* Check if a timestamp can be retrieved */ 1052 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 1053 break; 1054 1055 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 1056 1057 /* Retrieve the ts ID and Tx port */ 1058 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 1059 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 1060 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 1061 1062 port = ocelot->ports[txport]; 1063 1064 spin_lock(&ocelot->ts_id_lock); 1065 port->ptp_skbs_in_flight--; 1066 ocelot->ptp_skbs_in_flight--; 1067 spin_unlock(&ocelot->ts_id_lock); 1068 1069 /* Retrieve its associated skb */ 1070 try_again: 1071 spin_lock_irqsave(&port->tx_skbs.lock, flags); 1072 1073 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 1074 if (OCELOT_SKB_CB(skb)->ts_id != id) 1075 continue; 1076 __skb_unlink(skb, &port->tx_skbs); 1077 skb_match = skb; 1078 break; 1079 } 1080 1081 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 1082 1083 if (WARN_ON(!skb_match)) 1084 continue; 1085 1086 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 1087 dev_err_ratelimited(ocelot->dev, 1088 "port %d received stale TX timestamp for seqid %d, discarding\n", 1089 txport, seqid); 1090 dev_kfree_skb_any(skb); 1091 goto try_again; 1092 } 1093 1094 /* Get the h/w timestamp */ 1095 ocelot_get_hwtimestamp(ocelot, &ts); 1096 1097 /* Set the timestamp into the skb */ 1098 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1099 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1100 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 1101 1102 /* Next ts */ 1103 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 1104 } 1105 } 1106 EXPORT_SYMBOL(ocelot_get_txtstamp); 1107 1108 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1109 u32 *rval) 1110 { 1111 u32 bytes_valid, val; 1112 1113 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1114 if (val == XTR_NOT_READY) { 1115 if (ifh) 1116 return -EIO; 1117 1118 do { 1119 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1120 } while (val == XTR_NOT_READY); 1121 } 1122 1123 switch (val) { 1124 case XTR_ABORT: 1125 return -EIO; 1126 case XTR_EOF_0: 1127 case XTR_EOF_1: 1128 case XTR_EOF_2: 1129 case XTR_EOF_3: 1130 case XTR_PRUNED: 1131 bytes_valid = XTR_VALID_BYTES(val); 1132 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1133 if (val == XTR_ESCAPE) 1134 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1135 else 1136 *rval = val; 1137 1138 return bytes_valid; 1139 case XTR_ESCAPE: 1140 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1141 1142 return 4; 1143 default: 1144 *rval = val; 1145 1146 return 4; 1147 } 1148 } 1149 1150 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1151 { 1152 int i, err = 0; 1153 1154 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1155 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1156 if (err != 4) 1157 return (err < 0) ? err : -EIO; 1158 } 1159 1160 return 0; 1161 } 1162 1163 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1164 u64 timestamp) 1165 { 1166 struct skb_shared_hwtstamps *shhwtstamps; 1167 u64 tod_in_ns, full_ts_in_ns; 1168 struct timespec64 ts; 1169 1170 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1171 1172 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1173 if ((tod_in_ns & 0xffffffff) < timestamp) 1174 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1175 timestamp; 1176 else 1177 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1178 timestamp; 1179 1180 shhwtstamps = skb_hwtstamps(skb); 1181 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1182 shhwtstamps->hwtstamp = full_ts_in_ns; 1183 } 1184 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1185 1186 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1187 { 1188 u64 timestamp, src_port, len; 1189 u32 xfh[OCELOT_TAG_LEN / 4]; 1190 struct net_device *dev; 1191 struct sk_buff *skb; 1192 int sz, buf_len; 1193 u32 val, *buf; 1194 int err; 1195 1196 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1197 if (err) 1198 return err; 1199 1200 ocelot_xfh_get_src_port(xfh, &src_port); 1201 ocelot_xfh_get_len(xfh, &len); 1202 ocelot_xfh_get_rew_val(xfh, ×tamp); 1203 1204 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1205 return -EINVAL; 1206 1207 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1208 if (!dev) 1209 return -EINVAL; 1210 1211 skb = netdev_alloc_skb(dev, len); 1212 if (unlikely(!skb)) { 1213 netdev_err(dev, "Unable to allocate sk_buff\n"); 1214 return -ENOMEM; 1215 } 1216 1217 buf_len = len - ETH_FCS_LEN; 1218 buf = (u32 *)skb_put(skb, buf_len); 1219 1220 len = 0; 1221 do { 1222 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1223 if (sz < 0) { 1224 err = sz; 1225 goto out_free_skb; 1226 } 1227 *buf++ = val; 1228 len += sz; 1229 } while (len < buf_len); 1230 1231 /* Read the FCS */ 1232 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1233 if (sz < 0) { 1234 err = sz; 1235 goto out_free_skb; 1236 } 1237 1238 /* Update the statistics if part of the FCS was read before */ 1239 len -= ETH_FCS_LEN - sz; 1240 1241 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1242 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1243 *buf = val; 1244 } 1245 1246 if (ocelot->ptp) 1247 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1248 1249 /* Everything we see on an interface that is in the HW bridge 1250 * has already been forwarded. 1251 */ 1252 if (ocelot->ports[src_port]->bridge) 1253 skb->offload_fwd_mark = 1; 1254 1255 skb->protocol = eth_type_trans(skb, dev); 1256 1257 *nskb = skb; 1258 1259 return 0; 1260 1261 out_free_skb: 1262 kfree_skb(skb); 1263 return err; 1264 } 1265 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1266 1267 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1268 { 1269 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1270 1271 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1272 return false; 1273 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1274 return false; 1275 1276 return true; 1277 } 1278 EXPORT_SYMBOL(ocelot_can_inject); 1279 1280 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1281 { 1282 ocelot_ifh_set_bypass(ifh, 1); 1283 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1284 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1285 if (vlan_tag) 1286 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1287 if (rew_op) 1288 ocelot_ifh_set_rew_op(ifh, rew_op); 1289 } 1290 EXPORT_SYMBOL(ocelot_ifh_port_set); 1291 1292 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1293 u32 rew_op, struct sk_buff *skb) 1294 { 1295 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1296 unsigned int i, count, last; 1297 1298 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1299 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1300 1301 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1302 1303 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1304 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1305 1306 count = DIV_ROUND_UP(skb->len, 4); 1307 last = skb->len % 4; 1308 for (i = 0; i < count; i++) 1309 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1310 1311 /* Add padding */ 1312 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1313 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1314 i++; 1315 } 1316 1317 /* Indicate EOF and valid bytes in last word */ 1318 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1319 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1320 QS_INJ_CTRL_EOF, 1321 QS_INJ_CTRL, grp); 1322 1323 /* Add dummy CRC */ 1324 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1325 skb_tx_timestamp(skb); 1326 1327 skb->dev->stats.tx_packets++; 1328 skb->dev->stats.tx_bytes += skb->len; 1329 } 1330 EXPORT_SYMBOL(ocelot_port_inject_frame); 1331 1332 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1333 { 1334 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1335 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1336 } 1337 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1338 1339 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1340 u16 vid, const struct net_device *bridge) 1341 { 1342 int pgid = port; 1343 1344 if (port == ocelot->npi) 1345 pgid = PGID_CPU; 1346 1347 if (!vid) 1348 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1349 1350 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1351 } 1352 EXPORT_SYMBOL(ocelot_fdb_add); 1353 1354 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1355 u16 vid, const struct net_device *bridge) 1356 { 1357 if (!vid) 1358 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1359 1360 return ocelot_mact_forget(ocelot, addr, vid); 1361 } 1362 EXPORT_SYMBOL(ocelot_fdb_del); 1363 1364 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1365 bool is_static, void *data) 1366 { 1367 struct ocelot_dump_ctx *dump = data; 1368 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1369 u32 seq = dump->cb->nlh->nlmsg_seq; 1370 struct nlmsghdr *nlh; 1371 struct ndmsg *ndm; 1372 1373 if (dump->idx < dump->cb->args[2]) 1374 goto skip; 1375 1376 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1377 sizeof(*ndm), NLM_F_MULTI); 1378 if (!nlh) 1379 return -EMSGSIZE; 1380 1381 ndm = nlmsg_data(nlh); 1382 ndm->ndm_family = AF_BRIDGE; 1383 ndm->ndm_pad1 = 0; 1384 ndm->ndm_pad2 = 0; 1385 ndm->ndm_flags = NTF_SELF; 1386 ndm->ndm_type = 0; 1387 ndm->ndm_ifindex = dump->dev->ifindex; 1388 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1389 1390 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1391 goto nla_put_failure; 1392 1393 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1394 goto nla_put_failure; 1395 1396 nlmsg_end(dump->skb, nlh); 1397 1398 skip: 1399 dump->idx++; 1400 return 0; 1401 1402 nla_put_failure: 1403 nlmsg_cancel(dump->skb, nlh); 1404 return -EMSGSIZE; 1405 } 1406 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1407 1408 /* Caller must hold &ocelot->mact_lock */ 1409 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1410 struct ocelot_mact_entry *entry) 1411 { 1412 u32 val, dst, macl, mach; 1413 char mac[ETH_ALEN]; 1414 1415 /* Set row and column to read from */ 1416 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1417 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1418 1419 /* Issue a read command */ 1420 ocelot_write(ocelot, 1421 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1422 ANA_TABLES_MACACCESS); 1423 1424 if (ocelot_mact_wait_for_completion(ocelot)) 1425 return -ETIMEDOUT; 1426 1427 /* Read the entry flags */ 1428 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1429 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1430 return -EINVAL; 1431 1432 /* If the entry read has another port configured as its destination, 1433 * do not report it. 1434 */ 1435 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1436 if (dst != port) 1437 return -EINVAL; 1438 1439 /* Get the entry's MAC address and VLAN id */ 1440 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1441 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1442 1443 mac[0] = (mach >> 8) & 0xff; 1444 mac[1] = (mach >> 0) & 0xff; 1445 mac[2] = (macl >> 24) & 0xff; 1446 mac[3] = (macl >> 16) & 0xff; 1447 mac[4] = (macl >> 8) & 0xff; 1448 mac[5] = (macl >> 0) & 0xff; 1449 1450 entry->vid = (mach >> 16) & 0xfff; 1451 ether_addr_copy(entry->mac, mac); 1452 1453 return 0; 1454 } 1455 1456 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1457 { 1458 int err; 1459 1460 mutex_lock(&ocelot->mact_lock); 1461 1462 /* Program ageing filter for a single port */ 1463 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1464 ANA_ANAGEFIL); 1465 1466 /* Flushing dynamic FDB entries requires two successive age scans */ 1467 ocelot_write(ocelot, 1468 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1469 ANA_TABLES_MACACCESS); 1470 1471 err = ocelot_mact_wait_for_completion(ocelot); 1472 if (err) { 1473 mutex_unlock(&ocelot->mact_lock); 1474 return err; 1475 } 1476 1477 /* And second... */ 1478 ocelot_write(ocelot, 1479 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1480 ANA_TABLES_MACACCESS); 1481 1482 err = ocelot_mact_wait_for_completion(ocelot); 1483 1484 /* Restore ageing filter */ 1485 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1486 1487 mutex_unlock(&ocelot->mact_lock); 1488 1489 return err; 1490 } 1491 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1492 1493 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1494 dsa_fdb_dump_cb_t *cb, void *data) 1495 { 1496 int err = 0; 1497 int i, j; 1498 1499 /* We could take the lock just around ocelot_mact_read, but doing so 1500 * thousands of times in a row seems rather pointless and inefficient. 1501 */ 1502 mutex_lock(&ocelot->mact_lock); 1503 1504 /* Loop through all the mac tables entries. */ 1505 for (i = 0; i < ocelot->num_mact_rows; i++) { 1506 for (j = 0; j < 4; j++) { 1507 struct ocelot_mact_entry entry; 1508 bool is_static; 1509 1510 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1511 /* If the entry is invalid (wrong port, invalid...), 1512 * skip it. 1513 */ 1514 if (err == -EINVAL) 1515 continue; 1516 else if (err) 1517 break; 1518 1519 is_static = (entry.type == ENTRYTYPE_LOCKED); 1520 1521 /* Hide the reserved VLANs used for 1522 * VLAN-unaware bridging. 1523 */ 1524 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1525 entry.vid = 0; 1526 1527 err = cb(entry.mac, entry.vid, is_static, data); 1528 if (err) 1529 break; 1530 } 1531 } 1532 1533 mutex_unlock(&ocelot->mact_lock); 1534 1535 return err; 1536 } 1537 EXPORT_SYMBOL(ocelot_fdb_dump); 1538 1539 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap) 1540 { 1541 trap->key_type = OCELOT_VCAP_KEY_ETYPE; 1542 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588); 1543 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff); 1544 } 1545 1546 static void 1547 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1548 { 1549 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1550 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1551 trap->key.ipv4.proto.mask[0] = 0xff; 1552 trap->key.ipv4.dport.value = PTP_EV_PORT; 1553 trap->key.ipv4.dport.mask = 0xffff; 1554 } 1555 1556 static void 1557 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1558 { 1559 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1560 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1561 trap->key.ipv4.proto.mask[0] = 0xff; 1562 trap->key.ipv6.dport.value = PTP_EV_PORT; 1563 trap->key.ipv6.dport.mask = 0xffff; 1564 } 1565 1566 static void 1567 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1568 { 1569 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1570 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1571 trap->key.ipv4.proto.mask[0] = 0xff; 1572 trap->key.ipv4.dport.value = PTP_GEN_PORT; 1573 trap->key.ipv4.dport.mask = 0xffff; 1574 } 1575 1576 static void 1577 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1578 { 1579 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1580 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1581 trap->key.ipv4.proto.mask[0] = 0xff; 1582 trap->key.ipv6.dport.value = PTP_GEN_PORT; 1583 trap->key.ipv6.dport.mask = 0xffff; 1584 } 1585 1586 int ocelot_trap_add(struct ocelot *ocelot, int port, 1587 unsigned long cookie, bool take_ts, 1588 void (*populate)(struct ocelot_vcap_filter *f)) 1589 { 1590 struct ocelot_vcap_block *block_vcap_is2; 1591 struct ocelot_vcap_filter *trap; 1592 bool new = false; 1593 int err; 1594 1595 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1596 1597 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1598 false); 1599 if (!trap) { 1600 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1601 if (!trap) 1602 return -ENOMEM; 1603 1604 populate(trap); 1605 trap->prio = 1; 1606 trap->id.cookie = cookie; 1607 trap->id.tc_offload = false; 1608 trap->block_id = VCAP_IS2; 1609 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1610 trap->lookup = 0; 1611 trap->action.cpu_copy_ena = true; 1612 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1613 trap->action.port_mask = 0; 1614 trap->take_ts = take_ts; 1615 list_add_tail(&trap->trap_list, &ocelot->traps); 1616 new = true; 1617 } 1618 1619 trap->ingress_port_mask |= BIT(port); 1620 1621 if (new) 1622 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1623 else 1624 err = ocelot_vcap_filter_replace(ocelot, trap); 1625 if (err) { 1626 trap->ingress_port_mask &= ~BIT(port); 1627 if (!trap->ingress_port_mask) { 1628 list_del(&trap->trap_list); 1629 kfree(trap); 1630 } 1631 return err; 1632 } 1633 1634 return 0; 1635 } 1636 1637 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1638 { 1639 struct ocelot_vcap_block *block_vcap_is2; 1640 struct ocelot_vcap_filter *trap; 1641 1642 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1643 1644 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1645 false); 1646 if (!trap) 1647 return 0; 1648 1649 trap->ingress_port_mask &= ~BIT(port); 1650 if (!trap->ingress_port_mask) { 1651 list_del(&trap->trap_list); 1652 1653 return ocelot_vcap_filter_del(ocelot, trap); 1654 } 1655 1656 return ocelot_vcap_filter_replace(ocelot, trap); 1657 } 1658 1659 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port) 1660 { 1661 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot); 1662 1663 return ocelot_trap_add(ocelot, port, l2_cookie, true, 1664 ocelot_populate_l2_ptp_trap_key); 1665 } 1666 1667 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port) 1668 { 1669 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot); 1670 1671 return ocelot_trap_del(ocelot, port, l2_cookie); 1672 } 1673 1674 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port) 1675 { 1676 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot); 1677 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot); 1678 int err; 1679 1680 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, true, 1681 ocelot_populate_ipv4_ptp_event_trap_key); 1682 if (err) 1683 return err; 1684 1685 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, false, 1686 ocelot_populate_ipv4_ptp_general_trap_key); 1687 if (err) 1688 ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1689 1690 return err; 1691 } 1692 1693 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port) 1694 { 1695 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot); 1696 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot); 1697 int err; 1698 1699 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1700 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie); 1701 return err; 1702 } 1703 1704 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port) 1705 { 1706 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot); 1707 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot); 1708 int err; 1709 1710 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, true, 1711 ocelot_populate_ipv6_ptp_event_trap_key); 1712 if (err) 1713 return err; 1714 1715 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, false, 1716 ocelot_populate_ipv6_ptp_general_trap_key); 1717 if (err) 1718 ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1719 1720 return err; 1721 } 1722 1723 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) 1724 { 1725 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot); 1726 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot); 1727 int err; 1728 1729 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1730 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie); 1731 return err; 1732 } 1733 1734 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, 1735 bool l2, bool l4) 1736 { 1737 int err; 1738 1739 if (l2) 1740 err = ocelot_l2_ptp_trap_add(ocelot, port); 1741 else 1742 err = ocelot_l2_ptp_trap_del(ocelot, port); 1743 if (err) 1744 return err; 1745 1746 if (l4) { 1747 err = ocelot_ipv4_ptp_trap_add(ocelot, port); 1748 if (err) 1749 goto err_ipv4; 1750 1751 err = ocelot_ipv6_ptp_trap_add(ocelot, port); 1752 if (err) 1753 goto err_ipv6; 1754 } else { 1755 err = ocelot_ipv4_ptp_trap_del(ocelot, port); 1756 1757 err |= ocelot_ipv6_ptp_trap_del(ocelot, port); 1758 } 1759 if (err) 1760 return err; 1761 1762 return 0; 1763 1764 err_ipv6: 1765 ocelot_ipv4_ptp_trap_del(ocelot, port); 1766 err_ipv4: 1767 if (l2) 1768 ocelot_l2_ptp_trap_del(ocelot, port); 1769 return err; 1770 } 1771 1772 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1773 { 1774 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1775 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1776 } 1777 EXPORT_SYMBOL(ocelot_hwstamp_get); 1778 1779 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1780 { 1781 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1782 bool l2 = false, l4 = false; 1783 struct hwtstamp_config cfg; 1784 int err; 1785 1786 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1787 return -EFAULT; 1788 1789 /* Tx type sanity check */ 1790 switch (cfg.tx_type) { 1791 case HWTSTAMP_TX_ON: 1792 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1793 break; 1794 case HWTSTAMP_TX_ONESTEP_SYNC: 1795 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1796 * need to update the origin time. 1797 */ 1798 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1799 break; 1800 case HWTSTAMP_TX_OFF: 1801 ocelot_port->ptp_cmd = 0; 1802 break; 1803 default: 1804 return -ERANGE; 1805 } 1806 1807 mutex_lock(&ocelot->ptp_lock); 1808 1809 switch (cfg.rx_filter) { 1810 case HWTSTAMP_FILTER_NONE: 1811 break; 1812 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1813 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1814 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1815 l4 = true; 1816 break; 1817 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1818 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1819 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1820 l2 = true; 1821 break; 1822 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1823 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1824 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1825 l2 = true; 1826 l4 = true; 1827 break; 1828 default: 1829 mutex_unlock(&ocelot->ptp_lock); 1830 return -ERANGE; 1831 } 1832 1833 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); 1834 if (err) { 1835 mutex_unlock(&ocelot->ptp_lock); 1836 return err; 1837 } 1838 1839 if (l2 && l4) 1840 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1841 else if (l2) 1842 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1843 else if (l4) 1844 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1845 else 1846 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 1847 1848 /* Commit back the result & save it */ 1849 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1850 mutex_unlock(&ocelot->ptp_lock); 1851 1852 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1853 } 1854 EXPORT_SYMBOL(ocelot_hwstamp_set); 1855 1856 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1857 { 1858 int i; 1859 1860 if (sset != ETH_SS_STATS) 1861 return; 1862 1863 for (i = 0; i < ocelot->num_stats; i++) 1864 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1865 ETH_GSTRING_LEN); 1866 } 1867 EXPORT_SYMBOL(ocelot_get_strings); 1868 1869 /* Caller must hold &ocelot->stats_lock */ 1870 static int ocelot_port_update_stats(struct ocelot *ocelot, int port) 1871 { 1872 unsigned int idx = port * ocelot->num_stats; 1873 struct ocelot_stats_region *region; 1874 int err, j; 1875 1876 /* Configure the port to read the stats from */ 1877 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), SYS_STAT_CFG); 1878 1879 list_for_each_entry(region, &ocelot->stats_regions, node) { 1880 err = ocelot_bulk_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1881 region->offset, region->buf, 1882 region->count); 1883 if (err) 1884 return err; 1885 1886 for (j = 0; j < region->count; j++) { 1887 u64 *stat = &ocelot->stats[idx + j]; 1888 u64 val = region->buf[j]; 1889 1890 if (val < (*stat & U32_MAX)) 1891 *stat += (u64)1 << 32; 1892 1893 *stat = (*stat & ~(u64)U32_MAX) + val; 1894 } 1895 1896 idx += region->count; 1897 } 1898 1899 return err; 1900 } 1901 1902 static void ocelot_check_stats_work(struct work_struct *work) 1903 { 1904 struct delayed_work *del_work = to_delayed_work(work); 1905 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1906 stats_work); 1907 int i, err; 1908 1909 mutex_lock(&ocelot->stats_lock); 1910 for (i = 0; i < ocelot->num_phys_ports; i++) { 1911 err = ocelot_port_update_stats(ocelot, i); 1912 if (err) 1913 break; 1914 } 1915 mutex_unlock(&ocelot->stats_lock); 1916 1917 if (err) 1918 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); 1919 1920 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1921 OCELOT_STATS_CHECK_DELAY); 1922 } 1923 1924 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1925 { 1926 int i, err; 1927 1928 mutex_lock(&ocelot->stats_lock); 1929 1930 /* check and update now */ 1931 err = ocelot_port_update_stats(ocelot, port); 1932 1933 /* Copy all counters */ 1934 for (i = 0; i < ocelot->num_stats; i++) 1935 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1936 1937 mutex_unlock(&ocelot->stats_lock); 1938 1939 if (err) 1940 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); 1941 } 1942 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1943 1944 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1945 { 1946 if (sset != ETH_SS_STATS) 1947 return -EOPNOTSUPP; 1948 1949 return ocelot->num_stats; 1950 } 1951 EXPORT_SYMBOL(ocelot_get_sset_count); 1952 1953 static int ocelot_prepare_stats_regions(struct ocelot *ocelot) 1954 { 1955 struct ocelot_stats_region *region = NULL; 1956 unsigned int last; 1957 int i; 1958 1959 INIT_LIST_HEAD(&ocelot->stats_regions); 1960 1961 for (i = 0; i < ocelot->num_stats; i++) { 1962 if (region && ocelot->stats_layout[i].offset == last + 1) { 1963 region->count++; 1964 } else { 1965 region = devm_kzalloc(ocelot->dev, sizeof(*region), 1966 GFP_KERNEL); 1967 if (!region) 1968 return -ENOMEM; 1969 1970 region->offset = ocelot->stats_layout[i].offset; 1971 region->count = 1; 1972 list_add_tail(®ion->node, &ocelot->stats_regions); 1973 } 1974 1975 last = ocelot->stats_layout[i].offset; 1976 } 1977 1978 list_for_each_entry(region, &ocelot->stats_regions, node) { 1979 region->buf = devm_kcalloc(ocelot->dev, region->count, 1980 sizeof(*region->buf), GFP_KERNEL); 1981 if (!region->buf) 1982 return -ENOMEM; 1983 } 1984 1985 return 0; 1986 } 1987 1988 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1989 struct ethtool_ts_info *info) 1990 { 1991 info->phc_index = ocelot->ptp_clock ? 1992 ptp_clock_index(ocelot->ptp_clock) : -1; 1993 if (info->phc_index == -1) { 1994 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1995 SOF_TIMESTAMPING_RX_SOFTWARE | 1996 SOF_TIMESTAMPING_SOFTWARE; 1997 return 0; 1998 } 1999 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 2000 SOF_TIMESTAMPING_RX_SOFTWARE | 2001 SOF_TIMESTAMPING_SOFTWARE | 2002 SOF_TIMESTAMPING_TX_HARDWARE | 2003 SOF_TIMESTAMPING_RX_HARDWARE | 2004 SOF_TIMESTAMPING_RAW_HARDWARE; 2005 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 2006 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 2007 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 2008 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 2009 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2010 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 2011 2012 return 0; 2013 } 2014 EXPORT_SYMBOL(ocelot_get_ts_info); 2015 2016 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 2017 { 2018 u32 mask = 0; 2019 int port; 2020 2021 lockdep_assert_held(&ocelot->fwd_domain_lock); 2022 2023 for (port = 0; port < ocelot->num_phys_ports; port++) { 2024 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2025 2026 if (!ocelot_port) 2027 continue; 2028 2029 if (ocelot_port->bond == bond) 2030 mask |= BIT(port); 2031 } 2032 2033 return mask; 2034 } 2035 2036 /* The logical port number of a LAG is equal to the lowest numbered physical 2037 * port ID present in that LAG. It may change if that port ever leaves the LAG. 2038 */ 2039 static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 2040 { 2041 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 2042 2043 if (!bond_mask) 2044 return -ENOENT; 2045 2046 return __ffs(bond_mask); 2047 } 2048 2049 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 2050 { 2051 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 2052 const struct net_device *bridge; 2053 u32 mask = 0; 2054 int port; 2055 2056 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 2057 return 0; 2058 2059 bridge = ocelot_port->bridge; 2060 if (!bridge) 2061 return 0; 2062 2063 for (port = 0; port < ocelot->num_phys_ports; port++) { 2064 ocelot_port = ocelot->ports[port]; 2065 2066 if (!ocelot_port) 2067 continue; 2068 2069 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 2070 ocelot_port->bridge == bridge) 2071 mask |= BIT(port); 2072 } 2073 2074 return mask; 2075 } 2076 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 2077 2078 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 2079 { 2080 u32 mask = 0; 2081 int port; 2082 2083 for (port = 0; port < ocelot->num_phys_ports; port++) { 2084 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2085 2086 if (!ocelot_port) 2087 continue; 2088 2089 if (ocelot_port->is_dsa_8021q_cpu) 2090 mask |= BIT(port); 2091 } 2092 2093 return mask; 2094 } 2095 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask); 2096 2097 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 2098 { 2099 unsigned long cpu_fwd_mask; 2100 int port; 2101 2102 lockdep_assert_held(&ocelot->fwd_domain_lock); 2103 2104 /* If cut-through forwarding is supported, update the masks before a 2105 * port joins the forwarding domain, to avoid potential underruns if it 2106 * has the highest speed from the new domain. 2107 */ 2108 if (joining && ocelot->ops->cut_through_fwd) 2109 ocelot->ops->cut_through_fwd(ocelot); 2110 2111 /* If a DSA tag_8021q CPU exists, it needs to be included in the 2112 * regular forwarding path of the front ports regardless of whether 2113 * those are bridged or standalone. 2114 * If DSA tag_8021q is not used, this returns 0, which is fine because 2115 * the hardware-based CPU port module can be a destination for packets 2116 * even if it isn't part of PGID_SRC. 2117 */ 2118 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 2119 2120 /* Apply FWD mask. The loop is needed to add/remove the current port as 2121 * a source for the other ports. 2122 */ 2123 for (port = 0; port < ocelot->num_phys_ports; port++) { 2124 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2125 unsigned long mask; 2126 2127 if (!ocelot_port) { 2128 /* Unused ports can't send anywhere */ 2129 mask = 0; 2130 } else if (ocelot_port->is_dsa_8021q_cpu) { 2131 /* The DSA tag_8021q CPU ports need to be able to 2132 * forward packets to all other ports except for 2133 * themselves 2134 */ 2135 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 2136 mask &= ~cpu_fwd_mask; 2137 } else if (ocelot_port->bridge) { 2138 struct net_device *bond = ocelot_port->bond; 2139 2140 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2141 mask |= cpu_fwd_mask; 2142 mask &= ~BIT(port); 2143 if (bond) 2144 mask &= ~ocelot_get_bond_mask(ocelot, bond); 2145 } else { 2146 /* Standalone ports forward only to DSA tag_8021q CPU 2147 * ports (if those exist), or to the hardware CPU port 2148 * module otherwise. 2149 */ 2150 mask = cpu_fwd_mask; 2151 } 2152 2153 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 2154 } 2155 2156 /* If cut-through forwarding is supported and a port is leaving, there 2157 * is a chance that cut-through was disabled on the other ports due to 2158 * the port which is leaving (it has a higher link speed). We need to 2159 * update the cut-through masks of the remaining ports no earlier than 2160 * after the port has left, to prevent underruns from happening between 2161 * the cut-through update and the forwarding domain update. 2162 */ 2163 if (!joining && ocelot->ops->cut_through_fwd) 2164 ocelot->ops->cut_through_fwd(ocelot); 2165 } 2166 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 2167 2168 void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port) 2169 { 2170 u16 vid; 2171 2172 ocelot->ports[port]->is_dsa_8021q_cpu = true; 2173 2174 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 2175 ocelot_vlan_member_add(ocelot, port, vid, true); 2176 } 2177 EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu); 2178 2179 void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port) 2180 { 2181 u16 vid; 2182 2183 ocelot->ports[port]->is_dsa_8021q_cpu = false; 2184 2185 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 2186 ocelot_vlan_member_del(ocelot, port, vid); 2187 } 2188 EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu); 2189 2190 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 2191 { 2192 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2193 u32 learn_ena = 0; 2194 2195 mutex_lock(&ocelot->fwd_domain_lock); 2196 2197 ocelot_port->stp_state = state; 2198 2199 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 2200 ocelot_port->learn_ena) 2201 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 2202 2203 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 2204 ANA_PORT_PORT_CFG, port); 2205 2206 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 2207 2208 mutex_unlock(&ocelot->fwd_domain_lock); 2209 } 2210 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 2211 2212 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 2213 { 2214 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 2215 2216 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 2217 * which is clearly not what our intention is. So avoid that. 2218 */ 2219 if (!age_period) 2220 age_period = 1; 2221 2222 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 2223 } 2224 EXPORT_SYMBOL(ocelot_set_ageing_time); 2225 2226 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 2227 const unsigned char *addr, 2228 u16 vid) 2229 { 2230 struct ocelot_multicast *mc; 2231 2232 list_for_each_entry(mc, &ocelot->multicast, list) { 2233 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 2234 return mc; 2235 } 2236 2237 return NULL; 2238 } 2239 2240 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 2241 { 2242 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 2243 return ENTRYTYPE_MACv4; 2244 if (addr[0] == 0x33 && addr[1] == 0x33) 2245 return ENTRYTYPE_MACv6; 2246 return ENTRYTYPE_LOCKED; 2247 } 2248 2249 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 2250 unsigned long ports) 2251 { 2252 struct ocelot_pgid *pgid; 2253 2254 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 2255 if (!pgid) 2256 return ERR_PTR(-ENOMEM); 2257 2258 pgid->ports = ports; 2259 pgid->index = index; 2260 refcount_set(&pgid->refcount, 1); 2261 list_add_tail(&pgid->list, &ocelot->pgids); 2262 2263 return pgid; 2264 } 2265 2266 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2267 { 2268 if (!refcount_dec_and_test(&pgid->refcount)) 2269 return; 2270 2271 list_del(&pgid->list); 2272 kfree(pgid); 2273 } 2274 2275 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2276 const struct ocelot_multicast *mc) 2277 { 2278 struct ocelot_pgid *pgid; 2279 int index; 2280 2281 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2282 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2283 * destination mask table (PGID), the destination set is programmed as 2284 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2285 */ 2286 if (mc->entry_type == ENTRYTYPE_MACv4 || 2287 mc->entry_type == ENTRYTYPE_MACv6) 2288 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2289 2290 list_for_each_entry(pgid, &ocelot->pgids, list) { 2291 /* When searching for a nonreserved multicast PGID, ignore the 2292 * dummy PGID of zero that we have for MACv4/MACv6 entries 2293 */ 2294 if (pgid->index && pgid->ports == mc->ports) { 2295 refcount_inc(&pgid->refcount); 2296 return pgid; 2297 } 2298 } 2299 2300 /* Search for a free index in the nonreserved multicast PGID area */ 2301 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2302 bool used = false; 2303 2304 list_for_each_entry(pgid, &ocelot->pgids, list) { 2305 if (pgid->index == index) { 2306 used = true; 2307 break; 2308 } 2309 } 2310 2311 if (!used) 2312 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2313 } 2314 2315 return ERR_PTR(-ENOSPC); 2316 } 2317 2318 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2319 struct ocelot_multicast *mc) 2320 { 2321 ether_addr_copy(addr, mc->addr); 2322 2323 if (mc->entry_type == ENTRYTYPE_MACv4) { 2324 addr[0] = 0; 2325 addr[1] = mc->ports >> 8; 2326 addr[2] = mc->ports & 0xff; 2327 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2328 addr[0] = mc->ports >> 8; 2329 addr[1] = mc->ports & 0xff; 2330 } 2331 } 2332 2333 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2334 const struct switchdev_obj_port_mdb *mdb, 2335 const struct net_device *bridge) 2336 { 2337 unsigned char addr[ETH_ALEN]; 2338 struct ocelot_multicast *mc; 2339 struct ocelot_pgid *pgid; 2340 u16 vid = mdb->vid; 2341 2342 if (port == ocelot->npi) 2343 port = ocelot->num_phys_ports; 2344 2345 if (!vid) 2346 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2347 2348 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2349 if (!mc) { 2350 /* New entry */ 2351 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2352 if (!mc) 2353 return -ENOMEM; 2354 2355 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2356 ether_addr_copy(mc->addr, mdb->addr); 2357 mc->vid = vid; 2358 2359 list_add_tail(&mc->list, &ocelot->multicast); 2360 } else { 2361 /* Existing entry. Clean up the current port mask from 2362 * hardware now, because we'll be modifying it. 2363 */ 2364 ocelot_pgid_free(ocelot, mc->pgid); 2365 ocelot_encode_ports_to_mdb(addr, mc); 2366 ocelot_mact_forget(ocelot, addr, vid); 2367 } 2368 2369 mc->ports |= BIT(port); 2370 2371 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2372 if (IS_ERR(pgid)) { 2373 dev_err(ocelot->dev, 2374 "Cannot allocate PGID for mdb %pM vid %d\n", 2375 mc->addr, mc->vid); 2376 devm_kfree(ocelot->dev, mc); 2377 return PTR_ERR(pgid); 2378 } 2379 mc->pgid = pgid; 2380 2381 ocelot_encode_ports_to_mdb(addr, mc); 2382 2383 if (mc->entry_type != ENTRYTYPE_MACv4 && 2384 mc->entry_type != ENTRYTYPE_MACv6) 2385 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2386 pgid->index); 2387 2388 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2389 mc->entry_type); 2390 } 2391 EXPORT_SYMBOL(ocelot_port_mdb_add); 2392 2393 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2394 const struct switchdev_obj_port_mdb *mdb, 2395 const struct net_device *bridge) 2396 { 2397 unsigned char addr[ETH_ALEN]; 2398 struct ocelot_multicast *mc; 2399 struct ocelot_pgid *pgid; 2400 u16 vid = mdb->vid; 2401 2402 if (port == ocelot->npi) 2403 port = ocelot->num_phys_ports; 2404 2405 if (!vid) 2406 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2407 2408 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2409 if (!mc) 2410 return -ENOENT; 2411 2412 ocelot_encode_ports_to_mdb(addr, mc); 2413 ocelot_mact_forget(ocelot, addr, vid); 2414 2415 ocelot_pgid_free(ocelot, mc->pgid); 2416 mc->ports &= ~BIT(port); 2417 if (!mc->ports) { 2418 list_del(&mc->list); 2419 devm_kfree(ocelot->dev, mc); 2420 return 0; 2421 } 2422 2423 /* We have a PGID with fewer ports now */ 2424 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2425 if (IS_ERR(pgid)) 2426 return PTR_ERR(pgid); 2427 mc->pgid = pgid; 2428 2429 ocelot_encode_ports_to_mdb(addr, mc); 2430 2431 if (mc->entry_type != ENTRYTYPE_MACv4 && 2432 mc->entry_type != ENTRYTYPE_MACv6) 2433 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2434 pgid->index); 2435 2436 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2437 mc->entry_type); 2438 } 2439 EXPORT_SYMBOL(ocelot_port_mdb_del); 2440 2441 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2442 struct net_device *bridge, int bridge_num, 2443 struct netlink_ext_ack *extack) 2444 { 2445 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2446 int err; 2447 2448 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 2449 if (err) 2450 return err; 2451 2452 mutex_lock(&ocelot->fwd_domain_lock); 2453 2454 ocelot_port->bridge = bridge; 2455 ocelot_port->bridge_num = bridge_num; 2456 2457 ocelot_apply_bridge_fwd_mask(ocelot, true); 2458 2459 mutex_unlock(&ocelot->fwd_domain_lock); 2460 2461 if (br_vlan_enabled(bridge)) 2462 return 0; 2463 2464 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 2465 } 2466 EXPORT_SYMBOL(ocelot_port_bridge_join); 2467 2468 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2469 struct net_device *bridge) 2470 { 2471 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2472 2473 mutex_lock(&ocelot->fwd_domain_lock); 2474 2475 if (!br_vlan_enabled(bridge)) 2476 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 2477 2478 ocelot_port->bridge = NULL; 2479 ocelot_port->bridge_num = -1; 2480 2481 ocelot_port_set_pvid(ocelot, port, NULL); 2482 ocelot_port_manage_port_tag(ocelot, port); 2483 ocelot_apply_bridge_fwd_mask(ocelot, false); 2484 2485 mutex_unlock(&ocelot->fwd_domain_lock); 2486 } 2487 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2488 2489 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2490 { 2491 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2492 int i, port, lag; 2493 2494 /* Reset destination and aggregation PGIDS */ 2495 for_each_unicast_dest_pgid(ocelot, port) 2496 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2497 2498 for_each_aggr_pgid(ocelot, i) 2499 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2500 ANA_PGID_PGID, i); 2501 2502 /* The visited ports bitmask holds the list of ports offloading any 2503 * bonding interface. Initially we mark all these ports as unvisited, 2504 * then every time we visit a port in this bitmask, we know that it is 2505 * the lowest numbered port, i.e. the one whose logical ID == physical 2506 * port ID == LAG ID. So we mark as visited all further ports in the 2507 * bitmask that are offloading the same bonding interface. This way, 2508 * we set up the aggregation PGIDs only once per bonding interface. 2509 */ 2510 for (port = 0; port < ocelot->num_phys_ports; port++) { 2511 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2512 2513 if (!ocelot_port || !ocelot_port->bond) 2514 continue; 2515 2516 visited &= ~BIT(port); 2517 } 2518 2519 /* Now, set PGIDs for each active LAG */ 2520 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2521 struct net_device *bond = ocelot->ports[lag]->bond; 2522 int num_active_ports = 0; 2523 unsigned long bond_mask; 2524 u8 aggr_idx[16]; 2525 2526 if (!bond || (visited & BIT(lag))) 2527 continue; 2528 2529 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2530 2531 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2532 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2533 2534 // Destination mask 2535 ocelot_write_rix(ocelot, bond_mask, 2536 ANA_PGID_PGID, port); 2537 2538 if (ocelot_port->lag_tx_active) 2539 aggr_idx[num_active_ports++] = port; 2540 } 2541 2542 for_each_aggr_pgid(ocelot, i) { 2543 u32 ac; 2544 2545 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2546 ac &= ~bond_mask; 2547 /* Don't do division by zero if there was no active 2548 * port. Just make all aggregation codes zero. 2549 */ 2550 if (num_active_ports) 2551 ac |= BIT(aggr_idx[i % num_active_ports]); 2552 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2553 } 2554 2555 /* Mark all ports in the same LAG as visited to avoid applying 2556 * the same config again. 2557 */ 2558 for (port = lag; port < ocelot->num_phys_ports; port++) { 2559 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2560 2561 if (!ocelot_port) 2562 continue; 2563 2564 if (ocelot_port->bond == bond) 2565 visited |= BIT(port); 2566 } 2567 } 2568 } 2569 2570 /* When offloading a bonding interface, the switch ports configured under the 2571 * same bond must have the same logical port ID, equal to the physical port ID 2572 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2573 * bridged mode, each port has a logical port ID equal to its physical port ID. 2574 */ 2575 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2576 { 2577 int port; 2578 2579 for (port = 0; port < ocelot->num_phys_ports; port++) { 2580 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2581 struct net_device *bond; 2582 2583 if (!ocelot_port) 2584 continue; 2585 2586 bond = ocelot_port->bond; 2587 if (bond) { 2588 int lag = ocelot_bond_get_id(ocelot, bond); 2589 2590 ocelot_rmw_gix(ocelot, 2591 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2592 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2593 ANA_PORT_PORT_CFG, port); 2594 } else { 2595 ocelot_rmw_gix(ocelot, 2596 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2597 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2598 ANA_PORT_PORT_CFG, port); 2599 } 2600 } 2601 } 2602 2603 /* Documentation for PORTID_VAL says: 2604 * Logical port number for front port. If port is not a member of a LLAG, 2605 * then PORTID must be set to the physical port number. 2606 * If port is a member of a LLAG, then PORTID must be set to the common 2607 * PORTID_VAL used for all member ports of the LLAG. 2608 * The value must not exceed the number of physical ports on the device. 2609 * 2610 * This means we have little choice but to migrate FDB entries pointing towards 2611 * a logical port when that changes. 2612 */ 2613 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2614 struct net_device *bond, 2615 int lag) 2616 { 2617 struct ocelot_lag_fdb *fdb; 2618 int err; 2619 2620 lockdep_assert_held(&ocelot->fwd_domain_lock); 2621 2622 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2623 if (fdb->bond != bond) 2624 continue; 2625 2626 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2627 if (err) { 2628 dev_err(ocelot->dev, 2629 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2630 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2631 } 2632 2633 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2634 ENTRYTYPE_LOCKED); 2635 if (err) { 2636 dev_err(ocelot->dev, 2637 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2638 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2639 } 2640 } 2641 } 2642 2643 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2644 struct net_device *bond, 2645 struct netdev_lag_upper_info *info) 2646 { 2647 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2648 return -EOPNOTSUPP; 2649 2650 mutex_lock(&ocelot->fwd_domain_lock); 2651 2652 ocelot->ports[port]->bond = bond; 2653 2654 ocelot_setup_logical_port_ids(ocelot); 2655 ocelot_apply_bridge_fwd_mask(ocelot, true); 2656 ocelot_set_aggr_pgids(ocelot); 2657 2658 mutex_unlock(&ocelot->fwd_domain_lock); 2659 2660 return 0; 2661 } 2662 EXPORT_SYMBOL(ocelot_port_lag_join); 2663 2664 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2665 struct net_device *bond) 2666 { 2667 int old_lag_id, new_lag_id; 2668 2669 mutex_lock(&ocelot->fwd_domain_lock); 2670 2671 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2672 2673 ocelot->ports[port]->bond = NULL; 2674 2675 ocelot_setup_logical_port_ids(ocelot); 2676 ocelot_apply_bridge_fwd_mask(ocelot, false); 2677 ocelot_set_aggr_pgids(ocelot); 2678 2679 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2680 2681 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2682 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2683 2684 mutex_unlock(&ocelot->fwd_domain_lock); 2685 } 2686 EXPORT_SYMBOL(ocelot_port_lag_leave); 2687 2688 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2689 { 2690 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2691 2692 mutex_lock(&ocelot->fwd_domain_lock); 2693 2694 ocelot_port->lag_tx_active = lag_tx_active; 2695 2696 /* Rebalance the LAGs */ 2697 ocelot_set_aggr_pgids(ocelot); 2698 2699 mutex_unlock(&ocelot->fwd_domain_lock); 2700 } 2701 EXPORT_SYMBOL(ocelot_port_lag_change); 2702 2703 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2704 const unsigned char *addr, u16 vid, 2705 const struct net_device *bridge) 2706 { 2707 struct ocelot_lag_fdb *fdb; 2708 int lag, err; 2709 2710 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2711 if (!fdb) 2712 return -ENOMEM; 2713 2714 mutex_lock(&ocelot->fwd_domain_lock); 2715 2716 if (!vid) 2717 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2718 2719 ether_addr_copy(fdb->addr, addr); 2720 fdb->vid = vid; 2721 fdb->bond = bond; 2722 2723 lag = ocelot_bond_get_id(ocelot, bond); 2724 2725 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2726 if (err) { 2727 mutex_unlock(&ocelot->fwd_domain_lock); 2728 kfree(fdb); 2729 return err; 2730 } 2731 2732 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2733 mutex_unlock(&ocelot->fwd_domain_lock); 2734 2735 return 0; 2736 } 2737 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2738 2739 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2740 const unsigned char *addr, u16 vid, 2741 const struct net_device *bridge) 2742 { 2743 struct ocelot_lag_fdb *fdb, *tmp; 2744 2745 mutex_lock(&ocelot->fwd_domain_lock); 2746 2747 if (!vid) 2748 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2749 2750 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2751 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2752 fdb->bond != bond) 2753 continue; 2754 2755 ocelot_mact_forget(ocelot, addr, vid); 2756 list_del(&fdb->list); 2757 mutex_unlock(&ocelot->fwd_domain_lock); 2758 kfree(fdb); 2759 2760 return 0; 2761 } 2762 2763 mutex_unlock(&ocelot->fwd_domain_lock); 2764 2765 return -ENOENT; 2766 } 2767 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2768 2769 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2770 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2771 * In the special case that it's the NPI port that we're configuring, the 2772 * length of the tag and optional prefix needs to be accounted for privately, 2773 * in order to be able to sustain communication at the requested @sdu. 2774 */ 2775 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2776 { 2777 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2778 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2779 int pause_start, pause_stop; 2780 int atop, atop_tot; 2781 2782 if (port == ocelot->npi) { 2783 maxlen += OCELOT_TAG_LEN; 2784 2785 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2786 maxlen += OCELOT_SHORT_PREFIX_LEN; 2787 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2788 maxlen += OCELOT_LONG_PREFIX_LEN; 2789 } 2790 2791 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2792 2793 /* Set Pause watermark hysteresis */ 2794 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2795 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2796 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2797 pause_start); 2798 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2799 pause_stop); 2800 2801 /* Tail dropping watermarks */ 2802 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2803 OCELOT_BUFFER_CELL_SZ; 2804 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2805 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2806 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2807 } 2808 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2809 2810 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2811 { 2812 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2813 2814 if (port == ocelot->npi) { 2815 max_mtu -= OCELOT_TAG_LEN; 2816 2817 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2818 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2819 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2820 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2821 } 2822 2823 return max_mtu; 2824 } 2825 EXPORT_SYMBOL(ocelot_get_max_mtu); 2826 2827 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2828 bool enabled) 2829 { 2830 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2831 u32 val = 0; 2832 2833 if (enabled) 2834 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2835 2836 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2837 ANA_PORT_PORT_CFG, port); 2838 2839 ocelot_port->learn_ena = enabled; 2840 } 2841 2842 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2843 bool enabled) 2844 { 2845 u32 val = 0; 2846 2847 if (enabled) 2848 val = BIT(port); 2849 2850 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2851 } 2852 2853 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2854 bool enabled) 2855 { 2856 u32 val = 0; 2857 2858 if (enabled) 2859 val = BIT(port); 2860 2861 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2862 } 2863 2864 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2865 bool enabled) 2866 { 2867 u32 val = 0; 2868 2869 if (enabled) 2870 val = BIT(port); 2871 2872 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2873 } 2874 2875 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2876 struct switchdev_brport_flags flags) 2877 { 2878 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2879 BR_BCAST_FLOOD)) 2880 return -EINVAL; 2881 2882 return 0; 2883 } 2884 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2885 2886 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2887 struct switchdev_brport_flags flags) 2888 { 2889 if (port == ocelot->npi) 2890 port = ocelot->num_phys_ports; 2891 2892 if (flags.mask & BR_LEARNING) 2893 ocelot_port_set_learning(ocelot, port, 2894 !!(flags.val & BR_LEARNING)); 2895 2896 if (flags.mask & BR_FLOOD) 2897 ocelot_port_set_ucast_flood(ocelot, port, 2898 !!(flags.val & BR_FLOOD)); 2899 2900 if (flags.mask & BR_MCAST_FLOOD) 2901 ocelot_port_set_mcast_flood(ocelot, port, 2902 !!(flags.val & BR_MCAST_FLOOD)); 2903 2904 if (flags.mask & BR_BCAST_FLOOD) 2905 ocelot_port_set_bcast_flood(ocelot, port, 2906 !!(flags.val & BR_BCAST_FLOOD)); 2907 } 2908 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2909 2910 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2911 { 2912 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2913 2914 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2915 } 2916 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2917 2918 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2919 { 2920 if (prio >= OCELOT_NUM_TC) 2921 return -ERANGE; 2922 2923 ocelot_rmw_gix(ocelot, 2924 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2925 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2926 ANA_PORT_QOS_CFG, 2927 port); 2928 2929 return 0; 2930 } 2931 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2932 2933 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2934 { 2935 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2936 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2937 2938 /* Return error if DSCP prioritization isn't enabled */ 2939 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2940 return -EOPNOTSUPP; 2941 2942 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2943 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2944 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2945 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2946 } 2947 2948 /* If the DSCP value is not trusted, the QoS classification falls back 2949 * to VLAN PCP or port-based default. 2950 */ 2951 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2952 return -EOPNOTSUPP; 2953 2954 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2955 } 2956 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2957 2958 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2959 { 2960 int mask, val; 2961 2962 if (prio >= OCELOT_NUM_TC) 2963 return -ERANGE; 2964 2965 /* There is at least one app table priority (this one), so we need to 2966 * make sure DSCP prioritization is enabled on the port. 2967 * Also make sure DSCP translation is disabled 2968 * (dcbnl doesn't support it). 2969 */ 2970 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2971 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2972 2973 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2974 ANA_PORT_QOS_CFG, port); 2975 2976 /* Trust this DSCP value and map it to the given QoS class */ 2977 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2978 2979 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2980 2981 return 0; 2982 } 2983 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2984 2985 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2986 { 2987 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2988 int mask, i; 2989 2990 /* During a "dcb app replace" command, the new app table entry will be 2991 * added first, then the old one will be deleted. But the hardware only 2992 * supports one QoS class per DSCP value (duh), so if we blindly delete 2993 * the app table entry for this DSCP value, we end up deleting the 2994 * entry with the new priority. Avoid that by checking whether user 2995 * space wants to delete the priority which is currently configured, or 2996 * something else which is no longer current. 2997 */ 2998 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2999 return 0; 3000 3001 /* Untrust this DSCP value */ 3002 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 3003 3004 for (i = 0; i < 64; i++) { 3005 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 3006 3007 /* There are still app table entries on the port, so we need to 3008 * keep DSCP enabled, nothing to do. 3009 */ 3010 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 3011 return 0; 3012 } 3013 3014 /* Disable DSCP QoS classification if there isn't any trusted 3015 * DSCP value left. 3016 */ 3017 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 3018 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 3019 3020 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 3021 3022 return 0; 3023 } 3024 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 3025 3026 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 3027 struct netlink_ext_ack *extack) 3028 { 3029 struct ocelot_mirror *m = ocelot->mirror; 3030 3031 if (m) { 3032 if (m->to != to) { 3033 NL_SET_ERR_MSG_MOD(extack, 3034 "Mirroring already configured towards different egress port"); 3035 return ERR_PTR(-EBUSY); 3036 } 3037 3038 refcount_inc(&m->refcount); 3039 return m; 3040 } 3041 3042 m = kzalloc(sizeof(*m), GFP_KERNEL); 3043 if (!m) 3044 return ERR_PTR(-ENOMEM); 3045 3046 m->to = to; 3047 refcount_set(&m->refcount, 1); 3048 ocelot->mirror = m; 3049 3050 /* Program the mirror port to hardware */ 3051 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 3052 3053 return m; 3054 } 3055 3056 void ocelot_mirror_put(struct ocelot *ocelot) 3057 { 3058 struct ocelot_mirror *m = ocelot->mirror; 3059 3060 if (!refcount_dec_and_test(&m->refcount)) 3061 return; 3062 3063 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 3064 ocelot->mirror = NULL; 3065 kfree(m); 3066 } 3067 3068 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 3069 bool ingress, struct netlink_ext_ack *extack) 3070 { 3071 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 3072 3073 if (IS_ERR(m)) 3074 return PTR_ERR(m); 3075 3076 if (ingress) { 3077 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 3078 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 3079 ANA_PORT_PORT_CFG, from); 3080 } else { 3081 ocelot_rmw(ocelot, BIT(from), BIT(from), 3082 ANA_EMIRRORPORTS); 3083 } 3084 3085 return 0; 3086 } 3087 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 3088 3089 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 3090 { 3091 if (ingress) { 3092 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 3093 ANA_PORT_PORT_CFG, from); 3094 } else { 3095 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 3096 } 3097 3098 ocelot_mirror_put(ocelot); 3099 } 3100 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 3101 3102 void ocelot_init_port(struct ocelot *ocelot, int port) 3103 { 3104 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3105 3106 skb_queue_head_init(&ocelot_port->tx_skbs); 3107 3108 /* Basic L2 initialization */ 3109 3110 /* Set MAC IFG Gaps 3111 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 3112 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 3113 */ 3114 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 3115 DEV_MAC_IFG_CFG); 3116 3117 /* Load seed (0) and set MAC HDX late collision */ 3118 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 3119 DEV_MAC_HDX_CFG_SEED_LOAD, 3120 DEV_MAC_HDX_CFG); 3121 mdelay(1); 3122 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 3123 DEV_MAC_HDX_CFG); 3124 3125 /* Set Max Length and maximum tags allowed */ 3126 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 3127 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 3128 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 3129 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 3130 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 3131 DEV_MAC_TAGS_CFG); 3132 3133 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 3134 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 3135 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 3136 3137 /* Enable transmission of pause frames */ 3138 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 3139 3140 /* Drop frames with multicast source address */ 3141 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 3142 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 3143 ANA_PORT_DROP_CFG, port); 3144 3145 /* Set default VLAN and tag type to 8021Q. */ 3146 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 3147 REW_PORT_VLAN_CFG_PORT_TPID_M, 3148 REW_PORT_VLAN_CFG, port); 3149 3150 /* Disable source address learning for standalone mode */ 3151 ocelot_port_set_learning(ocelot, port, false); 3152 3153 /* Set the port's initial logical port ID value, enable receiving 3154 * frames on it, and configure the MAC address learning type to 3155 * automatic. 3156 */ 3157 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 3158 ANA_PORT_PORT_CFG_RECV_ENA | 3159 ANA_PORT_PORT_CFG_PORTID_VAL(port), 3160 ANA_PORT_PORT_CFG, port); 3161 3162 /* Enable vcap lookups */ 3163 ocelot_vcap_enable(ocelot, port); 3164 } 3165 EXPORT_SYMBOL(ocelot_init_port); 3166 3167 /* Configure and enable the CPU port module, which is a set of queues 3168 * accessible through register MMIO, frame DMA or Ethernet (in case 3169 * NPI mode is used). 3170 */ 3171 static void ocelot_cpu_port_init(struct ocelot *ocelot) 3172 { 3173 int cpu = ocelot->num_phys_ports; 3174 3175 /* The unicast destination PGID for the CPU port module is unused */ 3176 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 3177 /* Instead set up a multicast destination PGID for traffic copied to 3178 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 3179 * addresses will be copied to the CPU via this PGID. 3180 */ 3181 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 3182 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 3183 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 3184 ANA_PORT_PORT_CFG, cpu); 3185 3186 /* Enable CPU port module */ 3187 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 3188 /* CPU port Injection/Extraction configuration */ 3189 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 3190 OCELOT_TAG_PREFIX_NONE); 3191 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 3192 OCELOT_TAG_PREFIX_NONE); 3193 3194 /* Configure the CPU port to be VLAN aware */ 3195 ocelot_write_gix(ocelot, 3196 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 3197 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 3198 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 3199 ANA_PORT_VLAN_CFG, cpu); 3200 } 3201 3202 static void ocelot_detect_features(struct ocelot *ocelot) 3203 { 3204 int mmgt, eq_ctrl; 3205 3206 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 3207 * the number of 240-byte free memory words (aka 4-cell chunks) and not 3208 * 192 bytes as the documentation incorrectly says. 3209 */ 3210 mmgt = ocelot_read(ocelot, SYS_MMGT); 3211 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 3212 3213 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 3214 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 3215 } 3216 3217 int ocelot_init(struct ocelot *ocelot) 3218 { 3219 char queue_name[32]; 3220 int i, ret; 3221 u32 port; 3222 3223 if (ocelot->ops->reset) { 3224 ret = ocelot->ops->reset(ocelot); 3225 if (ret) { 3226 dev_err(ocelot->dev, "Switch reset failed\n"); 3227 return ret; 3228 } 3229 } 3230 3231 ocelot->stats = devm_kcalloc(ocelot->dev, 3232 ocelot->num_phys_ports * ocelot->num_stats, 3233 sizeof(u64), GFP_KERNEL); 3234 if (!ocelot->stats) 3235 return -ENOMEM; 3236 3237 mutex_init(&ocelot->stats_lock); 3238 mutex_init(&ocelot->ptp_lock); 3239 mutex_init(&ocelot->mact_lock); 3240 mutex_init(&ocelot->fwd_domain_lock); 3241 spin_lock_init(&ocelot->ptp_clock_lock); 3242 spin_lock_init(&ocelot->ts_id_lock); 3243 snprintf(queue_name, sizeof(queue_name), "%s-stats", 3244 dev_name(ocelot->dev)); 3245 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 3246 if (!ocelot->stats_queue) 3247 return -ENOMEM; 3248 3249 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 3250 if (!ocelot->owq) { 3251 destroy_workqueue(ocelot->stats_queue); 3252 return -ENOMEM; 3253 } 3254 3255 INIT_LIST_HEAD(&ocelot->multicast); 3256 INIT_LIST_HEAD(&ocelot->pgids); 3257 INIT_LIST_HEAD(&ocelot->vlans); 3258 INIT_LIST_HEAD(&ocelot->lag_fdbs); 3259 ocelot_detect_features(ocelot); 3260 ocelot_mact_init(ocelot); 3261 ocelot_vlan_init(ocelot); 3262 ocelot_vcap_init(ocelot); 3263 ocelot_cpu_port_init(ocelot); 3264 3265 if (ocelot->ops->psfp_init) 3266 ocelot->ops->psfp_init(ocelot); 3267 3268 for (port = 0; port < ocelot->num_phys_ports; port++) { 3269 /* Clear all counters (5 groups) */ 3270 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 3271 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 3272 SYS_STAT_CFG); 3273 } 3274 3275 /* Only use S-Tag */ 3276 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 3277 3278 /* Aggregation mode */ 3279 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 3280 ANA_AGGR_CFG_AC_DMAC_ENA | 3281 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 3282 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 3283 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 3284 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 3285 ANA_AGGR_CFG); 3286 3287 /* Set MAC age time to default value. The entry is aged after 3288 * 2*AGE_PERIOD 3289 */ 3290 ocelot_write(ocelot, 3291 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 3292 ANA_AUTOAGE); 3293 3294 /* Disable learning for frames discarded by VLAN ingress filtering */ 3295 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 3296 3297 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 3298 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 3299 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 3300 3301 /* Setup flooding PGIDs */ 3302 for (i = 0; i < ocelot->num_flooding_pgids; i++) 3303 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 3304 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 3305 ANA_FLOODING_FLD_UNICAST(PGID_UC), 3306 ANA_FLOODING, i); 3307 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 3308 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 3309 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 3310 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 3311 ANA_FLOODING_IPMC); 3312 3313 for (port = 0; port < ocelot->num_phys_ports; port++) { 3314 /* Transmit the frame to the local port. */ 3315 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 3316 /* Do not forward BPDU frames to the front ports. */ 3317 ocelot_write_gix(ocelot, 3318 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 3319 ANA_PORT_CPU_FWD_BPDU_CFG, 3320 port); 3321 /* Ensure bridging is disabled */ 3322 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 3323 } 3324 3325 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 3326 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 3327 3328 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 3329 } 3330 3331 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 3332 3333 /* Allow broadcast and unknown L2 multicast to the CPU. */ 3334 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3335 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3336 ANA_PGID_PGID, PGID_MC); 3337 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3338 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 3339 ANA_PGID_PGID, PGID_BC); 3340 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 3341 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 3342 3343 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 3344 * registers endianness. 3345 */ 3346 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 3347 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 3348 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 3349 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 3350 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 3351 ANA_CPUQ_CFG_CPUQ_LRN(2) | 3352 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 3353 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 3354 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 3355 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 3356 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 3357 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 3358 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 3359 for (i = 0; i < 16; i++) 3360 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 3361 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 3362 ANA_CPUQ_8021_CFG, i); 3363 3364 ret = ocelot_prepare_stats_regions(ocelot); 3365 if (ret) { 3366 destroy_workqueue(ocelot->stats_queue); 3367 destroy_workqueue(ocelot->owq); 3368 return ret; 3369 } 3370 3371 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 3372 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 3373 OCELOT_STATS_CHECK_DELAY); 3374 3375 return 0; 3376 } 3377 EXPORT_SYMBOL(ocelot_init); 3378 3379 void ocelot_deinit(struct ocelot *ocelot) 3380 { 3381 cancel_delayed_work(&ocelot->stats_work); 3382 destroy_workqueue(ocelot->stats_queue); 3383 destroy_workqueue(ocelot->owq); 3384 mutex_destroy(&ocelot->stats_lock); 3385 } 3386 EXPORT_SYMBOL(ocelot_deinit); 3387 3388 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3389 { 3390 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3391 3392 skb_queue_purge(&ocelot_port->tx_skbs); 3393 } 3394 EXPORT_SYMBOL(ocelot_deinit_port); 3395 3396 MODULE_LICENSE("Dual MIT/GPL"); 3397