1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/skbuff.h> 18 #include <net/arp.h> 19 #include <net/netevent.h> 20 #include <net/rtnetlink.h> 21 #include <net/switchdev.h> 22 23 #include "ocelot.h" 24 25 /* MAC table entry types. 26 * ENTRYTYPE_NORMAL is subject to aging. 27 * ENTRYTYPE_LOCKED is not subject to aging. 28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 30 */ 31 enum macaccess_entry_type { 32 ENTRYTYPE_NORMAL = 0, 33 ENTRYTYPE_LOCKED, 34 ENTRYTYPE_MACv4, 35 ENTRYTYPE_MACv6, 36 }; 37 38 struct ocelot_mact_entry { 39 u8 mac[ETH_ALEN]; 40 u16 vid; 41 enum macaccess_entry_type type; 42 }; 43 44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 45 { 46 unsigned int val, timeout = 10; 47 48 /* Wait for the issued mac table command to be completed, or timeout. 49 * When the command read from ANA_TABLES_MACACCESS is 50 * MACACCESS_CMD_IDLE, the issued command completed successfully. 51 */ 52 do { 53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M; 55 } while (val != MACACCESS_CMD_IDLE && timeout--); 56 57 if (!timeout) 58 return -ETIMEDOUT; 59 60 return 0; 61 } 62 63 static void ocelot_mact_select(struct ocelot *ocelot, 64 const unsigned char mac[ETH_ALEN], 65 unsigned int vid) 66 { 67 u32 macl = 0, mach = 0; 68 69 /* Set the MAC address to handle and the vlan associated in a format 70 * understood by the hardware. 71 */ 72 mach |= vid << 16; 73 mach |= mac[0] << 8; 74 mach |= mac[1] << 0; 75 macl |= mac[2] << 24; 76 macl |= mac[3] << 16; 77 macl |= mac[4] << 8; 78 macl |= mac[5] << 0; 79 80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 82 83 } 84 85 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 86 const unsigned char mac[ETH_ALEN], 87 unsigned int vid, 88 enum macaccess_entry_type type) 89 { 90 ocelot_mact_select(ocelot, mac, vid); 91 92 /* Issue a write command */ 93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 94 ANA_TABLES_MACACCESS_DEST_IDX(port) | 95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 97 ANA_TABLES_MACACCESS); 98 99 return ocelot_mact_wait_for_completion(ocelot); 100 } 101 102 static int ocelot_mact_forget(struct ocelot *ocelot, 103 const unsigned char mac[ETH_ALEN], 104 unsigned int vid) 105 { 106 ocelot_mact_select(ocelot, mac, vid); 107 108 /* Issue a forget command */ 109 ocelot_write(ocelot, 110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 111 ANA_TABLES_MACACCESS); 112 113 return ocelot_mact_wait_for_completion(ocelot); 114 } 115 116 static void ocelot_mact_init(struct ocelot *ocelot) 117 { 118 /* Configure the learning mode entries attributes: 119 * - Do not copy the frame to the CPU extraction queues. 120 * - Use the vlan and mac_cpoy for dmac lookup. 121 */ 122 ocelot_rmw(ocelot, 0, 123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 124 | ANA_AGENCTRL_LEARN_FWD_KILL 125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 126 ANA_AGENCTRL); 127 128 /* Clear the MAC table */ 129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 130 } 131 132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 133 { 134 unsigned int val, timeout = 10; 135 136 /* Wait for the issued vlan table command to be completed, or timeout. 137 * When the command read from ANA_TABLES_VLANACCESS is 138 * VLANACCESS_CMD_IDLE, the issued command completed successfully. 139 */ 140 do { 141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M; 143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--); 144 145 if (!timeout) 146 return -ETIMEDOUT; 147 148 return 0; 149 } 150 151 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 152 { 153 /* Select the VID to configure */ 154 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 155 ANA_TABLES_VLANTIDX); 156 /* Set the vlan port members mask and issue a write command */ 157 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 158 ANA_TABLES_VLANACCESS_CMD_WRITE, 159 ANA_TABLES_VLANACCESS); 160 161 return ocelot_vlant_wait_for_completion(ocelot); 162 } 163 164 static void ocelot_vlan_mode(struct ocelot_port *port, 165 netdev_features_t features) 166 { 167 struct ocelot *ocelot = port->ocelot; 168 u8 p = port->chip_port; 169 u32 val; 170 171 /* Filtering */ 172 val = ocelot_read(ocelot, ANA_VLANMASK); 173 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 174 val |= BIT(p); 175 else 176 val &= ~BIT(p); 177 ocelot_write(ocelot, val, ANA_VLANMASK); 178 } 179 180 static void ocelot_vlan_port_apply(struct ocelot *ocelot, 181 struct ocelot_port *port) 182 { 183 u32 val; 184 185 /* Ingress clasification (ANA_PORT_VLAN_CFG) */ 186 /* Default vlan to clasify for untagged frames (may be zero) */ 187 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid); 188 if (port->vlan_aware) 189 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 190 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 191 192 ocelot_rmw_gix(ocelot, val, 193 ANA_PORT_VLAN_CFG_VLAN_VID_M | 194 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 196 ANA_PORT_VLAN_CFG, port->chip_port); 197 198 /* Drop frames with multicast source address */ 199 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA; 200 if (port->vlan_aware && !port->vid) 201 /* If port is vlan-aware and tagged, drop untagged and priority 202 * tagged frames. 203 */ 204 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 205 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 206 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 207 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port); 208 209 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */ 210 val = REW_TAG_CFG_TAG_TPID_CFG(0); 211 212 if (port->vlan_aware) { 213 if (port->vid) 214 /* Tag all frames except when VID == DEFAULT_VLAN */ 215 val |= REW_TAG_CFG_TAG_CFG(1); 216 else 217 /* Tag all frames */ 218 val |= REW_TAG_CFG_TAG_CFG(3); 219 } 220 ocelot_rmw_gix(ocelot, val, 221 REW_TAG_CFG_TAG_TPID_CFG_M | 222 REW_TAG_CFG_TAG_CFG_M, 223 REW_TAG_CFG, port->chip_port); 224 225 /* Set default VLAN and tag type to 8021Q. */ 226 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) | 227 REW_PORT_VLAN_CFG_PORT_VID(port->vid); 228 ocelot_rmw_gix(ocelot, val, 229 REW_PORT_VLAN_CFG_PORT_TPID_M | 230 REW_PORT_VLAN_CFG_PORT_VID_M, 231 REW_PORT_VLAN_CFG, port->chip_port); 232 } 233 234 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 235 bool untagged) 236 { 237 struct ocelot_port *port = netdev_priv(dev); 238 struct ocelot *ocelot = port->ocelot; 239 int ret; 240 241 /* Add the port MAC address to with the right VLAN information */ 242 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 243 ENTRYTYPE_LOCKED); 244 245 /* Make the port a member of the VLAN */ 246 ocelot->vlan_mask[vid] |= BIT(port->chip_port); 247 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 248 if (ret) 249 return ret; 250 251 /* Default ingress vlan classification */ 252 if (pvid) 253 port->pvid = vid; 254 255 /* Untagged egress vlan clasification */ 256 if (untagged) 257 port->vid = vid; 258 259 ocelot_vlan_port_apply(ocelot, port); 260 261 return 0; 262 } 263 264 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 265 { 266 struct ocelot_port *port = netdev_priv(dev); 267 struct ocelot *ocelot = port->ocelot; 268 int ret; 269 270 /* 8021q removes VID 0 on module unload for all interfaces 271 * with VLAN filtering feature. We need to keep it to receive 272 * untagged traffic. 273 */ 274 if (vid == 0) 275 return 0; 276 277 /* Del the port MAC address to with the right VLAN information */ 278 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 279 280 /* Stop the port from being a member of the vlan */ 281 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port); 282 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 283 if (ret) 284 return ret; 285 286 /* Ingress */ 287 if (port->pvid == vid) 288 port->pvid = 0; 289 290 /* Egress */ 291 if (port->vid == vid) 292 port->vid = 0; 293 294 ocelot_vlan_port_apply(ocelot, port); 295 296 return 0; 297 } 298 299 static void ocelot_vlan_init(struct ocelot *ocelot) 300 { 301 u16 port, vid; 302 303 /* Clear VLAN table, by default all ports are members of all VLANs */ 304 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 305 ANA_TABLES_VLANACCESS); 306 ocelot_vlant_wait_for_completion(ocelot); 307 308 /* Configure the port VLAN memberships */ 309 for (vid = 1; vid < VLAN_N_VID; vid++) { 310 ocelot->vlan_mask[vid] = 0; 311 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 312 } 313 314 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 315 * traffic. It is added automatically if 8021q module is loaded, but 316 * we can't rely on it since module may be not loaded. 317 */ 318 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 319 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 320 321 /* Configure the CPU port to be VLAN aware */ 322 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 323 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 324 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 325 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports); 326 327 /* Set vlan ingress filter mask to all ports but the CPU port by 328 * default. 329 */ 330 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK); 331 332 for (port = 0; port < ocelot->num_phys_ports; port++) { 333 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 334 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 335 } 336 } 337 338 /* Watermark encode 339 * Bit 8: Unit; 0:1, 1:16 340 * Bit 7-0: Value to be multiplied with unit 341 */ 342 static u16 ocelot_wm_enc(u16 value) 343 { 344 if (value >= BIT(8)) 345 return BIT(8) | (value / 16); 346 347 return value; 348 } 349 350 static void ocelot_port_adjust_link(struct net_device *dev) 351 { 352 struct ocelot_port *port = netdev_priv(dev); 353 struct ocelot *ocelot = port->ocelot; 354 u8 p = port->chip_port; 355 int speed, atop_wm, mode = 0; 356 357 switch (dev->phydev->speed) { 358 case SPEED_10: 359 speed = OCELOT_SPEED_10; 360 break; 361 case SPEED_100: 362 speed = OCELOT_SPEED_100; 363 break; 364 case SPEED_1000: 365 speed = OCELOT_SPEED_1000; 366 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 367 break; 368 case SPEED_2500: 369 speed = OCELOT_SPEED_2500; 370 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 371 break; 372 default: 373 netdev_err(dev, "Unsupported PHY speed: %d\n", 374 dev->phydev->speed); 375 return; 376 } 377 378 phy_print_status(dev->phydev); 379 380 if (!dev->phydev->link) 381 return; 382 383 /* Only full duplex supported for now */ 384 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA | 385 mode, DEV_MAC_MODE_CFG); 386 387 /* Set MAC IFG Gaps 388 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 389 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 390 */ 391 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG); 392 393 /* Load seed (0) and set MAC HDX late collision */ 394 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 395 DEV_MAC_HDX_CFG_SEED_LOAD, 396 DEV_MAC_HDX_CFG); 397 mdelay(1); 398 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 399 DEV_MAC_HDX_CFG); 400 401 /* Disable HDX fast control */ 402 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC); 403 404 /* SGMII only for now */ 405 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG); 406 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 407 408 /* Enable PCS */ 409 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 410 411 /* No aneg on SGMII */ 412 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG); 413 414 /* No loopback */ 415 ocelot_port_writel(port, 0, PCS1G_LB_CFG); 416 417 /* Set Max Length and maximum tags allowed */ 418 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG); 419 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 420 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 421 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 422 DEV_MAC_TAGS_CFG); 423 424 /* Enable MAC module */ 425 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA | 426 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 427 428 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 429 * reset */ 430 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed), 431 DEV_CLOCK_CFG); 432 433 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 435 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG); 436 437 /* No PFC */ 438 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 439 ANA_PFC_PFC_CFG, p); 440 441 /* Set Pause WM hysteresis 442 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 443 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 444 */ 445 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 446 SYS_PAUSE_CFG_PAUSE_STOP(101) | 447 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p); 448 449 /* Core: Enable port for frame transfer */ 450 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 451 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 452 QSYS_SWITCH_PORT_MODE_PORT_ENA, 453 QSYS_SWITCH_PORT_MODE, p); 454 455 /* Flow control */ 456 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 457 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 458 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 459 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 460 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 461 SYS_MAC_FC_CFG, p); 462 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p); 463 464 /* Tail dropping watermark */ 465 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 466 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 467 SYS_ATOP, p); 468 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 469 } 470 471 static int ocelot_port_open(struct net_device *dev) 472 { 473 struct ocelot_port *port = netdev_priv(dev); 474 struct ocelot *ocelot = port->ocelot; 475 enum phy_mode phy_mode; 476 int err; 477 478 /* Enable receiving frames on the port, and activate auto-learning of 479 * MAC addresses. 480 */ 481 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 482 ANA_PORT_PORT_CFG_RECV_ENA | 483 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port), 484 ANA_PORT_PORT_CFG, port->chip_port); 485 486 if (port->serdes) { 487 if (port->phy_mode == PHY_INTERFACE_MODE_SGMII) 488 phy_mode = PHY_MODE_SGMII; 489 else 490 phy_mode = PHY_MODE_QSGMII; 491 492 err = phy_set_mode(port->serdes, phy_mode); 493 if (err) { 494 netdev_err(dev, "Could not set mode of SerDes\n"); 495 return err; 496 } 497 } 498 499 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link, 500 port->phy_mode); 501 if (err) { 502 netdev_err(dev, "Could not attach to PHY\n"); 503 return err; 504 } 505 506 dev->phydev = port->phy; 507 508 phy_attached_info(port->phy); 509 phy_start(port->phy); 510 return 0; 511 } 512 513 static int ocelot_port_stop(struct net_device *dev) 514 { 515 struct ocelot_port *port = netdev_priv(dev); 516 517 phy_disconnect(port->phy); 518 519 dev->phydev = NULL; 520 521 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG); 522 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 523 QSYS_SWITCH_PORT_MODE, port->chip_port); 524 return 0; 525 } 526 527 /* Generate the IFH for frame injection 528 * 529 * The IFH is a 128bit-value 530 * bit 127: bypass the analyzer processing 531 * bit 56-67: destination mask 532 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 533 * bit 20-27: cpu extraction queue mask 534 * bit 16: tag type 0: C-tag, 1: S-tag 535 * bit 0-11: VID 536 */ 537 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 538 { 539 ifh[0] = IFH_INJ_BYPASS; 540 ifh[1] = (0xf00 & info->port) >> 8; 541 ifh[2] = (0xff & info->port) << 24; 542 ifh[3] = (info->tag_type << 16) | info->vid; 543 544 return 0; 545 } 546 547 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 548 { 549 struct ocelot_port *port = netdev_priv(dev); 550 struct ocelot *ocelot = port->ocelot; 551 u32 val, ifh[IFH_LEN]; 552 struct frame_info info = {}; 553 u8 grp = 0; /* Send everything on CPU group 0 */ 554 unsigned int i, count, last; 555 556 val = ocelot_read(ocelot, QS_INJ_STATUS); 557 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 558 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 559 return NETDEV_TX_BUSY; 560 561 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 562 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 563 564 info.port = BIT(port->chip_port); 565 info.tag_type = IFH_TAG_TYPE_C; 566 info.vid = skb_vlan_tag_get(skb); 567 ocelot_gen_ifh(ifh, &info); 568 569 for (i = 0; i < IFH_LEN; i++) 570 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 571 QS_INJ_WR, grp); 572 573 count = (skb->len + 3) / 4; 574 last = skb->len % 4; 575 for (i = 0; i < count; i++) { 576 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 577 } 578 579 /* Add padding */ 580 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 581 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 582 i++; 583 } 584 585 /* Indicate EOF and valid bytes in last word */ 586 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 587 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 588 QS_INJ_CTRL_EOF, 589 QS_INJ_CTRL, grp); 590 591 /* Add dummy CRC */ 592 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 593 skb_tx_timestamp(skb); 594 595 dev->stats.tx_packets++; 596 dev->stats.tx_bytes += skb->len; 597 dev_kfree_skb_any(skb); 598 599 return NETDEV_TX_OK; 600 } 601 602 static void ocelot_mact_mc_reset(struct ocelot_port *port) 603 { 604 struct ocelot *ocelot = port->ocelot; 605 struct netdev_hw_addr *ha, *n; 606 607 /* Free and forget all the MAC addresses stored in the port private mc 608 * list. These are mc addresses that were previously added by calling 609 * ocelot_mact_mc_add(). 610 */ 611 list_for_each_entry_safe(ha, n, &port->mc, list) { 612 ocelot_mact_forget(ocelot, ha->addr, port->pvid); 613 list_del(&ha->list); 614 kfree(ha); 615 } 616 } 617 618 static int ocelot_mact_mc_add(struct ocelot_port *port, 619 struct netdev_hw_addr *hw_addr) 620 { 621 struct ocelot *ocelot = port->ocelot; 622 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL); 623 624 if (!ha) 625 return -ENOMEM; 626 627 memcpy(ha, hw_addr, sizeof(*ha)); 628 list_add_tail(&ha->list, &port->mc); 629 630 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid, 631 ENTRYTYPE_LOCKED); 632 633 return 0; 634 } 635 636 static void ocelot_set_rx_mode(struct net_device *dev) 637 { 638 struct ocelot_port *port = netdev_priv(dev); 639 struct ocelot *ocelot = port->ocelot; 640 struct netdev_hw_addr *ha; 641 int i; 642 u32 val; 643 644 /* This doesn't handle promiscuous mode because the bridge core is 645 * setting IFF_PROMISC on all slave interfaces and all frames would be 646 * forwarded to the CPU port. 647 */ 648 val = GENMASK(ocelot->num_phys_ports - 1, 0); 649 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 650 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 651 652 /* Handle the device multicast addresses. First remove all the 653 * previously installed addresses and then add the latest ones to the 654 * mac table. 655 */ 656 ocelot_mact_mc_reset(port); 657 netdev_for_each_mc_addr(ha, dev) 658 ocelot_mact_mc_add(port, ha); 659 } 660 661 static int ocelot_port_get_phys_port_name(struct net_device *dev, 662 char *buf, size_t len) 663 { 664 struct ocelot_port *port = netdev_priv(dev); 665 int ret; 666 667 ret = snprintf(buf, len, "p%d", port->chip_port); 668 if (ret >= len) 669 return -EINVAL; 670 671 return 0; 672 } 673 674 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 675 { 676 struct ocelot_port *port = netdev_priv(dev); 677 struct ocelot *ocelot = port->ocelot; 678 const struct sockaddr *addr = p; 679 680 /* Learn the new net device MAC address in the mac table. */ 681 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid, 682 ENTRYTYPE_LOCKED); 683 /* Then forget the previous one. */ 684 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid); 685 686 ether_addr_copy(dev->dev_addr, addr->sa_data); 687 return 0; 688 } 689 690 static void ocelot_get_stats64(struct net_device *dev, 691 struct rtnl_link_stats64 *stats) 692 { 693 struct ocelot_port *port = netdev_priv(dev); 694 struct ocelot *ocelot = port->ocelot; 695 696 /* Configure the port to read the stats from */ 697 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port), 698 SYS_STAT_CFG); 699 700 /* Get Rx stats */ 701 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 702 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 703 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 704 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 705 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 706 ocelot_read(ocelot, SYS_COUNT_RX_64) + 707 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 708 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 709 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 710 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 711 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 712 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 713 stats->rx_dropped = dev->stats.rx_dropped; 714 715 /* Get Tx stats */ 716 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 717 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 718 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 719 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 720 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 721 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 722 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 723 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 724 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 725 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 726 } 727 728 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 729 struct net_device *dev, const unsigned char *addr, 730 u16 vid, u16 flags) 731 { 732 struct ocelot_port *port = netdev_priv(dev); 733 struct ocelot *ocelot = port->ocelot; 734 735 if (!vid) { 736 if (!port->vlan_aware) 737 /* If the bridge is not VLAN aware and no VID was 738 * provided, set it to pvid to ensure the MAC entry 739 * matches incoming untagged packets 740 */ 741 vid = port->pvid; 742 else 743 /* If the bridge is VLAN aware a VID must be provided as 744 * otherwise the learnt entry wouldn't match any frame. 745 */ 746 return -EINVAL; 747 } 748 749 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid, 750 ENTRYTYPE_NORMAL); 751 } 752 753 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 754 struct net_device *dev, 755 const unsigned char *addr, u16 vid) 756 { 757 struct ocelot_port *port = netdev_priv(dev); 758 struct ocelot *ocelot = port->ocelot; 759 760 return ocelot_mact_forget(ocelot, addr, vid); 761 } 762 763 struct ocelot_dump_ctx { 764 struct net_device *dev; 765 struct sk_buff *skb; 766 struct netlink_callback *cb; 767 int idx; 768 }; 769 770 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry, 771 struct ocelot_dump_ctx *dump) 772 { 773 u32 portid = NETLINK_CB(dump->cb->skb).portid; 774 u32 seq = dump->cb->nlh->nlmsg_seq; 775 struct nlmsghdr *nlh; 776 struct ndmsg *ndm; 777 778 if (dump->idx < dump->cb->args[2]) 779 goto skip; 780 781 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 782 sizeof(*ndm), NLM_F_MULTI); 783 if (!nlh) 784 return -EMSGSIZE; 785 786 ndm = nlmsg_data(nlh); 787 ndm->ndm_family = AF_BRIDGE; 788 ndm->ndm_pad1 = 0; 789 ndm->ndm_pad2 = 0; 790 ndm->ndm_flags = NTF_SELF; 791 ndm->ndm_type = 0; 792 ndm->ndm_ifindex = dump->dev->ifindex; 793 ndm->ndm_state = NUD_REACHABLE; 794 795 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac)) 796 goto nla_put_failure; 797 798 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid)) 799 goto nla_put_failure; 800 801 nlmsg_end(dump->skb, nlh); 802 803 skip: 804 dump->idx++; 805 return 0; 806 807 nla_put_failure: 808 nlmsg_cancel(dump->skb, nlh); 809 return -EMSGSIZE; 810 } 811 812 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col, 813 struct ocelot_mact_entry *entry) 814 { 815 struct ocelot *ocelot = port->ocelot; 816 char mac[ETH_ALEN]; 817 u32 val, dst, macl, mach; 818 819 /* Set row and column to read from */ 820 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 821 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 822 823 /* Issue a read command */ 824 ocelot_write(ocelot, 825 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 826 ANA_TABLES_MACACCESS); 827 828 if (ocelot_mact_wait_for_completion(ocelot)) 829 return -ETIMEDOUT; 830 831 /* Read the entry flags */ 832 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 833 if (!(val & ANA_TABLES_MACACCESS_VALID)) 834 return -EINVAL; 835 836 /* If the entry read has another port configured as its destination, 837 * do not report it. 838 */ 839 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 840 if (dst != port->chip_port) 841 return -EINVAL; 842 843 /* Get the entry's MAC address and VLAN id */ 844 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 845 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 846 847 mac[0] = (mach >> 8) & 0xff; 848 mac[1] = (mach >> 0) & 0xff; 849 mac[2] = (macl >> 24) & 0xff; 850 mac[3] = (macl >> 16) & 0xff; 851 mac[4] = (macl >> 8) & 0xff; 852 mac[5] = (macl >> 0) & 0xff; 853 854 entry->vid = (mach >> 16) & 0xfff; 855 ether_addr_copy(entry->mac, mac); 856 857 return 0; 858 } 859 860 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb, 861 struct net_device *dev, 862 struct net_device *filter_dev, int *idx) 863 { 864 struct ocelot_port *port = netdev_priv(dev); 865 int i, j, ret = 0; 866 struct ocelot_dump_ctx dump = { 867 .dev = dev, 868 .skb = skb, 869 .cb = cb, 870 .idx = *idx, 871 }; 872 873 struct ocelot_mact_entry entry; 874 875 /* Loop through all the mac tables entries. There are 1024 rows of 4 876 * entries. 877 */ 878 for (i = 0; i < 1024; i++) { 879 for (j = 0; j < 4; j++) { 880 ret = ocelot_mact_read(port, i, j, &entry); 881 /* If the entry is invalid (wrong port, invalid...), 882 * skip it. 883 */ 884 if (ret == -EINVAL) 885 continue; 886 else if (ret) 887 goto end; 888 889 ret = ocelot_fdb_do_dump(&entry, &dump); 890 if (ret) 891 goto end; 892 } 893 } 894 895 end: 896 *idx = dump.idx; 897 return ret; 898 } 899 900 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 901 u16 vid) 902 { 903 return ocelot_vlan_vid_add(dev, vid, false, true); 904 } 905 906 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 907 u16 vid) 908 { 909 return ocelot_vlan_vid_del(dev, vid); 910 } 911 912 static int ocelot_set_features(struct net_device *dev, 913 netdev_features_t features) 914 { 915 struct ocelot_port *port = netdev_priv(dev); 916 netdev_features_t changed = dev->features ^ features; 917 918 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 919 ocelot_vlan_mode(port, features); 920 921 return 0; 922 } 923 924 static const struct net_device_ops ocelot_port_netdev_ops = { 925 .ndo_open = ocelot_port_open, 926 .ndo_stop = ocelot_port_stop, 927 .ndo_start_xmit = ocelot_port_xmit, 928 .ndo_set_rx_mode = ocelot_set_rx_mode, 929 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 930 .ndo_set_mac_address = ocelot_port_set_mac_address, 931 .ndo_get_stats64 = ocelot_get_stats64, 932 .ndo_fdb_add = ocelot_fdb_add, 933 .ndo_fdb_del = ocelot_fdb_del, 934 .ndo_fdb_dump = ocelot_fdb_dump, 935 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 936 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 937 .ndo_set_features = ocelot_set_features, 938 }; 939 940 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data) 941 { 942 struct ocelot_port *port = netdev_priv(netdev); 943 struct ocelot *ocelot = port->ocelot; 944 int i; 945 946 if (sset != ETH_SS_STATS) 947 return; 948 949 for (i = 0; i < ocelot->num_stats; i++) 950 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 951 ETH_GSTRING_LEN); 952 } 953 954 static void ocelot_check_stats(struct work_struct *work) 955 { 956 struct delayed_work *del_work = to_delayed_work(work); 957 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work); 958 int i, j; 959 960 mutex_lock(&ocelot->stats_lock); 961 962 for (i = 0; i < ocelot->num_phys_ports; i++) { 963 /* Configure the port to read the stats from */ 964 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 965 966 for (j = 0; j < ocelot->num_stats; j++) { 967 u32 val; 968 unsigned int idx = i * ocelot->num_stats + j; 969 970 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 971 ocelot->stats_layout[j].offset); 972 973 if (val < (ocelot->stats[idx] & U32_MAX)) 974 ocelot->stats[idx] += (u64)1 << 32; 975 976 ocelot->stats[idx] = (ocelot->stats[idx] & 977 ~(u64)U32_MAX) + val; 978 } 979 } 980 981 cancel_delayed_work(&ocelot->stats_work); 982 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 983 OCELOT_STATS_CHECK_DELAY); 984 985 mutex_unlock(&ocelot->stats_lock); 986 } 987 988 static void ocelot_get_ethtool_stats(struct net_device *dev, 989 struct ethtool_stats *stats, u64 *data) 990 { 991 struct ocelot_port *port = netdev_priv(dev); 992 struct ocelot *ocelot = port->ocelot; 993 int i; 994 995 /* check and update now */ 996 ocelot_check_stats(&ocelot->stats_work.work); 997 998 /* Copy all counters */ 999 for (i = 0; i < ocelot->num_stats; i++) 1000 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i]; 1001 } 1002 1003 static int ocelot_get_sset_count(struct net_device *dev, int sset) 1004 { 1005 struct ocelot_port *port = netdev_priv(dev); 1006 struct ocelot *ocelot = port->ocelot; 1007 1008 if (sset != ETH_SS_STATS) 1009 return -EOPNOTSUPP; 1010 return ocelot->num_stats; 1011 } 1012 1013 static const struct ethtool_ops ocelot_ethtool_ops = { 1014 .get_strings = ocelot_get_strings, 1015 .get_ethtool_stats = ocelot_get_ethtool_stats, 1016 .get_sset_count = ocelot_get_sset_count, 1017 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1018 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1019 }; 1020 1021 static int ocelot_port_attr_get(struct net_device *dev, 1022 struct switchdev_attr *attr) 1023 { 1024 struct ocelot_port *ocelot_port = netdev_priv(dev); 1025 struct ocelot *ocelot = ocelot_port->ocelot; 1026 1027 switch (attr->id) { 1028 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID: 1029 attr->u.ppid.id_len = sizeof(ocelot->base_mac); 1030 memcpy(&attr->u.ppid.id, &ocelot->base_mac, 1031 attr->u.ppid.id_len); 1032 break; 1033 default: 1034 return -EOPNOTSUPP; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port, 1041 struct switchdev_trans *trans, 1042 u8 state) 1043 { 1044 struct ocelot *ocelot = ocelot_port->ocelot; 1045 u32 port_cfg; 1046 int port, i; 1047 1048 if (switchdev_trans_ph_prepare(trans)) 1049 return 0; 1050 1051 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask)) 1052 return 0; 1053 1054 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, 1055 ocelot_port->chip_port); 1056 1057 switch (state) { 1058 case BR_STATE_FORWARDING: 1059 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port); 1060 /* Fallthrough */ 1061 case BR_STATE_LEARNING: 1062 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1063 break; 1064 1065 default: 1066 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1067 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port); 1068 break; 1069 } 1070 1071 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, 1072 ocelot_port->chip_port); 1073 1074 /* Apply FWD mask. The loop is needed to add/remove the current port as 1075 * a source for the other ports. 1076 */ 1077 for (port = 0; port < ocelot->num_phys_ports; port++) { 1078 if (ocelot->bridge_fwd_mask & BIT(port)) { 1079 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); 1080 1081 for (i = 0; i < ocelot->num_phys_ports; i++) { 1082 unsigned long bond_mask = ocelot->lags[i]; 1083 1084 if (!bond_mask) 1085 continue; 1086 1087 if (bond_mask & BIT(port)) { 1088 mask &= ~bond_mask; 1089 break; 1090 } 1091 } 1092 1093 ocelot_write_rix(ocelot, 1094 BIT(ocelot->num_phys_ports) | mask, 1095 ANA_PGID_PGID, PGID_SRC + port); 1096 } else { 1097 /* Only the CPU port, this is compatible with link 1098 * aggregation. 1099 */ 1100 ocelot_write_rix(ocelot, 1101 BIT(ocelot->num_phys_ports), 1102 ANA_PGID_PGID, PGID_SRC + port); 1103 } 1104 } 1105 1106 return 0; 1107 } 1108 1109 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port, 1110 unsigned long ageing_clock_t) 1111 { 1112 struct ocelot *ocelot = ocelot_port->ocelot; 1113 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1114 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1115 1116 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2), 1117 ANA_AUTOAGE); 1118 } 1119 1120 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc) 1121 { 1122 struct ocelot *ocelot = port->ocelot; 1123 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG, 1124 port->chip_port); 1125 1126 if (mc) 1127 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1128 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1129 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1130 else 1131 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1132 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1133 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA); 1134 1135 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port); 1136 } 1137 1138 static int ocelot_port_attr_set(struct net_device *dev, 1139 const struct switchdev_attr *attr, 1140 struct switchdev_trans *trans) 1141 { 1142 struct ocelot_port *ocelot_port = netdev_priv(dev); 1143 int err = 0; 1144 1145 switch (attr->id) { 1146 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1147 ocelot_port_attr_stp_state_set(ocelot_port, trans, 1148 attr->u.stp_state); 1149 break; 1150 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1151 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time); 1152 break; 1153 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1154 ocelot_port->vlan_aware = attr->u.vlan_filtering; 1155 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port); 1156 break; 1157 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1158 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled); 1159 break; 1160 default: 1161 err = -EOPNOTSUPP; 1162 break; 1163 } 1164 1165 return err; 1166 } 1167 1168 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1169 const struct switchdev_obj_port_vlan *vlan, 1170 struct switchdev_trans *trans) 1171 { 1172 int ret; 1173 u16 vid; 1174 1175 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1176 ret = ocelot_vlan_vid_add(dev, vid, 1177 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1178 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1179 if (ret) 1180 return ret; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1187 const struct switchdev_obj_port_vlan *vlan) 1188 { 1189 int ret; 1190 u16 vid; 1191 1192 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1193 ret = ocelot_vlan_vid_del(dev, vid); 1194 1195 if (ret) 1196 return ret; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1203 const unsigned char *addr, 1204 u16 vid) 1205 { 1206 struct ocelot_multicast *mc; 1207 1208 list_for_each_entry(mc, &ocelot->multicast, list) { 1209 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1210 return mc; 1211 } 1212 1213 return NULL; 1214 } 1215 1216 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1217 const struct switchdev_obj_port_mdb *mdb, 1218 struct switchdev_trans *trans) 1219 { 1220 struct ocelot_port *port = netdev_priv(dev); 1221 struct ocelot *ocelot = port->ocelot; 1222 struct ocelot_multicast *mc; 1223 unsigned char addr[ETH_ALEN]; 1224 u16 vid = mdb->vid; 1225 bool new = false; 1226 1227 if (!vid) 1228 vid = port->pvid; 1229 1230 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1231 if (!mc) { 1232 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1233 if (!mc) 1234 return -ENOMEM; 1235 1236 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1237 mc->vid = vid; 1238 1239 list_add_tail(&mc->list, &ocelot->multicast); 1240 new = true; 1241 } 1242 1243 memcpy(addr, mc->addr, ETH_ALEN); 1244 addr[0] = 0; 1245 1246 if (!new) { 1247 addr[2] = mc->ports << 0; 1248 addr[1] = mc->ports << 8; 1249 ocelot_mact_forget(ocelot, addr, vid); 1250 } 1251 1252 mc->ports |= BIT(port->chip_port); 1253 addr[2] = mc->ports << 0; 1254 addr[1] = mc->ports << 8; 1255 1256 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1257 } 1258 1259 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1260 const struct switchdev_obj_port_mdb *mdb) 1261 { 1262 struct ocelot_port *port = netdev_priv(dev); 1263 struct ocelot *ocelot = port->ocelot; 1264 struct ocelot_multicast *mc; 1265 unsigned char addr[ETH_ALEN]; 1266 u16 vid = mdb->vid; 1267 1268 if (!vid) 1269 vid = port->pvid; 1270 1271 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1272 if (!mc) 1273 return -ENOENT; 1274 1275 memcpy(addr, mc->addr, ETH_ALEN); 1276 addr[2] = mc->ports << 0; 1277 addr[1] = mc->ports << 8; 1278 addr[0] = 0; 1279 ocelot_mact_forget(ocelot, addr, vid); 1280 1281 mc->ports &= ~BIT(port->chip_port); 1282 if (!mc->ports) { 1283 list_del(&mc->list); 1284 devm_kfree(ocelot->dev, mc); 1285 return 0; 1286 } 1287 1288 addr[2] = mc->ports << 0; 1289 addr[1] = mc->ports << 8; 1290 1291 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1292 } 1293 1294 static int ocelot_port_obj_add(struct net_device *dev, 1295 const struct switchdev_obj *obj, 1296 struct switchdev_trans *trans) 1297 { 1298 int ret = 0; 1299 1300 switch (obj->id) { 1301 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1302 ret = ocelot_port_obj_add_vlan(dev, 1303 SWITCHDEV_OBJ_PORT_VLAN(obj), 1304 trans); 1305 break; 1306 case SWITCHDEV_OBJ_ID_PORT_MDB: 1307 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1308 trans); 1309 break; 1310 default: 1311 return -EOPNOTSUPP; 1312 } 1313 1314 return ret; 1315 } 1316 1317 static int ocelot_port_obj_del(struct net_device *dev, 1318 const struct switchdev_obj *obj) 1319 { 1320 int ret = 0; 1321 1322 switch (obj->id) { 1323 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1324 ret = ocelot_port_vlan_del_vlan(dev, 1325 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1326 break; 1327 case SWITCHDEV_OBJ_ID_PORT_MDB: 1328 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1329 break; 1330 default: 1331 return -EOPNOTSUPP; 1332 } 1333 1334 return ret; 1335 } 1336 1337 static const struct switchdev_ops ocelot_port_switchdev_ops = { 1338 .switchdev_port_attr_get = ocelot_port_attr_get, 1339 .switchdev_port_attr_set = ocelot_port_attr_set, 1340 .switchdev_port_obj_add = ocelot_port_obj_add, 1341 .switchdev_port_obj_del = ocelot_port_obj_del, 1342 }; 1343 1344 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port, 1345 struct net_device *bridge) 1346 { 1347 struct ocelot *ocelot = ocelot_port->ocelot; 1348 1349 if (!ocelot->bridge_mask) { 1350 ocelot->hw_bridge_dev = bridge; 1351 } else { 1352 if (ocelot->hw_bridge_dev != bridge) 1353 /* This is adding the port to a second bridge, this is 1354 * unsupported */ 1355 return -ENODEV; 1356 } 1357 1358 ocelot->bridge_mask |= BIT(ocelot_port->chip_port); 1359 1360 return 0; 1361 } 1362 1363 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port, 1364 struct net_device *bridge) 1365 { 1366 struct ocelot *ocelot = ocelot_port->ocelot; 1367 1368 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port); 1369 1370 if (!ocelot->bridge_mask) 1371 ocelot->hw_bridge_dev = NULL; 1372 1373 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */ 1374 ocelot_port->vlan_aware = 0; 1375 ocelot_port->pvid = 0; 1376 ocelot_port->vid = 0; 1377 } 1378 1379 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1380 { 1381 int i, port, lag; 1382 1383 /* Reset destination and aggregation PGIDS */ 1384 for (port = 0; port < ocelot->num_phys_ports; port++) 1385 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1386 1387 for (i = PGID_AGGR; i < PGID_SRC; i++) 1388 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1389 ANA_PGID_PGID, i); 1390 1391 /* Now, set PGIDs for each LAG */ 1392 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1393 unsigned long bond_mask; 1394 int aggr_count = 0; 1395 u8 aggr_idx[16]; 1396 1397 bond_mask = ocelot->lags[lag]; 1398 if (!bond_mask) 1399 continue; 1400 1401 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1402 // Destination mask 1403 ocelot_write_rix(ocelot, bond_mask, 1404 ANA_PGID_PGID, port); 1405 aggr_idx[aggr_count] = port; 1406 aggr_count++; 1407 } 1408 1409 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1410 u32 ac; 1411 1412 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1413 ac &= ~bond_mask; 1414 ac |= BIT(aggr_idx[i % aggr_count]); 1415 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1416 } 1417 } 1418 } 1419 1420 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1421 { 1422 unsigned long bond_mask = ocelot->lags[lag]; 1423 unsigned int p; 1424 1425 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1426 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1427 1428 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1429 1430 /* Use lag port as logical port for port i */ 1431 ocelot_write_gix(ocelot, port_cfg | 1432 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1433 ANA_PORT_PORT_CFG, p); 1434 } 1435 } 1436 1437 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port, 1438 struct net_device *bond) 1439 { 1440 struct ocelot *ocelot = ocelot_port->ocelot; 1441 int p = ocelot_port->chip_port; 1442 int lag, lp; 1443 struct net_device *ndev; 1444 u32 bond_mask = 0; 1445 1446 rcu_read_lock(); 1447 for_each_netdev_in_bond_rcu(bond, ndev) { 1448 struct ocelot_port *port = netdev_priv(ndev); 1449 1450 bond_mask |= BIT(port->chip_port); 1451 } 1452 rcu_read_unlock(); 1453 1454 lp = __ffs(bond_mask); 1455 1456 /* If the new port is the lowest one, use it as the logical port from 1457 * now on 1458 */ 1459 if (p == lp) { 1460 lag = p; 1461 ocelot->lags[p] = bond_mask; 1462 bond_mask &= ~BIT(p); 1463 if (bond_mask) { 1464 lp = __ffs(bond_mask); 1465 ocelot->lags[lp] = 0; 1466 } 1467 } else { 1468 lag = lp; 1469 ocelot->lags[lp] |= BIT(p); 1470 } 1471 1472 ocelot_setup_lag(ocelot, lag); 1473 ocelot_set_aggr_pgids(ocelot); 1474 1475 return 0; 1476 } 1477 1478 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port, 1479 struct net_device *bond) 1480 { 1481 struct ocelot *ocelot = ocelot_port->ocelot; 1482 int p = ocelot_port->chip_port; 1483 u32 port_cfg; 1484 int i; 1485 1486 /* Remove port from any lag */ 1487 for (i = 0; i < ocelot->num_phys_ports; i++) 1488 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port); 1489 1490 /* if it was the logical port of the lag, move the lag config to the 1491 * next port 1492 */ 1493 if (ocelot->lags[p]) { 1494 int n = __ffs(ocelot->lags[p]); 1495 1496 ocelot->lags[n] = ocelot->lags[p]; 1497 ocelot->lags[p] = 0; 1498 1499 ocelot_setup_lag(ocelot, n); 1500 } 1501 1502 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1503 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1504 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p), 1505 ANA_PORT_PORT_CFG, p); 1506 1507 ocelot_set_aggr_pgids(ocelot); 1508 } 1509 1510 /* Checks if the net_device instance given to us originate from our driver. */ 1511 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1512 { 1513 return dev->netdev_ops == &ocelot_port_netdev_ops; 1514 } 1515 1516 static int ocelot_netdevice_port_event(struct net_device *dev, 1517 unsigned long event, 1518 struct netdev_notifier_changeupper_info *info) 1519 { 1520 struct ocelot_port *ocelot_port = netdev_priv(dev); 1521 int err = 0; 1522 1523 if (!ocelot_netdevice_dev_check(dev)) 1524 return 0; 1525 1526 switch (event) { 1527 case NETDEV_CHANGEUPPER: 1528 if (netif_is_bridge_master(info->upper_dev)) { 1529 if (info->linking) 1530 err = ocelot_port_bridge_join(ocelot_port, 1531 info->upper_dev); 1532 else 1533 ocelot_port_bridge_leave(ocelot_port, 1534 info->upper_dev); 1535 1536 ocelot_vlan_port_apply(ocelot_port->ocelot, 1537 ocelot_port); 1538 } 1539 if (netif_is_lag_master(info->upper_dev)) { 1540 if (info->linking) 1541 err = ocelot_port_lag_join(ocelot_port, 1542 info->upper_dev); 1543 else 1544 ocelot_port_lag_leave(ocelot_port, 1545 info->upper_dev); 1546 } 1547 break; 1548 default: 1549 break; 1550 } 1551 1552 return err; 1553 } 1554 1555 static int ocelot_netdevice_event(struct notifier_block *unused, 1556 unsigned long event, void *ptr) 1557 { 1558 struct netdev_notifier_changeupper_info *info = ptr; 1559 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1560 int ret = 0; 1561 1562 if (event == NETDEV_PRECHANGEUPPER && 1563 netif_is_lag_master(info->upper_dev)) { 1564 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1565 struct netlink_ext_ack *extack; 1566 1567 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1568 extack = netdev_notifier_info_to_extack(&info->info); 1569 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1570 1571 ret = -EINVAL; 1572 goto notify; 1573 } 1574 } 1575 1576 if (netif_is_lag_master(dev)) { 1577 struct net_device *slave; 1578 struct list_head *iter; 1579 1580 netdev_for_each_lower_dev(dev, slave, iter) { 1581 ret = ocelot_netdevice_port_event(slave, event, info); 1582 if (ret) 1583 goto notify; 1584 } 1585 } else { 1586 ret = ocelot_netdevice_port_event(dev, event, info); 1587 } 1588 1589 notify: 1590 return notifier_from_errno(ret); 1591 } 1592 1593 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1594 .notifier_call = ocelot_netdevice_event, 1595 }; 1596 EXPORT_SYMBOL(ocelot_netdevice_nb); 1597 1598 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 1599 void __iomem *regs, 1600 struct phy_device *phy) 1601 { 1602 struct ocelot_port *ocelot_port; 1603 struct net_device *dev; 1604 int err; 1605 1606 dev = alloc_etherdev(sizeof(struct ocelot_port)); 1607 if (!dev) 1608 return -ENOMEM; 1609 SET_NETDEV_DEV(dev, ocelot->dev); 1610 ocelot_port = netdev_priv(dev); 1611 ocelot_port->dev = dev; 1612 ocelot_port->ocelot = ocelot; 1613 ocelot_port->regs = regs; 1614 ocelot_port->chip_port = port; 1615 ocelot_port->phy = phy; 1616 INIT_LIST_HEAD(&ocelot_port->mc); 1617 ocelot->ports[port] = ocelot_port; 1618 1619 dev->netdev_ops = &ocelot_port_netdev_ops; 1620 dev->ethtool_ops = &ocelot_ethtool_ops; 1621 dev->switchdev_ops = &ocelot_port_switchdev_ops; 1622 1623 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS; 1624 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1625 1626 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 1627 dev->dev_addr[ETH_ALEN - 1] += port; 1628 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 1629 ENTRYTYPE_LOCKED); 1630 1631 err = register_netdev(dev); 1632 if (err) { 1633 dev_err(ocelot->dev, "register_netdev failed\n"); 1634 goto err_register_netdev; 1635 } 1636 1637 /* Basic L2 initialization */ 1638 ocelot_vlan_port_apply(ocelot, ocelot_port); 1639 1640 return 0; 1641 1642 err_register_netdev: 1643 free_netdev(dev); 1644 return err; 1645 } 1646 EXPORT_SYMBOL(ocelot_probe_port); 1647 1648 int ocelot_init(struct ocelot *ocelot) 1649 { 1650 u32 port; 1651 int i, cpu = ocelot->num_phys_ports; 1652 char queue_name[32]; 1653 1654 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1655 sizeof(u32), GFP_KERNEL); 1656 if (!ocelot->lags) 1657 return -ENOMEM; 1658 1659 ocelot->stats = devm_kcalloc(ocelot->dev, 1660 ocelot->num_phys_ports * ocelot->num_stats, 1661 sizeof(u64), GFP_KERNEL); 1662 if (!ocelot->stats) 1663 return -ENOMEM; 1664 1665 mutex_init(&ocelot->stats_lock); 1666 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1667 dev_name(ocelot->dev)); 1668 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1669 if (!ocelot->stats_queue) 1670 return -ENOMEM; 1671 1672 ocelot_mact_init(ocelot); 1673 ocelot_vlan_init(ocelot); 1674 1675 for (port = 0; port < ocelot->num_phys_ports; port++) { 1676 /* Clear all counters (5 groups) */ 1677 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1678 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1679 SYS_STAT_CFG); 1680 } 1681 1682 /* Only use S-Tag */ 1683 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1684 1685 /* Aggregation mode */ 1686 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1687 ANA_AGGR_CFG_AC_DMAC_ENA | 1688 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1689 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1690 1691 /* Set MAC age time to default value. The entry is aged after 1692 * 2*AGE_PERIOD 1693 */ 1694 ocelot_write(ocelot, 1695 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1696 ANA_AUTOAGE); 1697 1698 /* Disable learning for frames discarded by VLAN ingress filtering */ 1699 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1700 1701 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1702 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1703 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1704 1705 /* Setup flooding PGIDs */ 1706 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1707 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1708 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1709 ANA_FLOODING, 0); 1710 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1711 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1712 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1713 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1714 ANA_FLOODING_IPMC); 1715 1716 for (port = 0; port < ocelot->num_phys_ports; port++) { 1717 /* Transmit the frame to the local port. */ 1718 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1719 /* Do not forward BPDU frames to the front ports. */ 1720 ocelot_write_gix(ocelot, 1721 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1722 ANA_PORT_CPU_FWD_BPDU_CFG, 1723 port); 1724 /* Ensure bridging is disabled */ 1725 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1726 } 1727 1728 /* Configure and enable the CPU port. */ 1729 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1730 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1731 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1732 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1733 ANA_PORT_PORT_CFG, cpu); 1734 1735 /* Allow broadcast MAC frames. */ 1736 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 1737 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1738 1739 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1740 } 1741 ocelot_write_rix(ocelot, 1742 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1743 ANA_PGID_PGID, PGID_MC); 1744 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1745 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1746 1747 /* CPU port Injection/Extraction configuration */ 1748 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1749 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1750 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1751 QSYS_SWITCH_PORT_MODE, cpu); 1752 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) | 1753 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu); 1754 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1755 * registers endianness. 1756 */ 1757 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1758 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1759 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1760 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1761 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1762 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1763 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1764 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1765 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1766 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1767 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1768 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1769 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1770 for (i = 0; i < 16; i++) 1771 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1772 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1773 ANA_CPUQ_8021_CFG, i); 1774 1775 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats); 1776 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1777 OCELOT_STATS_CHECK_DELAY); 1778 return 0; 1779 } 1780 EXPORT_SYMBOL(ocelot_init); 1781 1782 void ocelot_deinit(struct ocelot *ocelot) 1783 { 1784 destroy_workqueue(ocelot->stats_queue); 1785 mutex_destroy(&ocelot->stats_lock); 1786 } 1787 EXPORT_SYMBOL(ocelot_deinit); 1788 1789 MODULE_LICENSE("Dual MIT/GPL"); 1790