1 /* MOXA ART Ethernet (RTL8201CP) driver. 2 * 3 * Copyright (C) 2013 Jonas Jensen 4 * 5 * Jonas Jensen <jonas.jensen@gmail.com> 6 * 7 * Based on code from 8 * Moxa Technology Co., Ltd. <www.moxa.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/skbuff.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/ethtool.h> 21 #include <linux/platform_device.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/crc32.h> 27 #include <linux/crc32c.h> 28 #include <linux/circ_buf.h> 29 30 #include "moxart_ether.h" 31 32 static inline void moxart_desc_write(u32 data, u32 *desc) 33 { 34 *desc = cpu_to_le32(data); 35 } 36 37 static inline u32 moxart_desc_read(u32 *desc) 38 { 39 return le32_to_cpu(*desc); 40 } 41 42 static inline void moxart_emac_write(struct net_device *ndev, 43 unsigned int reg, unsigned long value) 44 { 45 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 46 47 writel(value, priv->base + reg); 48 } 49 50 static void moxart_update_mac_address(struct net_device *ndev) 51 { 52 moxart_emac_write(ndev, REG_MAC_MS_ADDRESS, 53 ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]))); 54 moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4, 55 ((ndev->dev_addr[2] << 24) | 56 (ndev->dev_addr[3] << 16) | 57 (ndev->dev_addr[4] << 8) | 58 (ndev->dev_addr[5]))); 59 } 60 61 static int moxart_set_mac_address(struct net_device *ndev, void *addr) 62 { 63 struct sockaddr *address = addr; 64 65 eth_hw_addr_set(ndev, address->sa_data); 66 moxart_update_mac_address(ndev); 67 68 return 0; 69 } 70 71 static void moxart_mac_free_memory(struct net_device *ndev) 72 { 73 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 74 int i; 75 76 for (i = 0; i < RX_DESC_NUM; i++) 77 dma_unmap_single(&priv->pdev->dev, priv->rx_mapping[i], 78 priv->rx_buf_size, DMA_FROM_DEVICE); 79 80 if (priv->tx_desc_base) 81 dma_free_coherent(&priv->pdev->dev, 82 TX_REG_DESC_SIZE * TX_DESC_NUM, 83 priv->tx_desc_base, priv->tx_base); 84 85 if (priv->rx_desc_base) 86 dma_free_coherent(&priv->pdev->dev, 87 RX_REG_DESC_SIZE * RX_DESC_NUM, 88 priv->rx_desc_base, priv->rx_base); 89 90 kfree(priv->tx_buf_base); 91 kfree(priv->rx_buf_base); 92 } 93 94 static void moxart_mac_reset(struct net_device *ndev) 95 { 96 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 97 98 writel(SW_RST, priv->base + REG_MAC_CTRL); 99 while (readl(priv->base + REG_MAC_CTRL) & SW_RST) 100 mdelay(10); 101 102 writel(0, priv->base + REG_INTERRUPT_MASK); 103 104 priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL; 105 } 106 107 static void moxart_mac_enable(struct net_device *ndev) 108 { 109 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 110 111 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); 112 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); 113 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); 114 115 priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M); 116 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 117 118 priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN); 119 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); 120 } 121 122 static void moxart_mac_setup_desc_ring(struct net_device *ndev) 123 { 124 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 125 void *desc; 126 int i; 127 128 for (i = 0; i < TX_DESC_NUM; i++) { 129 desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE; 130 memset(desc, 0, TX_REG_DESC_SIZE); 131 132 priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i; 133 } 134 moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1); 135 136 priv->tx_head = 0; 137 priv->tx_tail = 0; 138 139 for (i = 0; i < RX_DESC_NUM; i++) { 140 desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE; 141 memset(desc, 0, RX_REG_DESC_SIZE); 142 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); 143 moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK, 144 desc + RX_REG_OFFSET_DESC1); 145 146 priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i; 147 priv->rx_mapping[i] = dma_map_single(&priv->pdev->dev, 148 priv->rx_buf[i], 149 priv->rx_buf_size, 150 DMA_FROM_DEVICE); 151 if (dma_mapping_error(&priv->pdev->dev, priv->rx_mapping[i])) 152 netdev_err(ndev, "DMA mapping error\n"); 153 154 moxart_desc_write(priv->rx_mapping[i], 155 desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS); 156 moxart_desc_write((uintptr_t)priv->rx_buf[i], 157 desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT); 158 } 159 moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1); 160 161 priv->rx_head = 0; 162 163 /* reset the MAC controller TX/RX descriptor base address */ 164 writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS); 165 writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS); 166 } 167 168 static int moxart_mac_open(struct net_device *ndev) 169 { 170 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 171 172 napi_enable(&priv->napi); 173 174 moxart_mac_reset(ndev); 175 moxart_update_mac_address(ndev); 176 moxart_mac_setup_desc_ring(ndev); 177 moxart_mac_enable(ndev); 178 netif_start_queue(ndev); 179 180 netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n", 181 __func__, readl(priv->base + REG_INTERRUPT_MASK), 182 readl(priv->base + REG_MAC_CTRL)); 183 184 return 0; 185 } 186 187 static int moxart_mac_stop(struct net_device *ndev) 188 { 189 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 190 191 napi_disable(&priv->napi); 192 193 netif_stop_queue(ndev); 194 195 /* disable all interrupts */ 196 writel(0, priv->base + REG_INTERRUPT_MASK); 197 198 /* disable all functions */ 199 writel(0, priv->base + REG_MAC_CTRL); 200 201 return 0; 202 } 203 204 static int moxart_rx_poll(struct napi_struct *napi, int budget) 205 { 206 struct moxart_mac_priv_t *priv = container_of(napi, 207 struct moxart_mac_priv_t, 208 napi); 209 struct net_device *ndev = priv->ndev; 210 struct sk_buff *skb; 211 void *desc; 212 unsigned int desc0, len; 213 int rx_head = priv->rx_head; 214 int rx = 0; 215 216 while (rx < budget) { 217 desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head); 218 desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0); 219 rmb(); /* ensure desc0 is up to date */ 220 221 if (desc0 & RX_DESC0_DMA_OWN) 222 break; 223 224 if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL | 225 RX_DESC0_RUNT | RX_DESC0_ODD_NB)) { 226 net_dbg_ratelimited("packet error\n"); 227 ndev->stats.rx_dropped++; 228 ndev->stats.rx_errors++; 229 goto rx_next; 230 } 231 232 len = desc0 & RX_DESC0_FRAME_LEN_MASK; 233 234 if (len > RX_BUF_SIZE) 235 len = RX_BUF_SIZE; 236 237 dma_sync_single_for_cpu(&priv->pdev->dev, 238 priv->rx_mapping[rx_head], 239 priv->rx_buf_size, DMA_FROM_DEVICE); 240 skb = netdev_alloc_skb_ip_align(ndev, len); 241 242 if (unlikely(!skb)) { 243 net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n"); 244 ndev->stats.rx_dropped++; 245 ndev->stats.rx_errors++; 246 goto rx_next; 247 } 248 249 memcpy(skb->data, priv->rx_buf[rx_head], len); 250 skb_put(skb, len); 251 skb->protocol = eth_type_trans(skb, ndev); 252 napi_gro_receive(&priv->napi, skb); 253 rx++; 254 255 ndev->stats.rx_packets++; 256 ndev->stats.rx_bytes += len; 257 if (desc0 & RX_DESC0_MULTICAST) 258 ndev->stats.multicast++; 259 260 rx_next: 261 wmb(); /* prevent setting ownership back too early */ 262 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); 263 264 rx_head = RX_NEXT(rx_head); 265 priv->rx_head = rx_head; 266 } 267 268 if (rx < budget) 269 napi_complete_done(napi, rx); 270 271 priv->reg_imr |= RPKT_FINISH_M; 272 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 273 274 return rx; 275 } 276 277 static int moxart_tx_queue_space(struct net_device *ndev) 278 { 279 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 280 281 return CIRC_SPACE(priv->tx_head, priv->tx_tail, TX_DESC_NUM); 282 } 283 284 static void moxart_tx_finished(struct net_device *ndev) 285 { 286 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 287 unsigned int tx_head = priv->tx_head; 288 unsigned int tx_tail = priv->tx_tail; 289 290 while (tx_tail != tx_head) { 291 dma_unmap_single(&priv->pdev->dev, priv->tx_mapping[tx_tail], 292 priv->tx_len[tx_tail], DMA_TO_DEVICE); 293 294 ndev->stats.tx_packets++; 295 ndev->stats.tx_bytes += priv->tx_skb[tx_tail]->len; 296 297 dev_consume_skb_irq(priv->tx_skb[tx_tail]); 298 priv->tx_skb[tx_tail] = NULL; 299 300 tx_tail = TX_NEXT(tx_tail); 301 } 302 priv->tx_tail = tx_tail; 303 if (netif_queue_stopped(ndev) && 304 moxart_tx_queue_space(ndev) >= TX_WAKE_THRESHOLD) 305 netif_wake_queue(ndev); 306 } 307 308 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id) 309 { 310 struct net_device *ndev = (struct net_device *)dev_id; 311 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 312 unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS); 313 314 if (ists & XPKT_OK_INT_STS) 315 moxart_tx_finished(ndev); 316 317 if (ists & RPKT_FINISH) { 318 if (napi_schedule_prep(&priv->napi)) { 319 priv->reg_imr &= ~RPKT_FINISH_M; 320 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 321 __napi_schedule(&priv->napi); 322 } 323 } 324 325 return IRQ_HANDLED; 326 } 327 328 static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb, 329 struct net_device *ndev) 330 { 331 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 332 void *desc; 333 unsigned int len; 334 unsigned int tx_head; 335 u32 txdes1; 336 netdev_tx_t ret = NETDEV_TX_BUSY; 337 338 spin_lock_irq(&priv->txlock); 339 340 tx_head = priv->tx_head; 341 desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head); 342 343 if (moxart_tx_queue_space(ndev) == 1) 344 netif_stop_queue(ndev); 345 346 if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) { 347 net_dbg_ratelimited("no TX space for packet\n"); 348 ndev->stats.tx_dropped++; 349 goto out_unlock; 350 } 351 rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */ 352 353 len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len; 354 355 priv->tx_mapping[tx_head] = dma_map_single(&priv->pdev->dev, skb->data, 356 len, DMA_TO_DEVICE); 357 if (dma_mapping_error(&priv->pdev->dev, priv->tx_mapping[tx_head])) { 358 netdev_err(ndev, "DMA mapping error\n"); 359 goto out_unlock; 360 } 361 362 priv->tx_len[tx_head] = len; 363 priv->tx_skb[tx_head] = skb; 364 365 moxart_desc_write(priv->tx_mapping[tx_head], 366 desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS); 367 moxart_desc_write((uintptr_t)skb->data, 368 desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT); 369 370 if (skb->len < ETH_ZLEN) { 371 memset(&skb->data[skb->len], 372 0, ETH_ZLEN - skb->len); 373 len = ETH_ZLEN; 374 } 375 376 dma_sync_single_for_device(&priv->pdev->dev, priv->tx_mapping[tx_head], 377 priv->tx_buf_size, DMA_TO_DEVICE); 378 379 txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK); 380 if (tx_head == TX_DESC_NUM_MASK) 381 txdes1 |= TX_DESC1_END; 382 moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1); 383 wmb(); /* flush descriptor before transferring ownership */ 384 moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0); 385 386 /* start to send packet */ 387 writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND); 388 389 priv->tx_head = TX_NEXT(tx_head); 390 391 netif_trans_update(ndev); 392 ret = NETDEV_TX_OK; 393 out_unlock: 394 spin_unlock_irq(&priv->txlock); 395 396 return ret; 397 } 398 399 static void moxart_mac_setmulticast(struct net_device *ndev) 400 { 401 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 402 struct netdev_hw_addr *ha; 403 int crc_val; 404 405 netdev_for_each_mc_addr(ha, ndev) { 406 crc_val = crc32_le(~0, ha->addr, ETH_ALEN); 407 crc_val = (crc_val >> 26) & 0x3f; 408 if (crc_val >= 32) { 409 writel(readl(priv->base + REG_MCAST_HASH_TABLE1) | 410 (1UL << (crc_val - 32)), 411 priv->base + REG_MCAST_HASH_TABLE1); 412 } else { 413 writel(readl(priv->base + REG_MCAST_HASH_TABLE0) | 414 (1UL << crc_val), 415 priv->base + REG_MCAST_HASH_TABLE0); 416 } 417 } 418 } 419 420 static void moxart_mac_set_rx_mode(struct net_device *ndev) 421 { 422 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 423 424 spin_lock_irq(&priv->txlock); 425 426 (ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) : 427 (priv->reg_maccr &= ~RCV_ALL); 428 429 (ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) : 430 (priv->reg_maccr &= ~RX_MULTIPKT); 431 432 if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) { 433 priv->reg_maccr |= HT_MULTI_EN; 434 moxart_mac_setmulticast(ndev); 435 } else { 436 priv->reg_maccr &= ~HT_MULTI_EN; 437 } 438 439 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); 440 441 spin_unlock_irq(&priv->txlock); 442 } 443 444 static const struct net_device_ops moxart_netdev_ops = { 445 .ndo_open = moxart_mac_open, 446 .ndo_stop = moxart_mac_stop, 447 .ndo_start_xmit = moxart_mac_start_xmit, 448 .ndo_set_rx_mode = moxart_mac_set_rx_mode, 449 .ndo_set_mac_address = moxart_set_mac_address, 450 .ndo_validate_addr = eth_validate_addr, 451 }; 452 453 static int moxart_mac_probe(struct platform_device *pdev) 454 { 455 struct device *p_dev = &pdev->dev; 456 struct device_node *node = p_dev->of_node; 457 struct net_device *ndev; 458 struct moxart_mac_priv_t *priv; 459 struct resource *res; 460 unsigned int irq; 461 int ret; 462 463 ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t)); 464 if (!ndev) 465 return -ENOMEM; 466 467 irq = irq_of_parse_and_map(node, 0); 468 if (irq <= 0) { 469 netdev_err(ndev, "irq_of_parse_and_map failed\n"); 470 ret = -EINVAL; 471 goto irq_map_fail; 472 } 473 474 priv = netdev_priv(ndev); 475 priv->ndev = ndev; 476 priv->pdev = pdev; 477 478 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 479 if (IS_ERR(priv->base)) { 480 ret = PTR_ERR(priv->base); 481 goto init_fail; 482 } 483 ndev->base_addr = res->start; 484 485 ret = platform_get_ethdev_address(p_dev, ndev); 486 if (ret == -EPROBE_DEFER) 487 goto init_fail; 488 if (ret) 489 eth_hw_addr_random(ndev); 490 moxart_update_mac_address(ndev); 491 492 spin_lock_init(&priv->txlock); 493 494 priv->tx_buf_size = TX_BUF_SIZE; 495 priv->rx_buf_size = RX_BUF_SIZE; 496 497 priv->tx_desc_base = dma_alloc_coherent(p_dev, TX_REG_DESC_SIZE * 498 TX_DESC_NUM, &priv->tx_base, 499 GFP_DMA | GFP_KERNEL); 500 if (!priv->tx_desc_base) { 501 ret = -ENOMEM; 502 goto init_fail; 503 } 504 505 priv->rx_desc_base = dma_alloc_coherent(p_dev, RX_REG_DESC_SIZE * 506 RX_DESC_NUM, &priv->rx_base, 507 GFP_DMA | GFP_KERNEL); 508 if (!priv->rx_desc_base) { 509 ret = -ENOMEM; 510 goto init_fail; 511 } 512 513 priv->tx_buf_base = kmalloc_array(priv->tx_buf_size, TX_DESC_NUM, 514 GFP_KERNEL); 515 if (!priv->tx_buf_base) { 516 ret = -ENOMEM; 517 goto init_fail; 518 } 519 520 priv->rx_buf_base = kmalloc_array(priv->rx_buf_size, RX_DESC_NUM, 521 GFP_KERNEL); 522 if (!priv->rx_buf_base) { 523 ret = -ENOMEM; 524 goto init_fail; 525 } 526 527 platform_set_drvdata(pdev, ndev); 528 529 ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0, 530 pdev->name, ndev); 531 if (ret) { 532 netdev_err(ndev, "devm_request_irq failed\n"); 533 goto init_fail; 534 } 535 536 ndev->netdev_ops = &moxart_netdev_ops; 537 netif_napi_add_weight(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM); 538 ndev->priv_flags |= IFF_UNICAST_FLT; 539 ndev->irq = irq; 540 541 SET_NETDEV_DEV(ndev, &pdev->dev); 542 543 ret = register_netdev(ndev); 544 if (ret) 545 goto init_fail; 546 547 netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n", 548 __func__, ndev->irq, ndev->dev_addr); 549 550 return 0; 551 552 init_fail: 553 netdev_err(ndev, "init failed\n"); 554 moxart_mac_free_memory(ndev); 555 irq_map_fail: 556 free_netdev(ndev); 557 return ret; 558 } 559 560 static int moxart_remove(struct platform_device *pdev) 561 { 562 struct net_device *ndev = platform_get_drvdata(pdev); 563 564 unregister_netdev(ndev); 565 devm_free_irq(&pdev->dev, ndev->irq, ndev); 566 moxart_mac_free_memory(ndev); 567 free_netdev(ndev); 568 569 return 0; 570 } 571 572 static const struct of_device_id moxart_mac_match[] = { 573 { .compatible = "moxa,moxart-mac" }, 574 { } 575 }; 576 MODULE_DEVICE_TABLE(of, moxart_mac_match); 577 578 static struct platform_driver moxart_mac_driver = { 579 .probe = moxart_mac_probe, 580 .remove = moxart_remove, 581 .driver = { 582 .name = "moxart-ethernet", 583 .of_match_table = moxart_mac_match, 584 }, 585 }; 586 module_platform_driver(moxart_mac_driver); 587 588 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver"); 589 MODULE_LICENSE("GPL v2"); 590 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); 591