1 /* MOXA ART Ethernet (RTL8201CP) driver. 2 * 3 * Copyright (C) 2013 Jonas Jensen 4 * 5 * Jonas Jensen <jonas.jensen@gmail.com> 6 * 7 * Based on code from 8 * Moxa Technology Co., Ltd. <www.moxa.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/skbuff.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/ethtool.h> 21 #include <linux/platform_device.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/crc32.h> 27 #include <linux/crc32c.h> 28 #include <linux/circ_buf.h> 29 30 #include "moxart_ether.h" 31 32 static inline void moxart_desc_write(u32 data, u32 *desc) 33 { 34 *desc = cpu_to_le32(data); 35 } 36 37 static inline u32 moxart_desc_read(u32 *desc) 38 { 39 return le32_to_cpu(*desc); 40 } 41 42 static inline void moxart_emac_write(struct net_device *ndev, 43 unsigned int reg, unsigned long value) 44 { 45 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 46 47 writel(value, priv->base + reg); 48 } 49 50 static void moxart_update_mac_address(struct net_device *ndev) 51 { 52 moxart_emac_write(ndev, REG_MAC_MS_ADDRESS, 53 ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]))); 54 moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4, 55 ((ndev->dev_addr[2] << 24) | 56 (ndev->dev_addr[3] << 16) | 57 (ndev->dev_addr[4] << 8) | 58 (ndev->dev_addr[5]))); 59 } 60 61 static int moxart_set_mac_address(struct net_device *ndev, void *addr) 62 { 63 struct sockaddr *address = addr; 64 65 if (!is_valid_ether_addr(address->sa_data)) 66 return -EADDRNOTAVAIL; 67 68 memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len); 69 moxart_update_mac_address(ndev); 70 71 return 0; 72 } 73 74 static void moxart_mac_free_memory(struct net_device *ndev) 75 { 76 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 77 int i; 78 79 for (i = 0; i < RX_DESC_NUM; i++) 80 dma_unmap_single(&ndev->dev, priv->rx_mapping[i], 81 priv->rx_buf_size, DMA_FROM_DEVICE); 82 83 if (priv->tx_desc_base) 84 dma_free_coherent(NULL, TX_REG_DESC_SIZE * TX_DESC_NUM, 85 priv->tx_desc_base, priv->tx_base); 86 87 if (priv->rx_desc_base) 88 dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM, 89 priv->rx_desc_base, priv->rx_base); 90 91 kfree(priv->tx_buf_base); 92 kfree(priv->rx_buf_base); 93 } 94 95 static void moxart_mac_reset(struct net_device *ndev) 96 { 97 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 98 99 writel(SW_RST, priv->base + REG_MAC_CTRL); 100 while (readl(priv->base + REG_MAC_CTRL) & SW_RST) 101 mdelay(10); 102 103 writel(0, priv->base + REG_INTERRUPT_MASK); 104 105 priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL; 106 } 107 108 static void moxart_mac_enable(struct net_device *ndev) 109 { 110 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 111 112 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); 113 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); 114 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); 115 116 priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M); 117 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 118 119 priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN); 120 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); 121 } 122 123 static void moxart_mac_setup_desc_ring(struct net_device *ndev) 124 { 125 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 126 void *desc; 127 int i; 128 129 for (i = 0; i < TX_DESC_NUM; i++) { 130 desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE; 131 memset(desc, 0, TX_REG_DESC_SIZE); 132 133 priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i; 134 } 135 moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1); 136 137 priv->tx_head = 0; 138 priv->tx_tail = 0; 139 140 for (i = 0; i < RX_DESC_NUM; i++) { 141 desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE; 142 memset(desc, 0, RX_REG_DESC_SIZE); 143 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); 144 moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK, 145 desc + RX_REG_OFFSET_DESC1); 146 147 priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i; 148 priv->rx_mapping[i] = dma_map_single(&ndev->dev, 149 priv->rx_buf[i], 150 priv->rx_buf_size, 151 DMA_FROM_DEVICE); 152 if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i])) 153 netdev_err(ndev, "DMA mapping error\n"); 154 155 moxart_desc_write(priv->rx_mapping[i], 156 desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS); 157 moxart_desc_write((uintptr_t)priv->rx_buf[i], 158 desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT); 159 } 160 moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1); 161 162 priv->rx_head = 0; 163 164 /* reset the MAC controller TX/RX desciptor base address */ 165 writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS); 166 writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS); 167 } 168 169 static int moxart_mac_open(struct net_device *ndev) 170 { 171 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 172 173 if (!is_valid_ether_addr(ndev->dev_addr)) 174 return -EADDRNOTAVAIL; 175 176 napi_enable(&priv->napi); 177 178 moxart_mac_reset(ndev); 179 moxart_update_mac_address(ndev); 180 moxart_mac_setup_desc_ring(ndev); 181 moxart_mac_enable(ndev); 182 netif_start_queue(ndev); 183 184 netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n", 185 __func__, readl(priv->base + REG_INTERRUPT_MASK), 186 readl(priv->base + REG_MAC_CTRL)); 187 188 return 0; 189 } 190 191 static int moxart_mac_stop(struct net_device *ndev) 192 { 193 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 194 195 napi_disable(&priv->napi); 196 197 netif_stop_queue(ndev); 198 199 /* disable all interrupts */ 200 writel(0, priv->base + REG_INTERRUPT_MASK); 201 202 /* disable all functions */ 203 writel(0, priv->base + REG_MAC_CTRL); 204 205 return 0; 206 } 207 208 static int moxart_rx_poll(struct napi_struct *napi, int budget) 209 { 210 struct moxart_mac_priv_t *priv = container_of(napi, 211 struct moxart_mac_priv_t, 212 napi); 213 struct net_device *ndev = priv->ndev; 214 struct sk_buff *skb; 215 void *desc; 216 unsigned int desc0, len; 217 int rx_head = priv->rx_head; 218 int rx = 0; 219 220 while (rx < budget) { 221 desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head); 222 desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0); 223 rmb(); /* ensure desc0 is up to date */ 224 225 if (desc0 & RX_DESC0_DMA_OWN) 226 break; 227 228 if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL | 229 RX_DESC0_RUNT | RX_DESC0_ODD_NB)) { 230 net_dbg_ratelimited("packet error\n"); 231 priv->stats.rx_dropped++; 232 priv->stats.rx_errors++; 233 goto rx_next; 234 } 235 236 len = desc0 & RX_DESC0_FRAME_LEN_MASK; 237 238 if (len > RX_BUF_SIZE) 239 len = RX_BUF_SIZE; 240 241 dma_sync_single_for_cpu(&ndev->dev, 242 priv->rx_mapping[rx_head], 243 priv->rx_buf_size, DMA_FROM_DEVICE); 244 skb = netdev_alloc_skb_ip_align(ndev, len); 245 246 if (unlikely(!skb)) { 247 net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n"); 248 priv->stats.rx_dropped++; 249 priv->stats.rx_errors++; 250 goto rx_next; 251 } 252 253 memcpy(skb->data, priv->rx_buf[rx_head], len); 254 skb_put(skb, len); 255 skb->protocol = eth_type_trans(skb, ndev); 256 napi_gro_receive(&priv->napi, skb); 257 rx++; 258 259 priv->stats.rx_packets++; 260 priv->stats.rx_bytes += len; 261 if (desc0 & RX_DESC0_MULTICAST) 262 priv->stats.multicast++; 263 264 rx_next: 265 wmb(); /* prevent setting ownership back too early */ 266 moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); 267 268 rx_head = RX_NEXT(rx_head); 269 priv->rx_head = rx_head; 270 } 271 272 if (rx < budget) { 273 napi_complete_done(napi, rx); 274 } 275 276 priv->reg_imr |= RPKT_FINISH_M; 277 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 278 279 return rx; 280 } 281 282 static int moxart_tx_queue_space(struct net_device *ndev) 283 { 284 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 285 286 return CIRC_SPACE(priv->tx_head, priv->tx_tail, TX_DESC_NUM); 287 } 288 289 static void moxart_tx_finished(struct net_device *ndev) 290 { 291 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 292 unsigned tx_head = priv->tx_head; 293 unsigned tx_tail = priv->tx_tail; 294 295 while (tx_tail != tx_head) { 296 dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail], 297 priv->tx_len[tx_tail], DMA_TO_DEVICE); 298 299 priv->stats.tx_packets++; 300 priv->stats.tx_bytes += priv->tx_skb[tx_tail]->len; 301 302 dev_kfree_skb_irq(priv->tx_skb[tx_tail]); 303 priv->tx_skb[tx_tail] = NULL; 304 305 tx_tail = TX_NEXT(tx_tail); 306 } 307 priv->tx_tail = tx_tail; 308 if (netif_queue_stopped(ndev) && 309 moxart_tx_queue_space(ndev) >= TX_WAKE_THRESHOLD) 310 netif_wake_queue(ndev); 311 } 312 313 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id) 314 { 315 struct net_device *ndev = (struct net_device *) dev_id; 316 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 317 unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS); 318 319 if (ists & XPKT_OK_INT_STS) 320 moxart_tx_finished(ndev); 321 322 if (ists & RPKT_FINISH) { 323 if (napi_schedule_prep(&priv->napi)) { 324 priv->reg_imr &= ~RPKT_FINISH_M; 325 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); 326 __napi_schedule(&priv->napi); 327 } 328 } 329 330 return IRQ_HANDLED; 331 } 332 333 static int moxart_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev) 334 { 335 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 336 void *desc; 337 unsigned int len; 338 unsigned int tx_head; 339 u32 txdes1; 340 int ret = NETDEV_TX_BUSY; 341 342 spin_lock_irq(&priv->txlock); 343 344 tx_head = priv->tx_head; 345 desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head); 346 347 if (moxart_tx_queue_space(ndev) == 1) 348 netif_stop_queue(ndev); 349 350 if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) { 351 net_dbg_ratelimited("no TX space for packet\n"); 352 priv->stats.tx_dropped++; 353 goto out_unlock; 354 } 355 rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */ 356 357 len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len; 358 359 priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data, 360 len, DMA_TO_DEVICE); 361 if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) { 362 netdev_err(ndev, "DMA mapping error\n"); 363 goto out_unlock; 364 } 365 366 priv->tx_len[tx_head] = len; 367 priv->tx_skb[tx_head] = skb; 368 369 moxart_desc_write(priv->tx_mapping[tx_head], 370 desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS); 371 moxart_desc_write((uintptr_t)skb->data, 372 desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT); 373 374 if (skb->len < ETH_ZLEN) { 375 memset(&skb->data[skb->len], 376 0, ETH_ZLEN - skb->len); 377 len = ETH_ZLEN; 378 } 379 380 dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head], 381 priv->tx_buf_size, DMA_TO_DEVICE); 382 383 txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK); 384 if (tx_head == TX_DESC_NUM_MASK) 385 txdes1 |= TX_DESC1_END; 386 moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1); 387 wmb(); /* flush descriptor before transferring ownership */ 388 moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0); 389 390 /* start to send packet */ 391 writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND); 392 393 priv->tx_head = TX_NEXT(tx_head); 394 395 netif_trans_update(ndev); 396 ret = NETDEV_TX_OK; 397 out_unlock: 398 spin_unlock_irq(&priv->txlock); 399 400 return ret; 401 } 402 403 static struct net_device_stats *moxart_mac_get_stats(struct net_device *ndev) 404 { 405 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 406 407 return &priv->stats; 408 } 409 410 static void moxart_mac_setmulticast(struct net_device *ndev) 411 { 412 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 413 struct netdev_hw_addr *ha; 414 int crc_val; 415 416 netdev_for_each_mc_addr(ha, ndev) { 417 crc_val = crc32_le(~0, ha->addr, ETH_ALEN); 418 crc_val = (crc_val >> 26) & 0x3f; 419 if (crc_val >= 32) { 420 writel(readl(priv->base + REG_MCAST_HASH_TABLE1) | 421 (1UL << (crc_val - 32)), 422 priv->base + REG_MCAST_HASH_TABLE1); 423 } else { 424 writel(readl(priv->base + REG_MCAST_HASH_TABLE0) | 425 (1UL << crc_val), 426 priv->base + REG_MCAST_HASH_TABLE0); 427 } 428 } 429 } 430 431 static void moxart_mac_set_rx_mode(struct net_device *ndev) 432 { 433 struct moxart_mac_priv_t *priv = netdev_priv(ndev); 434 435 spin_lock_irq(&priv->txlock); 436 437 (ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) : 438 (priv->reg_maccr &= ~RCV_ALL); 439 440 (ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) : 441 (priv->reg_maccr &= ~RX_MULTIPKT); 442 443 if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) { 444 priv->reg_maccr |= HT_MULTI_EN; 445 moxart_mac_setmulticast(ndev); 446 } else { 447 priv->reg_maccr &= ~HT_MULTI_EN; 448 } 449 450 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); 451 452 spin_unlock_irq(&priv->txlock); 453 } 454 455 static const struct net_device_ops moxart_netdev_ops = { 456 .ndo_open = moxart_mac_open, 457 .ndo_stop = moxart_mac_stop, 458 .ndo_start_xmit = moxart_mac_start_xmit, 459 .ndo_get_stats = moxart_mac_get_stats, 460 .ndo_set_rx_mode = moxart_mac_set_rx_mode, 461 .ndo_set_mac_address = moxart_set_mac_address, 462 .ndo_validate_addr = eth_validate_addr, 463 }; 464 465 static int moxart_mac_probe(struct platform_device *pdev) 466 { 467 struct device *p_dev = &pdev->dev; 468 struct device_node *node = p_dev->of_node; 469 struct net_device *ndev; 470 struct moxart_mac_priv_t *priv; 471 struct resource *res; 472 unsigned int irq; 473 int ret; 474 475 ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t)); 476 if (!ndev) 477 return -ENOMEM; 478 479 irq = irq_of_parse_and_map(node, 0); 480 if (irq <= 0) { 481 netdev_err(ndev, "irq_of_parse_and_map failed\n"); 482 ret = -EINVAL; 483 goto irq_map_fail; 484 } 485 486 priv = netdev_priv(ndev); 487 priv->ndev = ndev; 488 489 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 490 ndev->base_addr = res->start; 491 priv->base = devm_ioremap_resource(p_dev, res); 492 if (IS_ERR(priv->base)) { 493 dev_err(p_dev, "devm_ioremap_resource failed\n"); 494 ret = PTR_ERR(priv->base); 495 goto init_fail; 496 } 497 498 spin_lock_init(&priv->txlock); 499 500 priv->tx_buf_size = TX_BUF_SIZE; 501 priv->rx_buf_size = RX_BUF_SIZE; 502 503 priv->tx_desc_base = dma_alloc_coherent(NULL, TX_REG_DESC_SIZE * 504 TX_DESC_NUM, &priv->tx_base, 505 GFP_DMA | GFP_KERNEL); 506 if (priv->tx_desc_base == NULL) { 507 ret = -ENOMEM; 508 goto init_fail; 509 } 510 511 priv->rx_desc_base = dma_alloc_coherent(NULL, RX_REG_DESC_SIZE * 512 RX_DESC_NUM, &priv->rx_base, 513 GFP_DMA | GFP_KERNEL); 514 if (priv->rx_desc_base == NULL) { 515 ret = -ENOMEM; 516 goto init_fail; 517 } 518 519 priv->tx_buf_base = kmalloc(priv->tx_buf_size * TX_DESC_NUM, 520 GFP_ATOMIC); 521 if (!priv->tx_buf_base) { 522 ret = -ENOMEM; 523 goto init_fail; 524 } 525 526 priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM, 527 GFP_ATOMIC); 528 if (!priv->rx_buf_base) { 529 ret = -ENOMEM; 530 goto init_fail; 531 } 532 533 platform_set_drvdata(pdev, ndev); 534 535 ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0, 536 pdev->name, ndev); 537 if (ret) { 538 netdev_err(ndev, "devm_request_irq failed\n"); 539 goto init_fail; 540 } 541 542 ndev->netdev_ops = &moxart_netdev_ops; 543 netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM); 544 ndev->priv_flags |= IFF_UNICAST_FLT; 545 ndev->irq = irq; 546 547 SET_NETDEV_DEV(ndev, &pdev->dev); 548 549 ret = register_netdev(ndev); 550 if (ret) { 551 free_netdev(ndev); 552 goto init_fail; 553 } 554 555 netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n", 556 __func__, ndev->irq, ndev->dev_addr); 557 558 return 0; 559 560 init_fail: 561 netdev_err(ndev, "init failed\n"); 562 moxart_mac_free_memory(ndev); 563 irq_map_fail: 564 free_netdev(ndev); 565 return ret; 566 } 567 568 static int moxart_remove(struct platform_device *pdev) 569 { 570 struct net_device *ndev = platform_get_drvdata(pdev); 571 572 unregister_netdev(ndev); 573 free_irq(ndev->irq, ndev); 574 moxart_mac_free_memory(ndev); 575 free_netdev(ndev); 576 577 return 0; 578 } 579 580 static const struct of_device_id moxart_mac_match[] = { 581 { .compatible = "moxa,moxart-mac" }, 582 { } 583 }; 584 MODULE_DEVICE_TABLE(of, moxart_mac_match); 585 586 static struct platform_driver moxart_mac_driver = { 587 .probe = moxart_mac_probe, 588 .remove = moxart_remove, 589 .driver = { 590 .name = "moxart-ethernet", 591 .of_match_table = moxart_mac_match, 592 }, 593 }; 594 module_platform_driver(moxart_mac_driver); 595 596 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver"); 597 MODULE_LICENSE("GPL v2"); 598 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); 599