1 /* MOXA ART Ethernet (RTL8201CP) driver.
2  *
3  * Copyright (C) 2013 Jonas Jensen
4  *
5  * Jonas Jensen <jonas.jensen@gmail.com>
6  *
7  * Based on code from
8  * Moxa Technology Co., Ltd. <www.moxa.com>
9  *
10  * This file is licensed under the terms of the GNU General Public
11  * License version 2.  This program is licensed "as is" without any
12  * warranty of any kind, whether express or implied.
13  */
14 
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/skbuff.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/ethtool.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/crc32.h>
27 #include <linux/crc32c.h>
28 #include <linux/circ_buf.h>
29 
30 #include "moxart_ether.h"
31 
32 static inline void moxart_desc_write(u32 data, u32 *desc)
33 {
34 	*desc = cpu_to_le32(data);
35 }
36 
37 static inline u32 moxart_desc_read(u32 *desc)
38 {
39 	return le32_to_cpu(*desc);
40 }
41 
42 static inline void moxart_emac_write(struct net_device *ndev,
43 				     unsigned int reg, unsigned long value)
44 {
45 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
46 
47 	writel(value, priv->base + reg);
48 }
49 
50 static void moxart_update_mac_address(struct net_device *ndev)
51 {
52 	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
53 			  ((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
54 	moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
55 			  ((ndev->dev_addr[2] << 24) |
56 			   (ndev->dev_addr[3] << 16) |
57 			   (ndev->dev_addr[4] << 8) |
58 			   (ndev->dev_addr[5])));
59 }
60 
61 static int moxart_set_mac_address(struct net_device *ndev, void *addr)
62 {
63 	struct sockaddr *address = addr;
64 
65 	if (!is_valid_ether_addr(address->sa_data))
66 		return -EADDRNOTAVAIL;
67 
68 	memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
69 	moxart_update_mac_address(ndev);
70 
71 	return 0;
72 }
73 
74 static void moxart_mac_free_memory(struct net_device *ndev)
75 {
76 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
77 	int i;
78 
79 	for (i = 0; i < RX_DESC_NUM; i++)
80 		dma_unmap_single(&ndev->dev, priv->rx_mapping[i],
81 				 priv->rx_buf_size, DMA_FROM_DEVICE);
82 
83 	if (priv->tx_desc_base)
84 		dma_free_coherent(&priv->pdev->dev,
85 				  TX_REG_DESC_SIZE * TX_DESC_NUM,
86 				  priv->tx_desc_base, priv->tx_base);
87 
88 	if (priv->rx_desc_base)
89 		dma_free_coherent(&priv->pdev->dev,
90 				  RX_REG_DESC_SIZE * RX_DESC_NUM,
91 				  priv->rx_desc_base, priv->rx_base);
92 
93 	kfree(priv->tx_buf_base);
94 	kfree(priv->rx_buf_base);
95 }
96 
97 static void moxart_mac_reset(struct net_device *ndev)
98 {
99 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
100 
101 	writel(SW_RST, priv->base + REG_MAC_CTRL);
102 	while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
103 		mdelay(10);
104 
105 	writel(0, priv->base + REG_INTERRUPT_MASK);
106 
107 	priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
108 }
109 
110 static void moxart_mac_enable(struct net_device *ndev)
111 {
112 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
113 
114 	writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
115 	writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
116 	writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
117 
118 	priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
119 	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
120 
121 	priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
122 	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
123 }
124 
125 static void moxart_mac_setup_desc_ring(struct net_device *ndev)
126 {
127 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
128 	void *desc;
129 	int i;
130 
131 	for (i = 0; i < TX_DESC_NUM; i++) {
132 		desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
133 		memset(desc, 0, TX_REG_DESC_SIZE);
134 
135 		priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
136 	}
137 	moxart_desc_write(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
138 
139 	priv->tx_head = 0;
140 	priv->tx_tail = 0;
141 
142 	for (i = 0; i < RX_DESC_NUM; i++) {
143 		desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
144 		memset(desc, 0, RX_REG_DESC_SIZE);
145 		moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
146 		moxart_desc_write(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
147 		       desc + RX_REG_OFFSET_DESC1);
148 
149 		priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
150 		priv->rx_mapping[i] = dma_map_single(&ndev->dev,
151 						     priv->rx_buf[i],
152 						     priv->rx_buf_size,
153 						     DMA_FROM_DEVICE);
154 		if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i]))
155 			netdev_err(ndev, "DMA mapping error\n");
156 
157 		moxart_desc_write(priv->rx_mapping[i],
158 		       desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
159 		moxart_desc_write((uintptr_t)priv->rx_buf[i],
160 		       desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
161 	}
162 	moxart_desc_write(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
163 
164 	priv->rx_head = 0;
165 
166 	/* reset the MAC controller TX/RX descriptor base address */
167 	writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
168 	writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
169 }
170 
171 static int moxart_mac_open(struct net_device *ndev)
172 {
173 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
174 
175 	if (!is_valid_ether_addr(ndev->dev_addr))
176 		return -EADDRNOTAVAIL;
177 
178 	napi_enable(&priv->napi);
179 
180 	moxart_mac_reset(ndev);
181 	moxart_update_mac_address(ndev);
182 	moxart_mac_setup_desc_ring(ndev);
183 	moxart_mac_enable(ndev);
184 	netif_start_queue(ndev);
185 
186 	netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
187 		   __func__, readl(priv->base + REG_INTERRUPT_MASK),
188 		   readl(priv->base + REG_MAC_CTRL));
189 
190 	return 0;
191 }
192 
193 static int moxart_mac_stop(struct net_device *ndev)
194 {
195 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
196 
197 	napi_disable(&priv->napi);
198 
199 	netif_stop_queue(ndev);
200 
201 	/* disable all interrupts */
202 	writel(0, priv->base + REG_INTERRUPT_MASK);
203 
204 	/* disable all functions */
205 	writel(0, priv->base + REG_MAC_CTRL);
206 
207 	return 0;
208 }
209 
210 static int moxart_rx_poll(struct napi_struct *napi, int budget)
211 {
212 	struct moxart_mac_priv_t *priv = container_of(napi,
213 						      struct moxart_mac_priv_t,
214 						      napi);
215 	struct net_device *ndev = priv->ndev;
216 	struct sk_buff *skb;
217 	void *desc;
218 	unsigned int desc0, len;
219 	int rx_head = priv->rx_head;
220 	int rx = 0;
221 
222 	while (rx < budget) {
223 		desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
224 		desc0 = moxart_desc_read(desc + RX_REG_OFFSET_DESC0);
225 		rmb(); /* ensure desc0 is up to date */
226 
227 		if (desc0 & RX_DESC0_DMA_OWN)
228 			break;
229 
230 		if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
231 			     RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
232 			net_dbg_ratelimited("packet error\n");
233 			ndev->stats.rx_dropped++;
234 			ndev->stats.rx_errors++;
235 			goto rx_next;
236 		}
237 
238 		len = desc0 & RX_DESC0_FRAME_LEN_MASK;
239 
240 		if (len > RX_BUF_SIZE)
241 			len = RX_BUF_SIZE;
242 
243 		dma_sync_single_for_cpu(&ndev->dev,
244 					priv->rx_mapping[rx_head],
245 					priv->rx_buf_size, DMA_FROM_DEVICE);
246 		skb = netdev_alloc_skb_ip_align(ndev, len);
247 
248 		if (unlikely(!skb)) {
249 			net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
250 			ndev->stats.rx_dropped++;
251 			ndev->stats.rx_errors++;
252 			goto rx_next;
253 		}
254 
255 		memcpy(skb->data, priv->rx_buf[rx_head], len);
256 		skb_put(skb, len);
257 		skb->protocol = eth_type_trans(skb, ndev);
258 		napi_gro_receive(&priv->napi, skb);
259 		rx++;
260 
261 		ndev->stats.rx_packets++;
262 		ndev->stats.rx_bytes += len;
263 		if (desc0 & RX_DESC0_MULTICAST)
264 			ndev->stats.multicast++;
265 
266 rx_next:
267 		wmb(); /* prevent setting ownership back too early */
268 		moxart_desc_write(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
269 
270 		rx_head = RX_NEXT(rx_head);
271 		priv->rx_head = rx_head;
272 	}
273 
274 	if (rx < budget)
275 		napi_complete_done(napi, rx);
276 
277 	priv->reg_imr |= RPKT_FINISH_M;
278 	writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
279 
280 	return rx;
281 }
282 
283 static int moxart_tx_queue_space(struct net_device *ndev)
284 {
285 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
286 
287 	return CIRC_SPACE(priv->tx_head, priv->tx_tail, TX_DESC_NUM);
288 }
289 
290 static void moxart_tx_finished(struct net_device *ndev)
291 {
292 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
293 	unsigned int tx_head = priv->tx_head;
294 	unsigned int tx_tail = priv->tx_tail;
295 
296 	while (tx_tail != tx_head) {
297 		dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail],
298 				 priv->tx_len[tx_tail], DMA_TO_DEVICE);
299 
300 		ndev->stats.tx_packets++;
301 		ndev->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
302 
303 		dev_consume_skb_irq(priv->tx_skb[tx_tail]);
304 		priv->tx_skb[tx_tail] = NULL;
305 
306 		tx_tail = TX_NEXT(tx_tail);
307 	}
308 	priv->tx_tail = tx_tail;
309 	if (netif_queue_stopped(ndev) &&
310 	    moxart_tx_queue_space(ndev) >= TX_WAKE_THRESHOLD)
311 		netif_wake_queue(ndev);
312 }
313 
314 static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
315 {
316 	struct net_device *ndev = (struct net_device *)dev_id;
317 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
318 	unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
319 
320 	if (ists & XPKT_OK_INT_STS)
321 		moxart_tx_finished(ndev);
322 
323 	if (ists & RPKT_FINISH) {
324 		if (napi_schedule_prep(&priv->napi)) {
325 			priv->reg_imr &= ~RPKT_FINISH_M;
326 			writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
327 			__napi_schedule(&priv->napi);
328 		}
329 	}
330 
331 	return IRQ_HANDLED;
332 }
333 
334 static netdev_tx_t moxart_mac_start_xmit(struct sk_buff *skb,
335 					 struct net_device *ndev)
336 {
337 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
338 	void *desc;
339 	unsigned int len;
340 	unsigned int tx_head;
341 	u32 txdes1;
342 	netdev_tx_t ret = NETDEV_TX_BUSY;
343 
344 	spin_lock_irq(&priv->txlock);
345 
346 	tx_head = priv->tx_head;
347 	desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
348 
349 	if (moxart_tx_queue_space(ndev) == 1)
350 		netif_stop_queue(ndev);
351 
352 	if (moxart_desc_read(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
353 		net_dbg_ratelimited("no TX space for packet\n");
354 		ndev->stats.tx_dropped++;
355 		goto out_unlock;
356 	}
357 	rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */
358 
359 	len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
360 
361 	priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data,
362 						   len, DMA_TO_DEVICE);
363 	if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) {
364 		netdev_err(ndev, "DMA mapping error\n");
365 		goto out_unlock;
366 	}
367 
368 	priv->tx_len[tx_head] = len;
369 	priv->tx_skb[tx_head] = skb;
370 
371 	moxart_desc_write(priv->tx_mapping[tx_head],
372 	       desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
373 	moxart_desc_write((uintptr_t)skb->data,
374 	       desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
375 
376 	if (skb->len < ETH_ZLEN) {
377 		memset(&skb->data[skb->len],
378 		       0, ETH_ZLEN - skb->len);
379 		len = ETH_ZLEN;
380 	}
381 
382 	dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head],
383 				   priv->tx_buf_size, DMA_TO_DEVICE);
384 
385 	txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
386 	if (tx_head == TX_DESC_NUM_MASK)
387 		txdes1 |= TX_DESC1_END;
388 	moxart_desc_write(txdes1, desc + TX_REG_OFFSET_DESC1);
389 	wmb(); /* flush descriptor before transferring ownership */
390 	moxart_desc_write(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
391 
392 	/* start to send packet */
393 	writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
394 
395 	priv->tx_head = TX_NEXT(tx_head);
396 
397 	netif_trans_update(ndev);
398 	ret = NETDEV_TX_OK;
399 out_unlock:
400 	spin_unlock_irq(&priv->txlock);
401 
402 	return ret;
403 }
404 
405 static void moxart_mac_setmulticast(struct net_device *ndev)
406 {
407 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
408 	struct netdev_hw_addr *ha;
409 	int crc_val;
410 
411 	netdev_for_each_mc_addr(ha, ndev) {
412 		crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
413 		crc_val = (crc_val >> 26) & 0x3f;
414 		if (crc_val >= 32) {
415 			writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
416 			       (1UL << (crc_val - 32)),
417 			       priv->base + REG_MCAST_HASH_TABLE1);
418 		} else {
419 			writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
420 			       (1UL << crc_val),
421 			       priv->base + REG_MCAST_HASH_TABLE0);
422 		}
423 	}
424 }
425 
426 static void moxart_mac_set_rx_mode(struct net_device *ndev)
427 {
428 	struct moxart_mac_priv_t *priv = netdev_priv(ndev);
429 
430 	spin_lock_irq(&priv->txlock);
431 
432 	(ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
433 				      (priv->reg_maccr &= ~RCV_ALL);
434 
435 	(ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
436 				       (priv->reg_maccr &= ~RX_MULTIPKT);
437 
438 	if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
439 		priv->reg_maccr |= HT_MULTI_EN;
440 		moxart_mac_setmulticast(ndev);
441 	} else {
442 		priv->reg_maccr &= ~HT_MULTI_EN;
443 	}
444 
445 	writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
446 
447 	spin_unlock_irq(&priv->txlock);
448 }
449 
450 static const struct net_device_ops moxart_netdev_ops = {
451 	.ndo_open		= moxart_mac_open,
452 	.ndo_stop		= moxart_mac_stop,
453 	.ndo_start_xmit		= moxart_mac_start_xmit,
454 	.ndo_set_rx_mode	= moxart_mac_set_rx_mode,
455 	.ndo_set_mac_address	= moxart_set_mac_address,
456 	.ndo_validate_addr	= eth_validate_addr,
457 };
458 
459 static int moxart_mac_probe(struct platform_device *pdev)
460 {
461 	struct device *p_dev = &pdev->dev;
462 	struct device_node *node = p_dev->of_node;
463 	struct net_device *ndev;
464 	struct moxart_mac_priv_t *priv;
465 	struct resource *res;
466 	unsigned int irq;
467 	int ret;
468 
469 	ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
470 	if (!ndev)
471 		return -ENOMEM;
472 
473 	irq = irq_of_parse_and_map(node, 0);
474 	if (irq <= 0) {
475 		netdev_err(ndev, "irq_of_parse_and_map failed\n");
476 		ret = -EINVAL;
477 		goto irq_map_fail;
478 	}
479 
480 	priv = netdev_priv(ndev);
481 	priv->ndev = ndev;
482 	priv->pdev = pdev;
483 
484 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 	ndev->base_addr = res->start;
486 	priv->base = devm_ioremap_resource(p_dev, res);
487 	if (IS_ERR(priv->base)) {
488 		dev_err(p_dev, "devm_ioremap_resource failed\n");
489 		ret = PTR_ERR(priv->base);
490 		goto init_fail;
491 	}
492 
493 	spin_lock_init(&priv->txlock);
494 
495 	priv->tx_buf_size = TX_BUF_SIZE;
496 	priv->rx_buf_size = RX_BUF_SIZE;
497 
498 	priv->tx_desc_base = dma_alloc_coherent(&pdev->dev, TX_REG_DESC_SIZE *
499 						TX_DESC_NUM, &priv->tx_base,
500 						GFP_DMA | GFP_KERNEL);
501 	if (!priv->tx_desc_base) {
502 		ret = -ENOMEM;
503 		goto init_fail;
504 	}
505 
506 	priv->rx_desc_base = dma_alloc_coherent(&pdev->dev, RX_REG_DESC_SIZE *
507 						RX_DESC_NUM, &priv->rx_base,
508 						GFP_DMA | GFP_KERNEL);
509 	if (!priv->rx_desc_base) {
510 		ret = -ENOMEM;
511 		goto init_fail;
512 	}
513 
514 	priv->tx_buf_base = kmalloc_array(priv->tx_buf_size, TX_DESC_NUM,
515 					  GFP_ATOMIC);
516 	if (!priv->tx_buf_base) {
517 		ret = -ENOMEM;
518 		goto init_fail;
519 	}
520 
521 	priv->rx_buf_base = kmalloc_array(priv->rx_buf_size, RX_DESC_NUM,
522 					  GFP_ATOMIC);
523 	if (!priv->rx_buf_base) {
524 		ret = -ENOMEM;
525 		goto init_fail;
526 	}
527 
528 	platform_set_drvdata(pdev, ndev);
529 
530 	ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
531 			       pdev->name, ndev);
532 	if (ret) {
533 		netdev_err(ndev, "devm_request_irq failed\n");
534 		goto init_fail;
535 	}
536 
537 	ndev->netdev_ops = &moxart_netdev_ops;
538 	netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
539 	ndev->priv_flags |= IFF_UNICAST_FLT;
540 	ndev->irq = irq;
541 
542 	SET_NETDEV_DEV(ndev, &pdev->dev);
543 
544 	ret = register_netdev(ndev);
545 	if (ret) {
546 		free_netdev(ndev);
547 		goto init_fail;
548 	}
549 
550 	netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
551 		   __func__, ndev->irq, ndev->dev_addr);
552 
553 	return 0;
554 
555 init_fail:
556 	netdev_err(ndev, "init failed\n");
557 	moxart_mac_free_memory(ndev);
558 irq_map_fail:
559 	free_netdev(ndev);
560 	return ret;
561 }
562 
563 static int moxart_remove(struct platform_device *pdev)
564 {
565 	struct net_device *ndev = platform_get_drvdata(pdev);
566 
567 	unregister_netdev(ndev);
568 	devm_free_irq(&pdev->dev, ndev->irq, ndev);
569 	moxart_mac_free_memory(ndev);
570 	free_netdev(ndev);
571 
572 	return 0;
573 }
574 
575 static const struct of_device_id moxart_mac_match[] = {
576 	{ .compatible = "moxa,moxart-mac" },
577 	{ }
578 };
579 MODULE_DEVICE_TABLE(of, moxart_mac_match);
580 
581 static struct platform_driver moxart_mac_driver = {
582 	.probe	= moxart_mac_probe,
583 	.remove	= moxart_remove,
584 	.driver	= {
585 		.name		= "moxart-ethernet",
586 		.of_match_table	= moxart_mac_match,
587 	},
588 };
589 module_platform_driver(moxart_mac_driver);
590 
591 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
592 MODULE_LICENSE("GPL v2");
593 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
594