1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/utsname.h> 7 #include <linux/version.h> 8 9 #include "mana.h" 10 11 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) 12 { 13 return readl(g->bar0_va + offset); 14 } 15 16 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) 17 { 18 return readq(g->bar0_va + offset); 19 } 20 21 static void mana_gd_init_pf_regs(struct pci_dev *pdev) 22 { 23 struct gdma_context *gc = pci_get_drvdata(pdev); 24 void __iomem *sriov_base_va; 25 u64 sriov_base_off; 26 27 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; 28 gc->db_page_base = gc->bar0_va + 29 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 30 31 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); 32 33 sriov_base_va = gc->bar0_va + sriov_base_off; 34 gc->shm_base = sriov_base_va + 35 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); 36 } 37 38 static void mana_gd_init_vf_regs(struct pci_dev *pdev) 39 { 40 struct gdma_context *gc = pci_get_drvdata(pdev); 41 42 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 43 44 gc->db_page_base = gc->bar0_va + 45 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 46 47 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET); 48 } 49 50 static void mana_gd_init_registers(struct pci_dev *pdev) 51 { 52 struct gdma_context *gc = pci_get_drvdata(pdev); 53 54 if (gc->is_pf) 55 mana_gd_init_pf_regs(pdev); 56 else 57 mana_gd_init_vf_regs(pdev); 58 } 59 60 static int mana_gd_query_max_resources(struct pci_dev *pdev) 61 { 62 struct gdma_context *gc = pci_get_drvdata(pdev); 63 struct gdma_query_max_resources_resp resp = {}; 64 struct gdma_general_req req = {}; 65 int err; 66 67 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 68 sizeof(req), sizeof(resp)); 69 70 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 71 if (err || resp.hdr.status) { 72 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", 73 err, resp.hdr.status); 74 return err ? err : -EPROTO; 75 } 76 77 if (gc->num_msix_usable > resp.max_msix) 78 gc->num_msix_usable = resp.max_msix; 79 80 if (gc->num_msix_usable <= 1) 81 return -ENOSPC; 82 83 gc->max_num_queues = num_online_cpus(); 84 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 85 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 86 87 if (gc->max_num_queues > resp.max_eq) 88 gc->max_num_queues = resp.max_eq; 89 90 if (gc->max_num_queues > resp.max_cq) 91 gc->max_num_queues = resp.max_cq; 92 93 if (gc->max_num_queues > resp.max_sq) 94 gc->max_num_queues = resp.max_sq; 95 96 if (gc->max_num_queues > resp.max_rq) 97 gc->max_num_queues = resp.max_rq; 98 99 /* The Hardware Channel (HWC) used 1 MSI-X */ 100 if (gc->max_num_queues > gc->num_msix_usable - 1) 101 gc->max_num_queues = gc->num_msix_usable - 1; 102 103 return 0; 104 } 105 106 static int mana_gd_detect_devices(struct pci_dev *pdev) 107 { 108 struct gdma_context *gc = pci_get_drvdata(pdev); 109 struct gdma_list_devices_resp resp = {}; 110 struct gdma_general_req req = {}; 111 struct gdma_dev_id dev; 112 u32 i, max_num_devs; 113 u16 dev_type; 114 int err; 115 116 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 117 sizeof(resp)); 118 119 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 120 if (err || resp.hdr.status) { 121 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, 122 resp.hdr.status); 123 return err ? err : -EPROTO; 124 } 125 126 max_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 127 128 for (i = 0; i < max_num_devs; i++) { 129 dev = resp.devs[i]; 130 dev_type = dev.type; 131 132 /* HWC is already detected in mana_hwc_create_channel(). */ 133 if (dev_type == GDMA_DEVICE_HWC) 134 continue; 135 136 if (dev_type == GDMA_DEVICE_MANA) { 137 gc->mana.gdma_context = gc; 138 gc->mana.dev_id = dev; 139 } 140 } 141 142 return gc->mana.dev_id.type == 0 ? -ENODEV : 0; 143 } 144 145 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 146 u32 resp_len, void *resp) 147 { 148 struct hw_channel_context *hwc = gc->hwc.driver_data; 149 150 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 151 } 152 153 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 154 struct gdma_mem_info *gmi) 155 { 156 dma_addr_t dma_handle; 157 void *buf; 158 159 if (length < PAGE_SIZE || !is_power_of_2(length)) 160 return -EINVAL; 161 162 gmi->dev = gc->dev; 163 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL); 164 if (!buf) 165 return -ENOMEM; 166 167 gmi->dma_handle = dma_handle; 168 gmi->virt_addr = buf; 169 gmi->length = length; 170 171 return 0; 172 } 173 174 void mana_gd_free_memory(struct gdma_mem_info *gmi) 175 { 176 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr, 177 gmi->dma_handle); 178 } 179 180 static int mana_gd_create_hw_eq(struct gdma_context *gc, 181 struct gdma_queue *queue) 182 { 183 struct gdma_create_queue_resp resp = {}; 184 struct gdma_create_queue_req req = {}; 185 int err; 186 187 if (queue->type != GDMA_EQ) 188 return -EINVAL; 189 190 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 191 sizeof(req), sizeof(resp)); 192 193 req.hdr.dev_id = queue->gdma_dev->dev_id; 194 req.type = queue->type; 195 req.pdid = queue->gdma_dev->pdid; 196 req.doolbell_id = queue->gdma_dev->doorbell; 197 req.gdma_region = queue->mem_info.gdma_region; 198 req.queue_size = queue->queue_size; 199 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 200 req.eq_pci_msix_index = queue->eq.msix_index; 201 202 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 203 if (err || resp.hdr.status) { 204 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err, 205 resp.hdr.status); 206 return err ? err : -EPROTO; 207 } 208 209 queue->id = resp.queue_index; 210 queue->eq.disable_needed = true; 211 queue->mem_info.gdma_region = GDMA_INVALID_DMA_REGION; 212 return 0; 213 } 214 215 static int mana_gd_disable_queue(struct gdma_queue *queue) 216 { 217 struct gdma_context *gc = queue->gdma_dev->gdma_context; 218 struct gdma_disable_queue_req req = {}; 219 struct gdma_general_resp resp = {}; 220 int err; 221 222 WARN_ON(queue->type != GDMA_EQ); 223 224 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 225 sizeof(req), sizeof(resp)); 226 227 req.hdr.dev_id = queue->gdma_dev->dev_id; 228 req.type = queue->type; 229 req.queue_index = queue->id; 230 req.alloc_res_id_on_creation = 1; 231 232 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 233 if (err || resp.hdr.status) { 234 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err, 235 resp.hdr.status); 236 return err ? err : -EPROTO; 237 } 238 239 return 0; 240 } 241 242 #define DOORBELL_OFFSET_SQ 0x0 243 #define DOORBELL_OFFSET_RQ 0x400 244 #define DOORBELL_OFFSET_CQ 0x800 245 #define DOORBELL_OFFSET_EQ 0xFF8 246 247 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index, 248 enum gdma_queue_type q_type, u32 qid, 249 u32 tail_ptr, u8 num_req) 250 { 251 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index; 252 union gdma_doorbell_entry e = {}; 253 254 switch (q_type) { 255 case GDMA_EQ: 256 e.eq.id = qid; 257 e.eq.tail_ptr = tail_ptr; 258 e.eq.arm = num_req; 259 260 addr += DOORBELL_OFFSET_EQ; 261 break; 262 263 case GDMA_CQ: 264 e.cq.id = qid; 265 e.cq.tail_ptr = tail_ptr; 266 e.cq.arm = num_req; 267 268 addr += DOORBELL_OFFSET_CQ; 269 break; 270 271 case GDMA_RQ: 272 e.rq.id = qid; 273 e.rq.tail_ptr = tail_ptr; 274 e.rq.wqe_cnt = num_req; 275 276 addr += DOORBELL_OFFSET_RQ; 277 break; 278 279 case GDMA_SQ: 280 e.sq.id = qid; 281 e.sq.tail_ptr = tail_ptr; 282 283 addr += DOORBELL_OFFSET_SQ; 284 break; 285 286 default: 287 WARN_ON(1); 288 return; 289 } 290 291 /* Ensure all writes are done before ring doorbell */ 292 wmb(); 293 294 writeq(e.as_uint64, addr); 295 } 296 297 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 298 { 299 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 300 queue->id, queue->head * GDMA_WQE_BU_SIZE, 1); 301 } 302 303 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit) 304 { 305 struct gdma_context *gc = cq->gdma_dev->gdma_context; 306 307 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE; 308 309 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 310 311 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 312 head, arm_bit); 313 } 314 315 static void mana_gd_process_eqe(struct gdma_queue *eq) 316 { 317 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 318 struct gdma_context *gc = eq->gdma_dev->gdma_context; 319 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 320 union gdma_eqe_info eqe_info; 321 enum gdma_eqe_type type; 322 struct gdma_event event; 323 struct gdma_queue *cq; 324 struct gdma_eqe *eqe; 325 u32 cq_id; 326 327 eqe = &eq_eqe_ptr[head]; 328 eqe_info.as_uint32 = eqe->eqe_info; 329 type = eqe_info.type; 330 331 switch (type) { 332 case GDMA_EQE_COMPLETION: 333 cq_id = eqe->details[0] & 0xFFFFFF; 334 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs)) 335 break; 336 337 cq = gc->cq_table[cq_id]; 338 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id)) 339 break; 340 341 if (cq->cq.callback) 342 cq->cq.callback(cq->cq.context, cq); 343 344 break; 345 346 case GDMA_EQE_TEST_EVENT: 347 gc->test_event_eq_id = eq->id; 348 complete(&gc->eq_test_event); 349 break; 350 351 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 352 case GDMA_EQE_HWC_INIT_DATA: 353 case GDMA_EQE_HWC_INIT_DONE: 354 if (!eq->eq.callback) 355 break; 356 357 event.type = type; 358 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 359 eq->eq.callback(eq->eq.context, eq, &event); 360 break; 361 362 default: 363 break; 364 } 365 } 366 367 static void mana_gd_process_eq_events(void *arg) 368 { 369 u32 owner_bits, new_bits, old_bits; 370 union gdma_eqe_info eqe_info; 371 struct gdma_eqe *eq_eqe_ptr; 372 struct gdma_queue *eq = arg; 373 struct gdma_context *gc; 374 struct gdma_eqe *eqe; 375 u32 head, num_eqe; 376 int i; 377 378 gc = eq->gdma_dev->gdma_context; 379 380 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 381 eq_eqe_ptr = eq->queue_mem_ptr; 382 383 /* Process up to 5 EQEs at a time, and update the HW head. */ 384 for (i = 0; i < 5; i++) { 385 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 386 eqe_info.as_uint32 = eqe->eqe_info; 387 owner_bits = eqe_info.owner_bits; 388 389 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 390 /* No more entries */ 391 if (owner_bits == old_bits) 392 break; 393 394 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 395 if (owner_bits != new_bits) { 396 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id); 397 break; 398 } 399 400 mana_gd_process_eqe(eq); 401 402 eq->head++; 403 } 404 405 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 406 407 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 408 head, SET_ARM_BIT); 409 } 410 411 static int mana_gd_register_irq(struct gdma_queue *queue, 412 const struct gdma_queue_spec *spec) 413 { 414 struct gdma_dev *gd = queue->gdma_dev; 415 struct gdma_irq_context *gic; 416 struct gdma_context *gc; 417 struct gdma_resource *r; 418 unsigned int msi_index; 419 unsigned long flags; 420 struct device *dev; 421 int err = 0; 422 423 gc = gd->gdma_context; 424 r = &gc->msix_resource; 425 dev = gc->dev; 426 427 spin_lock_irqsave(&r->lock, flags); 428 429 msi_index = find_first_zero_bit(r->map, r->size); 430 if (msi_index >= r->size || msi_index >= gc->num_msix_usable) { 431 err = -ENOSPC; 432 } else { 433 bitmap_set(r->map, msi_index, 1); 434 queue->eq.msix_index = msi_index; 435 } 436 437 spin_unlock_irqrestore(&r->lock, flags); 438 439 if (err) { 440 dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u", 441 err, msi_index, r->size, gc->num_msix_usable); 442 443 return err; 444 } 445 446 gic = &gc->irq_contexts[msi_index]; 447 448 WARN_ON(gic->handler || gic->arg); 449 450 gic->arg = queue; 451 452 gic->handler = mana_gd_process_eq_events; 453 454 return 0; 455 } 456 457 static void mana_gd_deregiser_irq(struct gdma_queue *queue) 458 { 459 struct gdma_dev *gd = queue->gdma_dev; 460 struct gdma_irq_context *gic; 461 struct gdma_context *gc; 462 struct gdma_resource *r; 463 unsigned int msix_index; 464 unsigned long flags; 465 466 gc = gd->gdma_context; 467 r = &gc->msix_resource; 468 469 /* At most num_online_cpus() + 1 interrupts are used. */ 470 msix_index = queue->eq.msix_index; 471 if (WARN_ON(msix_index >= gc->num_msix_usable)) 472 return; 473 474 gic = &gc->irq_contexts[msix_index]; 475 gic->handler = NULL; 476 gic->arg = NULL; 477 478 spin_lock_irqsave(&r->lock, flags); 479 bitmap_clear(r->map, msix_index, 1); 480 spin_unlock_irqrestore(&r->lock, flags); 481 482 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 483 } 484 485 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 486 { 487 struct gdma_generate_test_event_req req = {}; 488 struct gdma_general_resp resp = {}; 489 struct device *dev = gc->dev; 490 int err; 491 492 mutex_lock(&gc->eq_test_event_mutex); 493 494 init_completion(&gc->eq_test_event); 495 gc->test_event_eq_id = INVALID_QUEUE_ID; 496 497 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 498 sizeof(req), sizeof(resp)); 499 500 req.hdr.dev_id = eq->gdma_dev->dev_id; 501 req.queue_index = eq->id; 502 503 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 504 if (err) { 505 dev_err(dev, "test_eq failed: %d\n", err); 506 goto out; 507 } 508 509 err = -EPROTO; 510 511 if (resp.hdr.status) { 512 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status); 513 goto out; 514 } 515 516 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) { 517 dev_err(dev, "test_eq timed out on queue %d\n", eq->id); 518 goto out; 519 } 520 521 if (eq->id != gc->test_event_eq_id) { 522 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n", 523 gc->test_event_eq_id, eq->id); 524 goto out; 525 } 526 527 err = 0; 528 out: 529 mutex_unlock(&gc->eq_test_event_mutex); 530 return err; 531 } 532 533 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 534 struct gdma_queue *queue) 535 { 536 int err; 537 538 if (flush_evenets) { 539 err = mana_gd_test_eq(gc, queue); 540 if (err) 541 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err); 542 } 543 544 mana_gd_deregiser_irq(queue); 545 546 if (queue->eq.disable_needed) 547 mana_gd_disable_queue(queue); 548 } 549 550 static int mana_gd_create_eq(struct gdma_dev *gd, 551 const struct gdma_queue_spec *spec, 552 bool create_hwq, struct gdma_queue *queue) 553 { 554 struct gdma_context *gc = gd->gdma_context; 555 struct device *dev = gc->dev; 556 u32 log2_num_entries; 557 int err; 558 559 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 560 561 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 562 563 if (spec->eq.log2_throttle_limit > log2_num_entries) { 564 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n", 565 spec->eq.log2_throttle_limit, log2_num_entries); 566 return -EINVAL; 567 } 568 569 err = mana_gd_register_irq(queue, spec); 570 if (err) { 571 dev_err(dev, "Failed to register irq: %d\n", err); 572 return err; 573 } 574 575 queue->eq.callback = spec->eq.callback; 576 queue->eq.context = spec->eq.context; 577 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 578 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 579 580 if (create_hwq) { 581 err = mana_gd_create_hw_eq(gc, queue); 582 if (err) 583 goto out; 584 585 err = mana_gd_test_eq(gc, queue); 586 if (err) 587 goto out; 588 } 589 590 return 0; 591 out: 592 dev_err(dev, "Failed to create EQ: %d\n", err); 593 mana_gd_destroy_eq(gc, false, queue); 594 return err; 595 } 596 597 static void mana_gd_create_cq(const struct gdma_queue_spec *spec, 598 struct gdma_queue *queue) 599 { 600 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 601 602 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 603 queue->cq.parent = spec->cq.parent_eq; 604 queue->cq.context = spec->cq.context; 605 queue->cq.callback = spec->cq.callback; 606 } 607 608 static void mana_gd_destroy_cq(struct gdma_context *gc, 609 struct gdma_queue *queue) 610 { 611 u32 id = queue->id; 612 613 if (id >= gc->max_num_cqs) 614 return; 615 616 if (!gc->cq_table[id]) 617 return; 618 619 gc->cq_table[id] = NULL; 620 } 621 622 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 623 const struct gdma_queue_spec *spec, 624 struct gdma_queue **queue_ptr) 625 { 626 struct gdma_context *gc = gd->gdma_context; 627 struct gdma_mem_info *gmi; 628 struct gdma_queue *queue; 629 int err; 630 631 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 632 if (!queue) 633 return -ENOMEM; 634 635 gmi = &queue->mem_info; 636 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 637 if (err) 638 goto free_q; 639 640 queue->head = 0; 641 queue->tail = 0; 642 queue->queue_mem_ptr = gmi->virt_addr; 643 queue->queue_size = spec->queue_size; 644 queue->monitor_avl_buf = spec->monitor_avl_buf; 645 queue->type = spec->type; 646 queue->gdma_dev = gd; 647 648 if (spec->type == GDMA_EQ) 649 err = mana_gd_create_eq(gd, spec, false, queue); 650 else if (spec->type == GDMA_CQ) 651 mana_gd_create_cq(spec, queue); 652 653 if (err) 654 goto out; 655 656 *queue_ptr = queue; 657 return 0; 658 out: 659 mana_gd_free_memory(gmi); 660 free_q: 661 kfree(queue); 662 return err; 663 } 664 665 static void mana_gd_destroy_dma_region(struct gdma_context *gc, u64 gdma_region) 666 { 667 struct gdma_destroy_dma_region_req req = {}; 668 struct gdma_general_resp resp = {}; 669 int err; 670 671 if (gdma_region == GDMA_INVALID_DMA_REGION) 672 return; 673 674 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 675 sizeof(resp)); 676 req.gdma_region = gdma_region; 677 678 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 679 if (err || resp.hdr.status) 680 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n", 681 err, resp.hdr.status); 682 } 683 684 static int mana_gd_create_dma_region(struct gdma_dev *gd, 685 struct gdma_mem_info *gmi) 686 { 687 unsigned int num_page = gmi->length / PAGE_SIZE; 688 struct gdma_create_dma_region_req *req = NULL; 689 struct gdma_create_dma_region_resp resp = {}; 690 struct gdma_context *gc = gd->gdma_context; 691 struct hw_channel_context *hwc; 692 u32 length = gmi->length; 693 size_t req_msg_size; 694 int err; 695 int i; 696 697 if (length < PAGE_SIZE || !is_power_of_2(length)) 698 return -EINVAL; 699 700 if (offset_in_page(gmi->virt_addr) != 0) 701 return -EINVAL; 702 703 hwc = gc->hwc.driver_data; 704 req_msg_size = struct_size(req, page_addr_list, num_page); 705 if (req_msg_size > hwc->max_req_msg_size) 706 return -EINVAL; 707 708 req = kzalloc(req_msg_size, GFP_KERNEL); 709 if (!req) 710 return -ENOMEM; 711 712 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 713 req_msg_size, sizeof(resp)); 714 req->length = length; 715 req->offset_in_page = 0; 716 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 717 req->page_count = num_page; 718 req->page_addr_list_len = num_page; 719 720 for (i = 0; i < num_page; i++) 721 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 722 723 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 724 if (err) 725 goto out; 726 727 if (resp.hdr.status || resp.gdma_region == GDMA_INVALID_DMA_REGION) { 728 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n", 729 resp.hdr.status); 730 err = -EPROTO; 731 goto out; 732 } 733 734 gmi->gdma_region = resp.gdma_region; 735 out: 736 kfree(req); 737 return err; 738 } 739 740 int mana_gd_create_mana_eq(struct gdma_dev *gd, 741 const struct gdma_queue_spec *spec, 742 struct gdma_queue **queue_ptr) 743 { 744 struct gdma_context *gc = gd->gdma_context; 745 struct gdma_mem_info *gmi; 746 struct gdma_queue *queue; 747 int err; 748 749 if (spec->type != GDMA_EQ) 750 return -EINVAL; 751 752 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 753 if (!queue) 754 return -ENOMEM; 755 756 gmi = &queue->mem_info; 757 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 758 if (err) 759 goto free_q; 760 761 err = mana_gd_create_dma_region(gd, gmi); 762 if (err) 763 goto out; 764 765 queue->head = 0; 766 queue->tail = 0; 767 queue->queue_mem_ptr = gmi->virt_addr; 768 queue->queue_size = spec->queue_size; 769 queue->monitor_avl_buf = spec->monitor_avl_buf; 770 queue->type = spec->type; 771 queue->gdma_dev = gd; 772 773 err = mana_gd_create_eq(gd, spec, true, queue); 774 if (err) 775 goto out; 776 777 *queue_ptr = queue; 778 return 0; 779 out: 780 mana_gd_free_memory(gmi); 781 free_q: 782 kfree(queue); 783 return err; 784 } 785 786 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 787 const struct gdma_queue_spec *spec, 788 struct gdma_queue **queue_ptr) 789 { 790 struct gdma_context *gc = gd->gdma_context; 791 struct gdma_mem_info *gmi; 792 struct gdma_queue *queue; 793 int err; 794 795 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 796 spec->type != GDMA_RQ) 797 return -EINVAL; 798 799 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 800 if (!queue) 801 return -ENOMEM; 802 803 gmi = &queue->mem_info; 804 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 805 if (err) 806 goto free_q; 807 808 err = mana_gd_create_dma_region(gd, gmi); 809 if (err) 810 goto out; 811 812 queue->head = 0; 813 queue->tail = 0; 814 queue->queue_mem_ptr = gmi->virt_addr; 815 queue->queue_size = spec->queue_size; 816 queue->monitor_avl_buf = spec->monitor_avl_buf; 817 queue->type = spec->type; 818 queue->gdma_dev = gd; 819 820 if (spec->type == GDMA_CQ) 821 mana_gd_create_cq(spec, queue); 822 823 *queue_ptr = queue; 824 return 0; 825 out: 826 mana_gd_free_memory(gmi); 827 free_q: 828 kfree(queue); 829 return err; 830 } 831 832 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 833 { 834 struct gdma_mem_info *gmi = &queue->mem_info; 835 836 switch (queue->type) { 837 case GDMA_EQ: 838 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 839 break; 840 841 case GDMA_CQ: 842 mana_gd_destroy_cq(gc, queue); 843 break; 844 845 case GDMA_RQ: 846 break; 847 848 case GDMA_SQ: 849 break; 850 851 default: 852 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n", 853 queue->type); 854 return; 855 } 856 857 mana_gd_destroy_dma_region(gc, gmi->gdma_region); 858 mana_gd_free_memory(gmi); 859 kfree(queue); 860 } 861 862 int mana_gd_verify_vf_version(struct pci_dev *pdev) 863 { 864 struct gdma_context *gc = pci_get_drvdata(pdev); 865 struct gdma_verify_ver_resp resp = {}; 866 struct gdma_verify_ver_req req = {}; 867 int err; 868 869 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 870 sizeof(req), sizeof(resp)); 871 872 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 873 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 874 875 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1; 876 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2; 877 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3; 878 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4; 879 880 req.drv_ver = 0; /* Unused*/ 881 req.os_type = 0x10; /* Linux */ 882 req.os_ver_major = LINUX_VERSION_MAJOR; 883 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL; 884 req.os_ver_build = LINUX_VERSION_SUBLEVEL; 885 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1)); 886 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2)); 887 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3)); 888 889 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 890 if (err || resp.hdr.status) { 891 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n", 892 err, resp.hdr.status); 893 return err ? err : -EPROTO; 894 } 895 896 return 0; 897 } 898 899 int mana_gd_register_device(struct gdma_dev *gd) 900 { 901 struct gdma_context *gc = gd->gdma_context; 902 struct gdma_register_device_resp resp = {}; 903 struct gdma_general_req req = {}; 904 int err; 905 906 gd->pdid = INVALID_PDID; 907 gd->doorbell = INVALID_DOORBELL; 908 gd->gpa_mkey = INVALID_MEM_KEY; 909 910 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 911 sizeof(resp)); 912 913 req.hdr.dev_id = gd->dev_id; 914 915 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 916 if (err || resp.hdr.status) { 917 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n", 918 err, resp.hdr.status); 919 return err ? err : -EPROTO; 920 } 921 922 gd->pdid = resp.pdid; 923 gd->gpa_mkey = resp.gpa_mkey; 924 gd->doorbell = resp.db_id; 925 926 return 0; 927 } 928 929 int mana_gd_deregister_device(struct gdma_dev *gd) 930 { 931 struct gdma_context *gc = gd->gdma_context; 932 struct gdma_general_resp resp = {}; 933 struct gdma_general_req req = {}; 934 int err; 935 936 if (gd->pdid == INVALID_PDID) 937 return -EINVAL; 938 939 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 940 sizeof(resp)); 941 942 req.hdr.dev_id = gd->dev_id; 943 944 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 945 if (err || resp.hdr.status) { 946 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n", 947 err, resp.hdr.status); 948 if (!err) 949 err = -EPROTO; 950 } 951 952 gd->pdid = INVALID_PDID; 953 gd->doorbell = INVALID_DOORBELL; 954 gd->gpa_mkey = INVALID_MEM_KEY; 955 956 return err; 957 } 958 959 u32 mana_gd_wq_avail_space(struct gdma_queue *wq) 960 { 961 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 962 u32 wq_size = wq->queue_size; 963 964 WARN_ON_ONCE(used_space > wq_size); 965 966 return wq_size - used_space; 967 } 968 969 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset) 970 { 971 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 972 973 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size); 974 975 return wq->queue_mem_ptr + offset; 976 } 977 978 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 979 enum gdma_queue_type q_type, 980 u32 client_oob_size, u32 sgl_data_size, 981 u8 *wqe_ptr) 982 { 983 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 984 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 985 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 986 u8 *ptr; 987 988 memset(header, 0, sizeof(struct gdma_wqe)); 989 header->num_sge = wqe_req->num_sge; 990 header->inline_oob_size_div4 = client_oob_size / sizeof(u32); 991 992 if (oob_in_sgl) { 993 WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2); 994 995 header->client_oob_in_sgl = 1; 996 997 if (pad_data) 998 header->last_vbytes = wqe_req->sgl[0].size; 999 } 1000 1001 if (q_type == GDMA_SQ) 1002 header->client_data_unit = wqe_req->client_data_unit; 1003 1004 /* The size of gdma_wqe + client_oob_size must be less than or equal 1005 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1006 * the queue memory buffer boundary. 1007 */ 1008 ptr = wqe_ptr + sizeof(header); 1009 1010 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1011 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1012 1013 if (client_oob_size > wqe_req->inline_oob_size) 1014 memset(ptr + wqe_req->inline_oob_size, 0, 1015 client_oob_size - wqe_req->inline_oob_size); 1016 } 1017 1018 return sizeof(header) + client_oob_size; 1019 } 1020 1021 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr, 1022 const struct gdma_wqe_request *wqe_req) 1023 { 1024 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1025 const u8 *address = (u8 *)wqe_req->sgl; 1026 u8 *base_ptr, *end_ptr; 1027 u32 size_to_end; 1028 1029 base_ptr = wq->queue_mem_ptr; 1030 end_ptr = base_ptr + wq->queue_size; 1031 size_to_end = (u32)(end_ptr - wqe_ptr); 1032 1033 if (size_to_end < sgl_size) { 1034 memcpy(wqe_ptr, address, size_to_end); 1035 1036 wqe_ptr = base_ptr; 1037 address += size_to_end; 1038 sgl_size -= size_to_end; 1039 } 1040 1041 memcpy(wqe_ptr, address, sgl_size); 1042 } 1043 1044 int mana_gd_post_work_request(struct gdma_queue *wq, 1045 const struct gdma_wqe_request *wqe_req, 1046 struct gdma_posted_wqe_info *wqe_info) 1047 { 1048 u32 client_oob_size = wqe_req->inline_oob_size; 1049 struct gdma_context *gc; 1050 u32 sgl_data_size; 1051 u32 max_wqe_size; 1052 u32 wqe_size; 1053 u8 *wqe_ptr; 1054 1055 if (wqe_req->num_sge == 0) 1056 return -EINVAL; 1057 1058 if (wq->type == GDMA_RQ) { 1059 if (client_oob_size != 0) 1060 return -EINVAL; 1061 1062 client_oob_size = INLINE_OOB_SMALL_SIZE; 1063 1064 max_wqe_size = GDMA_MAX_RQE_SIZE; 1065 } else { 1066 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1067 client_oob_size != INLINE_OOB_LARGE_SIZE) 1068 return -EINVAL; 1069 1070 max_wqe_size = GDMA_MAX_SQE_SIZE; 1071 } 1072 1073 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1074 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1075 sgl_data_size, GDMA_WQE_BU_SIZE); 1076 if (wqe_size > max_wqe_size) 1077 return -EINVAL; 1078 1079 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1080 gc = wq->gdma_dev->gdma_context; 1081 dev_err(gc->dev, "unsuccessful flow control!\n"); 1082 return -ENOSPC; 1083 } 1084 1085 if (wqe_info) 1086 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1087 1088 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1089 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1090 sgl_data_size, wqe_ptr); 1091 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size) 1092 wqe_ptr -= wq->queue_size; 1093 1094 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1095 1096 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1097 1098 return 0; 1099 } 1100 1101 int mana_gd_post_and_ring(struct gdma_queue *queue, 1102 const struct gdma_wqe_request *wqe_req, 1103 struct gdma_posted_wqe_info *wqe_info) 1104 { 1105 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1106 int err; 1107 1108 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1109 if (err) 1110 return err; 1111 1112 mana_gd_wq_ring_doorbell(gc, queue); 1113 1114 return 0; 1115 } 1116 1117 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1118 { 1119 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1120 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1121 u32 owner_bits, new_bits, old_bits; 1122 struct gdma_cqe *cqe; 1123 1124 cqe = &cq_cqe[cq->head % num_cqe]; 1125 owner_bits = cqe->cqe_info.owner_bits; 1126 1127 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1128 /* Return 0 if no more entries. */ 1129 if (owner_bits == old_bits) 1130 return 0; 1131 1132 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1133 /* Return -1 if overflow detected. */ 1134 if (WARN_ON_ONCE(owner_bits != new_bits)) 1135 return -1; 1136 1137 comp->wq_num = cqe->cqe_info.wq_num; 1138 comp->is_sq = cqe->cqe_info.is_sq; 1139 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1140 1141 return 1; 1142 } 1143 1144 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1145 { 1146 int cqe_idx; 1147 int ret; 1148 1149 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1150 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1151 1152 if (ret < 0) { 1153 cq->head -= cqe_idx; 1154 return ret; 1155 } 1156 1157 if (ret == 0) 1158 break; 1159 1160 cq->head++; 1161 } 1162 1163 return cqe_idx; 1164 } 1165 1166 static irqreturn_t mana_gd_intr(int irq, void *arg) 1167 { 1168 struct gdma_irq_context *gic = arg; 1169 1170 if (gic->handler) 1171 gic->handler(gic->arg); 1172 1173 return IRQ_HANDLED; 1174 } 1175 1176 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r) 1177 { 1178 r->map = bitmap_zalloc(res_avail, GFP_KERNEL); 1179 if (!r->map) 1180 return -ENOMEM; 1181 1182 r->size = res_avail; 1183 spin_lock_init(&r->lock); 1184 1185 return 0; 1186 } 1187 1188 void mana_gd_free_res_map(struct gdma_resource *r) 1189 { 1190 bitmap_free(r->map); 1191 r->map = NULL; 1192 r->size = 0; 1193 } 1194 1195 static int mana_gd_setup_irqs(struct pci_dev *pdev) 1196 { 1197 unsigned int max_queues_per_port = num_online_cpus(); 1198 struct gdma_context *gc = pci_get_drvdata(pdev); 1199 struct gdma_irq_context *gic; 1200 unsigned int max_irqs; 1201 int nvec, irq; 1202 int err, i, j; 1203 1204 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1205 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1206 1207 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1208 max_irqs = max_queues_per_port + 1; 1209 1210 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); 1211 if (nvec < 0) 1212 return nvec; 1213 1214 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context), 1215 GFP_KERNEL); 1216 if (!gc->irq_contexts) { 1217 err = -ENOMEM; 1218 goto free_irq_vector; 1219 } 1220 1221 for (i = 0; i < nvec; i++) { 1222 gic = &gc->irq_contexts[i]; 1223 gic->handler = NULL; 1224 gic->arg = NULL; 1225 1226 irq = pci_irq_vector(pdev, i); 1227 if (irq < 0) { 1228 err = irq; 1229 goto free_irq; 1230 } 1231 1232 err = request_irq(irq, mana_gd_intr, 0, "mana_intr", gic); 1233 if (err) 1234 goto free_irq; 1235 } 1236 1237 err = mana_gd_alloc_res_map(nvec, &gc->msix_resource); 1238 if (err) 1239 goto free_irq; 1240 1241 gc->max_num_msix = nvec; 1242 gc->num_msix_usable = nvec; 1243 1244 return 0; 1245 1246 free_irq: 1247 for (j = i - 1; j >= 0; j--) { 1248 irq = pci_irq_vector(pdev, j); 1249 gic = &gc->irq_contexts[j]; 1250 free_irq(irq, gic); 1251 } 1252 1253 kfree(gc->irq_contexts); 1254 gc->irq_contexts = NULL; 1255 free_irq_vector: 1256 pci_free_irq_vectors(pdev); 1257 return err; 1258 } 1259 1260 static void mana_gd_remove_irqs(struct pci_dev *pdev) 1261 { 1262 struct gdma_context *gc = pci_get_drvdata(pdev); 1263 struct gdma_irq_context *gic; 1264 int irq, i; 1265 1266 if (gc->max_num_msix < 1) 1267 return; 1268 1269 mana_gd_free_res_map(&gc->msix_resource); 1270 1271 for (i = 0; i < gc->max_num_msix; i++) { 1272 irq = pci_irq_vector(pdev, i); 1273 if (irq < 0) 1274 continue; 1275 1276 gic = &gc->irq_contexts[i]; 1277 free_irq(irq, gic); 1278 } 1279 1280 pci_free_irq_vectors(pdev); 1281 1282 gc->max_num_msix = 0; 1283 gc->num_msix_usable = 0; 1284 kfree(gc->irq_contexts); 1285 gc->irq_contexts = NULL; 1286 } 1287 1288 static int mana_gd_setup(struct pci_dev *pdev) 1289 { 1290 struct gdma_context *gc = pci_get_drvdata(pdev); 1291 int err; 1292 1293 mana_gd_init_registers(pdev); 1294 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1295 1296 err = mana_gd_setup_irqs(pdev); 1297 if (err) 1298 return err; 1299 1300 err = mana_hwc_create_channel(gc); 1301 if (err) 1302 goto remove_irq; 1303 1304 err = mana_gd_verify_vf_version(pdev); 1305 if (err) 1306 goto destroy_hwc; 1307 1308 err = mana_gd_query_max_resources(pdev); 1309 if (err) 1310 goto destroy_hwc; 1311 1312 err = mana_gd_detect_devices(pdev); 1313 if (err) 1314 goto destroy_hwc; 1315 1316 return 0; 1317 1318 destroy_hwc: 1319 mana_hwc_destroy_channel(gc); 1320 remove_irq: 1321 mana_gd_remove_irqs(pdev); 1322 return err; 1323 } 1324 1325 static void mana_gd_cleanup(struct pci_dev *pdev) 1326 { 1327 struct gdma_context *gc = pci_get_drvdata(pdev); 1328 1329 mana_hwc_destroy_channel(gc); 1330 1331 mana_gd_remove_irqs(pdev); 1332 } 1333 1334 static bool mana_is_pf(unsigned short dev_id) 1335 { 1336 return dev_id == MANA_PF_DEVICE_ID; 1337 } 1338 1339 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1340 { 1341 struct gdma_context *gc; 1342 void __iomem *bar0_va; 1343 int bar = 0; 1344 int err; 1345 1346 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */ 1347 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE); 1348 1349 err = pci_enable_device(pdev); 1350 if (err) 1351 return -ENXIO; 1352 1353 pci_set_master(pdev); 1354 1355 err = pci_request_regions(pdev, "mana"); 1356 if (err) 1357 goto disable_dev; 1358 1359 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1360 if (err) 1361 goto release_region; 1362 1363 err = -ENOMEM; 1364 gc = vzalloc(sizeof(*gc)); 1365 if (!gc) 1366 goto release_region; 1367 1368 mutex_init(&gc->eq_test_event_mutex); 1369 pci_set_drvdata(pdev, gc); 1370 1371 bar0_va = pci_iomap(pdev, bar, 0); 1372 if (!bar0_va) 1373 goto free_gc; 1374 1375 gc->is_pf = mana_is_pf(pdev->device); 1376 gc->bar0_va = bar0_va; 1377 gc->dev = &pdev->dev; 1378 1379 err = mana_gd_setup(pdev); 1380 if (err) 1381 goto unmap_bar; 1382 1383 err = mana_probe(&gc->mana, false); 1384 if (err) 1385 goto cleanup_gd; 1386 1387 return 0; 1388 1389 cleanup_gd: 1390 mana_gd_cleanup(pdev); 1391 unmap_bar: 1392 pci_iounmap(pdev, bar0_va); 1393 free_gc: 1394 pci_set_drvdata(pdev, NULL); 1395 vfree(gc); 1396 release_region: 1397 pci_release_regions(pdev); 1398 disable_dev: 1399 pci_clear_master(pdev); 1400 pci_disable_device(pdev); 1401 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err); 1402 return err; 1403 } 1404 1405 static void mana_gd_remove(struct pci_dev *pdev) 1406 { 1407 struct gdma_context *gc = pci_get_drvdata(pdev); 1408 1409 mana_remove(&gc->mana, false); 1410 1411 mana_gd_cleanup(pdev); 1412 1413 pci_iounmap(pdev, gc->bar0_va); 1414 1415 vfree(gc); 1416 1417 pci_release_regions(pdev); 1418 pci_clear_master(pdev); 1419 pci_disable_device(pdev); 1420 } 1421 1422 /* The 'state' parameter is not used. */ 1423 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state) 1424 { 1425 struct gdma_context *gc = pci_get_drvdata(pdev); 1426 1427 mana_remove(&gc->mana, true); 1428 1429 mana_gd_cleanup(pdev); 1430 1431 return 0; 1432 } 1433 1434 /* In case the NIC hardware stops working, the suspend and resume callbacks will 1435 * fail -- if this happens, it's safer to just report an error than try to undo 1436 * what has been done. 1437 */ 1438 static int mana_gd_resume(struct pci_dev *pdev) 1439 { 1440 struct gdma_context *gc = pci_get_drvdata(pdev); 1441 int err; 1442 1443 err = mana_gd_setup(pdev); 1444 if (err) 1445 return err; 1446 1447 err = mana_probe(&gc->mana, true); 1448 if (err) 1449 return err; 1450 1451 return 0; 1452 } 1453 1454 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */ 1455 static void mana_gd_shutdown(struct pci_dev *pdev) 1456 { 1457 struct gdma_context *gc = pci_get_drvdata(pdev); 1458 1459 dev_info(&pdev->dev, "Shutdown was called\n"); 1460 1461 mana_remove(&gc->mana, true); 1462 1463 mana_gd_cleanup(pdev); 1464 1465 pci_disable_device(pdev); 1466 } 1467 1468 #ifndef PCI_VENDOR_ID_MICROSOFT 1469 #define PCI_VENDOR_ID_MICROSOFT 0x1414 1470 #endif 1471 1472 static const struct pci_device_id mana_id_table[] = { 1473 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) }, 1474 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) }, 1475 { } 1476 }; 1477 1478 static struct pci_driver mana_driver = { 1479 .name = "mana", 1480 .id_table = mana_id_table, 1481 .probe = mana_gd_probe, 1482 .remove = mana_gd_remove, 1483 .suspend = mana_gd_suspend, 1484 .resume = mana_gd_resume, 1485 .shutdown = mana_gd_shutdown, 1486 }; 1487 1488 module_pci_driver(mana_driver); 1489 1490 MODULE_DEVICE_TABLE(pci, mana_id_table); 1491 1492 MODULE_LICENSE("Dual BSD/GPL"); 1493 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver"); 1494