1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/utsname.h> 7 #include <linux/version.h> 8 9 #include <net/mana/mana.h> 10 11 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) 12 { 13 return readl(g->bar0_va + offset); 14 } 15 16 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) 17 { 18 return readq(g->bar0_va + offset); 19 } 20 21 static void mana_gd_init_pf_regs(struct pci_dev *pdev) 22 { 23 struct gdma_context *gc = pci_get_drvdata(pdev); 24 void __iomem *sriov_base_va; 25 u64 sriov_base_off; 26 27 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; 28 gc->db_page_base = gc->bar0_va + 29 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 30 31 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); 32 33 sriov_base_va = gc->bar0_va + sriov_base_off; 34 gc->shm_base = sriov_base_va + 35 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); 36 } 37 38 static void mana_gd_init_vf_regs(struct pci_dev *pdev) 39 { 40 struct gdma_context *gc = pci_get_drvdata(pdev); 41 42 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 43 44 gc->db_page_base = gc->bar0_va + 45 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 46 47 gc->phys_db_page_base = gc->bar0_pa + 48 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 49 50 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET); 51 } 52 53 static void mana_gd_init_registers(struct pci_dev *pdev) 54 { 55 struct gdma_context *gc = pci_get_drvdata(pdev); 56 57 if (gc->is_pf) 58 mana_gd_init_pf_regs(pdev); 59 else 60 mana_gd_init_vf_regs(pdev); 61 } 62 63 static int mana_gd_query_max_resources(struct pci_dev *pdev) 64 { 65 struct gdma_context *gc = pci_get_drvdata(pdev); 66 struct gdma_query_max_resources_resp resp = {}; 67 struct gdma_general_req req = {}; 68 int err; 69 70 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 71 sizeof(req), sizeof(resp)); 72 73 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 74 if (err || resp.hdr.status) { 75 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", 76 err, resp.hdr.status); 77 return err ? err : -EPROTO; 78 } 79 80 if (gc->num_msix_usable > resp.max_msix) 81 gc->num_msix_usable = resp.max_msix; 82 83 if (gc->num_msix_usable <= 1) 84 return -ENOSPC; 85 86 gc->max_num_queues = num_online_cpus(); 87 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 88 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 89 90 if (gc->max_num_queues > resp.max_eq) 91 gc->max_num_queues = resp.max_eq; 92 93 if (gc->max_num_queues > resp.max_cq) 94 gc->max_num_queues = resp.max_cq; 95 96 if (gc->max_num_queues > resp.max_sq) 97 gc->max_num_queues = resp.max_sq; 98 99 if (gc->max_num_queues > resp.max_rq) 100 gc->max_num_queues = resp.max_rq; 101 102 /* The Hardware Channel (HWC) used 1 MSI-X */ 103 if (gc->max_num_queues > gc->num_msix_usable - 1) 104 gc->max_num_queues = gc->num_msix_usable - 1; 105 106 return 0; 107 } 108 109 static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val) 110 { 111 struct gdma_context *gc = pci_get_drvdata(pdev); 112 struct gdma_query_hwc_timeout_resp resp = {}; 113 struct gdma_query_hwc_timeout_req req = {}; 114 int err; 115 116 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT, 117 sizeof(req), sizeof(resp)); 118 req.timeout_ms = *timeout_val; 119 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 120 if (err || resp.hdr.status) 121 return err ? err : -EPROTO; 122 123 *timeout_val = resp.timeout_ms; 124 125 return 0; 126 } 127 128 static int mana_gd_detect_devices(struct pci_dev *pdev) 129 { 130 struct gdma_context *gc = pci_get_drvdata(pdev); 131 struct gdma_list_devices_resp resp = {}; 132 struct gdma_general_req req = {}; 133 struct gdma_dev_id dev; 134 u32 i, max_num_devs; 135 u16 dev_type; 136 int err; 137 138 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 139 sizeof(resp)); 140 141 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 142 if (err || resp.hdr.status) { 143 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, 144 resp.hdr.status); 145 return err ? err : -EPROTO; 146 } 147 148 max_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 149 150 for (i = 0; i < max_num_devs; i++) { 151 dev = resp.devs[i]; 152 dev_type = dev.type; 153 154 /* HWC is already detected in mana_hwc_create_channel(). */ 155 if (dev_type == GDMA_DEVICE_HWC) 156 continue; 157 158 if (dev_type == GDMA_DEVICE_MANA) { 159 gc->mana.gdma_context = gc; 160 gc->mana.dev_id = dev; 161 } 162 } 163 164 return gc->mana.dev_id.type == 0 ? -ENODEV : 0; 165 } 166 167 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 168 u32 resp_len, void *resp) 169 { 170 struct hw_channel_context *hwc = gc->hwc.driver_data; 171 172 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 173 } 174 EXPORT_SYMBOL_NS(mana_gd_send_request, NET_MANA); 175 176 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 177 struct gdma_mem_info *gmi) 178 { 179 dma_addr_t dma_handle; 180 void *buf; 181 182 if (length < PAGE_SIZE || !is_power_of_2(length)) 183 return -EINVAL; 184 185 gmi->dev = gc->dev; 186 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL); 187 if (!buf) 188 return -ENOMEM; 189 190 gmi->dma_handle = dma_handle; 191 gmi->virt_addr = buf; 192 gmi->length = length; 193 194 return 0; 195 } 196 197 void mana_gd_free_memory(struct gdma_mem_info *gmi) 198 { 199 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr, 200 gmi->dma_handle); 201 } 202 203 static int mana_gd_create_hw_eq(struct gdma_context *gc, 204 struct gdma_queue *queue) 205 { 206 struct gdma_create_queue_resp resp = {}; 207 struct gdma_create_queue_req req = {}; 208 int err; 209 210 if (queue->type != GDMA_EQ) 211 return -EINVAL; 212 213 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 214 sizeof(req), sizeof(resp)); 215 216 req.hdr.dev_id = queue->gdma_dev->dev_id; 217 req.type = queue->type; 218 req.pdid = queue->gdma_dev->pdid; 219 req.doolbell_id = queue->gdma_dev->doorbell; 220 req.gdma_region = queue->mem_info.dma_region_handle; 221 req.queue_size = queue->queue_size; 222 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 223 req.eq_pci_msix_index = queue->eq.msix_index; 224 225 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 226 if (err || resp.hdr.status) { 227 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err, 228 resp.hdr.status); 229 return err ? err : -EPROTO; 230 } 231 232 queue->id = resp.queue_index; 233 queue->eq.disable_needed = true; 234 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 235 return 0; 236 } 237 238 static int mana_gd_disable_queue(struct gdma_queue *queue) 239 { 240 struct gdma_context *gc = queue->gdma_dev->gdma_context; 241 struct gdma_disable_queue_req req = {}; 242 struct gdma_general_resp resp = {}; 243 int err; 244 245 WARN_ON(queue->type != GDMA_EQ); 246 247 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 248 sizeof(req), sizeof(resp)); 249 250 req.hdr.dev_id = queue->gdma_dev->dev_id; 251 req.type = queue->type; 252 req.queue_index = queue->id; 253 req.alloc_res_id_on_creation = 1; 254 255 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 256 if (err || resp.hdr.status) { 257 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err, 258 resp.hdr.status); 259 return err ? err : -EPROTO; 260 } 261 262 return 0; 263 } 264 265 #define DOORBELL_OFFSET_SQ 0x0 266 #define DOORBELL_OFFSET_RQ 0x400 267 #define DOORBELL_OFFSET_CQ 0x800 268 #define DOORBELL_OFFSET_EQ 0xFF8 269 270 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index, 271 enum gdma_queue_type q_type, u32 qid, 272 u32 tail_ptr, u8 num_req) 273 { 274 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index; 275 union gdma_doorbell_entry e = {}; 276 277 switch (q_type) { 278 case GDMA_EQ: 279 e.eq.id = qid; 280 e.eq.tail_ptr = tail_ptr; 281 e.eq.arm = num_req; 282 283 addr += DOORBELL_OFFSET_EQ; 284 break; 285 286 case GDMA_CQ: 287 e.cq.id = qid; 288 e.cq.tail_ptr = tail_ptr; 289 e.cq.arm = num_req; 290 291 addr += DOORBELL_OFFSET_CQ; 292 break; 293 294 case GDMA_RQ: 295 e.rq.id = qid; 296 e.rq.tail_ptr = tail_ptr; 297 e.rq.wqe_cnt = num_req; 298 299 addr += DOORBELL_OFFSET_RQ; 300 break; 301 302 case GDMA_SQ: 303 e.sq.id = qid; 304 e.sq.tail_ptr = tail_ptr; 305 306 addr += DOORBELL_OFFSET_SQ; 307 break; 308 309 default: 310 WARN_ON(1); 311 return; 312 } 313 314 /* Ensure all writes are done before ring doorbell */ 315 wmb(); 316 317 writeq(e.as_uint64, addr); 318 } 319 320 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 321 { 322 /* Hardware Spec specifies that software client should set 0 for 323 * wqe_cnt for Receive Queues. This value is not used in Send Queues. 324 */ 325 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 326 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 327 } 328 329 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit) 330 { 331 struct gdma_context *gc = cq->gdma_dev->gdma_context; 332 333 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE; 334 335 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 336 337 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 338 head, arm_bit); 339 } 340 341 static void mana_gd_process_eqe(struct gdma_queue *eq) 342 { 343 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 344 struct gdma_context *gc = eq->gdma_dev->gdma_context; 345 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 346 union gdma_eqe_info eqe_info; 347 enum gdma_eqe_type type; 348 struct gdma_event event; 349 struct gdma_queue *cq; 350 struct gdma_eqe *eqe; 351 u32 cq_id; 352 353 eqe = &eq_eqe_ptr[head]; 354 eqe_info.as_uint32 = eqe->eqe_info; 355 type = eqe_info.type; 356 357 switch (type) { 358 case GDMA_EQE_COMPLETION: 359 cq_id = eqe->details[0] & 0xFFFFFF; 360 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs)) 361 break; 362 363 cq = gc->cq_table[cq_id]; 364 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id)) 365 break; 366 367 if (cq->cq.callback) 368 cq->cq.callback(cq->cq.context, cq); 369 370 break; 371 372 case GDMA_EQE_TEST_EVENT: 373 gc->test_event_eq_id = eq->id; 374 complete(&gc->eq_test_event); 375 break; 376 377 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 378 case GDMA_EQE_HWC_INIT_DATA: 379 case GDMA_EQE_HWC_INIT_DONE: 380 if (!eq->eq.callback) 381 break; 382 383 event.type = type; 384 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 385 eq->eq.callback(eq->eq.context, eq, &event); 386 break; 387 388 default: 389 break; 390 } 391 } 392 393 static void mana_gd_process_eq_events(void *arg) 394 { 395 u32 owner_bits, new_bits, old_bits; 396 union gdma_eqe_info eqe_info; 397 struct gdma_eqe *eq_eqe_ptr; 398 struct gdma_queue *eq = arg; 399 struct gdma_context *gc; 400 struct gdma_eqe *eqe; 401 u32 head, num_eqe; 402 int i; 403 404 gc = eq->gdma_dev->gdma_context; 405 406 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 407 eq_eqe_ptr = eq->queue_mem_ptr; 408 409 /* Process up to 5 EQEs at a time, and update the HW head. */ 410 for (i = 0; i < 5; i++) { 411 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 412 eqe_info.as_uint32 = eqe->eqe_info; 413 owner_bits = eqe_info.owner_bits; 414 415 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 416 /* No more entries */ 417 if (owner_bits == old_bits) 418 break; 419 420 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 421 if (owner_bits != new_bits) { 422 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id); 423 break; 424 } 425 426 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 427 * reading eqe. 428 */ 429 rmb(); 430 431 mana_gd_process_eqe(eq); 432 433 eq->head++; 434 } 435 436 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 437 438 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 439 head, SET_ARM_BIT); 440 } 441 442 static int mana_gd_register_irq(struct gdma_queue *queue, 443 const struct gdma_queue_spec *spec) 444 { 445 struct gdma_dev *gd = queue->gdma_dev; 446 struct gdma_irq_context *gic; 447 struct gdma_context *gc; 448 struct gdma_resource *r; 449 unsigned int msi_index; 450 unsigned long flags; 451 struct device *dev; 452 int err = 0; 453 454 gc = gd->gdma_context; 455 r = &gc->msix_resource; 456 dev = gc->dev; 457 458 spin_lock_irqsave(&r->lock, flags); 459 460 msi_index = find_first_zero_bit(r->map, r->size); 461 if (msi_index >= r->size || msi_index >= gc->num_msix_usable) { 462 err = -ENOSPC; 463 } else { 464 bitmap_set(r->map, msi_index, 1); 465 queue->eq.msix_index = msi_index; 466 } 467 468 spin_unlock_irqrestore(&r->lock, flags); 469 470 if (err) { 471 dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u", 472 err, msi_index, r->size, gc->num_msix_usable); 473 474 return err; 475 } 476 477 gic = &gc->irq_contexts[msi_index]; 478 479 WARN_ON(gic->handler || gic->arg); 480 481 gic->arg = queue; 482 483 gic->handler = mana_gd_process_eq_events; 484 485 return 0; 486 } 487 488 static void mana_gd_deregiser_irq(struct gdma_queue *queue) 489 { 490 struct gdma_dev *gd = queue->gdma_dev; 491 struct gdma_irq_context *gic; 492 struct gdma_context *gc; 493 struct gdma_resource *r; 494 unsigned int msix_index; 495 unsigned long flags; 496 497 gc = gd->gdma_context; 498 r = &gc->msix_resource; 499 500 /* At most num_online_cpus() + 1 interrupts are used. */ 501 msix_index = queue->eq.msix_index; 502 if (WARN_ON(msix_index >= gc->num_msix_usable)) 503 return; 504 505 gic = &gc->irq_contexts[msix_index]; 506 gic->handler = NULL; 507 gic->arg = NULL; 508 509 spin_lock_irqsave(&r->lock, flags); 510 bitmap_clear(r->map, msix_index, 1); 511 spin_unlock_irqrestore(&r->lock, flags); 512 513 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 514 } 515 516 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 517 { 518 struct gdma_generate_test_event_req req = {}; 519 struct gdma_general_resp resp = {}; 520 struct device *dev = gc->dev; 521 int err; 522 523 mutex_lock(&gc->eq_test_event_mutex); 524 525 init_completion(&gc->eq_test_event); 526 gc->test_event_eq_id = INVALID_QUEUE_ID; 527 528 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 529 sizeof(req), sizeof(resp)); 530 531 req.hdr.dev_id = eq->gdma_dev->dev_id; 532 req.queue_index = eq->id; 533 534 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 535 if (err) { 536 dev_err(dev, "test_eq failed: %d\n", err); 537 goto out; 538 } 539 540 err = -EPROTO; 541 542 if (resp.hdr.status) { 543 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status); 544 goto out; 545 } 546 547 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) { 548 dev_err(dev, "test_eq timed out on queue %d\n", eq->id); 549 goto out; 550 } 551 552 if (eq->id != gc->test_event_eq_id) { 553 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n", 554 gc->test_event_eq_id, eq->id); 555 goto out; 556 } 557 558 err = 0; 559 out: 560 mutex_unlock(&gc->eq_test_event_mutex); 561 return err; 562 } 563 564 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 565 struct gdma_queue *queue) 566 { 567 int err; 568 569 if (flush_evenets) { 570 err = mana_gd_test_eq(gc, queue); 571 if (err) 572 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err); 573 } 574 575 mana_gd_deregiser_irq(queue); 576 577 if (queue->eq.disable_needed) 578 mana_gd_disable_queue(queue); 579 } 580 581 static int mana_gd_create_eq(struct gdma_dev *gd, 582 const struct gdma_queue_spec *spec, 583 bool create_hwq, struct gdma_queue *queue) 584 { 585 struct gdma_context *gc = gd->gdma_context; 586 struct device *dev = gc->dev; 587 u32 log2_num_entries; 588 int err; 589 590 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 591 592 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 593 594 if (spec->eq.log2_throttle_limit > log2_num_entries) { 595 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n", 596 spec->eq.log2_throttle_limit, log2_num_entries); 597 return -EINVAL; 598 } 599 600 err = mana_gd_register_irq(queue, spec); 601 if (err) { 602 dev_err(dev, "Failed to register irq: %d\n", err); 603 return err; 604 } 605 606 queue->eq.callback = spec->eq.callback; 607 queue->eq.context = spec->eq.context; 608 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 609 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 610 611 if (create_hwq) { 612 err = mana_gd_create_hw_eq(gc, queue); 613 if (err) 614 goto out; 615 616 err = mana_gd_test_eq(gc, queue); 617 if (err) 618 goto out; 619 } 620 621 return 0; 622 out: 623 dev_err(dev, "Failed to create EQ: %d\n", err); 624 mana_gd_destroy_eq(gc, false, queue); 625 return err; 626 } 627 628 static void mana_gd_create_cq(const struct gdma_queue_spec *spec, 629 struct gdma_queue *queue) 630 { 631 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 632 633 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 634 queue->cq.parent = spec->cq.parent_eq; 635 queue->cq.context = spec->cq.context; 636 queue->cq.callback = spec->cq.callback; 637 } 638 639 static void mana_gd_destroy_cq(struct gdma_context *gc, 640 struct gdma_queue *queue) 641 { 642 u32 id = queue->id; 643 644 if (id >= gc->max_num_cqs) 645 return; 646 647 if (!gc->cq_table[id]) 648 return; 649 650 gc->cq_table[id] = NULL; 651 } 652 653 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 654 const struct gdma_queue_spec *spec, 655 struct gdma_queue **queue_ptr) 656 { 657 struct gdma_context *gc = gd->gdma_context; 658 struct gdma_mem_info *gmi; 659 struct gdma_queue *queue; 660 int err; 661 662 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 663 if (!queue) 664 return -ENOMEM; 665 666 gmi = &queue->mem_info; 667 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 668 if (err) 669 goto free_q; 670 671 queue->head = 0; 672 queue->tail = 0; 673 queue->queue_mem_ptr = gmi->virt_addr; 674 queue->queue_size = spec->queue_size; 675 queue->monitor_avl_buf = spec->monitor_avl_buf; 676 queue->type = spec->type; 677 queue->gdma_dev = gd; 678 679 if (spec->type == GDMA_EQ) 680 err = mana_gd_create_eq(gd, spec, false, queue); 681 else if (spec->type == GDMA_CQ) 682 mana_gd_create_cq(spec, queue); 683 684 if (err) 685 goto out; 686 687 *queue_ptr = queue; 688 return 0; 689 out: 690 mana_gd_free_memory(gmi); 691 free_q: 692 kfree(queue); 693 return err; 694 } 695 696 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle) 697 { 698 struct gdma_destroy_dma_region_req req = {}; 699 struct gdma_general_resp resp = {}; 700 int err; 701 702 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 703 return 0; 704 705 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 706 sizeof(resp)); 707 req.dma_region_handle = dma_region_handle; 708 709 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 710 if (err || resp.hdr.status) { 711 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n", 712 err, resp.hdr.status); 713 return -EPROTO; 714 } 715 716 return 0; 717 } 718 EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, NET_MANA); 719 720 static int mana_gd_create_dma_region(struct gdma_dev *gd, 721 struct gdma_mem_info *gmi) 722 { 723 unsigned int num_page = gmi->length / PAGE_SIZE; 724 struct gdma_create_dma_region_req *req = NULL; 725 struct gdma_create_dma_region_resp resp = {}; 726 struct gdma_context *gc = gd->gdma_context; 727 struct hw_channel_context *hwc; 728 u32 length = gmi->length; 729 size_t req_msg_size; 730 int err; 731 int i; 732 733 if (length < PAGE_SIZE || !is_power_of_2(length)) 734 return -EINVAL; 735 736 if (offset_in_page(gmi->virt_addr) != 0) 737 return -EINVAL; 738 739 hwc = gc->hwc.driver_data; 740 req_msg_size = struct_size(req, page_addr_list, num_page); 741 if (req_msg_size > hwc->max_req_msg_size) 742 return -EINVAL; 743 744 req = kzalloc(req_msg_size, GFP_KERNEL); 745 if (!req) 746 return -ENOMEM; 747 748 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 749 req_msg_size, sizeof(resp)); 750 req->length = length; 751 req->offset_in_page = 0; 752 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 753 req->page_count = num_page; 754 req->page_addr_list_len = num_page; 755 756 for (i = 0; i < num_page; i++) 757 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 758 759 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 760 if (err) 761 goto out; 762 763 if (resp.hdr.status || 764 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 765 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n", 766 resp.hdr.status); 767 err = -EPROTO; 768 goto out; 769 } 770 771 gmi->dma_region_handle = resp.dma_region_handle; 772 out: 773 kfree(req); 774 return err; 775 } 776 777 int mana_gd_create_mana_eq(struct gdma_dev *gd, 778 const struct gdma_queue_spec *spec, 779 struct gdma_queue **queue_ptr) 780 { 781 struct gdma_context *gc = gd->gdma_context; 782 struct gdma_mem_info *gmi; 783 struct gdma_queue *queue; 784 int err; 785 786 if (spec->type != GDMA_EQ) 787 return -EINVAL; 788 789 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 790 if (!queue) 791 return -ENOMEM; 792 793 gmi = &queue->mem_info; 794 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 795 if (err) 796 goto free_q; 797 798 err = mana_gd_create_dma_region(gd, gmi); 799 if (err) 800 goto out; 801 802 queue->head = 0; 803 queue->tail = 0; 804 queue->queue_mem_ptr = gmi->virt_addr; 805 queue->queue_size = spec->queue_size; 806 queue->monitor_avl_buf = spec->monitor_avl_buf; 807 queue->type = spec->type; 808 queue->gdma_dev = gd; 809 810 err = mana_gd_create_eq(gd, spec, true, queue); 811 if (err) 812 goto out; 813 814 *queue_ptr = queue; 815 return 0; 816 out: 817 mana_gd_free_memory(gmi); 818 free_q: 819 kfree(queue); 820 return err; 821 } 822 823 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 824 const struct gdma_queue_spec *spec, 825 struct gdma_queue **queue_ptr) 826 { 827 struct gdma_context *gc = gd->gdma_context; 828 struct gdma_mem_info *gmi; 829 struct gdma_queue *queue; 830 int err; 831 832 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 833 spec->type != GDMA_RQ) 834 return -EINVAL; 835 836 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 837 if (!queue) 838 return -ENOMEM; 839 840 gmi = &queue->mem_info; 841 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 842 if (err) 843 goto free_q; 844 845 err = mana_gd_create_dma_region(gd, gmi); 846 if (err) 847 goto out; 848 849 queue->head = 0; 850 queue->tail = 0; 851 queue->queue_mem_ptr = gmi->virt_addr; 852 queue->queue_size = spec->queue_size; 853 queue->monitor_avl_buf = spec->monitor_avl_buf; 854 queue->type = spec->type; 855 queue->gdma_dev = gd; 856 857 if (spec->type == GDMA_CQ) 858 mana_gd_create_cq(spec, queue); 859 860 *queue_ptr = queue; 861 return 0; 862 out: 863 mana_gd_free_memory(gmi); 864 free_q: 865 kfree(queue); 866 return err; 867 } 868 869 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 870 { 871 struct gdma_mem_info *gmi = &queue->mem_info; 872 873 switch (queue->type) { 874 case GDMA_EQ: 875 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 876 break; 877 878 case GDMA_CQ: 879 mana_gd_destroy_cq(gc, queue); 880 break; 881 882 case GDMA_RQ: 883 break; 884 885 case GDMA_SQ: 886 break; 887 888 default: 889 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n", 890 queue->type); 891 return; 892 } 893 894 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 895 mana_gd_free_memory(gmi); 896 kfree(queue); 897 } 898 899 int mana_gd_verify_vf_version(struct pci_dev *pdev) 900 { 901 struct gdma_context *gc = pci_get_drvdata(pdev); 902 struct gdma_verify_ver_resp resp = {}; 903 struct gdma_verify_ver_req req = {}; 904 struct hw_channel_context *hwc; 905 int err; 906 907 hwc = gc->hwc.driver_data; 908 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 909 sizeof(req), sizeof(resp)); 910 911 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 912 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 913 914 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1; 915 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2; 916 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3; 917 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4; 918 919 req.drv_ver = 0; /* Unused*/ 920 req.os_type = 0x10; /* Linux */ 921 req.os_ver_major = LINUX_VERSION_MAJOR; 922 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL; 923 req.os_ver_build = LINUX_VERSION_SUBLEVEL; 924 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1)); 925 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2)); 926 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3)); 927 928 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 929 if (err || resp.hdr.status) { 930 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n", 931 err, resp.hdr.status); 932 return err ? err : -EPROTO; 933 } 934 if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) { 935 err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout); 936 if (err) { 937 dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err); 938 return err; 939 } 940 dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout); 941 } 942 return 0; 943 } 944 945 int mana_gd_register_device(struct gdma_dev *gd) 946 { 947 struct gdma_context *gc = gd->gdma_context; 948 struct gdma_register_device_resp resp = {}; 949 struct gdma_general_req req = {}; 950 int err; 951 952 gd->pdid = INVALID_PDID; 953 gd->doorbell = INVALID_DOORBELL; 954 gd->gpa_mkey = INVALID_MEM_KEY; 955 956 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 957 sizeof(resp)); 958 959 req.hdr.dev_id = gd->dev_id; 960 961 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 962 if (err || resp.hdr.status) { 963 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n", 964 err, resp.hdr.status); 965 return err ? err : -EPROTO; 966 } 967 968 gd->pdid = resp.pdid; 969 gd->gpa_mkey = resp.gpa_mkey; 970 gd->doorbell = resp.db_id; 971 972 return 0; 973 } 974 975 int mana_gd_deregister_device(struct gdma_dev *gd) 976 { 977 struct gdma_context *gc = gd->gdma_context; 978 struct gdma_general_resp resp = {}; 979 struct gdma_general_req req = {}; 980 int err; 981 982 if (gd->pdid == INVALID_PDID) 983 return -EINVAL; 984 985 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 986 sizeof(resp)); 987 988 req.hdr.dev_id = gd->dev_id; 989 990 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 991 if (err || resp.hdr.status) { 992 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n", 993 err, resp.hdr.status); 994 if (!err) 995 err = -EPROTO; 996 } 997 998 gd->pdid = INVALID_PDID; 999 gd->doorbell = INVALID_DOORBELL; 1000 gd->gpa_mkey = INVALID_MEM_KEY; 1001 1002 return err; 1003 } 1004 1005 u32 mana_gd_wq_avail_space(struct gdma_queue *wq) 1006 { 1007 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1008 u32 wq_size = wq->queue_size; 1009 1010 WARN_ON_ONCE(used_space > wq_size); 1011 1012 return wq_size - used_space; 1013 } 1014 1015 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset) 1016 { 1017 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1018 1019 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size); 1020 1021 return wq->queue_mem_ptr + offset; 1022 } 1023 1024 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1025 enum gdma_queue_type q_type, 1026 u32 client_oob_size, u32 sgl_data_size, 1027 u8 *wqe_ptr) 1028 { 1029 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1030 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1031 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1032 u8 *ptr; 1033 1034 memset(header, 0, sizeof(struct gdma_wqe)); 1035 header->num_sge = wqe_req->num_sge; 1036 header->inline_oob_size_div4 = client_oob_size / sizeof(u32); 1037 1038 if (oob_in_sgl) { 1039 WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2); 1040 1041 header->client_oob_in_sgl = 1; 1042 1043 if (pad_data) 1044 header->last_vbytes = wqe_req->sgl[0].size; 1045 } 1046 1047 if (q_type == GDMA_SQ) 1048 header->client_data_unit = wqe_req->client_data_unit; 1049 1050 /* The size of gdma_wqe + client_oob_size must be less than or equal 1051 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1052 * the queue memory buffer boundary. 1053 */ 1054 ptr = wqe_ptr + sizeof(header); 1055 1056 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1057 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1058 1059 if (client_oob_size > wqe_req->inline_oob_size) 1060 memset(ptr + wqe_req->inline_oob_size, 0, 1061 client_oob_size - wqe_req->inline_oob_size); 1062 } 1063 1064 return sizeof(header) + client_oob_size; 1065 } 1066 1067 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr, 1068 const struct gdma_wqe_request *wqe_req) 1069 { 1070 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1071 const u8 *address = (u8 *)wqe_req->sgl; 1072 u8 *base_ptr, *end_ptr; 1073 u32 size_to_end; 1074 1075 base_ptr = wq->queue_mem_ptr; 1076 end_ptr = base_ptr + wq->queue_size; 1077 size_to_end = (u32)(end_ptr - wqe_ptr); 1078 1079 if (size_to_end < sgl_size) { 1080 memcpy(wqe_ptr, address, size_to_end); 1081 1082 wqe_ptr = base_ptr; 1083 address += size_to_end; 1084 sgl_size -= size_to_end; 1085 } 1086 1087 memcpy(wqe_ptr, address, sgl_size); 1088 } 1089 1090 int mana_gd_post_work_request(struct gdma_queue *wq, 1091 const struct gdma_wqe_request *wqe_req, 1092 struct gdma_posted_wqe_info *wqe_info) 1093 { 1094 u32 client_oob_size = wqe_req->inline_oob_size; 1095 struct gdma_context *gc; 1096 u32 sgl_data_size; 1097 u32 max_wqe_size; 1098 u32 wqe_size; 1099 u8 *wqe_ptr; 1100 1101 if (wqe_req->num_sge == 0) 1102 return -EINVAL; 1103 1104 if (wq->type == GDMA_RQ) { 1105 if (client_oob_size != 0) 1106 return -EINVAL; 1107 1108 client_oob_size = INLINE_OOB_SMALL_SIZE; 1109 1110 max_wqe_size = GDMA_MAX_RQE_SIZE; 1111 } else { 1112 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1113 client_oob_size != INLINE_OOB_LARGE_SIZE) 1114 return -EINVAL; 1115 1116 max_wqe_size = GDMA_MAX_SQE_SIZE; 1117 } 1118 1119 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1120 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1121 sgl_data_size, GDMA_WQE_BU_SIZE); 1122 if (wqe_size > max_wqe_size) 1123 return -EINVAL; 1124 1125 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1126 gc = wq->gdma_dev->gdma_context; 1127 dev_err(gc->dev, "unsuccessful flow control!\n"); 1128 return -ENOSPC; 1129 } 1130 1131 if (wqe_info) 1132 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1133 1134 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1135 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1136 sgl_data_size, wqe_ptr); 1137 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size) 1138 wqe_ptr -= wq->queue_size; 1139 1140 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1141 1142 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1143 1144 return 0; 1145 } 1146 1147 int mana_gd_post_and_ring(struct gdma_queue *queue, 1148 const struct gdma_wqe_request *wqe_req, 1149 struct gdma_posted_wqe_info *wqe_info) 1150 { 1151 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1152 int err; 1153 1154 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1155 if (err) 1156 return err; 1157 1158 mana_gd_wq_ring_doorbell(gc, queue); 1159 1160 return 0; 1161 } 1162 1163 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1164 { 1165 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1166 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1167 u32 owner_bits, new_bits, old_bits; 1168 struct gdma_cqe *cqe; 1169 1170 cqe = &cq_cqe[cq->head % num_cqe]; 1171 owner_bits = cqe->cqe_info.owner_bits; 1172 1173 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1174 /* Return 0 if no more entries. */ 1175 if (owner_bits == old_bits) 1176 return 0; 1177 1178 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1179 /* Return -1 if overflow detected. */ 1180 if (WARN_ON_ONCE(owner_bits != new_bits)) 1181 return -1; 1182 1183 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 1184 * reading completion info 1185 */ 1186 rmb(); 1187 1188 comp->wq_num = cqe->cqe_info.wq_num; 1189 comp->is_sq = cqe->cqe_info.is_sq; 1190 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1191 1192 return 1; 1193 } 1194 1195 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1196 { 1197 int cqe_idx; 1198 int ret; 1199 1200 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1201 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1202 1203 if (ret < 0) { 1204 cq->head -= cqe_idx; 1205 return ret; 1206 } 1207 1208 if (ret == 0) 1209 break; 1210 1211 cq->head++; 1212 } 1213 1214 return cqe_idx; 1215 } 1216 1217 static irqreturn_t mana_gd_intr(int irq, void *arg) 1218 { 1219 struct gdma_irq_context *gic = arg; 1220 1221 if (gic->handler) 1222 gic->handler(gic->arg); 1223 1224 return IRQ_HANDLED; 1225 } 1226 1227 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r) 1228 { 1229 r->map = bitmap_zalloc(res_avail, GFP_KERNEL); 1230 if (!r->map) 1231 return -ENOMEM; 1232 1233 r->size = res_avail; 1234 spin_lock_init(&r->lock); 1235 1236 return 0; 1237 } 1238 1239 void mana_gd_free_res_map(struct gdma_resource *r) 1240 { 1241 bitmap_free(r->map); 1242 r->map = NULL; 1243 r->size = 0; 1244 } 1245 1246 static int mana_gd_setup_irqs(struct pci_dev *pdev) 1247 { 1248 unsigned int max_queues_per_port = num_online_cpus(); 1249 struct gdma_context *gc = pci_get_drvdata(pdev); 1250 struct gdma_irq_context *gic; 1251 unsigned int max_irqs, cpu; 1252 int nvec, irq; 1253 int err, i = 0, j; 1254 1255 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1256 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1257 1258 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1259 max_irqs = max_queues_per_port + 1; 1260 1261 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); 1262 if (nvec < 0) 1263 return nvec; 1264 1265 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context), 1266 GFP_KERNEL); 1267 if (!gc->irq_contexts) { 1268 err = -ENOMEM; 1269 goto free_irq_vector; 1270 } 1271 1272 for (i = 0; i < nvec; i++) { 1273 gic = &gc->irq_contexts[i]; 1274 gic->handler = NULL; 1275 gic->arg = NULL; 1276 1277 if (!i) 1278 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s", 1279 pci_name(pdev)); 1280 else 1281 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", 1282 i - 1, pci_name(pdev)); 1283 1284 irq = pci_irq_vector(pdev, i); 1285 if (irq < 0) { 1286 err = irq; 1287 goto free_irq; 1288 } 1289 1290 err = request_irq(irq, mana_gd_intr, 0, gic->name, gic); 1291 if (err) 1292 goto free_irq; 1293 1294 cpu = cpumask_local_spread(i, gc->numa_node); 1295 irq_set_affinity_and_hint(irq, cpumask_of(cpu)); 1296 } 1297 1298 err = mana_gd_alloc_res_map(nvec, &gc->msix_resource); 1299 if (err) 1300 goto free_irq; 1301 1302 gc->max_num_msix = nvec; 1303 gc->num_msix_usable = nvec; 1304 1305 return 0; 1306 1307 free_irq: 1308 for (j = i - 1; j >= 0; j--) { 1309 irq = pci_irq_vector(pdev, j); 1310 gic = &gc->irq_contexts[j]; 1311 1312 irq_update_affinity_hint(irq, NULL); 1313 free_irq(irq, gic); 1314 } 1315 1316 kfree(gc->irq_contexts); 1317 gc->irq_contexts = NULL; 1318 free_irq_vector: 1319 pci_free_irq_vectors(pdev); 1320 return err; 1321 } 1322 1323 static void mana_gd_remove_irqs(struct pci_dev *pdev) 1324 { 1325 struct gdma_context *gc = pci_get_drvdata(pdev); 1326 struct gdma_irq_context *gic; 1327 int irq, i; 1328 1329 if (gc->max_num_msix < 1) 1330 return; 1331 1332 mana_gd_free_res_map(&gc->msix_resource); 1333 1334 for (i = 0; i < gc->max_num_msix; i++) { 1335 irq = pci_irq_vector(pdev, i); 1336 if (irq < 0) 1337 continue; 1338 1339 gic = &gc->irq_contexts[i]; 1340 1341 /* Need to clear the hint before free_irq */ 1342 irq_update_affinity_hint(irq, NULL); 1343 free_irq(irq, gic); 1344 } 1345 1346 pci_free_irq_vectors(pdev); 1347 1348 gc->max_num_msix = 0; 1349 gc->num_msix_usable = 0; 1350 kfree(gc->irq_contexts); 1351 gc->irq_contexts = NULL; 1352 } 1353 1354 static int mana_gd_setup(struct pci_dev *pdev) 1355 { 1356 struct gdma_context *gc = pci_get_drvdata(pdev); 1357 int err; 1358 1359 mana_gd_init_registers(pdev); 1360 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1361 1362 err = mana_gd_setup_irqs(pdev); 1363 if (err) 1364 return err; 1365 1366 err = mana_hwc_create_channel(gc); 1367 if (err) 1368 goto remove_irq; 1369 1370 err = mana_gd_verify_vf_version(pdev); 1371 if (err) 1372 goto destroy_hwc; 1373 1374 err = mana_gd_query_max_resources(pdev); 1375 if (err) 1376 goto destroy_hwc; 1377 1378 err = mana_gd_detect_devices(pdev); 1379 if (err) 1380 goto destroy_hwc; 1381 1382 return 0; 1383 1384 destroy_hwc: 1385 mana_hwc_destroy_channel(gc); 1386 remove_irq: 1387 mana_gd_remove_irqs(pdev); 1388 return err; 1389 } 1390 1391 static void mana_gd_cleanup(struct pci_dev *pdev) 1392 { 1393 struct gdma_context *gc = pci_get_drvdata(pdev); 1394 1395 mana_hwc_destroy_channel(gc); 1396 1397 mana_gd_remove_irqs(pdev); 1398 } 1399 1400 static bool mana_is_pf(unsigned short dev_id) 1401 { 1402 return dev_id == MANA_PF_DEVICE_ID; 1403 } 1404 1405 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1406 { 1407 struct gdma_context *gc; 1408 void __iomem *bar0_va; 1409 int bar = 0; 1410 int err; 1411 1412 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */ 1413 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE); 1414 1415 err = pci_enable_device(pdev); 1416 if (err) 1417 return -ENXIO; 1418 1419 pci_set_master(pdev); 1420 1421 err = pci_request_regions(pdev, "mana"); 1422 if (err) 1423 goto disable_dev; 1424 1425 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1426 if (err) 1427 goto release_region; 1428 1429 err = dma_set_max_seg_size(&pdev->dev, UINT_MAX); 1430 if (err) { 1431 dev_err(&pdev->dev, "Failed to set dma device segment size\n"); 1432 goto release_region; 1433 } 1434 1435 err = -ENOMEM; 1436 gc = vzalloc(sizeof(*gc)); 1437 if (!gc) 1438 goto release_region; 1439 1440 mutex_init(&gc->eq_test_event_mutex); 1441 pci_set_drvdata(pdev, gc); 1442 gc->bar0_pa = pci_resource_start(pdev, 0); 1443 1444 bar0_va = pci_iomap(pdev, bar, 0); 1445 if (!bar0_va) 1446 goto free_gc; 1447 1448 gc->numa_node = dev_to_node(&pdev->dev); 1449 gc->is_pf = mana_is_pf(pdev->device); 1450 gc->bar0_va = bar0_va; 1451 gc->dev = &pdev->dev; 1452 1453 err = mana_gd_setup(pdev); 1454 if (err) 1455 goto unmap_bar; 1456 1457 err = mana_probe(&gc->mana, false); 1458 if (err) 1459 goto cleanup_gd; 1460 1461 return 0; 1462 1463 cleanup_gd: 1464 mana_gd_cleanup(pdev); 1465 unmap_bar: 1466 pci_iounmap(pdev, bar0_va); 1467 free_gc: 1468 pci_set_drvdata(pdev, NULL); 1469 vfree(gc); 1470 release_region: 1471 pci_release_regions(pdev); 1472 disable_dev: 1473 pci_disable_device(pdev); 1474 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err); 1475 return err; 1476 } 1477 1478 static void mana_gd_remove(struct pci_dev *pdev) 1479 { 1480 struct gdma_context *gc = pci_get_drvdata(pdev); 1481 1482 mana_remove(&gc->mana, false); 1483 1484 mana_gd_cleanup(pdev); 1485 1486 pci_iounmap(pdev, gc->bar0_va); 1487 1488 vfree(gc); 1489 1490 pci_release_regions(pdev); 1491 pci_disable_device(pdev); 1492 } 1493 1494 /* The 'state' parameter is not used. */ 1495 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state) 1496 { 1497 struct gdma_context *gc = pci_get_drvdata(pdev); 1498 1499 mana_remove(&gc->mana, true); 1500 1501 mana_gd_cleanup(pdev); 1502 1503 return 0; 1504 } 1505 1506 /* In case the NIC hardware stops working, the suspend and resume callbacks will 1507 * fail -- if this happens, it's safer to just report an error than try to undo 1508 * what has been done. 1509 */ 1510 static int mana_gd_resume(struct pci_dev *pdev) 1511 { 1512 struct gdma_context *gc = pci_get_drvdata(pdev); 1513 int err; 1514 1515 err = mana_gd_setup(pdev); 1516 if (err) 1517 return err; 1518 1519 err = mana_probe(&gc->mana, true); 1520 if (err) 1521 return err; 1522 1523 return 0; 1524 } 1525 1526 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */ 1527 static void mana_gd_shutdown(struct pci_dev *pdev) 1528 { 1529 struct gdma_context *gc = pci_get_drvdata(pdev); 1530 1531 dev_info(&pdev->dev, "Shutdown was called\n"); 1532 1533 mana_remove(&gc->mana, true); 1534 1535 mana_gd_cleanup(pdev); 1536 1537 pci_disable_device(pdev); 1538 } 1539 1540 static const struct pci_device_id mana_id_table[] = { 1541 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) }, 1542 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) }, 1543 { } 1544 }; 1545 1546 static struct pci_driver mana_driver = { 1547 .name = "mana", 1548 .id_table = mana_id_table, 1549 .probe = mana_gd_probe, 1550 .remove = mana_gd_remove, 1551 .suspend = mana_gd_suspend, 1552 .resume = mana_gd_resume, 1553 .shutdown = mana_gd_shutdown, 1554 }; 1555 1556 module_pci_driver(mana_driver); 1557 1558 MODULE_DEVICE_TABLE(pci, mana_id_table); 1559 1560 MODULE_LICENSE("Dual BSD/GPL"); 1561 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver"); 1562