1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
3  * Microchip VCAP API Test VCAP Model Data
4  */
5 
6 #include <linux/types.h>
7 #include <linux/kernel.h>
8 
9 #include "vcap_api.h"
10 #include "vcap_model_kunit.h"
11 
12 /* keyfields */
13 static const struct vcap_field is0_mll_keyfield[] = {
14 	[VCAP_KF_TYPE] = {
15 		.type = VCAP_FIELD_U32,
16 		.offset = 0,
17 		.width = 2,
18 	},
19 	[VCAP_KF_LOOKUP_FIRST_IS] = {
20 		.type = VCAP_FIELD_BIT,
21 		.offset = 2,
22 		.width = 1,
23 	},
24 	[VCAP_KF_IF_IGR_PORT] = {
25 		.type = VCAP_FIELD_U32,
26 		.offset = 3,
27 		.width = 7,
28 	},
29 	[VCAP_KF_8021Q_VLAN_TAGS] = {
30 		.type = VCAP_FIELD_U32,
31 		.offset = 10,
32 		.width = 3,
33 	},
34 	[VCAP_KF_8021Q_TPID0] = {
35 		.type = VCAP_FIELD_U32,
36 		.offset = 13,
37 		.width = 3,
38 	},
39 	[VCAP_KF_8021Q_VID0] = {
40 		.type = VCAP_FIELD_U32,
41 		.offset = 16,
42 		.width = 12,
43 	},
44 	[VCAP_KF_8021Q_TPID1] = {
45 		.type = VCAP_FIELD_U32,
46 		.offset = 28,
47 		.width = 3,
48 	},
49 	[VCAP_KF_8021Q_VID1] = {
50 		.type = VCAP_FIELD_U32,
51 		.offset = 31,
52 		.width = 12,
53 	},
54 	[VCAP_KF_L2_DMAC] = {
55 		.type = VCAP_FIELD_U48,
56 		.offset = 43,
57 		.width = 48,
58 	},
59 	[VCAP_KF_L2_SMAC] = {
60 		.type = VCAP_FIELD_U48,
61 		.offset = 91,
62 		.width = 48,
63 	},
64 	[VCAP_KF_ETYPE_MPLS] = {
65 		.type = VCAP_FIELD_U32,
66 		.offset = 139,
67 		.width = 2,
68 	},
69 	[VCAP_KF_L4_RNG] = {
70 		.type = VCAP_FIELD_U32,
71 		.offset = 141,
72 		.width = 8,
73 	},
74 };
75 
76 static const struct vcap_field is0_tri_vid_keyfield[] = {
77 	[VCAP_KF_TYPE] = {
78 		.type = VCAP_FIELD_U32,
79 		.offset = 0,
80 		.width = 2,
81 	},
82 	[VCAP_KF_LOOKUP_FIRST_IS] = {
83 		.type = VCAP_FIELD_BIT,
84 		.offset = 2,
85 		.width = 1,
86 	},
87 	[VCAP_KF_IF_IGR_PORT] = {
88 		.type = VCAP_FIELD_U32,
89 		.offset = 3,
90 		.width = 7,
91 	},
92 	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
93 		.type = VCAP_FIELD_U32,
94 		.offset = 10,
95 		.width = 2,
96 	},
97 	[VCAP_KF_LOOKUP_GEN_IDX] = {
98 		.type = VCAP_FIELD_U32,
99 		.offset = 12,
100 		.width = 12,
101 	},
102 	[VCAP_KF_8021Q_VLAN_TAGS] = {
103 		.type = VCAP_FIELD_U32,
104 		.offset = 24,
105 		.width = 3,
106 	},
107 	[VCAP_KF_8021Q_TPID0] = {
108 		.type = VCAP_FIELD_U32,
109 		.offset = 27,
110 		.width = 3,
111 	},
112 	[VCAP_KF_8021Q_PCP0] = {
113 		.type = VCAP_FIELD_U32,
114 		.offset = 30,
115 		.width = 3,
116 	},
117 	[VCAP_KF_8021Q_DEI0] = {
118 		.type = VCAP_FIELD_BIT,
119 		.offset = 33,
120 		.width = 1,
121 	},
122 	[VCAP_KF_8021Q_VID0] = {
123 		.type = VCAP_FIELD_U32,
124 		.offset = 34,
125 		.width = 12,
126 	},
127 	[VCAP_KF_8021Q_TPID1] = {
128 		.type = VCAP_FIELD_U32,
129 		.offset = 46,
130 		.width = 3,
131 	},
132 	[VCAP_KF_8021Q_PCP1] = {
133 		.type = VCAP_FIELD_U32,
134 		.offset = 49,
135 		.width = 3,
136 	},
137 	[VCAP_KF_8021Q_DEI1] = {
138 		.type = VCAP_FIELD_BIT,
139 		.offset = 52,
140 		.width = 1,
141 	},
142 	[VCAP_KF_8021Q_VID1] = {
143 		.type = VCAP_FIELD_U32,
144 		.offset = 53,
145 		.width = 12,
146 	},
147 	[VCAP_KF_8021Q_TPID2] = {
148 		.type = VCAP_FIELD_U32,
149 		.offset = 65,
150 		.width = 3,
151 	},
152 	[VCAP_KF_8021Q_PCP2] = {
153 		.type = VCAP_FIELD_U32,
154 		.offset = 68,
155 		.width = 3,
156 	},
157 	[VCAP_KF_8021Q_DEI2] = {
158 		.type = VCAP_FIELD_BIT,
159 		.offset = 71,
160 		.width = 1,
161 	},
162 	[VCAP_KF_8021Q_VID2] = {
163 		.type = VCAP_FIELD_U32,
164 		.offset = 72,
165 		.width = 12,
166 	},
167 	[VCAP_KF_L4_RNG] = {
168 		.type = VCAP_FIELD_U32,
169 		.offset = 84,
170 		.width = 8,
171 	},
172 	[VCAP_KF_OAM_Y1731_IS] = {
173 		.type = VCAP_FIELD_BIT,
174 		.offset = 92,
175 		.width = 1,
176 	},
177 	[VCAP_KF_OAM_MEL_FLAGS] = {
178 		.type = VCAP_FIELD_U32,
179 		.offset = 93,
180 		.width = 7,
181 	},
182 };
183 
184 static const struct vcap_field is0_ll_full_keyfield[] = {
185 	[VCAP_KF_TYPE] = {
186 		.type = VCAP_FIELD_U32,
187 		.offset = 0,
188 		.width = 2,
189 	},
190 	[VCAP_KF_LOOKUP_FIRST_IS] = {
191 		.type = VCAP_FIELD_BIT,
192 		.offset = 2,
193 		.width = 1,
194 	},
195 	[VCAP_KF_IF_IGR_PORT] = {
196 		.type = VCAP_FIELD_U32,
197 		.offset = 3,
198 		.width = 7,
199 	},
200 	[VCAP_KF_8021Q_VLAN_TAGS] = {
201 		.type = VCAP_FIELD_U32,
202 		.offset = 10,
203 		.width = 3,
204 	},
205 	[VCAP_KF_8021Q_TPID0] = {
206 		.type = VCAP_FIELD_U32,
207 		.offset = 13,
208 		.width = 3,
209 	},
210 	[VCAP_KF_8021Q_PCP0] = {
211 		.type = VCAP_FIELD_U32,
212 		.offset = 16,
213 		.width = 3,
214 	},
215 	[VCAP_KF_8021Q_DEI0] = {
216 		.type = VCAP_FIELD_BIT,
217 		.offset = 19,
218 		.width = 1,
219 	},
220 	[VCAP_KF_8021Q_VID0] = {
221 		.type = VCAP_FIELD_U32,
222 		.offset = 20,
223 		.width = 12,
224 	},
225 	[VCAP_KF_8021Q_TPID1] = {
226 		.type = VCAP_FIELD_U32,
227 		.offset = 32,
228 		.width = 3,
229 	},
230 	[VCAP_KF_8021Q_PCP1] = {
231 		.type = VCAP_FIELD_U32,
232 		.offset = 35,
233 		.width = 3,
234 	},
235 	[VCAP_KF_8021Q_DEI1] = {
236 		.type = VCAP_FIELD_BIT,
237 		.offset = 38,
238 		.width = 1,
239 	},
240 	[VCAP_KF_8021Q_VID1] = {
241 		.type = VCAP_FIELD_U32,
242 		.offset = 39,
243 		.width = 12,
244 	},
245 	[VCAP_KF_8021Q_TPID2] = {
246 		.type = VCAP_FIELD_U32,
247 		.offset = 51,
248 		.width = 3,
249 	},
250 	[VCAP_KF_8021Q_PCP2] = {
251 		.type = VCAP_FIELD_U32,
252 		.offset = 54,
253 		.width = 3,
254 	},
255 	[VCAP_KF_8021Q_DEI2] = {
256 		.type = VCAP_FIELD_BIT,
257 		.offset = 57,
258 		.width = 1,
259 	},
260 	[VCAP_KF_8021Q_VID2] = {
261 		.type = VCAP_FIELD_U32,
262 		.offset = 58,
263 		.width = 12,
264 	},
265 	[VCAP_KF_L2_DMAC] = {
266 		.type = VCAP_FIELD_U48,
267 		.offset = 70,
268 		.width = 48,
269 	},
270 	[VCAP_KF_L2_SMAC] = {
271 		.type = VCAP_FIELD_U48,
272 		.offset = 118,
273 		.width = 48,
274 	},
275 	[VCAP_KF_ETYPE_LEN_IS] = {
276 		.type = VCAP_FIELD_BIT,
277 		.offset = 166,
278 		.width = 1,
279 	},
280 	[VCAP_KF_ETYPE] = {
281 		.type = VCAP_FIELD_U32,
282 		.offset = 167,
283 		.width = 16,
284 	},
285 	[VCAP_KF_IP_SNAP_IS] = {
286 		.type = VCAP_FIELD_BIT,
287 		.offset = 183,
288 		.width = 1,
289 	},
290 	[VCAP_KF_IP4_IS] = {
291 		.type = VCAP_FIELD_BIT,
292 		.offset = 184,
293 		.width = 1,
294 	},
295 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
296 		.type = VCAP_FIELD_U32,
297 		.offset = 185,
298 		.width = 2,
299 	},
300 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
301 		.type = VCAP_FIELD_BIT,
302 		.offset = 187,
303 		.width = 1,
304 	},
305 	[VCAP_KF_L3_OPTIONS_IS] = {
306 		.type = VCAP_FIELD_BIT,
307 		.offset = 188,
308 		.width = 1,
309 	},
310 	[VCAP_KF_L3_DSCP] = {
311 		.type = VCAP_FIELD_U32,
312 		.offset = 189,
313 		.width = 6,
314 	},
315 	[VCAP_KF_L3_IP4_DIP] = {
316 		.type = VCAP_FIELD_U32,
317 		.offset = 195,
318 		.width = 32,
319 	},
320 	[VCAP_KF_L3_IP4_SIP] = {
321 		.type = VCAP_FIELD_U32,
322 		.offset = 227,
323 		.width = 32,
324 	},
325 	[VCAP_KF_TCP_UDP_IS] = {
326 		.type = VCAP_FIELD_BIT,
327 		.offset = 259,
328 		.width = 1,
329 	},
330 	[VCAP_KF_TCP_IS] = {
331 		.type = VCAP_FIELD_BIT,
332 		.offset = 260,
333 		.width = 1,
334 	},
335 	[VCAP_KF_L4_SPORT] = {
336 		.type = VCAP_FIELD_U32,
337 		.offset = 261,
338 		.width = 16,
339 	},
340 	[VCAP_KF_L4_RNG] = {
341 		.type = VCAP_FIELD_U32,
342 		.offset = 277,
343 		.width = 8,
344 	},
345 };
346 
347 static const struct vcap_field is0_normal_keyfield[] = {
348 	[VCAP_KF_TYPE] = {
349 		.type = VCAP_FIELD_U32,
350 		.offset = 0,
351 		.width = 2,
352 	},
353 	[VCAP_KF_LOOKUP_FIRST_IS] = {
354 		.type = VCAP_FIELD_BIT,
355 		.offset = 2,
356 		.width = 1,
357 	},
358 	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
359 		.type = VCAP_FIELD_U32,
360 		.offset = 3,
361 		.width = 2,
362 	},
363 	[VCAP_KF_LOOKUP_GEN_IDX] = {
364 		.type = VCAP_FIELD_U32,
365 		.offset = 5,
366 		.width = 12,
367 	},
368 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
369 		.type = VCAP_FIELD_U32,
370 		.offset = 17,
371 		.width = 2,
372 	},
373 	[VCAP_KF_IF_IGR_PORT_MASK] = {
374 		.type = VCAP_FIELD_U72,
375 		.offset = 19,
376 		.width = 65,
377 	},
378 	[VCAP_KF_L2_MC_IS] = {
379 		.type = VCAP_FIELD_BIT,
380 		.offset = 84,
381 		.width = 1,
382 	},
383 	[VCAP_KF_L2_BC_IS] = {
384 		.type = VCAP_FIELD_BIT,
385 		.offset = 85,
386 		.width = 1,
387 	},
388 	[VCAP_KF_8021Q_VLAN_TAGS] = {
389 		.type = VCAP_FIELD_U32,
390 		.offset = 86,
391 		.width = 3,
392 	},
393 	[VCAP_KF_8021Q_TPID0] = {
394 		.type = VCAP_FIELD_U32,
395 		.offset = 89,
396 		.width = 3,
397 	},
398 	[VCAP_KF_8021Q_PCP0] = {
399 		.type = VCAP_FIELD_U32,
400 		.offset = 92,
401 		.width = 3,
402 	},
403 	[VCAP_KF_8021Q_DEI0] = {
404 		.type = VCAP_FIELD_BIT,
405 		.offset = 95,
406 		.width = 1,
407 	},
408 	[VCAP_KF_8021Q_VID0] = {
409 		.type = VCAP_FIELD_U32,
410 		.offset = 96,
411 		.width = 12,
412 	},
413 	[VCAP_KF_8021Q_TPID1] = {
414 		.type = VCAP_FIELD_U32,
415 		.offset = 108,
416 		.width = 3,
417 	},
418 	[VCAP_KF_8021Q_PCP1] = {
419 		.type = VCAP_FIELD_U32,
420 		.offset = 111,
421 		.width = 3,
422 	},
423 	[VCAP_KF_8021Q_DEI1] = {
424 		.type = VCAP_FIELD_BIT,
425 		.offset = 114,
426 		.width = 1,
427 	},
428 	[VCAP_KF_8021Q_VID1] = {
429 		.type = VCAP_FIELD_U32,
430 		.offset = 115,
431 		.width = 12,
432 	},
433 	[VCAP_KF_8021Q_TPID2] = {
434 		.type = VCAP_FIELD_U32,
435 		.offset = 127,
436 		.width = 3,
437 	},
438 	[VCAP_KF_8021Q_PCP2] = {
439 		.type = VCAP_FIELD_U32,
440 		.offset = 130,
441 		.width = 3,
442 	},
443 	[VCAP_KF_8021Q_DEI2] = {
444 		.type = VCAP_FIELD_BIT,
445 		.offset = 133,
446 		.width = 1,
447 	},
448 	[VCAP_KF_8021Q_VID2] = {
449 		.type = VCAP_FIELD_U32,
450 		.offset = 134,
451 		.width = 12,
452 	},
453 	[VCAP_KF_DST_ENTRY] = {
454 		.type = VCAP_FIELD_BIT,
455 		.offset = 146,
456 		.width = 1,
457 	},
458 	[VCAP_KF_L2_SMAC] = {
459 		.type = VCAP_FIELD_U48,
460 		.offset = 147,
461 		.width = 48,
462 	},
463 	[VCAP_KF_IP_MC_IS] = {
464 		.type = VCAP_FIELD_BIT,
465 		.offset = 195,
466 		.width = 1,
467 	},
468 	[VCAP_KF_ETYPE_LEN_IS] = {
469 		.type = VCAP_FIELD_BIT,
470 		.offset = 196,
471 		.width = 1,
472 	},
473 	[VCAP_KF_ETYPE] = {
474 		.type = VCAP_FIELD_U32,
475 		.offset = 197,
476 		.width = 16,
477 	},
478 	[VCAP_KF_IP_SNAP_IS] = {
479 		.type = VCAP_FIELD_BIT,
480 		.offset = 213,
481 		.width = 1,
482 	},
483 	[VCAP_KF_IP4_IS] = {
484 		.type = VCAP_FIELD_BIT,
485 		.offset = 214,
486 		.width = 1,
487 	},
488 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
489 		.type = VCAP_FIELD_U32,
490 		.offset = 215,
491 		.width = 2,
492 	},
493 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
494 		.type = VCAP_FIELD_BIT,
495 		.offset = 217,
496 		.width = 1,
497 	},
498 	[VCAP_KF_L3_OPTIONS_IS] = {
499 		.type = VCAP_FIELD_BIT,
500 		.offset = 218,
501 		.width = 1,
502 	},
503 	[VCAP_KF_L3_DSCP] = {
504 		.type = VCAP_FIELD_U32,
505 		.offset = 219,
506 		.width = 6,
507 	},
508 	[VCAP_KF_L3_IP4_SIP] = {
509 		.type = VCAP_FIELD_U32,
510 		.offset = 225,
511 		.width = 32,
512 	},
513 	[VCAP_KF_TCP_UDP_IS] = {
514 		.type = VCAP_FIELD_BIT,
515 		.offset = 257,
516 		.width = 1,
517 	},
518 	[VCAP_KF_TCP_IS] = {
519 		.type = VCAP_FIELD_BIT,
520 		.offset = 258,
521 		.width = 1,
522 	},
523 	[VCAP_KF_L4_SPORT] = {
524 		.type = VCAP_FIELD_U32,
525 		.offset = 259,
526 		.width = 16,
527 	},
528 	[VCAP_KF_L4_RNG] = {
529 		.type = VCAP_FIELD_U32,
530 		.offset = 275,
531 		.width = 8,
532 	},
533 };
534 
535 static const struct vcap_field is0_normal_7tuple_keyfield[] = {
536 	[VCAP_KF_TYPE] = {
537 		.type = VCAP_FIELD_BIT,
538 		.offset = 0,
539 		.width = 1,
540 	},
541 	[VCAP_KF_LOOKUP_FIRST_IS] = {
542 		.type = VCAP_FIELD_BIT,
543 		.offset = 1,
544 		.width = 1,
545 	},
546 	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
547 		.type = VCAP_FIELD_U32,
548 		.offset = 2,
549 		.width = 2,
550 	},
551 	[VCAP_KF_LOOKUP_GEN_IDX] = {
552 		.type = VCAP_FIELD_U32,
553 		.offset = 4,
554 		.width = 12,
555 	},
556 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
557 		.type = VCAP_FIELD_U32,
558 		.offset = 16,
559 		.width = 2,
560 	},
561 	[VCAP_KF_IF_IGR_PORT_MASK] = {
562 		.type = VCAP_FIELD_U72,
563 		.offset = 18,
564 		.width = 65,
565 	},
566 	[VCAP_KF_L2_MC_IS] = {
567 		.type = VCAP_FIELD_BIT,
568 		.offset = 83,
569 		.width = 1,
570 	},
571 	[VCAP_KF_L2_BC_IS] = {
572 		.type = VCAP_FIELD_BIT,
573 		.offset = 84,
574 		.width = 1,
575 	},
576 	[VCAP_KF_8021Q_VLAN_TAGS] = {
577 		.type = VCAP_FIELD_U32,
578 		.offset = 85,
579 		.width = 3,
580 	},
581 	[VCAP_KF_8021Q_TPID0] = {
582 		.type = VCAP_FIELD_U32,
583 		.offset = 88,
584 		.width = 3,
585 	},
586 	[VCAP_KF_8021Q_PCP0] = {
587 		.type = VCAP_FIELD_U32,
588 		.offset = 91,
589 		.width = 3,
590 	},
591 	[VCAP_KF_8021Q_DEI0] = {
592 		.type = VCAP_FIELD_BIT,
593 		.offset = 94,
594 		.width = 1,
595 	},
596 	[VCAP_KF_8021Q_VID0] = {
597 		.type = VCAP_FIELD_U32,
598 		.offset = 95,
599 		.width = 12,
600 	},
601 	[VCAP_KF_8021Q_TPID1] = {
602 		.type = VCAP_FIELD_U32,
603 		.offset = 107,
604 		.width = 3,
605 	},
606 	[VCAP_KF_8021Q_PCP1] = {
607 		.type = VCAP_FIELD_U32,
608 		.offset = 110,
609 		.width = 3,
610 	},
611 	[VCAP_KF_8021Q_DEI1] = {
612 		.type = VCAP_FIELD_BIT,
613 		.offset = 113,
614 		.width = 1,
615 	},
616 	[VCAP_KF_8021Q_VID1] = {
617 		.type = VCAP_FIELD_U32,
618 		.offset = 114,
619 		.width = 12,
620 	},
621 	[VCAP_KF_8021Q_TPID2] = {
622 		.type = VCAP_FIELD_U32,
623 		.offset = 126,
624 		.width = 3,
625 	},
626 	[VCAP_KF_8021Q_PCP2] = {
627 		.type = VCAP_FIELD_U32,
628 		.offset = 129,
629 		.width = 3,
630 	},
631 	[VCAP_KF_8021Q_DEI2] = {
632 		.type = VCAP_FIELD_BIT,
633 		.offset = 132,
634 		.width = 1,
635 	},
636 	[VCAP_KF_8021Q_VID2] = {
637 		.type = VCAP_FIELD_U32,
638 		.offset = 133,
639 		.width = 12,
640 	},
641 	[VCAP_KF_L2_DMAC] = {
642 		.type = VCAP_FIELD_U48,
643 		.offset = 145,
644 		.width = 48,
645 	},
646 	[VCAP_KF_L2_SMAC] = {
647 		.type = VCAP_FIELD_U48,
648 		.offset = 193,
649 		.width = 48,
650 	},
651 	[VCAP_KF_IP_MC_IS] = {
652 		.type = VCAP_FIELD_BIT,
653 		.offset = 241,
654 		.width = 1,
655 	},
656 	[VCAP_KF_ETYPE_LEN_IS] = {
657 		.type = VCAP_FIELD_BIT,
658 		.offset = 242,
659 		.width = 1,
660 	},
661 	[VCAP_KF_ETYPE] = {
662 		.type = VCAP_FIELD_U32,
663 		.offset = 243,
664 		.width = 16,
665 	},
666 	[VCAP_KF_IP_SNAP_IS] = {
667 		.type = VCAP_FIELD_BIT,
668 		.offset = 259,
669 		.width = 1,
670 	},
671 	[VCAP_KF_IP4_IS] = {
672 		.type = VCAP_FIELD_BIT,
673 		.offset = 260,
674 		.width = 1,
675 	},
676 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
677 		.type = VCAP_FIELD_U32,
678 		.offset = 261,
679 		.width = 2,
680 	},
681 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
682 		.type = VCAP_FIELD_BIT,
683 		.offset = 263,
684 		.width = 1,
685 	},
686 	[VCAP_KF_L3_OPTIONS_IS] = {
687 		.type = VCAP_FIELD_BIT,
688 		.offset = 264,
689 		.width = 1,
690 	},
691 	[VCAP_KF_L3_DSCP] = {
692 		.type = VCAP_FIELD_U32,
693 		.offset = 265,
694 		.width = 6,
695 	},
696 	[VCAP_KF_L3_IP6_DIP] = {
697 		.type = VCAP_FIELD_U128,
698 		.offset = 271,
699 		.width = 128,
700 	},
701 	[VCAP_KF_L3_IP6_SIP] = {
702 		.type = VCAP_FIELD_U128,
703 		.offset = 399,
704 		.width = 128,
705 	},
706 	[VCAP_KF_TCP_UDP_IS] = {
707 		.type = VCAP_FIELD_BIT,
708 		.offset = 527,
709 		.width = 1,
710 	},
711 	[VCAP_KF_TCP_IS] = {
712 		.type = VCAP_FIELD_BIT,
713 		.offset = 528,
714 		.width = 1,
715 	},
716 	[VCAP_KF_L4_SPORT] = {
717 		.type = VCAP_FIELD_U32,
718 		.offset = 529,
719 		.width = 16,
720 	},
721 	[VCAP_KF_L4_RNG] = {
722 		.type = VCAP_FIELD_U32,
723 		.offset = 545,
724 		.width = 8,
725 	},
726 };
727 
728 static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {
729 	[VCAP_KF_TYPE] = {
730 		.type = VCAP_FIELD_U32,
731 		.offset = 0,
732 		.width = 2,
733 	},
734 	[VCAP_KF_LOOKUP_FIRST_IS] = {
735 		.type = VCAP_FIELD_BIT,
736 		.offset = 2,
737 		.width = 1,
738 	},
739 	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
740 		.type = VCAP_FIELD_U32,
741 		.offset = 3,
742 		.width = 2,
743 	},
744 	[VCAP_KF_LOOKUP_GEN_IDX] = {
745 		.type = VCAP_FIELD_U32,
746 		.offset = 5,
747 		.width = 12,
748 	},
749 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
750 		.type = VCAP_FIELD_U32,
751 		.offset = 17,
752 		.width = 2,
753 	},
754 	[VCAP_KF_IF_IGR_PORT_MASK] = {
755 		.type = VCAP_FIELD_U72,
756 		.offset = 19,
757 		.width = 65,
758 	},
759 	[VCAP_KF_L2_MC_IS] = {
760 		.type = VCAP_FIELD_BIT,
761 		.offset = 84,
762 		.width = 1,
763 	},
764 	[VCAP_KF_L2_BC_IS] = {
765 		.type = VCAP_FIELD_BIT,
766 		.offset = 85,
767 		.width = 1,
768 	},
769 	[VCAP_KF_8021Q_VLAN_TAGS] = {
770 		.type = VCAP_FIELD_U32,
771 		.offset = 86,
772 		.width = 3,
773 	},
774 	[VCAP_KF_8021Q_TPID0] = {
775 		.type = VCAP_FIELD_U32,
776 		.offset = 89,
777 		.width = 3,
778 	},
779 	[VCAP_KF_8021Q_PCP0] = {
780 		.type = VCAP_FIELD_U32,
781 		.offset = 92,
782 		.width = 3,
783 	},
784 	[VCAP_KF_8021Q_DEI0] = {
785 		.type = VCAP_FIELD_BIT,
786 		.offset = 95,
787 		.width = 1,
788 	},
789 	[VCAP_KF_8021Q_VID0] = {
790 		.type = VCAP_FIELD_U32,
791 		.offset = 96,
792 		.width = 12,
793 	},
794 	[VCAP_KF_8021Q_TPID1] = {
795 		.type = VCAP_FIELD_U32,
796 		.offset = 108,
797 		.width = 3,
798 	},
799 	[VCAP_KF_8021Q_PCP1] = {
800 		.type = VCAP_FIELD_U32,
801 		.offset = 111,
802 		.width = 3,
803 	},
804 	[VCAP_KF_8021Q_DEI1] = {
805 		.type = VCAP_FIELD_BIT,
806 		.offset = 114,
807 		.width = 1,
808 	},
809 	[VCAP_KF_8021Q_VID1] = {
810 		.type = VCAP_FIELD_U32,
811 		.offset = 115,
812 		.width = 12,
813 	},
814 	[VCAP_KF_8021Q_TPID2] = {
815 		.type = VCAP_FIELD_U32,
816 		.offset = 127,
817 		.width = 3,
818 	},
819 	[VCAP_KF_8021Q_PCP2] = {
820 		.type = VCAP_FIELD_U32,
821 		.offset = 130,
822 		.width = 3,
823 	},
824 	[VCAP_KF_8021Q_DEI2] = {
825 		.type = VCAP_FIELD_BIT,
826 		.offset = 133,
827 		.width = 1,
828 	},
829 	[VCAP_KF_8021Q_VID2] = {
830 		.type = VCAP_FIELD_U32,
831 		.offset = 134,
832 		.width = 12,
833 	},
834 	[VCAP_KF_IP_MC_IS] = {
835 		.type = VCAP_FIELD_BIT,
836 		.offset = 146,
837 		.width = 1,
838 	},
839 	[VCAP_KF_IP4_IS] = {
840 		.type = VCAP_FIELD_BIT,
841 		.offset = 147,
842 		.width = 1,
843 	},
844 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
845 		.type = VCAP_FIELD_U32,
846 		.offset = 148,
847 		.width = 2,
848 	},
849 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
850 		.type = VCAP_FIELD_BIT,
851 		.offset = 150,
852 		.width = 1,
853 	},
854 	[VCAP_KF_L3_OPTIONS_IS] = {
855 		.type = VCAP_FIELD_BIT,
856 		.offset = 151,
857 		.width = 1,
858 	},
859 	[VCAP_KF_L3_DSCP] = {
860 		.type = VCAP_FIELD_U32,
861 		.offset = 152,
862 		.width = 6,
863 	},
864 	[VCAP_KF_L3_IP4_DIP] = {
865 		.type = VCAP_FIELD_U32,
866 		.offset = 158,
867 		.width = 32,
868 	},
869 	[VCAP_KF_L3_IP4_SIP] = {
870 		.type = VCAP_FIELD_U32,
871 		.offset = 190,
872 		.width = 32,
873 	},
874 	[VCAP_KF_L3_IP_PROTO] = {
875 		.type = VCAP_FIELD_U32,
876 		.offset = 222,
877 		.width = 8,
878 	},
879 	[VCAP_KF_TCP_UDP_IS] = {
880 		.type = VCAP_FIELD_BIT,
881 		.offset = 230,
882 		.width = 1,
883 	},
884 	[VCAP_KF_TCP_IS] = {
885 		.type = VCAP_FIELD_BIT,
886 		.offset = 231,
887 		.width = 1,
888 	},
889 	[VCAP_KF_L4_RNG] = {
890 		.type = VCAP_FIELD_U32,
891 		.offset = 232,
892 		.width = 8,
893 	},
894 	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {
895 		.type = VCAP_FIELD_U32,
896 		.offset = 240,
897 		.width = 32,
898 	},
899 };
900 
901 static const struct vcap_field is0_pure_5tuple_ip4_keyfield[] = {
902 	[VCAP_KF_TYPE] = {
903 		.type = VCAP_FIELD_U32,
904 		.offset = 0,
905 		.width = 2,
906 	},
907 	[VCAP_KF_LOOKUP_FIRST_IS] = {
908 		.type = VCAP_FIELD_BIT,
909 		.offset = 2,
910 		.width = 1,
911 	},
912 	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
913 		.type = VCAP_FIELD_U32,
914 		.offset = 3,
915 		.width = 2,
916 	},
917 	[VCAP_KF_LOOKUP_GEN_IDX] = {
918 		.type = VCAP_FIELD_U32,
919 		.offset = 5,
920 		.width = 12,
921 	},
922 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
923 		.type = VCAP_FIELD_U32,
924 		.offset = 17,
925 		.width = 2,
926 	},
927 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
928 		.type = VCAP_FIELD_BIT,
929 		.offset = 19,
930 		.width = 1,
931 	},
932 	[VCAP_KF_L3_OPTIONS_IS] = {
933 		.type = VCAP_FIELD_BIT,
934 		.offset = 20,
935 		.width = 1,
936 	},
937 	[VCAP_KF_L3_DSCP] = {
938 		.type = VCAP_FIELD_U32,
939 		.offset = 21,
940 		.width = 6,
941 	},
942 	[VCAP_KF_L3_IP4_DIP] = {
943 		.type = VCAP_FIELD_U32,
944 		.offset = 27,
945 		.width = 32,
946 	},
947 	[VCAP_KF_L3_IP4_SIP] = {
948 		.type = VCAP_FIELD_U32,
949 		.offset = 59,
950 		.width = 32,
951 	},
952 	[VCAP_KF_L3_IP_PROTO] = {
953 		.type = VCAP_FIELD_U32,
954 		.offset = 91,
955 		.width = 8,
956 	},
957 	[VCAP_KF_L4_RNG] = {
958 		.type = VCAP_FIELD_U32,
959 		.offset = 99,
960 		.width = 8,
961 	},
962 	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {
963 		.type = VCAP_FIELD_U32,
964 		.offset = 107,
965 		.width = 32,
966 	},
967 };
968 
969 static const struct vcap_field is0_etag_keyfield[] = {
970 	[VCAP_KF_TYPE] = {
971 		.type = VCAP_FIELD_U32,
972 		.offset = 0,
973 		.width = 2,
974 	},
975 	[VCAP_KF_LOOKUP_FIRST_IS] = {
976 		.type = VCAP_FIELD_BIT,
977 		.offset = 2,
978 		.width = 1,
979 	},
980 	[VCAP_KF_IF_IGR_PORT] = {
981 		.type = VCAP_FIELD_U32,
982 		.offset = 3,
983 		.width = 7,
984 	},
985 	[VCAP_KF_8021BR_E_TAGGED] = {
986 		.type = VCAP_FIELD_BIT,
987 		.offset = 10,
988 		.width = 1,
989 	},
990 	[VCAP_KF_8021BR_GRP] = {
991 		.type = VCAP_FIELD_U32,
992 		.offset = 11,
993 		.width = 2,
994 	},
995 	[VCAP_KF_8021BR_ECID_EXT] = {
996 		.type = VCAP_FIELD_U32,
997 		.offset = 13,
998 		.width = 8,
999 	},
1000 	[VCAP_KF_8021BR_ECID_BASE] = {
1001 		.type = VCAP_FIELD_U32,
1002 		.offset = 21,
1003 		.width = 12,
1004 	},
1005 	[VCAP_KF_8021BR_IGR_ECID_EXT] = {
1006 		.type = VCAP_FIELD_U32,
1007 		.offset = 33,
1008 		.width = 8,
1009 	},
1010 	[VCAP_KF_8021BR_IGR_ECID_BASE] = {
1011 		.type = VCAP_FIELD_U32,
1012 		.offset = 41,
1013 		.width = 12,
1014 	},
1015 };
1016 
1017 static const struct vcap_field is2_mac_etype_keyfield[] = {
1018 	[VCAP_KF_TYPE] = {
1019 		.type = VCAP_FIELD_U32,
1020 		.offset = 0,
1021 		.width = 4,
1022 	},
1023 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1024 		.type = VCAP_FIELD_BIT,
1025 		.offset = 4,
1026 		.width = 1,
1027 	},
1028 	[VCAP_KF_LOOKUP_PAG] = {
1029 		.type = VCAP_FIELD_U32,
1030 		.offset = 5,
1031 		.width = 8,
1032 	},
1033 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1034 		.type = VCAP_FIELD_BIT,
1035 		.offset = 13,
1036 		.width = 1,
1037 	},
1038 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1039 		.type = VCAP_FIELD_U32,
1040 		.offset = 14,
1041 		.width = 4,
1042 	},
1043 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1044 		.type = VCAP_FIELD_U32,
1045 		.offset = 18,
1046 		.width = 2,
1047 	},
1048 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1049 		.type = VCAP_FIELD_U32,
1050 		.offset = 20,
1051 		.width = 32,
1052 	},
1053 	[VCAP_KF_L2_MC_IS] = {
1054 		.type = VCAP_FIELD_BIT,
1055 		.offset = 52,
1056 		.width = 1,
1057 	},
1058 	[VCAP_KF_L2_BC_IS] = {
1059 		.type = VCAP_FIELD_BIT,
1060 		.offset = 53,
1061 		.width = 1,
1062 	},
1063 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1064 		.type = VCAP_FIELD_BIT,
1065 		.offset = 54,
1066 		.width = 1,
1067 	},
1068 	[VCAP_KF_ISDX_GT0_IS] = {
1069 		.type = VCAP_FIELD_BIT,
1070 		.offset = 55,
1071 		.width = 1,
1072 	},
1073 	[VCAP_KF_ISDX_CLS] = {
1074 		.type = VCAP_FIELD_U32,
1075 		.offset = 56,
1076 		.width = 12,
1077 	},
1078 	[VCAP_KF_8021Q_VID_CLS] = {
1079 		.type = VCAP_FIELD_U32,
1080 		.offset = 68,
1081 		.width = 13,
1082 	},
1083 	[VCAP_KF_8021Q_DEI_CLS] = {
1084 		.type = VCAP_FIELD_BIT,
1085 		.offset = 81,
1086 		.width = 1,
1087 	},
1088 	[VCAP_KF_8021Q_PCP_CLS] = {
1089 		.type = VCAP_FIELD_U32,
1090 		.offset = 82,
1091 		.width = 3,
1092 	},
1093 	[VCAP_KF_L2_FWD_IS] = {
1094 		.type = VCAP_FIELD_BIT,
1095 		.offset = 85,
1096 		.width = 1,
1097 	},
1098 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
1099 		.type = VCAP_FIELD_BIT,
1100 		.offset = 86,
1101 		.width = 1,
1102 	},
1103 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
1104 		.type = VCAP_FIELD_BIT,
1105 		.offset = 87,
1106 		.width = 1,
1107 	},
1108 	[VCAP_KF_L3_RT_IS] = {
1109 		.type = VCAP_FIELD_BIT,
1110 		.offset = 88,
1111 		.width = 1,
1112 	},
1113 	[VCAP_KF_L3_DST_IS] = {
1114 		.type = VCAP_FIELD_BIT,
1115 		.offset = 89,
1116 		.width = 1,
1117 	},
1118 	[VCAP_KF_L2_DMAC] = {
1119 		.type = VCAP_FIELD_U48,
1120 		.offset = 90,
1121 		.width = 48,
1122 	},
1123 	[VCAP_KF_L2_SMAC] = {
1124 		.type = VCAP_FIELD_U48,
1125 		.offset = 138,
1126 		.width = 48,
1127 	},
1128 	[VCAP_KF_ETYPE_LEN_IS] = {
1129 		.type = VCAP_FIELD_BIT,
1130 		.offset = 186,
1131 		.width = 1,
1132 	},
1133 	[VCAP_KF_ETYPE] = {
1134 		.type = VCAP_FIELD_U32,
1135 		.offset = 187,
1136 		.width = 16,
1137 	},
1138 	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
1139 		.type = VCAP_FIELD_U64,
1140 		.offset = 203,
1141 		.width = 64,
1142 	},
1143 	[VCAP_KF_L4_RNG] = {
1144 		.type = VCAP_FIELD_U32,
1145 		.offset = 267,
1146 		.width = 16,
1147 	},
1148 	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
1149 		.type = VCAP_FIELD_BIT,
1150 		.offset = 283,
1151 		.width = 1,
1152 	},
1153 	[VCAP_KF_OAM_Y1731_IS] = {
1154 		.type = VCAP_FIELD_BIT,
1155 		.offset = 284,
1156 		.width = 1,
1157 	},
1158 };
1159 
1160 static const struct vcap_field is2_arp_keyfield[] = {
1161 	[VCAP_KF_TYPE] = {
1162 		.type = VCAP_FIELD_U32,
1163 		.offset = 0,
1164 		.width = 4,
1165 	},
1166 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1167 		.type = VCAP_FIELD_BIT,
1168 		.offset = 4,
1169 		.width = 1,
1170 	},
1171 	[VCAP_KF_LOOKUP_PAG] = {
1172 		.type = VCAP_FIELD_U32,
1173 		.offset = 5,
1174 		.width = 8,
1175 	},
1176 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1177 		.type = VCAP_FIELD_BIT,
1178 		.offset = 13,
1179 		.width = 1,
1180 	},
1181 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1182 		.type = VCAP_FIELD_U32,
1183 		.offset = 14,
1184 		.width = 4,
1185 	},
1186 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1187 		.type = VCAP_FIELD_U32,
1188 		.offset = 18,
1189 		.width = 2,
1190 	},
1191 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1192 		.type = VCAP_FIELD_U32,
1193 		.offset = 20,
1194 		.width = 32,
1195 	},
1196 	[VCAP_KF_L2_MC_IS] = {
1197 		.type = VCAP_FIELD_BIT,
1198 		.offset = 52,
1199 		.width = 1,
1200 	},
1201 	[VCAP_KF_L2_BC_IS] = {
1202 		.type = VCAP_FIELD_BIT,
1203 		.offset = 53,
1204 		.width = 1,
1205 	},
1206 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1207 		.type = VCAP_FIELD_BIT,
1208 		.offset = 54,
1209 		.width = 1,
1210 	},
1211 	[VCAP_KF_ISDX_GT0_IS] = {
1212 		.type = VCAP_FIELD_BIT,
1213 		.offset = 55,
1214 		.width = 1,
1215 	},
1216 	[VCAP_KF_ISDX_CLS] = {
1217 		.type = VCAP_FIELD_U32,
1218 		.offset = 56,
1219 		.width = 12,
1220 	},
1221 	[VCAP_KF_8021Q_VID_CLS] = {
1222 		.type = VCAP_FIELD_U32,
1223 		.offset = 68,
1224 		.width = 13,
1225 	},
1226 	[VCAP_KF_8021Q_DEI_CLS] = {
1227 		.type = VCAP_FIELD_BIT,
1228 		.offset = 81,
1229 		.width = 1,
1230 	},
1231 	[VCAP_KF_8021Q_PCP_CLS] = {
1232 		.type = VCAP_FIELD_U32,
1233 		.offset = 82,
1234 		.width = 3,
1235 	},
1236 	[VCAP_KF_L2_FWD_IS] = {
1237 		.type = VCAP_FIELD_BIT,
1238 		.offset = 85,
1239 		.width = 1,
1240 	},
1241 	[VCAP_KF_L2_SMAC] = {
1242 		.type = VCAP_FIELD_U48,
1243 		.offset = 86,
1244 		.width = 48,
1245 	},
1246 	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
1247 		.type = VCAP_FIELD_BIT,
1248 		.offset = 134,
1249 		.width = 1,
1250 	},
1251 	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
1252 		.type = VCAP_FIELD_BIT,
1253 		.offset = 135,
1254 		.width = 1,
1255 	},
1256 	[VCAP_KF_ARP_LEN_OK_IS] = {
1257 		.type = VCAP_FIELD_BIT,
1258 		.offset = 136,
1259 		.width = 1,
1260 	},
1261 	[VCAP_KF_ARP_TGT_MATCH_IS] = {
1262 		.type = VCAP_FIELD_BIT,
1263 		.offset = 137,
1264 		.width = 1,
1265 	},
1266 	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
1267 		.type = VCAP_FIELD_BIT,
1268 		.offset = 138,
1269 		.width = 1,
1270 	},
1271 	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
1272 		.type = VCAP_FIELD_BIT,
1273 		.offset = 139,
1274 		.width = 1,
1275 	},
1276 	[VCAP_KF_ARP_OPCODE] = {
1277 		.type = VCAP_FIELD_U32,
1278 		.offset = 140,
1279 		.width = 2,
1280 	},
1281 	[VCAP_KF_L3_IP4_DIP] = {
1282 		.type = VCAP_FIELD_U32,
1283 		.offset = 142,
1284 		.width = 32,
1285 	},
1286 	[VCAP_KF_L3_IP4_SIP] = {
1287 		.type = VCAP_FIELD_U32,
1288 		.offset = 174,
1289 		.width = 32,
1290 	},
1291 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1292 		.type = VCAP_FIELD_BIT,
1293 		.offset = 206,
1294 		.width = 1,
1295 	},
1296 	[VCAP_KF_L4_RNG] = {
1297 		.type = VCAP_FIELD_U32,
1298 		.offset = 207,
1299 		.width = 16,
1300 	},
1301 };
1302 
1303 static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
1304 	[VCAP_KF_TYPE] = {
1305 		.type = VCAP_FIELD_U32,
1306 		.offset = 0,
1307 		.width = 4,
1308 	},
1309 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1310 		.type = VCAP_FIELD_BIT,
1311 		.offset = 4,
1312 		.width = 1,
1313 	},
1314 	[VCAP_KF_LOOKUP_PAG] = {
1315 		.type = VCAP_FIELD_U32,
1316 		.offset = 5,
1317 		.width = 8,
1318 	},
1319 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1320 		.type = VCAP_FIELD_BIT,
1321 		.offset = 13,
1322 		.width = 1,
1323 	},
1324 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1325 		.type = VCAP_FIELD_U32,
1326 		.offset = 14,
1327 		.width = 4,
1328 	},
1329 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1330 		.type = VCAP_FIELD_U32,
1331 		.offset = 18,
1332 		.width = 2,
1333 	},
1334 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1335 		.type = VCAP_FIELD_U32,
1336 		.offset = 20,
1337 		.width = 32,
1338 	},
1339 	[VCAP_KF_L2_MC_IS] = {
1340 		.type = VCAP_FIELD_BIT,
1341 		.offset = 52,
1342 		.width = 1,
1343 	},
1344 	[VCAP_KF_L2_BC_IS] = {
1345 		.type = VCAP_FIELD_BIT,
1346 		.offset = 53,
1347 		.width = 1,
1348 	},
1349 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1350 		.type = VCAP_FIELD_BIT,
1351 		.offset = 54,
1352 		.width = 1,
1353 	},
1354 	[VCAP_KF_ISDX_GT0_IS] = {
1355 		.type = VCAP_FIELD_BIT,
1356 		.offset = 55,
1357 		.width = 1,
1358 	},
1359 	[VCAP_KF_ISDX_CLS] = {
1360 		.type = VCAP_FIELD_U32,
1361 		.offset = 56,
1362 		.width = 12,
1363 	},
1364 	[VCAP_KF_8021Q_VID_CLS] = {
1365 		.type = VCAP_FIELD_U32,
1366 		.offset = 68,
1367 		.width = 13,
1368 	},
1369 	[VCAP_KF_8021Q_DEI_CLS] = {
1370 		.type = VCAP_FIELD_BIT,
1371 		.offset = 81,
1372 		.width = 1,
1373 	},
1374 	[VCAP_KF_8021Q_PCP_CLS] = {
1375 		.type = VCAP_FIELD_U32,
1376 		.offset = 82,
1377 		.width = 3,
1378 	},
1379 	[VCAP_KF_L2_FWD_IS] = {
1380 		.type = VCAP_FIELD_BIT,
1381 		.offset = 85,
1382 		.width = 1,
1383 	},
1384 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
1385 		.type = VCAP_FIELD_BIT,
1386 		.offset = 86,
1387 		.width = 1,
1388 	},
1389 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
1390 		.type = VCAP_FIELD_BIT,
1391 		.offset = 87,
1392 		.width = 1,
1393 	},
1394 	[VCAP_KF_L3_RT_IS] = {
1395 		.type = VCAP_FIELD_BIT,
1396 		.offset = 88,
1397 		.width = 1,
1398 	},
1399 	[VCAP_KF_L3_DST_IS] = {
1400 		.type = VCAP_FIELD_BIT,
1401 		.offset = 89,
1402 		.width = 1,
1403 	},
1404 	[VCAP_KF_IP4_IS] = {
1405 		.type = VCAP_FIELD_BIT,
1406 		.offset = 90,
1407 		.width = 1,
1408 	},
1409 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
1410 		.type = VCAP_FIELD_U32,
1411 		.offset = 91,
1412 		.width = 2,
1413 	},
1414 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
1415 		.type = VCAP_FIELD_BIT,
1416 		.offset = 93,
1417 		.width = 1,
1418 	},
1419 	[VCAP_KF_L3_OPTIONS_IS] = {
1420 		.type = VCAP_FIELD_BIT,
1421 		.offset = 94,
1422 		.width = 1,
1423 	},
1424 	[VCAP_KF_L3_TTL_GT0] = {
1425 		.type = VCAP_FIELD_BIT,
1426 		.offset = 95,
1427 		.width = 1,
1428 	},
1429 	[VCAP_KF_L3_TOS] = {
1430 		.type = VCAP_FIELD_U32,
1431 		.offset = 96,
1432 		.width = 8,
1433 	},
1434 	[VCAP_KF_L3_IP4_DIP] = {
1435 		.type = VCAP_FIELD_U32,
1436 		.offset = 104,
1437 		.width = 32,
1438 	},
1439 	[VCAP_KF_L3_IP4_SIP] = {
1440 		.type = VCAP_FIELD_U32,
1441 		.offset = 136,
1442 		.width = 32,
1443 	},
1444 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1445 		.type = VCAP_FIELD_BIT,
1446 		.offset = 168,
1447 		.width = 1,
1448 	},
1449 	[VCAP_KF_TCP_IS] = {
1450 		.type = VCAP_FIELD_BIT,
1451 		.offset = 169,
1452 		.width = 1,
1453 	},
1454 	[VCAP_KF_L4_DPORT] = {
1455 		.type = VCAP_FIELD_U32,
1456 		.offset = 170,
1457 		.width = 16,
1458 	},
1459 	[VCAP_KF_L4_SPORT] = {
1460 		.type = VCAP_FIELD_U32,
1461 		.offset = 186,
1462 		.width = 16,
1463 	},
1464 	[VCAP_KF_L4_RNG] = {
1465 		.type = VCAP_FIELD_U32,
1466 		.offset = 202,
1467 		.width = 16,
1468 	},
1469 	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
1470 		.type = VCAP_FIELD_BIT,
1471 		.offset = 218,
1472 		.width = 1,
1473 	},
1474 	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
1475 		.type = VCAP_FIELD_BIT,
1476 		.offset = 219,
1477 		.width = 1,
1478 	},
1479 	[VCAP_KF_L4_FIN] = {
1480 		.type = VCAP_FIELD_BIT,
1481 		.offset = 220,
1482 		.width = 1,
1483 	},
1484 	[VCAP_KF_L4_SYN] = {
1485 		.type = VCAP_FIELD_BIT,
1486 		.offset = 221,
1487 		.width = 1,
1488 	},
1489 	[VCAP_KF_L4_RST] = {
1490 		.type = VCAP_FIELD_BIT,
1491 		.offset = 222,
1492 		.width = 1,
1493 	},
1494 	[VCAP_KF_L4_PSH] = {
1495 		.type = VCAP_FIELD_BIT,
1496 		.offset = 223,
1497 		.width = 1,
1498 	},
1499 	[VCAP_KF_L4_ACK] = {
1500 		.type = VCAP_FIELD_BIT,
1501 		.offset = 224,
1502 		.width = 1,
1503 	},
1504 	[VCAP_KF_L4_URG] = {
1505 		.type = VCAP_FIELD_BIT,
1506 		.offset = 225,
1507 		.width = 1,
1508 	},
1509 	[VCAP_KF_L4_PAYLOAD] = {
1510 		.type = VCAP_FIELD_U64,
1511 		.offset = 226,
1512 		.width = 64,
1513 	},
1514 };
1515 
1516 static const struct vcap_field is2_ip4_other_keyfield[] = {
1517 	[VCAP_KF_TYPE] = {
1518 		.type = VCAP_FIELD_U32,
1519 		.offset = 0,
1520 		.width = 4,
1521 	},
1522 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1523 		.type = VCAP_FIELD_BIT,
1524 		.offset = 4,
1525 		.width = 1,
1526 	},
1527 	[VCAP_KF_LOOKUP_PAG] = {
1528 		.type = VCAP_FIELD_U32,
1529 		.offset = 5,
1530 		.width = 8,
1531 	},
1532 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1533 		.type = VCAP_FIELD_BIT,
1534 		.offset = 13,
1535 		.width = 1,
1536 	},
1537 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1538 		.type = VCAP_FIELD_U32,
1539 		.offset = 14,
1540 		.width = 4,
1541 	},
1542 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1543 		.type = VCAP_FIELD_U32,
1544 		.offset = 18,
1545 		.width = 2,
1546 	},
1547 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1548 		.type = VCAP_FIELD_U32,
1549 		.offset = 20,
1550 		.width = 32,
1551 	},
1552 	[VCAP_KF_L2_MC_IS] = {
1553 		.type = VCAP_FIELD_BIT,
1554 		.offset = 52,
1555 		.width = 1,
1556 	},
1557 	[VCAP_KF_L2_BC_IS] = {
1558 		.type = VCAP_FIELD_BIT,
1559 		.offset = 53,
1560 		.width = 1,
1561 	},
1562 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1563 		.type = VCAP_FIELD_BIT,
1564 		.offset = 54,
1565 		.width = 1,
1566 	},
1567 	[VCAP_KF_ISDX_GT0_IS] = {
1568 		.type = VCAP_FIELD_BIT,
1569 		.offset = 55,
1570 		.width = 1,
1571 	},
1572 	[VCAP_KF_ISDX_CLS] = {
1573 		.type = VCAP_FIELD_U32,
1574 		.offset = 56,
1575 		.width = 12,
1576 	},
1577 	[VCAP_KF_8021Q_VID_CLS] = {
1578 		.type = VCAP_FIELD_U32,
1579 		.offset = 68,
1580 		.width = 13,
1581 	},
1582 	[VCAP_KF_8021Q_DEI_CLS] = {
1583 		.type = VCAP_FIELD_BIT,
1584 		.offset = 81,
1585 		.width = 1,
1586 	},
1587 	[VCAP_KF_8021Q_PCP_CLS] = {
1588 		.type = VCAP_FIELD_U32,
1589 		.offset = 82,
1590 		.width = 3,
1591 	},
1592 	[VCAP_KF_L2_FWD_IS] = {
1593 		.type = VCAP_FIELD_BIT,
1594 		.offset = 85,
1595 		.width = 1,
1596 	},
1597 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
1598 		.type = VCAP_FIELD_BIT,
1599 		.offset = 86,
1600 		.width = 1,
1601 	},
1602 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
1603 		.type = VCAP_FIELD_BIT,
1604 		.offset = 87,
1605 		.width = 1,
1606 	},
1607 	[VCAP_KF_L3_RT_IS] = {
1608 		.type = VCAP_FIELD_BIT,
1609 		.offset = 88,
1610 		.width = 1,
1611 	},
1612 	[VCAP_KF_L3_DST_IS] = {
1613 		.type = VCAP_FIELD_BIT,
1614 		.offset = 89,
1615 		.width = 1,
1616 	},
1617 	[VCAP_KF_IP4_IS] = {
1618 		.type = VCAP_FIELD_BIT,
1619 		.offset = 90,
1620 		.width = 1,
1621 	},
1622 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
1623 		.type = VCAP_FIELD_U32,
1624 		.offset = 91,
1625 		.width = 2,
1626 	},
1627 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
1628 		.type = VCAP_FIELD_BIT,
1629 		.offset = 93,
1630 		.width = 1,
1631 	},
1632 	[VCAP_KF_L3_OPTIONS_IS] = {
1633 		.type = VCAP_FIELD_BIT,
1634 		.offset = 94,
1635 		.width = 1,
1636 	},
1637 	[VCAP_KF_L3_TTL_GT0] = {
1638 		.type = VCAP_FIELD_BIT,
1639 		.offset = 95,
1640 		.width = 1,
1641 	},
1642 	[VCAP_KF_L3_TOS] = {
1643 		.type = VCAP_FIELD_U32,
1644 		.offset = 96,
1645 		.width = 8,
1646 	},
1647 	[VCAP_KF_L3_IP4_DIP] = {
1648 		.type = VCAP_FIELD_U32,
1649 		.offset = 104,
1650 		.width = 32,
1651 	},
1652 	[VCAP_KF_L3_IP4_SIP] = {
1653 		.type = VCAP_FIELD_U32,
1654 		.offset = 136,
1655 		.width = 32,
1656 	},
1657 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1658 		.type = VCAP_FIELD_BIT,
1659 		.offset = 168,
1660 		.width = 1,
1661 	},
1662 	[VCAP_KF_L3_IP_PROTO] = {
1663 		.type = VCAP_FIELD_U32,
1664 		.offset = 169,
1665 		.width = 8,
1666 	},
1667 	[VCAP_KF_L4_RNG] = {
1668 		.type = VCAP_FIELD_U32,
1669 		.offset = 177,
1670 		.width = 16,
1671 	},
1672 	[VCAP_KF_L3_PAYLOAD] = {
1673 		.type = VCAP_FIELD_U112,
1674 		.offset = 193,
1675 		.width = 96,
1676 	},
1677 };
1678 
1679 static const struct vcap_field is2_ip6_std_keyfield[] = {
1680 	[VCAP_KF_TYPE] = {
1681 		.type = VCAP_FIELD_U32,
1682 		.offset = 0,
1683 		.width = 4,
1684 	},
1685 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1686 		.type = VCAP_FIELD_BIT,
1687 		.offset = 4,
1688 		.width = 1,
1689 	},
1690 	[VCAP_KF_LOOKUP_PAG] = {
1691 		.type = VCAP_FIELD_U32,
1692 		.offset = 5,
1693 		.width = 8,
1694 	},
1695 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1696 		.type = VCAP_FIELD_BIT,
1697 		.offset = 13,
1698 		.width = 1,
1699 	},
1700 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1701 		.type = VCAP_FIELD_U32,
1702 		.offset = 14,
1703 		.width = 4,
1704 	},
1705 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1706 		.type = VCAP_FIELD_U32,
1707 		.offset = 18,
1708 		.width = 2,
1709 	},
1710 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1711 		.type = VCAP_FIELD_U32,
1712 		.offset = 20,
1713 		.width = 32,
1714 	},
1715 	[VCAP_KF_L2_MC_IS] = {
1716 		.type = VCAP_FIELD_BIT,
1717 		.offset = 52,
1718 		.width = 1,
1719 	},
1720 	[VCAP_KF_L2_BC_IS] = {
1721 		.type = VCAP_FIELD_BIT,
1722 		.offset = 53,
1723 		.width = 1,
1724 	},
1725 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1726 		.type = VCAP_FIELD_BIT,
1727 		.offset = 54,
1728 		.width = 1,
1729 	},
1730 	[VCAP_KF_ISDX_GT0_IS] = {
1731 		.type = VCAP_FIELD_BIT,
1732 		.offset = 55,
1733 		.width = 1,
1734 	},
1735 	[VCAP_KF_ISDX_CLS] = {
1736 		.type = VCAP_FIELD_U32,
1737 		.offset = 56,
1738 		.width = 12,
1739 	},
1740 	[VCAP_KF_8021Q_VID_CLS] = {
1741 		.type = VCAP_FIELD_U32,
1742 		.offset = 68,
1743 		.width = 13,
1744 	},
1745 	[VCAP_KF_8021Q_DEI_CLS] = {
1746 		.type = VCAP_FIELD_BIT,
1747 		.offset = 81,
1748 		.width = 1,
1749 	},
1750 	[VCAP_KF_8021Q_PCP_CLS] = {
1751 		.type = VCAP_FIELD_U32,
1752 		.offset = 82,
1753 		.width = 3,
1754 	},
1755 	[VCAP_KF_L2_FWD_IS] = {
1756 		.type = VCAP_FIELD_BIT,
1757 		.offset = 85,
1758 		.width = 1,
1759 	},
1760 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
1761 		.type = VCAP_FIELD_BIT,
1762 		.offset = 86,
1763 		.width = 1,
1764 	},
1765 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
1766 		.type = VCAP_FIELD_BIT,
1767 		.offset = 87,
1768 		.width = 1,
1769 	},
1770 	[VCAP_KF_L3_RT_IS] = {
1771 		.type = VCAP_FIELD_BIT,
1772 		.offset = 88,
1773 		.width = 1,
1774 	},
1775 	[VCAP_KF_L3_DST_IS] = {
1776 		.type = VCAP_FIELD_BIT,
1777 		.offset = 89,
1778 		.width = 1,
1779 	},
1780 	[VCAP_KF_L3_TTL_GT0] = {
1781 		.type = VCAP_FIELD_BIT,
1782 		.offset = 90,
1783 		.width = 1,
1784 	},
1785 	[VCAP_KF_L3_IP6_SIP] = {
1786 		.type = VCAP_FIELD_U128,
1787 		.offset = 91,
1788 		.width = 128,
1789 	},
1790 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1791 		.type = VCAP_FIELD_BIT,
1792 		.offset = 219,
1793 		.width = 1,
1794 	},
1795 	[VCAP_KF_L3_IP_PROTO] = {
1796 		.type = VCAP_FIELD_U32,
1797 		.offset = 220,
1798 		.width = 8,
1799 	},
1800 	[VCAP_KF_L4_RNG] = {
1801 		.type = VCAP_FIELD_U32,
1802 		.offset = 228,
1803 		.width = 16,
1804 	},
1805 	[VCAP_KF_L3_PAYLOAD] = {
1806 		.type = VCAP_FIELD_U48,
1807 		.offset = 244,
1808 		.width = 40,
1809 	},
1810 };
1811 
1812 static const struct vcap_field is2_ip_7tuple_keyfield[] = {
1813 	[VCAP_KF_TYPE] = {
1814 		.type = VCAP_FIELD_U32,
1815 		.offset = 0,
1816 		.width = 2,
1817 	},
1818 	[VCAP_KF_LOOKUP_FIRST_IS] = {
1819 		.type = VCAP_FIELD_BIT,
1820 		.offset = 2,
1821 		.width = 1,
1822 	},
1823 	[VCAP_KF_LOOKUP_PAG] = {
1824 		.type = VCAP_FIELD_U32,
1825 		.offset = 3,
1826 		.width = 8,
1827 	},
1828 	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
1829 		.type = VCAP_FIELD_BIT,
1830 		.offset = 11,
1831 		.width = 1,
1832 	},
1833 	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
1834 		.type = VCAP_FIELD_U32,
1835 		.offset = 12,
1836 		.width = 4,
1837 	},
1838 	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
1839 		.type = VCAP_FIELD_U32,
1840 		.offset = 16,
1841 		.width = 2,
1842 	},
1843 	[VCAP_KF_IF_IGR_PORT_MASK] = {
1844 		.type = VCAP_FIELD_U72,
1845 		.offset = 18,
1846 		.width = 65,
1847 	},
1848 	[VCAP_KF_L2_MC_IS] = {
1849 		.type = VCAP_FIELD_BIT,
1850 		.offset = 83,
1851 		.width = 1,
1852 	},
1853 	[VCAP_KF_L2_BC_IS] = {
1854 		.type = VCAP_FIELD_BIT,
1855 		.offset = 84,
1856 		.width = 1,
1857 	},
1858 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1859 		.type = VCAP_FIELD_BIT,
1860 		.offset = 85,
1861 		.width = 1,
1862 	},
1863 	[VCAP_KF_ISDX_GT0_IS] = {
1864 		.type = VCAP_FIELD_BIT,
1865 		.offset = 86,
1866 		.width = 1,
1867 	},
1868 	[VCAP_KF_ISDX_CLS] = {
1869 		.type = VCAP_FIELD_U32,
1870 		.offset = 87,
1871 		.width = 12,
1872 	},
1873 	[VCAP_KF_8021Q_VID_CLS] = {
1874 		.type = VCAP_FIELD_U32,
1875 		.offset = 99,
1876 		.width = 13,
1877 	},
1878 	[VCAP_KF_8021Q_DEI_CLS] = {
1879 		.type = VCAP_FIELD_BIT,
1880 		.offset = 112,
1881 		.width = 1,
1882 	},
1883 	[VCAP_KF_8021Q_PCP_CLS] = {
1884 		.type = VCAP_FIELD_U32,
1885 		.offset = 113,
1886 		.width = 3,
1887 	},
1888 	[VCAP_KF_L2_FWD_IS] = {
1889 		.type = VCAP_FIELD_BIT,
1890 		.offset = 116,
1891 		.width = 1,
1892 	},
1893 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
1894 		.type = VCAP_FIELD_BIT,
1895 		.offset = 117,
1896 		.width = 1,
1897 	},
1898 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
1899 		.type = VCAP_FIELD_BIT,
1900 		.offset = 118,
1901 		.width = 1,
1902 	},
1903 	[VCAP_KF_L3_RT_IS] = {
1904 		.type = VCAP_FIELD_BIT,
1905 		.offset = 119,
1906 		.width = 1,
1907 	},
1908 	[VCAP_KF_L3_DST_IS] = {
1909 		.type = VCAP_FIELD_BIT,
1910 		.offset = 120,
1911 		.width = 1,
1912 	},
1913 	[VCAP_KF_L2_DMAC] = {
1914 		.type = VCAP_FIELD_U48,
1915 		.offset = 121,
1916 		.width = 48,
1917 	},
1918 	[VCAP_KF_L2_SMAC] = {
1919 		.type = VCAP_FIELD_U48,
1920 		.offset = 169,
1921 		.width = 48,
1922 	},
1923 	[VCAP_KF_IP4_IS] = {
1924 		.type = VCAP_FIELD_BIT,
1925 		.offset = 217,
1926 		.width = 1,
1927 	},
1928 	[VCAP_KF_L3_TTL_GT0] = {
1929 		.type = VCAP_FIELD_BIT,
1930 		.offset = 218,
1931 		.width = 1,
1932 	},
1933 	[VCAP_KF_L3_TOS] = {
1934 		.type = VCAP_FIELD_U32,
1935 		.offset = 219,
1936 		.width = 8,
1937 	},
1938 	[VCAP_KF_L3_IP6_DIP] = {
1939 		.type = VCAP_FIELD_U128,
1940 		.offset = 227,
1941 		.width = 128,
1942 	},
1943 	[VCAP_KF_L3_IP6_SIP] = {
1944 		.type = VCAP_FIELD_U128,
1945 		.offset = 355,
1946 		.width = 128,
1947 	},
1948 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1949 		.type = VCAP_FIELD_BIT,
1950 		.offset = 483,
1951 		.width = 1,
1952 	},
1953 	[VCAP_KF_TCP_UDP_IS] = {
1954 		.type = VCAP_FIELD_BIT,
1955 		.offset = 484,
1956 		.width = 1,
1957 	},
1958 	[VCAP_KF_TCP_IS] = {
1959 		.type = VCAP_FIELD_BIT,
1960 		.offset = 485,
1961 		.width = 1,
1962 	},
1963 	[VCAP_KF_L4_DPORT] = {
1964 		.type = VCAP_FIELD_U32,
1965 		.offset = 486,
1966 		.width = 16,
1967 	},
1968 	[VCAP_KF_L4_SPORT] = {
1969 		.type = VCAP_FIELD_U32,
1970 		.offset = 502,
1971 		.width = 16,
1972 	},
1973 	[VCAP_KF_L4_RNG] = {
1974 		.type = VCAP_FIELD_U32,
1975 		.offset = 518,
1976 		.width = 16,
1977 	},
1978 	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
1979 		.type = VCAP_FIELD_BIT,
1980 		.offset = 534,
1981 		.width = 1,
1982 	},
1983 	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
1984 		.type = VCAP_FIELD_BIT,
1985 		.offset = 535,
1986 		.width = 1,
1987 	},
1988 	[VCAP_KF_L4_FIN] = {
1989 		.type = VCAP_FIELD_BIT,
1990 		.offset = 536,
1991 		.width = 1,
1992 	},
1993 	[VCAP_KF_L4_SYN] = {
1994 		.type = VCAP_FIELD_BIT,
1995 		.offset = 537,
1996 		.width = 1,
1997 	},
1998 	[VCAP_KF_L4_RST] = {
1999 		.type = VCAP_FIELD_BIT,
2000 		.offset = 538,
2001 		.width = 1,
2002 	},
2003 	[VCAP_KF_L4_PSH] = {
2004 		.type = VCAP_FIELD_BIT,
2005 		.offset = 539,
2006 		.width = 1,
2007 	},
2008 	[VCAP_KF_L4_ACK] = {
2009 		.type = VCAP_FIELD_BIT,
2010 		.offset = 540,
2011 		.width = 1,
2012 	},
2013 	[VCAP_KF_L4_URG] = {
2014 		.type = VCAP_FIELD_BIT,
2015 		.offset = 541,
2016 		.width = 1,
2017 	},
2018 	[VCAP_KF_L4_PAYLOAD] = {
2019 		.type = VCAP_FIELD_U64,
2020 		.offset = 542,
2021 		.width = 64,
2022 	},
2023 };
2024 
2025 static const struct vcap_field is2_ip6_vid_keyfield[] = {
2026 	[VCAP_KF_TYPE] = {
2027 		.type = VCAP_FIELD_U32,
2028 		.offset = 0,
2029 		.width = 4,
2030 	},
2031 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2032 		.type = VCAP_FIELD_BIT,
2033 		.offset = 4,
2034 		.width = 1,
2035 	},
2036 	[VCAP_KF_LOOKUP_PAG] = {
2037 		.type = VCAP_FIELD_U32,
2038 		.offset = 5,
2039 		.width = 8,
2040 	},
2041 	[VCAP_KF_ISDX_GT0_IS] = {
2042 		.type = VCAP_FIELD_BIT,
2043 		.offset = 13,
2044 		.width = 1,
2045 	},
2046 	[VCAP_KF_ISDX_CLS] = {
2047 		.type = VCAP_FIELD_U32,
2048 		.offset = 14,
2049 		.width = 12,
2050 	},
2051 	[VCAP_KF_8021Q_VID_CLS] = {
2052 		.type = VCAP_FIELD_U32,
2053 		.offset = 26,
2054 		.width = 13,
2055 	},
2056 	[VCAP_KF_L3_SMAC_SIP_MATCH] = {
2057 		.type = VCAP_FIELD_BIT,
2058 		.offset = 39,
2059 		.width = 1,
2060 	},
2061 	[VCAP_KF_L3_DMAC_DIP_MATCH] = {
2062 		.type = VCAP_FIELD_BIT,
2063 		.offset = 40,
2064 		.width = 1,
2065 	},
2066 	[VCAP_KF_L3_RT_IS] = {
2067 		.type = VCAP_FIELD_BIT,
2068 		.offset = 41,
2069 		.width = 1,
2070 	},
2071 	[VCAP_KF_L3_DST_IS] = {
2072 		.type = VCAP_FIELD_BIT,
2073 		.offset = 42,
2074 		.width = 1,
2075 	},
2076 	[VCAP_KF_L3_IP6_DIP] = {
2077 		.type = VCAP_FIELD_U128,
2078 		.offset = 43,
2079 		.width = 128,
2080 	},
2081 	[VCAP_KF_L3_IP6_SIP] = {
2082 		.type = VCAP_FIELD_U128,
2083 		.offset = 171,
2084 		.width = 128,
2085 	},
2086 };
2087 
2088 static const struct vcap_field es2_mac_etype_keyfield[] = {
2089 	[VCAP_KF_TYPE] = {
2090 		.type = VCAP_FIELD_U32,
2091 		.offset = 0,
2092 		.width = 3,
2093 	},
2094 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2095 		.type = VCAP_FIELD_BIT,
2096 		.offset = 3,
2097 		.width = 1,
2098 	},
2099 	[VCAP_KF_ACL_GRP_ID] = {
2100 		.type = VCAP_FIELD_U32,
2101 		.offset = 4,
2102 		.width = 8,
2103 	},
2104 	[VCAP_KF_PROT_ACTIVE] = {
2105 		.type = VCAP_FIELD_BIT,
2106 		.offset = 12,
2107 		.width = 1,
2108 	},
2109 	[VCAP_KF_L2_MC_IS] = {
2110 		.type = VCAP_FIELD_BIT,
2111 		.offset = 13,
2112 		.width = 1,
2113 	},
2114 	[VCAP_KF_L2_BC_IS] = {
2115 		.type = VCAP_FIELD_BIT,
2116 		.offset = 14,
2117 		.width = 1,
2118 	},
2119 	[VCAP_KF_ISDX_GT0_IS] = {
2120 		.type = VCAP_FIELD_BIT,
2121 		.offset = 15,
2122 		.width = 1,
2123 	},
2124 	[VCAP_KF_ISDX_CLS] = {
2125 		.type = VCAP_FIELD_U32,
2126 		.offset = 16,
2127 		.width = 12,
2128 	},
2129 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2130 		.type = VCAP_FIELD_BIT,
2131 		.offset = 28,
2132 		.width = 1,
2133 	},
2134 	[VCAP_KF_8021Q_VID_CLS] = {
2135 		.type = VCAP_FIELD_U32,
2136 		.offset = 29,
2137 		.width = 13,
2138 	},
2139 	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2140 		.type = VCAP_FIELD_U32,
2141 		.offset = 42,
2142 		.width = 3,
2143 	},
2144 	[VCAP_KF_IF_EGR_PORT_MASK] = {
2145 		.type = VCAP_FIELD_U32,
2146 		.offset = 45,
2147 		.width = 32,
2148 	},
2149 	[VCAP_KF_IF_IGR_PORT_SEL] = {
2150 		.type = VCAP_FIELD_BIT,
2151 		.offset = 77,
2152 		.width = 1,
2153 	},
2154 	[VCAP_KF_IF_IGR_PORT] = {
2155 		.type = VCAP_FIELD_U32,
2156 		.offset = 78,
2157 		.width = 9,
2158 	},
2159 	[VCAP_KF_8021Q_PCP_CLS] = {
2160 		.type = VCAP_FIELD_U32,
2161 		.offset = 87,
2162 		.width = 3,
2163 	},
2164 	[VCAP_KF_8021Q_DEI_CLS] = {
2165 		.type = VCAP_FIELD_BIT,
2166 		.offset = 90,
2167 		.width = 1,
2168 	},
2169 	[VCAP_KF_COSID_CLS] = {
2170 		.type = VCAP_FIELD_U32,
2171 		.offset = 91,
2172 		.width = 3,
2173 	},
2174 	[VCAP_KF_L3_DPL_CLS] = {
2175 		.type = VCAP_FIELD_BIT,
2176 		.offset = 94,
2177 		.width = 1,
2178 	},
2179 	[VCAP_KF_L3_RT_IS] = {
2180 		.type = VCAP_FIELD_BIT,
2181 		.offset = 95,
2182 		.width = 1,
2183 	},
2184 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
2185 		.type = VCAP_FIELD_BIT,
2186 		.offset = 96,
2187 		.width = 1,
2188 	},
2189 	[VCAP_KF_MIRROR_ENA] = {
2190 		.type = VCAP_FIELD_U32,
2191 		.offset = 97,
2192 		.width = 2,
2193 	},
2194 	[VCAP_KF_L2_DMAC] = {
2195 		.type = VCAP_FIELD_U48,
2196 		.offset = 99,
2197 		.width = 48,
2198 	},
2199 	[VCAP_KF_L2_SMAC] = {
2200 		.type = VCAP_FIELD_U48,
2201 		.offset = 147,
2202 		.width = 48,
2203 	},
2204 	[VCAP_KF_ETYPE_LEN_IS] = {
2205 		.type = VCAP_FIELD_BIT,
2206 		.offset = 195,
2207 		.width = 1,
2208 	},
2209 	[VCAP_KF_ETYPE] = {
2210 		.type = VCAP_FIELD_U32,
2211 		.offset = 196,
2212 		.width = 16,
2213 	},
2214 	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
2215 		.type = VCAP_FIELD_U64,
2216 		.offset = 212,
2217 		.width = 64,
2218 	},
2219 	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
2220 		.type = VCAP_FIELD_BIT,
2221 		.offset = 276,
2222 		.width = 1,
2223 	},
2224 	[VCAP_KF_OAM_Y1731_IS] = {
2225 		.type = VCAP_FIELD_BIT,
2226 		.offset = 277,
2227 		.width = 1,
2228 	},
2229 };
2230 
2231 static const struct vcap_field es2_arp_keyfield[] = {
2232 	[VCAP_KF_TYPE] = {
2233 		.type = VCAP_FIELD_U32,
2234 		.offset = 0,
2235 		.width = 3,
2236 	},
2237 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2238 		.type = VCAP_FIELD_BIT,
2239 		.offset = 3,
2240 		.width = 1,
2241 	},
2242 	[VCAP_KF_ACL_GRP_ID] = {
2243 		.type = VCAP_FIELD_U32,
2244 		.offset = 4,
2245 		.width = 8,
2246 	},
2247 	[VCAP_KF_PROT_ACTIVE] = {
2248 		.type = VCAP_FIELD_BIT,
2249 		.offset = 12,
2250 		.width = 1,
2251 	},
2252 	[VCAP_KF_L2_MC_IS] = {
2253 		.type = VCAP_FIELD_BIT,
2254 		.offset = 13,
2255 		.width = 1,
2256 	},
2257 	[VCAP_KF_L2_BC_IS] = {
2258 		.type = VCAP_FIELD_BIT,
2259 		.offset = 14,
2260 		.width = 1,
2261 	},
2262 	[VCAP_KF_ISDX_GT0_IS] = {
2263 		.type = VCAP_FIELD_BIT,
2264 		.offset = 15,
2265 		.width = 1,
2266 	},
2267 	[VCAP_KF_ISDX_CLS] = {
2268 		.type = VCAP_FIELD_U32,
2269 		.offset = 16,
2270 		.width = 12,
2271 	},
2272 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2273 		.type = VCAP_FIELD_BIT,
2274 		.offset = 28,
2275 		.width = 1,
2276 	},
2277 	[VCAP_KF_8021Q_VID_CLS] = {
2278 		.type = VCAP_FIELD_U32,
2279 		.offset = 29,
2280 		.width = 13,
2281 	},
2282 	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2283 		.type = VCAP_FIELD_U32,
2284 		.offset = 42,
2285 		.width = 3,
2286 	},
2287 	[VCAP_KF_IF_EGR_PORT_MASK] = {
2288 		.type = VCAP_FIELD_U32,
2289 		.offset = 45,
2290 		.width = 32,
2291 	},
2292 	[VCAP_KF_IF_IGR_PORT_SEL] = {
2293 		.type = VCAP_FIELD_BIT,
2294 		.offset = 77,
2295 		.width = 1,
2296 	},
2297 	[VCAP_KF_IF_IGR_PORT] = {
2298 		.type = VCAP_FIELD_U32,
2299 		.offset = 78,
2300 		.width = 9,
2301 	},
2302 	[VCAP_KF_8021Q_PCP_CLS] = {
2303 		.type = VCAP_FIELD_U32,
2304 		.offset = 87,
2305 		.width = 3,
2306 	},
2307 	[VCAP_KF_8021Q_DEI_CLS] = {
2308 		.type = VCAP_FIELD_BIT,
2309 		.offset = 90,
2310 		.width = 1,
2311 	},
2312 	[VCAP_KF_COSID_CLS] = {
2313 		.type = VCAP_FIELD_U32,
2314 		.offset = 91,
2315 		.width = 3,
2316 	},
2317 	[VCAP_KF_L3_DPL_CLS] = {
2318 		.type = VCAP_FIELD_BIT,
2319 		.offset = 94,
2320 		.width = 1,
2321 	},
2322 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
2323 		.type = VCAP_FIELD_BIT,
2324 		.offset = 95,
2325 		.width = 1,
2326 	},
2327 	[VCAP_KF_MIRROR_ENA] = {
2328 		.type = VCAP_FIELD_U32,
2329 		.offset = 96,
2330 		.width = 2,
2331 	},
2332 	[VCAP_KF_L2_SMAC] = {
2333 		.type = VCAP_FIELD_U48,
2334 		.offset = 98,
2335 		.width = 48,
2336 	},
2337 	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
2338 		.type = VCAP_FIELD_BIT,
2339 		.offset = 146,
2340 		.width = 1,
2341 	},
2342 	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
2343 		.type = VCAP_FIELD_BIT,
2344 		.offset = 147,
2345 		.width = 1,
2346 	},
2347 	[VCAP_KF_ARP_LEN_OK_IS] = {
2348 		.type = VCAP_FIELD_BIT,
2349 		.offset = 148,
2350 		.width = 1,
2351 	},
2352 	[VCAP_KF_ARP_TGT_MATCH_IS] = {
2353 		.type = VCAP_FIELD_BIT,
2354 		.offset = 149,
2355 		.width = 1,
2356 	},
2357 	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
2358 		.type = VCAP_FIELD_BIT,
2359 		.offset = 150,
2360 		.width = 1,
2361 	},
2362 	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
2363 		.type = VCAP_FIELD_BIT,
2364 		.offset = 151,
2365 		.width = 1,
2366 	},
2367 	[VCAP_KF_ARP_OPCODE] = {
2368 		.type = VCAP_FIELD_U32,
2369 		.offset = 152,
2370 		.width = 2,
2371 	},
2372 	[VCAP_KF_L3_IP4_DIP] = {
2373 		.type = VCAP_FIELD_U32,
2374 		.offset = 154,
2375 		.width = 32,
2376 	},
2377 	[VCAP_KF_L3_IP4_SIP] = {
2378 		.type = VCAP_FIELD_U32,
2379 		.offset = 186,
2380 		.width = 32,
2381 	},
2382 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2383 		.type = VCAP_FIELD_BIT,
2384 		.offset = 218,
2385 		.width = 1,
2386 	},
2387 };
2388 
2389 static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {
2390 	[VCAP_KF_TYPE] = {
2391 		.type = VCAP_FIELD_U32,
2392 		.offset = 0,
2393 		.width = 3,
2394 	},
2395 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2396 		.type = VCAP_FIELD_BIT,
2397 		.offset = 3,
2398 		.width = 1,
2399 	},
2400 	[VCAP_KF_ACL_GRP_ID] = {
2401 		.type = VCAP_FIELD_U32,
2402 		.offset = 4,
2403 		.width = 8,
2404 	},
2405 	[VCAP_KF_PROT_ACTIVE] = {
2406 		.type = VCAP_FIELD_BIT,
2407 		.offset = 12,
2408 		.width = 1,
2409 	},
2410 	[VCAP_KF_L2_MC_IS] = {
2411 		.type = VCAP_FIELD_BIT,
2412 		.offset = 13,
2413 		.width = 1,
2414 	},
2415 	[VCAP_KF_L2_BC_IS] = {
2416 		.type = VCAP_FIELD_BIT,
2417 		.offset = 14,
2418 		.width = 1,
2419 	},
2420 	[VCAP_KF_ISDX_GT0_IS] = {
2421 		.type = VCAP_FIELD_BIT,
2422 		.offset = 15,
2423 		.width = 1,
2424 	},
2425 	[VCAP_KF_ISDX_CLS] = {
2426 		.type = VCAP_FIELD_U32,
2427 		.offset = 16,
2428 		.width = 12,
2429 	},
2430 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2431 		.type = VCAP_FIELD_BIT,
2432 		.offset = 28,
2433 		.width = 1,
2434 	},
2435 	[VCAP_KF_8021Q_VID_CLS] = {
2436 		.type = VCAP_FIELD_U32,
2437 		.offset = 29,
2438 		.width = 13,
2439 	},
2440 	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2441 		.type = VCAP_FIELD_U32,
2442 		.offset = 42,
2443 		.width = 3,
2444 	},
2445 	[VCAP_KF_IF_EGR_PORT_MASK] = {
2446 		.type = VCAP_FIELD_U32,
2447 		.offset = 45,
2448 		.width = 32,
2449 	},
2450 	[VCAP_KF_IF_IGR_PORT_SEL] = {
2451 		.type = VCAP_FIELD_BIT,
2452 		.offset = 77,
2453 		.width = 1,
2454 	},
2455 	[VCAP_KF_IF_IGR_PORT] = {
2456 		.type = VCAP_FIELD_U32,
2457 		.offset = 78,
2458 		.width = 9,
2459 	},
2460 	[VCAP_KF_8021Q_PCP_CLS] = {
2461 		.type = VCAP_FIELD_U32,
2462 		.offset = 87,
2463 		.width = 3,
2464 	},
2465 	[VCAP_KF_8021Q_DEI_CLS] = {
2466 		.type = VCAP_FIELD_BIT,
2467 		.offset = 90,
2468 		.width = 1,
2469 	},
2470 	[VCAP_KF_COSID_CLS] = {
2471 		.type = VCAP_FIELD_U32,
2472 		.offset = 91,
2473 		.width = 3,
2474 	},
2475 	[VCAP_KF_L3_DPL_CLS] = {
2476 		.type = VCAP_FIELD_BIT,
2477 		.offset = 94,
2478 		.width = 1,
2479 	},
2480 	[VCAP_KF_L3_RT_IS] = {
2481 		.type = VCAP_FIELD_BIT,
2482 		.offset = 95,
2483 		.width = 1,
2484 	},
2485 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
2486 		.type = VCAP_FIELD_BIT,
2487 		.offset = 96,
2488 		.width = 1,
2489 	},
2490 	[VCAP_KF_MIRROR_ENA] = {
2491 		.type = VCAP_FIELD_U32,
2492 		.offset = 97,
2493 		.width = 2,
2494 	},
2495 	[VCAP_KF_IP4_IS] = {
2496 		.type = VCAP_FIELD_BIT,
2497 		.offset = 99,
2498 		.width = 1,
2499 	},
2500 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
2501 		.type = VCAP_FIELD_U32,
2502 		.offset = 100,
2503 		.width = 2,
2504 	},
2505 	[VCAP_KF_L3_OPTIONS_IS] = {
2506 		.type = VCAP_FIELD_BIT,
2507 		.offset = 102,
2508 		.width = 1,
2509 	},
2510 	[VCAP_KF_L3_TTL_GT0] = {
2511 		.type = VCAP_FIELD_BIT,
2512 		.offset = 103,
2513 		.width = 1,
2514 	},
2515 	[VCAP_KF_L3_TOS] = {
2516 		.type = VCAP_FIELD_U32,
2517 		.offset = 104,
2518 		.width = 8,
2519 	},
2520 	[VCAP_KF_L3_IP4_DIP] = {
2521 		.type = VCAP_FIELD_U32,
2522 		.offset = 112,
2523 		.width = 32,
2524 	},
2525 	[VCAP_KF_L3_IP4_SIP] = {
2526 		.type = VCAP_FIELD_U32,
2527 		.offset = 144,
2528 		.width = 32,
2529 	},
2530 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2531 		.type = VCAP_FIELD_BIT,
2532 		.offset = 176,
2533 		.width = 1,
2534 	},
2535 	[VCAP_KF_TCP_IS] = {
2536 		.type = VCAP_FIELD_BIT,
2537 		.offset = 177,
2538 		.width = 1,
2539 	},
2540 	[VCAP_KF_L4_DPORT] = {
2541 		.type = VCAP_FIELD_U32,
2542 		.offset = 178,
2543 		.width = 16,
2544 	},
2545 	[VCAP_KF_L4_SPORT] = {
2546 		.type = VCAP_FIELD_U32,
2547 		.offset = 194,
2548 		.width = 16,
2549 	},
2550 	[VCAP_KF_L4_RNG] = {
2551 		.type = VCAP_FIELD_U32,
2552 		.offset = 210,
2553 		.width = 16,
2554 	},
2555 	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
2556 		.type = VCAP_FIELD_BIT,
2557 		.offset = 226,
2558 		.width = 1,
2559 	},
2560 	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
2561 		.type = VCAP_FIELD_BIT,
2562 		.offset = 227,
2563 		.width = 1,
2564 	},
2565 	[VCAP_KF_L4_FIN] = {
2566 		.type = VCAP_FIELD_BIT,
2567 		.offset = 228,
2568 		.width = 1,
2569 	},
2570 	[VCAP_KF_L4_SYN] = {
2571 		.type = VCAP_FIELD_BIT,
2572 		.offset = 229,
2573 		.width = 1,
2574 	},
2575 	[VCAP_KF_L4_RST] = {
2576 		.type = VCAP_FIELD_BIT,
2577 		.offset = 230,
2578 		.width = 1,
2579 	},
2580 	[VCAP_KF_L4_PSH] = {
2581 		.type = VCAP_FIELD_BIT,
2582 		.offset = 231,
2583 		.width = 1,
2584 	},
2585 	[VCAP_KF_L4_ACK] = {
2586 		.type = VCAP_FIELD_BIT,
2587 		.offset = 232,
2588 		.width = 1,
2589 	},
2590 	[VCAP_KF_L4_URG] = {
2591 		.type = VCAP_FIELD_BIT,
2592 		.offset = 233,
2593 		.width = 1,
2594 	},
2595 	[VCAP_KF_L4_PAYLOAD] = {
2596 		.type = VCAP_FIELD_U64,
2597 		.offset = 234,
2598 		.width = 64,
2599 	},
2600 };
2601 
2602 static const struct vcap_field es2_ip4_other_keyfield[] = {
2603 	[VCAP_KF_TYPE] = {
2604 		.type = VCAP_FIELD_U32,
2605 		.offset = 0,
2606 		.width = 3,
2607 	},
2608 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2609 		.type = VCAP_FIELD_BIT,
2610 		.offset = 3,
2611 		.width = 1,
2612 	},
2613 	[VCAP_KF_ACL_GRP_ID] = {
2614 		.type = VCAP_FIELD_U32,
2615 		.offset = 4,
2616 		.width = 8,
2617 	},
2618 	[VCAP_KF_PROT_ACTIVE] = {
2619 		.type = VCAP_FIELD_BIT,
2620 		.offset = 12,
2621 		.width = 1,
2622 	},
2623 	[VCAP_KF_L2_MC_IS] = {
2624 		.type = VCAP_FIELD_BIT,
2625 		.offset = 13,
2626 		.width = 1,
2627 	},
2628 	[VCAP_KF_L2_BC_IS] = {
2629 		.type = VCAP_FIELD_BIT,
2630 		.offset = 14,
2631 		.width = 1,
2632 	},
2633 	[VCAP_KF_ISDX_GT0_IS] = {
2634 		.type = VCAP_FIELD_BIT,
2635 		.offset = 15,
2636 		.width = 1,
2637 	},
2638 	[VCAP_KF_ISDX_CLS] = {
2639 		.type = VCAP_FIELD_U32,
2640 		.offset = 16,
2641 		.width = 12,
2642 	},
2643 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2644 		.type = VCAP_FIELD_BIT,
2645 		.offset = 28,
2646 		.width = 1,
2647 	},
2648 	[VCAP_KF_8021Q_VID_CLS] = {
2649 		.type = VCAP_FIELD_U32,
2650 		.offset = 29,
2651 		.width = 13,
2652 	},
2653 	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2654 		.type = VCAP_FIELD_U32,
2655 		.offset = 42,
2656 		.width = 3,
2657 	},
2658 	[VCAP_KF_IF_EGR_PORT_MASK] = {
2659 		.type = VCAP_FIELD_U32,
2660 		.offset = 45,
2661 		.width = 32,
2662 	},
2663 	[VCAP_KF_IF_IGR_PORT_SEL] = {
2664 		.type = VCAP_FIELD_BIT,
2665 		.offset = 77,
2666 		.width = 1,
2667 	},
2668 	[VCAP_KF_IF_IGR_PORT] = {
2669 		.type = VCAP_FIELD_U32,
2670 		.offset = 78,
2671 		.width = 9,
2672 	},
2673 	[VCAP_KF_8021Q_PCP_CLS] = {
2674 		.type = VCAP_FIELD_U32,
2675 		.offset = 87,
2676 		.width = 3,
2677 	},
2678 	[VCAP_KF_8021Q_DEI_CLS] = {
2679 		.type = VCAP_FIELD_BIT,
2680 		.offset = 90,
2681 		.width = 1,
2682 	},
2683 	[VCAP_KF_COSID_CLS] = {
2684 		.type = VCAP_FIELD_U32,
2685 		.offset = 91,
2686 		.width = 3,
2687 	},
2688 	[VCAP_KF_L3_DPL_CLS] = {
2689 		.type = VCAP_FIELD_BIT,
2690 		.offset = 94,
2691 		.width = 1,
2692 	},
2693 	[VCAP_KF_L3_RT_IS] = {
2694 		.type = VCAP_FIELD_BIT,
2695 		.offset = 95,
2696 		.width = 1,
2697 	},
2698 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
2699 		.type = VCAP_FIELD_BIT,
2700 		.offset = 96,
2701 		.width = 1,
2702 	},
2703 	[VCAP_KF_MIRROR_ENA] = {
2704 		.type = VCAP_FIELD_U32,
2705 		.offset = 97,
2706 		.width = 2,
2707 	},
2708 	[VCAP_KF_IP4_IS] = {
2709 		.type = VCAP_FIELD_BIT,
2710 		.offset = 99,
2711 		.width = 1,
2712 	},
2713 	[VCAP_KF_L3_FRAGMENT_TYPE] = {
2714 		.type = VCAP_FIELD_U32,
2715 		.offset = 100,
2716 		.width = 2,
2717 	},
2718 	[VCAP_KF_L3_OPTIONS_IS] = {
2719 		.type = VCAP_FIELD_BIT,
2720 		.offset = 102,
2721 		.width = 1,
2722 	},
2723 	[VCAP_KF_L3_TTL_GT0] = {
2724 		.type = VCAP_FIELD_BIT,
2725 		.offset = 103,
2726 		.width = 1,
2727 	},
2728 	[VCAP_KF_L3_TOS] = {
2729 		.type = VCAP_FIELD_U32,
2730 		.offset = 104,
2731 		.width = 8,
2732 	},
2733 	[VCAP_KF_L3_IP4_DIP] = {
2734 		.type = VCAP_FIELD_U32,
2735 		.offset = 112,
2736 		.width = 32,
2737 	},
2738 	[VCAP_KF_L3_IP4_SIP] = {
2739 		.type = VCAP_FIELD_U32,
2740 		.offset = 144,
2741 		.width = 32,
2742 	},
2743 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2744 		.type = VCAP_FIELD_BIT,
2745 		.offset = 176,
2746 		.width = 1,
2747 	},
2748 	[VCAP_KF_L3_IP_PROTO] = {
2749 		.type = VCAP_FIELD_U32,
2750 		.offset = 177,
2751 		.width = 8,
2752 	},
2753 	[VCAP_KF_L3_PAYLOAD] = {
2754 		.type = VCAP_FIELD_U112,
2755 		.offset = 185,
2756 		.width = 96,
2757 	},
2758 };
2759 
2760 static const struct vcap_field es2_ip_7tuple_keyfield[] = {
2761 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2762 		.type = VCAP_FIELD_BIT,
2763 		.offset = 0,
2764 		.width = 1,
2765 	},
2766 	[VCAP_KF_ACL_GRP_ID] = {
2767 		.type = VCAP_FIELD_U32,
2768 		.offset = 1,
2769 		.width = 8,
2770 	},
2771 	[VCAP_KF_PROT_ACTIVE] = {
2772 		.type = VCAP_FIELD_BIT,
2773 		.offset = 9,
2774 		.width = 1,
2775 	},
2776 	[VCAP_KF_L2_MC_IS] = {
2777 		.type = VCAP_FIELD_BIT,
2778 		.offset = 10,
2779 		.width = 1,
2780 	},
2781 	[VCAP_KF_L2_BC_IS] = {
2782 		.type = VCAP_FIELD_BIT,
2783 		.offset = 11,
2784 		.width = 1,
2785 	},
2786 	[VCAP_KF_ISDX_GT0_IS] = {
2787 		.type = VCAP_FIELD_BIT,
2788 		.offset = 12,
2789 		.width = 1,
2790 	},
2791 	[VCAP_KF_ISDX_CLS] = {
2792 		.type = VCAP_FIELD_U32,
2793 		.offset = 13,
2794 		.width = 12,
2795 	},
2796 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
2797 		.type = VCAP_FIELD_BIT,
2798 		.offset = 25,
2799 		.width = 1,
2800 	},
2801 	[VCAP_KF_8021Q_VID_CLS] = {
2802 		.type = VCAP_FIELD_U32,
2803 		.offset = 26,
2804 		.width = 13,
2805 	},
2806 	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
2807 		.type = VCAP_FIELD_U32,
2808 		.offset = 39,
2809 		.width = 3,
2810 	},
2811 	[VCAP_KF_IF_EGR_PORT_MASK] = {
2812 		.type = VCAP_FIELD_U32,
2813 		.offset = 42,
2814 		.width = 32,
2815 	},
2816 	[VCAP_KF_IF_IGR_PORT_SEL] = {
2817 		.type = VCAP_FIELD_BIT,
2818 		.offset = 74,
2819 		.width = 1,
2820 	},
2821 	[VCAP_KF_IF_IGR_PORT] = {
2822 		.type = VCAP_FIELD_U32,
2823 		.offset = 75,
2824 		.width = 9,
2825 	},
2826 	[VCAP_KF_8021Q_PCP_CLS] = {
2827 		.type = VCAP_FIELD_U32,
2828 		.offset = 84,
2829 		.width = 3,
2830 	},
2831 	[VCAP_KF_8021Q_DEI_CLS] = {
2832 		.type = VCAP_FIELD_BIT,
2833 		.offset = 87,
2834 		.width = 1,
2835 	},
2836 	[VCAP_KF_COSID_CLS] = {
2837 		.type = VCAP_FIELD_U32,
2838 		.offset = 88,
2839 		.width = 3,
2840 	},
2841 	[VCAP_KF_L3_DPL_CLS] = {
2842 		.type = VCAP_FIELD_BIT,
2843 		.offset = 91,
2844 		.width = 1,
2845 	},
2846 	[VCAP_KF_L3_RT_IS] = {
2847 		.type = VCAP_FIELD_BIT,
2848 		.offset = 92,
2849 		.width = 1,
2850 	},
2851 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
2852 		.type = VCAP_FIELD_BIT,
2853 		.offset = 93,
2854 		.width = 1,
2855 	},
2856 	[VCAP_KF_MIRROR_ENA] = {
2857 		.type = VCAP_FIELD_U32,
2858 		.offset = 94,
2859 		.width = 2,
2860 	},
2861 	[VCAP_KF_L2_DMAC] = {
2862 		.type = VCAP_FIELD_U48,
2863 		.offset = 96,
2864 		.width = 48,
2865 	},
2866 	[VCAP_KF_L2_SMAC] = {
2867 		.type = VCAP_FIELD_U48,
2868 		.offset = 144,
2869 		.width = 48,
2870 	},
2871 	[VCAP_KF_IP4_IS] = {
2872 		.type = VCAP_FIELD_BIT,
2873 		.offset = 192,
2874 		.width = 1,
2875 	},
2876 	[VCAP_KF_L3_TTL_GT0] = {
2877 		.type = VCAP_FIELD_BIT,
2878 		.offset = 193,
2879 		.width = 1,
2880 	},
2881 	[VCAP_KF_L3_TOS] = {
2882 		.type = VCAP_FIELD_U32,
2883 		.offset = 194,
2884 		.width = 8,
2885 	},
2886 	[VCAP_KF_L3_IP6_DIP] = {
2887 		.type = VCAP_FIELD_U128,
2888 		.offset = 202,
2889 		.width = 128,
2890 	},
2891 	[VCAP_KF_L3_IP6_SIP] = {
2892 		.type = VCAP_FIELD_U128,
2893 		.offset = 330,
2894 		.width = 128,
2895 	},
2896 	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
2897 		.type = VCAP_FIELD_BIT,
2898 		.offset = 458,
2899 		.width = 1,
2900 	},
2901 	[VCAP_KF_TCP_UDP_IS] = {
2902 		.type = VCAP_FIELD_BIT,
2903 		.offset = 459,
2904 		.width = 1,
2905 	},
2906 	[VCAP_KF_TCP_IS] = {
2907 		.type = VCAP_FIELD_BIT,
2908 		.offset = 460,
2909 		.width = 1,
2910 	},
2911 	[VCAP_KF_L4_DPORT] = {
2912 		.type = VCAP_FIELD_U32,
2913 		.offset = 461,
2914 		.width = 16,
2915 	},
2916 	[VCAP_KF_L4_SPORT] = {
2917 		.type = VCAP_FIELD_U32,
2918 		.offset = 477,
2919 		.width = 16,
2920 	},
2921 	[VCAP_KF_L4_RNG] = {
2922 		.type = VCAP_FIELD_U32,
2923 		.offset = 493,
2924 		.width = 16,
2925 	},
2926 	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
2927 		.type = VCAP_FIELD_BIT,
2928 		.offset = 509,
2929 		.width = 1,
2930 	},
2931 	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
2932 		.type = VCAP_FIELD_BIT,
2933 		.offset = 510,
2934 		.width = 1,
2935 	},
2936 	[VCAP_KF_L4_FIN] = {
2937 		.type = VCAP_FIELD_BIT,
2938 		.offset = 511,
2939 		.width = 1,
2940 	},
2941 	[VCAP_KF_L4_SYN] = {
2942 		.type = VCAP_FIELD_BIT,
2943 		.offset = 512,
2944 		.width = 1,
2945 	},
2946 	[VCAP_KF_L4_RST] = {
2947 		.type = VCAP_FIELD_BIT,
2948 		.offset = 513,
2949 		.width = 1,
2950 	},
2951 	[VCAP_KF_L4_PSH] = {
2952 		.type = VCAP_FIELD_BIT,
2953 		.offset = 514,
2954 		.width = 1,
2955 	},
2956 	[VCAP_KF_L4_ACK] = {
2957 		.type = VCAP_FIELD_BIT,
2958 		.offset = 515,
2959 		.width = 1,
2960 	},
2961 	[VCAP_KF_L4_URG] = {
2962 		.type = VCAP_FIELD_BIT,
2963 		.offset = 516,
2964 		.width = 1,
2965 	},
2966 	[VCAP_KF_L4_PAYLOAD] = {
2967 		.type = VCAP_FIELD_U64,
2968 		.offset = 517,
2969 		.width = 64,
2970 	},
2971 };
2972 
2973 static const struct vcap_field es2_ip4_vid_keyfield[] = {
2974 	[VCAP_KF_LOOKUP_FIRST_IS] = {
2975 		.type = VCAP_FIELD_BIT,
2976 		.offset = 0,
2977 		.width = 1,
2978 	},
2979 	[VCAP_KF_ACL_GRP_ID] = {
2980 		.type = VCAP_FIELD_U32,
2981 		.offset = 1,
2982 		.width = 8,
2983 	},
2984 	[VCAP_KF_PROT_ACTIVE] = {
2985 		.type = VCAP_FIELD_BIT,
2986 		.offset = 9,
2987 		.width = 1,
2988 	},
2989 	[VCAP_KF_L2_MC_IS] = {
2990 		.type = VCAP_FIELD_BIT,
2991 		.offset = 10,
2992 		.width = 1,
2993 	},
2994 	[VCAP_KF_L2_BC_IS] = {
2995 		.type = VCAP_FIELD_BIT,
2996 		.offset = 11,
2997 		.width = 1,
2998 	},
2999 	[VCAP_KF_ISDX_GT0_IS] = {
3000 		.type = VCAP_FIELD_BIT,
3001 		.offset = 12,
3002 		.width = 1,
3003 	},
3004 	[VCAP_KF_ISDX_CLS] = {
3005 		.type = VCAP_FIELD_U32,
3006 		.offset = 13,
3007 		.width = 12,
3008 	},
3009 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
3010 		.type = VCAP_FIELD_BIT,
3011 		.offset = 25,
3012 		.width = 1,
3013 	},
3014 	[VCAP_KF_8021Q_VID_CLS] = {
3015 		.type = VCAP_FIELD_U32,
3016 		.offset = 26,
3017 		.width = 13,
3018 	},
3019 	[VCAP_KF_8021Q_PCP_CLS] = {
3020 		.type = VCAP_FIELD_U32,
3021 		.offset = 39,
3022 		.width = 3,
3023 	},
3024 	[VCAP_KF_8021Q_DEI_CLS] = {
3025 		.type = VCAP_FIELD_BIT,
3026 		.offset = 42,
3027 		.width = 1,
3028 	},
3029 	[VCAP_KF_COSID_CLS] = {
3030 		.type = VCAP_FIELD_U32,
3031 		.offset = 43,
3032 		.width = 3,
3033 	},
3034 	[VCAP_KF_L3_DPL_CLS] = {
3035 		.type = VCAP_FIELD_BIT,
3036 		.offset = 46,
3037 		.width = 1,
3038 	},
3039 	[VCAP_KF_L3_RT_IS] = {
3040 		.type = VCAP_FIELD_BIT,
3041 		.offset = 47,
3042 		.width = 1,
3043 	},
3044 	[VCAP_KF_ES0_ISDX_KEY_ENA] = {
3045 		.type = VCAP_FIELD_BIT,
3046 		.offset = 48,
3047 		.width = 1,
3048 	},
3049 	[VCAP_KF_MIRROR_ENA] = {
3050 		.type = VCAP_FIELD_U32,
3051 		.offset = 49,
3052 		.width = 2,
3053 	},
3054 	[VCAP_KF_IP4_IS] = {
3055 		.type = VCAP_FIELD_BIT,
3056 		.offset = 51,
3057 		.width = 1,
3058 	},
3059 	[VCAP_KF_L3_IP4_DIP] = {
3060 		.type = VCAP_FIELD_U32,
3061 		.offset = 52,
3062 		.width = 32,
3063 	},
3064 	[VCAP_KF_L3_IP4_SIP] = {
3065 		.type = VCAP_FIELD_U32,
3066 		.offset = 84,
3067 		.width = 32,
3068 	},
3069 	[VCAP_KF_L4_RNG] = {
3070 		.type = VCAP_FIELD_U32,
3071 		.offset = 116,
3072 		.width = 16,
3073 	},
3074 };
3075 
3076 static const struct vcap_field es2_ip6_vid_keyfield[] = {
3077 	[VCAP_KF_TYPE] = {
3078 		.type = VCAP_FIELD_U32,
3079 		.offset = 0,
3080 		.width = 3,
3081 	},
3082 	[VCAP_KF_LOOKUP_FIRST_IS] = {
3083 		.type = VCAP_FIELD_BIT,
3084 		.offset = 3,
3085 		.width = 1,
3086 	},
3087 	[VCAP_KF_ACL_GRP_ID] = {
3088 		.type = VCAP_FIELD_U32,
3089 		.offset = 4,
3090 		.width = 8,
3091 	},
3092 	[VCAP_KF_PROT_ACTIVE] = {
3093 		.type = VCAP_FIELD_BIT,
3094 		.offset = 12,
3095 		.width = 1,
3096 	},
3097 	[VCAP_KF_L2_MC_IS] = {
3098 		.type = VCAP_FIELD_BIT,
3099 		.offset = 13,
3100 		.width = 1,
3101 	},
3102 	[VCAP_KF_L2_BC_IS] = {
3103 		.type = VCAP_FIELD_BIT,
3104 		.offset = 14,
3105 		.width = 1,
3106 	},
3107 	[VCAP_KF_ISDX_GT0_IS] = {
3108 		.type = VCAP_FIELD_BIT,
3109 		.offset = 15,
3110 		.width = 1,
3111 	},
3112 	[VCAP_KF_ISDX_CLS] = {
3113 		.type = VCAP_FIELD_U32,
3114 		.offset = 16,
3115 		.width = 12,
3116 	},
3117 	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
3118 		.type = VCAP_FIELD_BIT,
3119 		.offset = 28,
3120 		.width = 1,
3121 	},
3122 	[VCAP_KF_8021Q_VID_CLS] = {
3123 		.type = VCAP_FIELD_U32,
3124 		.offset = 29,
3125 		.width = 13,
3126 	},
3127 	[VCAP_KF_L3_RT_IS] = {
3128 		.type = VCAP_FIELD_BIT,
3129 		.offset = 42,
3130 		.width = 1,
3131 	},
3132 	[VCAP_KF_L3_IP6_DIP] = {
3133 		.type = VCAP_FIELD_U128,
3134 		.offset = 43,
3135 		.width = 128,
3136 	},
3137 	[VCAP_KF_L3_IP6_SIP] = {
3138 		.type = VCAP_FIELD_U128,
3139 		.offset = 171,
3140 		.width = 128,
3141 	},
3142 };
3143 
3144 /* keyfield_set */
3145 static const struct vcap_set is0_keyfield_set[] = {
3146 	[VCAP_KFS_MLL] = {
3147 		.type_id = 0,
3148 		.sw_per_item = 3,
3149 		.sw_cnt = 4,
3150 	},
3151 	[VCAP_KFS_TRI_VID] = {
3152 		.type_id = 0,
3153 		.sw_per_item = 2,
3154 		.sw_cnt = 6,
3155 	},
3156 	[VCAP_KFS_LL_FULL] = {
3157 		.type_id = 0,
3158 		.sw_per_item = 6,
3159 		.sw_cnt = 2,
3160 	},
3161 	[VCAP_KFS_NORMAL] = {
3162 		.type_id = 1,
3163 		.sw_per_item = 6,
3164 		.sw_cnt = 2,
3165 	},
3166 	[VCAP_KFS_NORMAL_7TUPLE] = {
3167 		.type_id = 0,
3168 		.sw_per_item = 12,
3169 		.sw_cnt = 1,
3170 	},
3171 	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {
3172 		.type_id = 2,
3173 		.sw_per_item = 6,
3174 		.sw_cnt = 2,
3175 	},
3176 	[VCAP_KFS_PURE_5TUPLE_IP4] = {
3177 		.type_id = 2,
3178 		.sw_per_item = 3,
3179 		.sw_cnt = 4,
3180 	},
3181 	[VCAP_KFS_ETAG] = {
3182 		.type_id = 3,
3183 		.sw_per_item = 2,
3184 		.sw_cnt = 6,
3185 	},
3186 };
3187 
3188 static const struct vcap_set is2_keyfield_set[] = {
3189 	[VCAP_KFS_MAC_ETYPE] = {
3190 		.type_id = 0,
3191 		.sw_per_item = 6,
3192 		.sw_cnt = 2,
3193 	},
3194 	[VCAP_KFS_ARP] = {
3195 		.type_id = 3,
3196 		.sw_per_item = 6,
3197 		.sw_cnt = 2,
3198 	},
3199 	[VCAP_KFS_IP4_TCP_UDP] = {
3200 		.type_id = 4,
3201 		.sw_per_item = 6,
3202 		.sw_cnt = 2,
3203 	},
3204 	[VCAP_KFS_IP4_OTHER] = {
3205 		.type_id = 5,
3206 		.sw_per_item = 6,
3207 		.sw_cnt = 2,
3208 	},
3209 	[VCAP_KFS_IP6_STD] = {
3210 		.type_id = 6,
3211 		.sw_per_item = 6,
3212 		.sw_cnt = 2,
3213 	},
3214 	[VCAP_KFS_IP_7TUPLE] = {
3215 		.type_id = 1,
3216 		.sw_per_item = 12,
3217 		.sw_cnt = 1,
3218 	},
3219 	[VCAP_KFS_IP6_VID] = {
3220 		.type_id = 9,
3221 		.sw_per_item = 6,
3222 		.sw_cnt = 2,
3223 	},
3224 };
3225 
3226 static const struct vcap_set es2_keyfield_set[] = {
3227 	[VCAP_KFS_MAC_ETYPE] = {
3228 		.type_id = 0,
3229 		.sw_per_item = 6,
3230 		.sw_cnt = 2,
3231 	},
3232 	[VCAP_KFS_ARP] = {
3233 		.type_id = 1,
3234 		.sw_per_item = 6,
3235 		.sw_cnt = 2,
3236 	},
3237 	[VCAP_KFS_IP4_TCP_UDP] = {
3238 		.type_id = 2,
3239 		.sw_per_item = 6,
3240 		.sw_cnt = 2,
3241 	},
3242 	[VCAP_KFS_IP4_OTHER] = {
3243 		.type_id = 3,
3244 		.sw_per_item = 6,
3245 		.sw_cnt = 2,
3246 	},
3247 	[VCAP_KFS_IP_7TUPLE] = {
3248 		.type_id = -1,
3249 		.sw_per_item = 12,
3250 		.sw_cnt = 1,
3251 	},
3252 	[VCAP_KFS_IP4_VID] = {
3253 		.type_id = -1,
3254 		.sw_per_item = 3,
3255 		.sw_cnt = 4,
3256 	},
3257 	[VCAP_KFS_IP6_VID] = {
3258 		.type_id = 5,
3259 		.sw_per_item = 6,
3260 		.sw_cnt = 2,
3261 	},
3262 };
3263 
3264 /* keyfield_set map */
3265 static const struct vcap_field *is0_keyfield_set_map[] = {
3266 	[VCAP_KFS_MLL] = is0_mll_keyfield,
3267 	[VCAP_KFS_TRI_VID] = is0_tri_vid_keyfield,
3268 	[VCAP_KFS_LL_FULL] = is0_ll_full_keyfield,
3269 	[VCAP_KFS_NORMAL] = is0_normal_keyfield,
3270 	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,
3271 	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,
3272 	[VCAP_KFS_PURE_5TUPLE_IP4] = is0_pure_5tuple_ip4_keyfield,
3273 	[VCAP_KFS_ETAG] = is0_etag_keyfield,
3274 };
3275 
3276 static const struct vcap_field *is2_keyfield_set_map[] = {
3277 	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
3278 	[VCAP_KFS_ARP] = is2_arp_keyfield,
3279 	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
3280 	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
3281 	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
3282 	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,
3283 	[VCAP_KFS_IP6_VID] = is2_ip6_vid_keyfield,
3284 };
3285 
3286 static const struct vcap_field *es2_keyfield_set_map[] = {
3287 	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
3288 	[VCAP_KFS_ARP] = es2_arp_keyfield,
3289 	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,
3290 	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,
3291 	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,
3292 	[VCAP_KFS_IP4_VID] = es2_ip4_vid_keyfield,
3293 	[VCAP_KFS_IP6_VID] = es2_ip6_vid_keyfield,
3294 };
3295 
3296 /* keyfield_set map sizes */
3297 static int is0_keyfield_set_map_size[] = {
3298 	[VCAP_KFS_MLL] = ARRAY_SIZE(is0_mll_keyfield),
3299 	[VCAP_KFS_TRI_VID] = ARRAY_SIZE(is0_tri_vid_keyfield),
3300 	[VCAP_KFS_LL_FULL] = ARRAY_SIZE(is0_ll_full_keyfield),
3301 	[VCAP_KFS_NORMAL] = ARRAY_SIZE(is0_normal_keyfield),
3302 	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),
3303 	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),
3304 	[VCAP_KFS_PURE_5TUPLE_IP4] = ARRAY_SIZE(is0_pure_5tuple_ip4_keyfield),
3305 	[VCAP_KFS_ETAG] = ARRAY_SIZE(is0_etag_keyfield),
3306 };
3307 
3308 static int is2_keyfield_set_map_size[] = {
3309 	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
3310 	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
3311 	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
3312 	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
3313 	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
3314 	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),
3315 	[VCAP_KFS_IP6_VID] = ARRAY_SIZE(is2_ip6_vid_keyfield),
3316 };
3317 
3318 static int es2_keyfield_set_map_size[] = {
3319 	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
3320 	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
3321 	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),
3322 	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),
3323 	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),
3324 	[VCAP_KFS_IP4_VID] = ARRAY_SIZE(es2_ip4_vid_keyfield),
3325 	[VCAP_KFS_IP6_VID] = ARRAY_SIZE(es2_ip6_vid_keyfield),
3326 };
3327 
3328 /* actionfields */
3329 static const struct vcap_field is0_mlbs_actionfield[] = {
3330 	[VCAP_AF_TYPE] = {
3331 		.type = VCAP_FIELD_BIT,
3332 		.offset = 0,
3333 		.width = 1,
3334 	},
3335 	[VCAP_AF_COSID_ENA] = {
3336 		.type = VCAP_FIELD_BIT,
3337 		.offset = 1,
3338 		.width = 1,
3339 	},
3340 	[VCAP_AF_COSID_VAL] = {
3341 		.type = VCAP_FIELD_U32,
3342 		.offset = 2,
3343 		.width = 3,
3344 	},
3345 	[VCAP_AF_QOS_ENA] = {
3346 		.type = VCAP_FIELD_BIT,
3347 		.offset = 5,
3348 		.width = 1,
3349 	},
3350 	[VCAP_AF_QOS_VAL] = {
3351 		.type = VCAP_FIELD_U32,
3352 		.offset = 6,
3353 		.width = 3,
3354 	},
3355 	[VCAP_AF_DP_ENA] = {
3356 		.type = VCAP_FIELD_BIT,
3357 		.offset = 9,
3358 		.width = 1,
3359 	},
3360 	[VCAP_AF_DP_VAL] = {
3361 		.type = VCAP_FIELD_U32,
3362 		.offset = 10,
3363 		.width = 2,
3364 	},
3365 	[VCAP_AF_MAP_LOOKUP_SEL] = {
3366 		.type = VCAP_FIELD_U32,
3367 		.offset = 12,
3368 		.width = 2,
3369 	},
3370 	[VCAP_AF_MAP_KEY] = {
3371 		.type = VCAP_FIELD_U32,
3372 		.offset = 14,
3373 		.width = 3,
3374 	},
3375 	[VCAP_AF_MAP_IDX] = {
3376 		.type = VCAP_FIELD_U32,
3377 		.offset = 17,
3378 		.width = 9,
3379 	},
3380 	[VCAP_AF_CLS_VID_SEL] = {
3381 		.type = VCAP_FIELD_U32,
3382 		.offset = 26,
3383 		.width = 3,
3384 	},
3385 	[VCAP_AF_GVID_ADD_REPLACE_SEL] = {
3386 		.type = VCAP_FIELD_U32,
3387 		.offset = 29,
3388 		.width = 3,
3389 	},
3390 	[VCAP_AF_VID_VAL] = {
3391 		.type = VCAP_FIELD_U32,
3392 		.offset = 32,
3393 		.width = 13,
3394 	},
3395 	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
3396 		.type = VCAP_FIELD_BIT,
3397 		.offset = 45,
3398 		.width = 1,
3399 	},
3400 	[VCAP_AF_ISDX_VAL] = {
3401 		.type = VCAP_FIELD_U32,
3402 		.offset = 46,
3403 		.width = 12,
3404 	},
3405 	[VCAP_AF_FWD_DIS] = {
3406 		.type = VCAP_FIELD_BIT,
3407 		.offset = 58,
3408 		.width = 1,
3409 	},
3410 	[VCAP_AF_CPU_ENA] = {
3411 		.type = VCAP_FIELD_BIT,
3412 		.offset = 59,
3413 		.width = 1,
3414 	},
3415 	[VCAP_AF_CPU_Q] = {
3416 		.type = VCAP_FIELD_U32,
3417 		.offset = 60,
3418 		.width = 3,
3419 	},
3420 	[VCAP_AF_OAM_Y1731_SEL] = {
3421 		.type = VCAP_FIELD_U32,
3422 		.offset = 63,
3423 		.width = 3,
3424 	},
3425 	[VCAP_AF_OAM_TWAMP_ENA] = {
3426 		.type = VCAP_FIELD_BIT,
3427 		.offset = 66,
3428 		.width = 1,
3429 	},
3430 	[VCAP_AF_OAM_IP_BFD_ENA] = {
3431 		.type = VCAP_FIELD_BIT,
3432 		.offset = 67,
3433 		.width = 1,
3434 	},
3435 	[VCAP_AF_TC_LABEL] = {
3436 		.type = VCAP_FIELD_U32,
3437 		.offset = 68,
3438 		.width = 3,
3439 	},
3440 	[VCAP_AF_TTL_LABEL] = {
3441 		.type = VCAP_FIELD_U32,
3442 		.offset = 71,
3443 		.width = 3,
3444 	},
3445 	[VCAP_AF_NUM_VLD_LABELS] = {
3446 		.type = VCAP_FIELD_U32,
3447 		.offset = 74,
3448 		.width = 2,
3449 	},
3450 	[VCAP_AF_FWD_TYPE] = {
3451 		.type = VCAP_FIELD_U32,
3452 		.offset = 76,
3453 		.width = 3,
3454 	},
3455 	[VCAP_AF_MPLS_OAM_TYPE] = {
3456 		.type = VCAP_FIELD_U32,
3457 		.offset = 79,
3458 		.width = 3,
3459 	},
3460 	[VCAP_AF_MPLS_MEP_ENA] = {
3461 		.type = VCAP_FIELD_BIT,
3462 		.offset = 82,
3463 		.width = 1,
3464 	},
3465 	[VCAP_AF_MPLS_MIP_ENA] = {
3466 		.type = VCAP_FIELD_BIT,
3467 		.offset = 83,
3468 		.width = 1,
3469 	},
3470 	[VCAP_AF_MPLS_OAM_FLAVOR] = {
3471 		.type = VCAP_FIELD_BIT,
3472 		.offset = 84,
3473 		.width = 1,
3474 	},
3475 	[VCAP_AF_MPLS_IP_CTRL_ENA] = {
3476 		.type = VCAP_FIELD_BIT,
3477 		.offset = 85,
3478 		.width = 1,
3479 	},
3480 	[VCAP_AF_PAG_OVERRIDE_MASK] = {
3481 		.type = VCAP_FIELD_U32,
3482 		.offset = 86,
3483 		.width = 8,
3484 	},
3485 	[VCAP_AF_PAG_VAL] = {
3486 		.type = VCAP_FIELD_U32,
3487 		.offset = 94,
3488 		.width = 8,
3489 	},
3490 	[VCAP_AF_S2_KEY_SEL_ENA] = {
3491 		.type = VCAP_FIELD_BIT,
3492 		.offset = 102,
3493 		.width = 1,
3494 	},
3495 	[VCAP_AF_S2_KEY_SEL_IDX] = {
3496 		.type = VCAP_FIELD_U32,
3497 		.offset = 103,
3498 		.width = 6,
3499 	},
3500 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
3501 		.type = VCAP_FIELD_U32,
3502 		.offset = 109,
3503 		.width = 2,
3504 	},
3505 	[VCAP_AF_PIPELINE_ACT_SEL] = {
3506 		.type = VCAP_FIELD_BIT,
3507 		.offset = 111,
3508 		.width = 1,
3509 	},
3510 	[VCAP_AF_PIPELINE_PT] = {
3511 		.type = VCAP_FIELD_U32,
3512 		.offset = 112,
3513 		.width = 5,
3514 	},
3515 	[VCAP_AF_NXT_KEY_TYPE] = {
3516 		.type = VCAP_FIELD_U32,
3517 		.offset = 117,
3518 		.width = 5,
3519 	},
3520 	[VCAP_AF_NXT_NORM_W16_OFFSET] = {
3521 		.type = VCAP_FIELD_U32,
3522 		.offset = 122,
3523 		.width = 5,
3524 	},
3525 	[VCAP_AF_NXT_OFFSET_FROM_TYPE] = {
3526 		.type = VCAP_FIELD_U32,
3527 		.offset = 127,
3528 		.width = 2,
3529 	},
3530 	[VCAP_AF_NXT_TYPE_AFTER_OFFSET] = {
3531 		.type = VCAP_FIELD_U32,
3532 		.offset = 129,
3533 		.width = 2,
3534 	},
3535 	[VCAP_AF_NXT_NORMALIZE] = {
3536 		.type = VCAP_FIELD_BIT,
3537 		.offset = 131,
3538 		.width = 1,
3539 	},
3540 	[VCAP_AF_NXT_IDX_CTRL] = {
3541 		.type = VCAP_FIELD_U32,
3542 		.offset = 132,
3543 		.width = 3,
3544 	},
3545 	[VCAP_AF_NXT_IDX] = {
3546 		.type = VCAP_FIELD_U32,
3547 		.offset = 135,
3548 		.width = 12,
3549 	},
3550 };
3551 
3552 static const struct vcap_field is0_mlbs_reduced_actionfield[] = {
3553 	[VCAP_AF_TYPE] = {
3554 		.type = VCAP_FIELD_BIT,
3555 		.offset = 0,
3556 		.width = 1,
3557 	},
3558 	[VCAP_AF_COSID_ENA] = {
3559 		.type = VCAP_FIELD_BIT,
3560 		.offset = 1,
3561 		.width = 1,
3562 	},
3563 	[VCAP_AF_COSID_VAL] = {
3564 		.type = VCAP_FIELD_U32,
3565 		.offset = 2,
3566 		.width = 3,
3567 	},
3568 	[VCAP_AF_QOS_ENA] = {
3569 		.type = VCAP_FIELD_BIT,
3570 		.offset = 5,
3571 		.width = 1,
3572 	},
3573 	[VCAP_AF_QOS_VAL] = {
3574 		.type = VCAP_FIELD_U32,
3575 		.offset = 6,
3576 		.width = 3,
3577 	},
3578 	[VCAP_AF_DP_ENA] = {
3579 		.type = VCAP_FIELD_BIT,
3580 		.offset = 9,
3581 		.width = 1,
3582 	},
3583 	[VCAP_AF_DP_VAL] = {
3584 		.type = VCAP_FIELD_U32,
3585 		.offset = 10,
3586 		.width = 2,
3587 	},
3588 	[VCAP_AF_MAP_LOOKUP_SEL] = {
3589 		.type = VCAP_FIELD_U32,
3590 		.offset = 12,
3591 		.width = 2,
3592 	},
3593 	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
3594 		.type = VCAP_FIELD_BIT,
3595 		.offset = 14,
3596 		.width = 1,
3597 	},
3598 	[VCAP_AF_ISDX_VAL] = {
3599 		.type = VCAP_FIELD_U32,
3600 		.offset = 15,
3601 		.width = 12,
3602 	},
3603 	[VCAP_AF_FWD_DIS] = {
3604 		.type = VCAP_FIELD_BIT,
3605 		.offset = 27,
3606 		.width = 1,
3607 	},
3608 	[VCAP_AF_CPU_ENA] = {
3609 		.type = VCAP_FIELD_BIT,
3610 		.offset = 28,
3611 		.width = 1,
3612 	},
3613 	[VCAP_AF_CPU_Q] = {
3614 		.type = VCAP_FIELD_U32,
3615 		.offset = 29,
3616 		.width = 3,
3617 	},
3618 	[VCAP_AF_TC_ENA] = {
3619 		.type = VCAP_FIELD_BIT,
3620 		.offset = 32,
3621 		.width = 1,
3622 	},
3623 	[VCAP_AF_TTL_ENA] = {
3624 		.type = VCAP_FIELD_BIT,
3625 		.offset = 33,
3626 		.width = 1,
3627 	},
3628 	[VCAP_AF_FWD_TYPE] = {
3629 		.type = VCAP_FIELD_U32,
3630 		.offset = 34,
3631 		.width = 3,
3632 	},
3633 	[VCAP_AF_MPLS_OAM_TYPE] = {
3634 		.type = VCAP_FIELD_U32,
3635 		.offset = 37,
3636 		.width = 3,
3637 	},
3638 	[VCAP_AF_MPLS_MEP_ENA] = {
3639 		.type = VCAP_FIELD_BIT,
3640 		.offset = 40,
3641 		.width = 1,
3642 	},
3643 	[VCAP_AF_MPLS_MIP_ENA] = {
3644 		.type = VCAP_FIELD_BIT,
3645 		.offset = 41,
3646 		.width = 1,
3647 	},
3648 	[VCAP_AF_MPLS_OAM_FLAVOR] = {
3649 		.type = VCAP_FIELD_BIT,
3650 		.offset = 42,
3651 		.width = 1,
3652 	},
3653 	[VCAP_AF_MPLS_IP_CTRL_ENA] = {
3654 		.type = VCAP_FIELD_BIT,
3655 		.offset = 43,
3656 		.width = 1,
3657 	},
3658 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
3659 		.type = VCAP_FIELD_U32,
3660 		.offset = 44,
3661 		.width = 2,
3662 	},
3663 	[VCAP_AF_PIPELINE_ACT_SEL] = {
3664 		.type = VCAP_FIELD_BIT,
3665 		.offset = 46,
3666 		.width = 1,
3667 	},
3668 	[VCAP_AF_PIPELINE_PT_REDUCED] = {
3669 		.type = VCAP_FIELD_U32,
3670 		.offset = 47,
3671 		.width = 3,
3672 	},
3673 	[VCAP_AF_NXT_KEY_TYPE] = {
3674 		.type = VCAP_FIELD_U32,
3675 		.offset = 50,
3676 		.width = 5,
3677 	},
3678 	[VCAP_AF_NXT_NORM_W32_OFFSET] = {
3679 		.type = VCAP_FIELD_U32,
3680 		.offset = 55,
3681 		.width = 2,
3682 	},
3683 	[VCAP_AF_NXT_TYPE_AFTER_OFFSET] = {
3684 		.type = VCAP_FIELD_U32,
3685 		.offset = 57,
3686 		.width = 2,
3687 	},
3688 	[VCAP_AF_NXT_NORMALIZE] = {
3689 		.type = VCAP_FIELD_BIT,
3690 		.offset = 59,
3691 		.width = 1,
3692 	},
3693 	[VCAP_AF_NXT_IDX_CTRL] = {
3694 		.type = VCAP_FIELD_U32,
3695 		.offset = 60,
3696 		.width = 3,
3697 	},
3698 	[VCAP_AF_NXT_IDX] = {
3699 		.type = VCAP_FIELD_U32,
3700 		.offset = 63,
3701 		.width = 12,
3702 	},
3703 };
3704 
3705 static const struct vcap_field is0_classification_actionfield[] = {
3706 	[VCAP_AF_TYPE] = {
3707 		.type = VCAP_FIELD_BIT,
3708 		.offset = 0,
3709 		.width = 1,
3710 	},
3711 	[VCAP_AF_DSCP_ENA] = {
3712 		.type = VCAP_FIELD_BIT,
3713 		.offset = 1,
3714 		.width = 1,
3715 	},
3716 	[VCAP_AF_DSCP_VAL] = {
3717 		.type = VCAP_FIELD_U32,
3718 		.offset = 2,
3719 		.width = 6,
3720 	},
3721 	[VCAP_AF_COSID_ENA] = {
3722 		.type = VCAP_FIELD_BIT,
3723 		.offset = 8,
3724 		.width = 1,
3725 	},
3726 	[VCAP_AF_COSID_VAL] = {
3727 		.type = VCAP_FIELD_U32,
3728 		.offset = 9,
3729 		.width = 3,
3730 	},
3731 	[VCAP_AF_QOS_ENA] = {
3732 		.type = VCAP_FIELD_BIT,
3733 		.offset = 12,
3734 		.width = 1,
3735 	},
3736 	[VCAP_AF_QOS_VAL] = {
3737 		.type = VCAP_FIELD_U32,
3738 		.offset = 13,
3739 		.width = 3,
3740 	},
3741 	[VCAP_AF_DP_ENA] = {
3742 		.type = VCAP_FIELD_BIT,
3743 		.offset = 16,
3744 		.width = 1,
3745 	},
3746 	[VCAP_AF_DP_VAL] = {
3747 		.type = VCAP_FIELD_U32,
3748 		.offset = 17,
3749 		.width = 2,
3750 	},
3751 	[VCAP_AF_DEI_ENA] = {
3752 		.type = VCAP_FIELD_BIT,
3753 		.offset = 19,
3754 		.width = 1,
3755 	},
3756 	[VCAP_AF_DEI_VAL] = {
3757 		.type = VCAP_FIELD_BIT,
3758 		.offset = 20,
3759 		.width = 1,
3760 	},
3761 	[VCAP_AF_PCP_ENA] = {
3762 		.type = VCAP_FIELD_BIT,
3763 		.offset = 21,
3764 		.width = 1,
3765 	},
3766 	[VCAP_AF_PCP_VAL] = {
3767 		.type = VCAP_FIELD_U32,
3768 		.offset = 22,
3769 		.width = 3,
3770 	},
3771 	[VCAP_AF_MAP_LOOKUP_SEL] = {
3772 		.type = VCAP_FIELD_U32,
3773 		.offset = 25,
3774 		.width = 2,
3775 	},
3776 	[VCAP_AF_MAP_KEY] = {
3777 		.type = VCAP_FIELD_U32,
3778 		.offset = 27,
3779 		.width = 3,
3780 	},
3781 	[VCAP_AF_MAP_IDX] = {
3782 		.type = VCAP_FIELD_U32,
3783 		.offset = 30,
3784 		.width = 9,
3785 	},
3786 	[VCAP_AF_CLS_VID_SEL] = {
3787 		.type = VCAP_FIELD_U32,
3788 		.offset = 39,
3789 		.width = 3,
3790 	},
3791 	[VCAP_AF_GVID_ADD_REPLACE_SEL] = {
3792 		.type = VCAP_FIELD_U32,
3793 		.offset = 42,
3794 		.width = 3,
3795 	},
3796 	[VCAP_AF_VID_VAL] = {
3797 		.type = VCAP_FIELD_U32,
3798 		.offset = 45,
3799 		.width = 13,
3800 	},
3801 	[VCAP_AF_VLAN_POP_CNT_ENA] = {
3802 		.type = VCAP_FIELD_BIT,
3803 		.offset = 58,
3804 		.width = 1,
3805 	},
3806 	[VCAP_AF_VLAN_POP_CNT] = {
3807 		.type = VCAP_FIELD_U32,
3808 		.offset = 59,
3809 		.width = 2,
3810 	},
3811 	[VCAP_AF_VLAN_PUSH_CNT_ENA] = {
3812 		.type = VCAP_FIELD_BIT,
3813 		.offset = 61,
3814 		.width = 1,
3815 	},
3816 	[VCAP_AF_VLAN_PUSH_CNT] = {
3817 		.type = VCAP_FIELD_U32,
3818 		.offset = 62,
3819 		.width = 2,
3820 	},
3821 	[VCAP_AF_TPID_SEL] = {
3822 		.type = VCAP_FIELD_U32,
3823 		.offset = 64,
3824 		.width = 2,
3825 	},
3826 	[VCAP_AF_VLAN_WAS_TAGGED] = {
3827 		.type = VCAP_FIELD_U32,
3828 		.offset = 66,
3829 		.width = 2,
3830 	},
3831 	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
3832 		.type = VCAP_FIELD_BIT,
3833 		.offset = 68,
3834 		.width = 1,
3835 	},
3836 	[VCAP_AF_ISDX_VAL] = {
3837 		.type = VCAP_FIELD_U32,
3838 		.offset = 69,
3839 		.width = 12,
3840 	},
3841 	[VCAP_AF_RT_SEL] = {
3842 		.type = VCAP_FIELD_U32,
3843 		.offset = 81,
3844 		.width = 2,
3845 	},
3846 	[VCAP_AF_LPM_AFFIX_ENA] = {
3847 		.type = VCAP_FIELD_BIT,
3848 		.offset = 83,
3849 		.width = 1,
3850 	},
3851 	[VCAP_AF_LPM_AFFIX_VAL] = {
3852 		.type = VCAP_FIELD_U32,
3853 		.offset = 84,
3854 		.width = 10,
3855 	},
3856 	[VCAP_AF_RLEG_DMAC_CHK_DIS] = {
3857 		.type = VCAP_FIELD_BIT,
3858 		.offset = 94,
3859 		.width = 1,
3860 	},
3861 	[VCAP_AF_TTL_DECR_DIS] = {
3862 		.type = VCAP_FIELD_BIT,
3863 		.offset = 95,
3864 		.width = 1,
3865 	},
3866 	[VCAP_AF_L3_MAC_UPDATE_DIS] = {
3867 		.type = VCAP_FIELD_BIT,
3868 		.offset = 96,
3869 		.width = 1,
3870 	},
3871 	[VCAP_AF_FWD_DIS] = {
3872 		.type = VCAP_FIELD_BIT,
3873 		.offset = 97,
3874 		.width = 1,
3875 	},
3876 	[VCAP_AF_CPU_ENA] = {
3877 		.type = VCAP_FIELD_BIT,
3878 		.offset = 98,
3879 		.width = 1,
3880 	},
3881 	[VCAP_AF_CPU_Q] = {
3882 		.type = VCAP_FIELD_U32,
3883 		.offset = 99,
3884 		.width = 3,
3885 	},
3886 	[VCAP_AF_MIP_SEL] = {
3887 		.type = VCAP_FIELD_U32,
3888 		.offset = 102,
3889 		.width = 2,
3890 	},
3891 	[VCAP_AF_OAM_Y1731_SEL] = {
3892 		.type = VCAP_FIELD_U32,
3893 		.offset = 104,
3894 		.width = 3,
3895 	},
3896 	[VCAP_AF_OAM_TWAMP_ENA] = {
3897 		.type = VCAP_FIELD_BIT,
3898 		.offset = 107,
3899 		.width = 1,
3900 	},
3901 	[VCAP_AF_OAM_IP_BFD_ENA] = {
3902 		.type = VCAP_FIELD_BIT,
3903 		.offset = 108,
3904 		.width = 1,
3905 	},
3906 	[VCAP_AF_PAG_OVERRIDE_MASK] = {
3907 		.type = VCAP_FIELD_U32,
3908 		.offset = 109,
3909 		.width = 8,
3910 	},
3911 	[VCAP_AF_PAG_VAL] = {
3912 		.type = VCAP_FIELD_U32,
3913 		.offset = 117,
3914 		.width = 8,
3915 	},
3916 	[VCAP_AF_S2_KEY_SEL_ENA] = {
3917 		.type = VCAP_FIELD_BIT,
3918 		.offset = 125,
3919 		.width = 1,
3920 	},
3921 	[VCAP_AF_S2_KEY_SEL_IDX] = {
3922 		.type = VCAP_FIELD_U32,
3923 		.offset = 126,
3924 		.width = 6,
3925 	},
3926 	[VCAP_AF_INJ_MASQ_ENA] = {
3927 		.type = VCAP_FIELD_BIT,
3928 		.offset = 132,
3929 		.width = 1,
3930 	},
3931 	[VCAP_AF_INJ_MASQ_PORT] = {
3932 		.type = VCAP_FIELD_U32,
3933 		.offset = 133,
3934 		.width = 7,
3935 	},
3936 	[VCAP_AF_LPORT_ENA] = {
3937 		.type = VCAP_FIELD_BIT,
3938 		.offset = 140,
3939 		.width = 1,
3940 	},
3941 	[VCAP_AF_INJ_MASQ_LPORT] = {
3942 		.type = VCAP_FIELD_U32,
3943 		.offset = 141,
3944 		.width = 7,
3945 	},
3946 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
3947 		.type = VCAP_FIELD_U32,
3948 		.offset = 148,
3949 		.width = 2,
3950 	},
3951 	[VCAP_AF_PIPELINE_ACT_SEL] = {
3952 		.type = VCAP_FIELD_BIT,
3953 		.offset = 150,
3954 		.width = 1,
3955 	},
3956 	[VCAP_AF_PIPELINE_PT] = {
3957 		.type = VCAP_FIELD_U32,
3958 		.offset = 151,
3959 		.width = 5,
3960 	},
3961 	[VCAP_AF_NXT_KEY_TYPE] = {
3962 		.type = VCAP_FIELD_U32,
3963 		.offset = 156,
3964 		.width = 5,
3965 	},
3966 	[VCAP_AF_NXT_NORM_W16_OFFSET] = {
3967 		.type = VCAP_FIELD_U32,
3968 		.offset = 161,
3969 		.width = 5,
3970 	},
3971 	[VCAP_AF_NXT_OFFSET_FROM_TYPE] = {
3972 		.type = VCAP_FIELD_U32,
3973 		.offset = 166,
3974 		.width = 2,
3975 	},
3976 	[VCAP_AF_NXT_TYPE_AFTER_OFFSET] = {
3977 		.type = VCAP_FIELD_U32,
3978 		.offset = 168,
3979 		.width = 2,
3980 	},
3981 	[VCAP_AF_NXT_NORMALIZE] = {
3982 		.type = VCAP_FIELD_BIT,
3983 		.offset = 170,
3984 		.width = 1,
3985 	},
3986 	[VCAP_AF_NXT_IDX_CTRL] = {
3987 		.type = VCAP_FIELD_U32,
3988 		.offset = 171,
3989 		.width = 3,
3990 	},
3991 	[VCAP_AF_NXT_IDX] = {
3992 		.type = VCAP_FIELD_U32,
3993 		.offset = 174,
3994 		.width = 12,
3995 	},
3996 };
3997 
3998 static const struct vcap_field is0_full_actionfield[] = {
3999 	[VCAP_AF_DSCP_ENA] = {
4000 		.type = VCAP_FIELD_BIT,
4001 		.offset = 0,
4002 		.width = 1,
4003 	},
4004 	[VCAP_AF_DSCP_VAL] = {
4005 		.type = VCAP_FIELD_U32,
4006 		.offset = 1,
4007 		.width = 6,
4008 	},
4009 	[VCAP_AF_COSID_ENA] = {
4010 		.type = VCAP_FIELD_BIT,
4011 		.offset = 7,
4012 		.width = 1,
4013 	},
4014 	[VCAP_AF_COSID_VAL] = {
4015 		.type = VCAP_FIELD_U32,
4016 		.offset = 8,
4017 		.width = 3,
4018 	},
4019 	[VCAP_AF_QOS_ENA] = {
4020 		.type = VCAP_FIELD_BIT,
4021 		.offset = 11,
4022 		.width = 1,
4023 	},
4024 	[VCAP_AF_QOS_VAL] = {
4025 		.type = VCAP_FIELD_U32,
4026 		.offset = 12,
4027 		.width = 3,
4028 	},
4029 	[VCAP_AF_DP_ENA] = {
4030 		.type = VCAP_FIELD_BIT,
4031 		.offset = 15,
4032 		.width = 1,
4033 	},
4034 	[VCAP_AF_DP_VAL] = {
4035 		.type = VCAP_FIELD_U32,
4036 		.offset = 16,
4037 		.width = 2,
4038 	},
4039 	[VCAP_AF_DEI_ENA] = {
4040 		.type = VCAP_FIELD_BIT,
4041 		.offset = 18,
4042 		.width = 1,
4043 	},
4044 	[VCAP_AF_DEI_VAL] = {
4045 		.type = VCAP_FIELD_BIT,
4046 		.offset = 19,
4047 		.width = 1,
4048 	},
4049 	[VCAP_AF_PCP_ENA] = {
4050 		.type = VCAP_FIELD_BIT,
4051 		.offset = 20,
4052 		.width = 1,
4053 	},
4054 	[VCAP_AF_PCP_VAL] = {
4055 		.type = VCAP_FIELD_U32,
4056 		.offset = 21,
4057 		.width = 3,
4058 	},
4059 	[VCAP_AF_MAP_LOOKUP_SEL] = {
4060 		.type = VCAP_FIELD_U32,
4061 		.offset = 24,
4062 		.width = 2,
4063 	},
4064 	[VCAP_AF_MAP_KEY] = {
4065 		.type = VCAP_FIELD_U32,
4066 		.offset = 26,
4067 		.width = 3,
4068 	},
4069 	[VCAP_AF_MAP_IDX] = {
4070 		.type = VCAP_FIELD_U32,
4071 		.offset = 29,
4072 		.width = 9,
4073 	},
4074 	[VCAP_AF_CLS_VID_SEL] = {
4075 		.type = VCAP_FIELD_U32,
4076 		.offset = 38,
4077 		.width = 3,
4078 	},
4079 	[VCAP_AF_GVID_ADD_REPLACE_SEL] = {
4080 		.type = VCAP_FIELD_U32,
4081 		.offset = 41,
4082 		.width = 3,
4083 	},
4084 	[VCAP_AF_VID_VAL] = {
4085 		.type = VCAP_FIELD_U32,
4086 		.offset = 44,
4087 		.width = 13,
4088 	},
4089 	[VCAP_AF_VLAN_POP_CNT_ENA] = {
4090 		.type = VCAP_FIELD_BIT,
4091 		.offset = 57,
4092 		.width = 1,
4093 	},
4094 	[VCAP_AF_VLAN_POP_CNT] = {
4095 		.type = VCAP_FIELD_U32,
4096 		.offset = 58,
4097 		.width = 2,
4098 	},
4099 	[VCAP_AF_VLAN_PUSH_CNT_ENA] = {
4100 		.type = VCAP_FIELD_BIT,
4101 		.offset = 60,
4102 		.width = 1,
4103 	},
4104 	[VCAP_AF_VLAN_PUSH_CNT] = {
4105 		.type = VCAP_FIELD_U32,
4106 		.offset = 61,
4107 		.width = 2,
4108 	},
4109 	[VCAP_AF_TPID_SEL] = {
4110 		.type = VCAP_FIELD_U32,
4111 		.offset = 63,
4112 		.width = 2,
4113 	},
4114 	[VCAP_AF_VLAN_WAS_TAGGED] = {
4115 		.type = VCAP_FIELD_U32,
4116 		.offset = 65,
4117 		.width = 2,
4118 	},
4119 	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
4120 		.type = VCAP_FIELD_BIT,
4121 		.offset = 67,
4122 		.width = 1,
4123 	},
4124 	[VCAP_AF_ISDX_VAL] = {
4125 		.type = VCAP_FIELD_U32,
4126 		.offset = 68,
4127 		.width = 12,
4128 	},
4129 	[VCAP_AF_MASK_MODE] = {
4130 		.type = VCAP_FIELD_U32,
4131 		.offset = 80,
4132 		.width = 3,
4133 	},
4134 	[VCAP_AF_PORT_MASK] = {
4135 		.type = VCAP_FIELD_U72,
4136 		.offset = 83,
4137 		.width = 65,
4138 	},
4139 	[VCAP_AF_RT_SEL] = {
4140 		.type = VCAP_FIELD_U32,
4141 		.offset = 148,
4142 		.width = 2,
4143 	},
4144 	[VCAP_AF_LPM_AFFIX_ENA] = {
4145 		.type = VCAP_FIELD_BIT,
4146 		.offset = 150,
4147 		.width = 1,
4148 	},
4149 	[VCAP_AF_LPM_AFFIX_VAL] = {
4150 		.type = VCAP_FIELD_U32,
4151 		.offset = 151,
4152 		.width = 10,
4153 	},
4154 	[VCAP_AF_RLEG_DMAC_CHK_DIS] = {
4155 		.type = VCAP_FIELD_BIT,
4156 		.offset = 161,
4157 		.width = 1,
4158 	},
4159 	[VCAP_AF_TTL_DECR_DIS] = {
4160 		.type = VCAP_FIELD_BIT,
4161 		.offset = 162,
4162 		.width = 1,
4163 	},
4164 	[VCAP_AF_L3_MAC_UPDATE_DIS] = {
4165 		.type = VCAP_FIELD_BIT,
4166 		.offset = 163,
4167 		.width = 1,
4168 	},
4169 	[VCAP_AF_CPU_ENA] = {
4170 		.type = VCAP_FIELD_BIT,
4171 		.offset = 164,
4172 		.width = 1,
4173 	},
4174 	[VCAP_AF_CPU_Q] = {
4175 		.type = VCAP_FIELD_U32,
4176 		.offset = 165,
4177 		.width = 3,
4178 	},
4179 	[VCAP_AF_MIP_SEL] = {
4180 		.type = VCAP_FIELD_U32,
4181 		.offset = 168,
4182 		.width = 2,
4183 	},
4184 	[VCAP_AF_OAM_Y1731_SEL] = {
4185 		.type = VCAP_FIELD_U32,
4186 		.offset = 170,
4187 		.width = 3,
4188 	},
4189 	[VCAP_AF_OAM_TWAMP_ENA] = {
4190 		.type = VCAP_FIELD_BIT,
4191 		.offset = 173,
4192 		.width = 1,
4193 	},
4194 	[VCAP_AF_OAM_IP_BFD_ENA] = {
4195 		.type = VCAP_FIELD_BIT,
4196 		.offset = 174,
4197 		.width = 1,
4198 	},
4199 	[VCAP_AF_RSVD_LBL_VAL] = {
4200 		.type = VCAP_FIELD_U32,
4201 		.offset = 175,
4202 		.width = 4,
4203 	},
4204 	[VCAP_AF_TC_LABEL] = {
4205 		.type = VCAP_FIELD_U32,
4206 		.offset = 179,
4207 		.width = 3,
4208 	},
4209 	[VCAP_AF_TTL_LABEL] = {
4210 		.type = VCAP_FIELD_U32,
4211 		.offset = 182,
4212 		.width = 3,
4213 	},
4214 	[VCAP_AF_NUM_VLD_LABELS] = {
4215 		.type = VCAP_FIELD_U32,
4216 		.offset = 185,
4217 		.width = 2,
4218 	},
4219 	[VCAP_AF_FWD_TYPE] = {
4220 		.type = VCAP_FIELD_U32,
4221 		.offset = 187,
4222 		.width = 3,
4223 	},
4224 	[VCAP_AF_MPLS_OAM_TYPE] = {
4225 		.type = VCAP_FIELD_U32,
4226 		.offset = 190,
4227 		.width = 3,
4228 	},
4229 	[VCAP_AF_MPLS_MEP_ENA] = {
4230 		.type = VCAP_FIELD_BIT,
4231 		.offset = 193,
4232 		.width = 1,
4233 	},
4234 	[VCAP_AF_MPLS_MIP_ENA] = {
4235 		.type = VCAP_FIELD_BIT,
4236 		.offset = 194,
4237 		.width = 1,
4238 	},
4239 	[VCAP_AF_MPLS_OAM_FLAVOR] = {
4240 		.type = VCAP_FIELD_BIT,
4241 		.offset = 195,
4242 		.width = 1,
4243 	},
4244 	[VCAP_AF_MPLS_IP_CTRL_ENA] = {
4245 		.type = VCAP_FIELD_BIT,
4246 		.offset = 196,
4247 		.width = 1,
4248 	},
4249 	[VCAP_AF_CUSTOM_ACE_ENA] = {
4250 		.type = VCAP_FIELD_U32,
4251 		.offset = 197,
4252 		.width = 5,
4253 	},
4254 	[VCAP_AF_CUSTOM_ACE_OFFSET] = {
4255 		.type = VCAP_FIELD_U32,
4256 		.offset = 202,
4257 		.width = 2,
4258 	},
4259 	[VCAP_AF_PAG_OVERRIDE_MASK] = {
4260 		.type = VCAP_FIELD_U32,
4261 		.offset = 204,
4262 		.width = 8,
4263 	},
4264 	[VCAP_AF_PAG_VAL] = {
4265 		.type = VCAP_FIELD_U32,
4266 		.offset = 212,
4267 		.width = 8,
4268 	},
4269 	[VCAP_AF_S2_KEY_SEL_ENA] = {
4270 		.type = VCAP_FIELD_BIT,
4271 		.offset = 220,
4272 		.width = 1,
4273 	},
4274 	[VCAP_AF_S2_KEY_SEL_IDX] = {
4275 		.type = VCAP_FIELD_U32,
4276 		.offset = 221,
4277 		.width = 6,
4278 	},
4279 	[VCAP_AF_INJ_MASQ_ENA] = {
4280 		.type = VCAP_FIELD_BIT,
4281 		.offset = 227,
4282 		.width = 1,
4283 	},
4284 	[VCAP_AF_INJ_MASQ_PORT] = {
4285 		.type = VCAP_FIELD_U32,
4286 		.offset = 228,
4287 		.width = 7,
4288 	},
4289 	[VCAP_AF_LPORT_ENA] = {
4290 		.type = VCAP_FIELD_BIT,
4291 		.offset = 235,
4292 		.width = 1,
4293 	},
4294 	[VCAP_AF_INJ_MASQ_LPORT] = {
4295 		.type = VCAP_FIELD_U32,
4296 		.offset = 236,
4297 		.width = 7,
4298 	},
4299 	[VCAP_AF_MATCH_ID] = {
4300 		.type = VCAP_FIELD_U32,
4301 		.offset = 243,
4302 		.width = 16,
4303 	},
4304 	[VCAP_AF_MATCH_ID_MASK] = {
4305 		.type = VCAP_FIELD_U32,
4306 		.offset = 259,
4307 		.width = 16,
4308 	},
4309 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
4310 		.type = VCAP_FIELD_U32,
4311 		.offset = 275,
4312 		.width = 2,
4313 	},
4314 	[VCAP_AF_PIPELINE_ACT_SEL] = {
4315 		.type = VCAP_FIELD_BIT,
4316 		.offset = 277,
4317 		.width = 1,
4318 	},
4319 	[VCAP_AF_PIPELINE_PT] = {
4320 		.type = VCAP_FIELD_U32,
4321 		.offset = 278,
4322 		.width = 5,
4323 	},
4324 	[VCAP_AF_NXT_KEY_TYPE] = {
4325 		.type = VCAP_FIELD_U32,
4326 		.offset = 283,
4327 		.width = 5,
4328 	},
4329 	[VCAP_AF_NXT_NORM_W16_OFFSET] = {
4330 		.type = VCAP_FIELD_U32,
4331 		.offset = 288,
4332 		.width = 5,
4333 	},
4334 	[VCAP_AF_NXT_OFFSET_FROM_TYPE] = {
4335 		.type = VCAP_FIELD_U32,
4336 		.offset = 293,
4337 		.width = 2,
4338 	},
4339 	[VCAP_AF_NXT_TYPE_AFTER_OFFSET] = {
4340 		.type = VCAP_FIELD_U32,
4341 		.offset = 295,
4342 		.width = 2,
4343 	},
4344 	[VCAP_AF_NXT_NORMALIZE] = {
4345 		.type = VCAP_FIELD_BIT,
4346 		.offset = 297,
4347 		.width = 1,
4348 	},
4349 	[VCAP_AF_NXT_IDX_CTRL] = {
4350 		.type = VCAP_FIELD_U32,
4351 		.offset = 298,
4352 		.width = 3,
4353 	},
4354 	[VCAP_AF_NXT_IDX] = {
4355 		.type = VCAP_FIELD_U32,
4356 		.offset = 301,
4357 		.width = 12,
4358 	},
4359 };
4360 
4361 static const struct vcap_field is0_class_reduced_actionfield[] = {
4362 	[VCAP_AF_TYPE] = {
4363 		.type = VCAP_FIELD_BIT,
4364 		.offset = 0,
4365 		.width = 1,
4366 	},
4367 	[VCAP_AF_COSID_ENA] = {
4368 		.type = VCAP_FIELD_BIT,
4369 		.offset = 1,
4370 		.width = 1,
4371 	},
4372 	[VCAP_AF_COSID_VAL] = {
4373 		.type = VCAP_FIELD_U32,
4374 		.offset = 2,
4375 		.width = 3,
4376 	},
4377 	[VCAP_AF_QOS_ENA] = {
4378 		.type = VCAP_FIELD_BIT,
4379 		.offset = 5,
4380 		.width = 1,
4381 	},
4382 	[VCAP_AF_QOS_VAL] = {
4383 		.type = VCAP_FIELD_U32,
4384 		.offset = 6,
4385 		.width = 3,
4386 	},
4387 	[VCAP_AF_DP_ENA] = {
4388 		.type = VCAP_FIELD_BIT,
4389 		.offset = 9,
4390 		.width = 1,
4391 	},
4392 	[VCAP_AF_DP_VAL] = {
4393 		.type = VCAP_FIELD_U32,
4394 		.offset = 10,
4395 		.width = 2,
4396 	},
4397 	[VCAP_AF_MAP_LOOKUP_SEL] = {
4398 		.type = VCAP_FIELD_U32,
4399 		.offset = 12,
4400 		.width = 2,
4401 	},
4402 	[VCAP_AF_MAP_KEY] = {
4403 		.type = VCAP_FIELD_U32,
4404 		.offset = 14,
4405 		.width = 3,
4406 	},
4407 	[VCAP_AF_CLS_VID_SEL] = {
4408 		.type = VCAP_FIELD_U32,
4409 		.offset = 17,
4410 		.width = 3,
4411 	},
4412 	[VCAP_AF_GVID_ADD_REPLACE_SEL] = {
4413 		.type = VCAP_FIELD_U32,
4414 		.offset = 20,
4415 		.width = 3,
4416 	},
4417 	[VCAP_AF_VID_VAL] = {
4418 		.type = VCAP_FIELD_U32,
4419 		.offset = 23,
4420 		.width = 13,
4421 	},
4422 	[VCAP_AF_VLAN_POP_CNT_ENA] = {
4423 		.type = VCAP_FIELD_BIT,
4424 		.offset = 36,
4425 		.width = 1,
4426 	},
4427 	[VCAP_AF_VLAN_POP_CNT] = {
4428 		.type = VCAP_FIELD_U32,
4429 		.offset = 37,
4430 		.width = 2,
4431 	},
4432 	[VCAP_AF_VLAN_PUSH_CNT_ENA] = {
4433 		.type = VCAP_FIELD_BIT,
4434 		.offset = 39,
4435 		.width = 1,
4436 	},
4437 	[VCAP_AF_VLAN_PUSH_CNT] = {
4438 		.type = VCAP_FIELD_U32,
4439 		.offset = 40,
4440 		.width = 2,
4441 	},
4442 	[VCAP_AF_TPID_SEL] = {
4443 		.type = VCAP_FIELD_U32,
4444 		.offset = 42,
4445 		.width = 2,
4446 	},
4447 	[VCAP_AF_VLAN_WAS_TAGGED] = {
4448 		.type = VCAP_FIELD_U32,
4449 		.offset = 44,
4450 		.width = 2,
4451 	},
4452 	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
4453 		.type = VCAP_FIELD_BIT,
4454 		.offset = 46,
4455 		.width = 1,
4456 	},
4457 	[VCAP_AF_ISDX_VAL] = {
4458 		.type = VCAP_FIELD_U32,
4459 		.offset = 47,
4460 		.width = 12,
4461 	},
4462 	[VCAP_AF_FWD_DIS] = {
4463 		.type = VCAP_FIELD_BIT,
4464 		.offset = 59,
4465 		.width = 1,
4466 	},
4467 	[VCAP_AF_CPU_ENA] = {
4468 		.type = VCAP_FIELD_BIT,
4469 		.offset = 60,
4470 		.width = 1,
4471 	},
4472 	[VCAP_AF_CPU_Q] = {
4473 		.type = VCAP_FIELD_U32,
4474 		.offset = 61,
4475 		.width = 3,
4476 	},
4477 	[VCAP_AF_MIP_SEL] = {
4478 		.type = VCAP_FIELD_U32,
4479 		.offset = 64,
4480 		.width = 2,
4481 	},
4482 	[VCAP_AF_OAM_Y1731_SEL] = {
4483 		.type = VCAP_FIELD_U32,
4484 		.offset = 66,
4485 		.width = 3,
4486 	},
4487 	[VCAP_AF_LPORT_ENA] = {
4488 		.type = VCAP_FIELD_BIT,
4489 		.offset = 69,
4490 		.width = 1,
4491 	},
4492 	[VCAP_AF_INJ_MASQ_LPORT] = {
4493 		.type = VCAP_FIELD_U32,
4494 		.offset = 70,
4495 		.width = 7,
4496 	},
4497 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
4498 		.type = VCAP_FIELD_U32,
4499 		.offset = 77,
4500 		.width = 2,
4501 	},
4502 	[VCAP_AF_PIPELINE_ACT_SEL] = {
4503 		.type = VCAP_FIELD_BIT,
4504 		.offset = 79,
4505 		.width = 1,
4506 	},
4507 	[VCAP_AF_PIPELINE_PT] = {
4508 		.type = VCAP_FIELD_U32,
4509 		.offset = 80,
4510 		.width = 5,
4511 	},
4512 	[VCAP_AF_NXT_KEY_TYPE] = {
4513 		.type = VCAP_FIELD_U32,
4514 		.offset = 85,
4515 		.width = 5,
4516 	},
4517 	[VCAP_AF_NXT_IDX_CTRL] = {
4518 		.type = VCAP_FIELD_U32,
4519 		.offset = 90,
4520 		.width = 3,
4521 	},
4522 	[VCAP_AF_NXT_IDX] = {
4523 		.type = VCAP_FIELD_U32,
4524 		.offset = 93,
4525 		.width = 12,
4526 	},
4527 };
4528 
4529 static const struct vcap_field is2_base_type_actionfield[] = {
4530 	[VCAP_AF_IS_INNER_ACL] = {
4531 		.type = VCAP_FIELD_BIT,
4532 		.offset = 0,
4533 		.width = 1,
4534 	},
4535 	[VCAP_AF_PIPELINE_FORCE_ENA] = {
4536 		.type = VCAP_FIELD_BIT,
4537 		.offset = 1,
4538 		.width = 1,
4539 	},
4540 	[VCAP_AF_PIPELINE_PT] = {
4541 		.type = VCAP_FIELD_U32,
4542 		.offset = 2,
4543 		.width = 5,
4544 	},
4545 	[VCAP_AF_HIT_ME_ONCE] = {
4546 		.type = VCAP_FIELD_BIT,
4547 		.offset = 7,
4548 		.width = 1,
4549 	},
4550 	[VCAP_AF_INTR_ENA] = {
4551 		.type = VCAP_FIELD_BIT,
4552 		.offset = 8,
4553 		.width = 1,
4554 	},
4555 	[VCAP_AF_CPU_COPY_ENA] = {
4556 		.type = VCAP_FIELD_BIT,
4557 		.offset = 9,
4558 		.width = 1,
4559 	},
4560 	[VCAP_AF_CPU_QUEUE_NUM] = {
4561 		.type = VCAP_FIELD_U32,
4562 		.offset = 10,
4563 		.width = 3,
4564 	},
4565 	[VCAP_AF_CPU_DIS] = {
4566 		.type = VCAP_FIELD_BIT,
4567 		.offset = 13,
4568 		.width = 1,
4569 	},
4570 	[VCAP_AF_LRN_DIS] = {
4571 		.type = VCAP_FIELD_BIT,
4572 		.offset = 14,
4573 		.width = 1,
4574 	},
4575 	[VCAP_AF_RT_DIS] = {
4576 		.type = VCAP_FIELD_BIT,
4577 		.offset = 15,
4578 		.width = 1,
4579 	},
4580 	[VCAP_AF_POLICE_ENA] = {
4581 		.type = VCAP_FIELD_BIT,
4582 		.offset = 16,
4583 		.width = 1,
4584 	},
4585 	[VCAP_AF_POLICE_IDX] = {
4586 		.type = VCAP_FIELD_U32,
4587 		.offset = 17,
4588 		.width = 6,
4589 	},
4590 	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
4591 		.type = VCAP_FIELD_BIT,
4592 		.offset = 23,
4593 		.width = 1,
4594 	},
4595 	[VCAP_AF_DLB_OFFSET] = {
4596 		.type = VCAP_FIELD_U32,
4597 		.offset = 24,
4598 		.width = 3,
4599 	},
4600 	[VCAP_AF_MASK_MODE] = {
4601 		.type = VCAP_FIELD_U32,
4602 		.offset = 27,
4603 		.width = 3,
4604 	},
4605 	[VCAP_AF_PORT_MASK] = {
4606 		.type = VCAP_FIELD_U72,
4607 		.offset = 30,
4608 		.width = 68,
4609 	},
4610 	[VCAP_AF_RSDX_ENA] = {
4611 		.type = VCAP_FIELD_BIT,
4612 		.offset = 98,
4613 		.width = 1,
4614 	},
4615 	[VCAP_AF_RSDX_VAL] = {
4616 		.type = VCAP_FIELD_U32,
4617 		.offset = 99,
4618 		.width = 12,
4619 	},
4620 	[VCAP_AF_MIRROR_PROBE] = {
4621 		.type = VCAP_FIELD_U32,
4622 		.offset = 111,
4623 		.width = 2,
4624 	},
4625 	[VCAP_AF_REW_CMD] = {
4626 		.type = VCAP_FIELD_U32,
4627 		.offset = 113,
4628 		.width = 11,
4629 	},
4630 	[VCAP_AF_TTL_UPDATE_ENA] = {
4631 		.type = VCAP_FIELD_BIT,
4632 		.offset = 124,
4633 		.width = 1,
4634 	},
4635 	[VCAP_AF_SAM_SEQ_ENA] = {
4636 		.type = VCAP_FIELD_BIT,
4637 		.offset = 125,
4638 		.width = 1,
4639 	},
4640 	[VCAP_AF_TCP_UDP_ENA] = {
4641 		.type = VCAP_FIELD_BIT,
4642 		.offset = 126,
4643 		.width = 1,
4644 	},
4645 	[VCAP_AF_TCP_UDP_DPORT] = {
4646 		.type = VCAP_FIELD_U32,
4647 		.offset = 127,
4648 		.width = 16,
4649 	},
4650 	[VCAP_AF_TCP_UDP_SPORT] = {
4651 		.type = VCAP_FIELD_U32,
4652 		.offset = 143,
4653 		.width = 16,
4654 	},
4655 	[VCAP_AF_MATCH_ID] = {
4656 		.type = VCAP_FIELD_U32,
4657 		.offset = 159,
4658 		.width = 16,
4659 	},
4660 	[VCAP_AF_MATCH_ID_MASK] = {
4661 		.type = VCAP_FIELD_U32,
4662 		.offset = 175,
4663 		.width = 16,
4664 	},
4665 	[VCAP_AF_CNT_ID] = {
4666 		.type = VCAP_FIELD_U32,
4667 		.offset = 191,
4668 		.width = 12,
4669 	},
4670 	[VCAP_AF_SWAP_MAC_ENA] = {
4671 		.type = VCAP_FIELD_BIT,
4672 		.offset = 203,
4673 		.width = 1,
4674 	},
4675 	[VCAP_AF_ACL_RT_MODE] = {
4676 		.type = VCAP_FIELD_U32,
4677 		.offset = 204,
4678 		.width = 4,
4679 	},
4680 	[VCAP_AF_ACL_MAC] = {
4681 		.type = VCAP_FIELD_U48,
4682 		.offset = 208,
4683 		.width = 48,
4684 	},
4685 	[VCAP_AF_DMAC_OFFSET_ENA] = {
4686 		.type = VCAP_FIELD_BIT,
4687 		.offset = 256,
4688 		.width = 1,
4689 	},
4690 	[VCAP_AF_PTP_MASTER_SEL] = {
4691 		.type = VCAP_FIELD_U32,
4692 		.offset = 257,
4693 		.width = 2,
4694 	},
4695 	[VCAP_AF_LOG_MSG_INTERVAL] = {
4696 		.type = VCAP_FIELD_U32,
4697 		.offset = 259,
4698 		.width = 4,
4699 	},
4700 	[VCAP_AF_SIP_IDX] = {
4701 		.type = VCAP_FIELD_U32,
4702 		.offset = 263,
4703 		.width = 5,
4704 	},
4705 	[VCAP_AF_RLEG_STAT_IDX] = {
4706 		.type = VCAP_FIELD_U32,
4707 		.offset = 268,
4708 		.width = 3,
4709 	},
4710 	[VCAP_AF_IGR_ACL_ENA] = {
4711 		.type = VCAP_FIELD_BIT,
4712 		.offset = 271,
4713 		.width = 1,
4714 	},
4715 	[VCAP_AF_EGR_ACL_ENA] = {
4716 		.type = VCAP_FIELD_BIT,
4717 		.offset = 272,
4718 		.width = 1,
4719 	},
4720 };
4721 
4722 static const struct vcap_field es2_base_type_actionfield[] = {
4723 	[VCAP_AF_HIT_ME_ONCE] = {
4724 		.type = VCAP_FIELD_BIT,
4725 		.offset = 0,
4726 		.width = 1,
4727 	},
4728 	[VCAP_AF_INTR_ENA] = {
4729 		.type = VCAP_FIELD_BIT,
4730 		.offset = 1,
4731 		.width = 1,
4732 	},
4733 	[VCAP_AF_FWD_MODE] = {
4734 		.type = VCAP_FIELD_U32,
4735 		.offset = 2,
4736 		.width = 2,
4737 	},
4738 	[VCAP_AF_COPY_QUEUE_NUM] = {
4739 		.type = VCAP_FIELD_U32,
4740 		.offset = 4,
4741 		.width = 16,
4742 	},
4743 	[VCAP_AF_COPY_PORT_NUM] = {
4744 		.type = VCAP_FIELD_U32,
4745 		.offset = 20,
4746 		.width = 7,
4747 	},
4748 	[VCAP_AF_MIRROR_PROBE_ID] = {
4749 		.type = VCAP_FIELD_U32,
4750 		.offset = 27,
4751 		.width = 2,
4752 	},
4753 	[VCAP_AF_CPU_COPY_ENA] = {
4754 		.type = VCAP_FIELD_BIT,
4755 		.offset = 29,
4756 		.width = 1,
4757 	},
4758 	[VCAP_AF_CPU_QUEUE_NUM] = {
4759 		.type = VCAP_FIELD_U32,
4760 		.offset = 30,
4761 		.width = 3,
4762 	},
4763 	[VCAP_AF_POLICE_ENA] = {
4764 		.type = VCAP_FIELD_BIT,
4765 		.offset = 33,
4766 		.width = 1,
4767 	},
4768 	[VCAP_AF_POLICE_REMARK] = {
4769 		.type = VCAP_FIELD_BIT,
4770 		.offset = 34,
4771 		.width = 1,
4772 	},
4773 	[VCAP_AF_POLICE_IDX] = {
4774 		.type = VCAP_FIELD_U32,
4775 		.offset = 35,
4776 		.width = 6,
4777 	},
4778 	[VCAP_AF_ES2_REW_CMD] = {
4779 		.type = VCAP_FIELD_U32,
4780 		.offset = 41,
4781 		.width = 3,
4782 	},
4783 	[VCAP_AF_CNT_ID] = {
4784 		.type = VCAP_FIELD_U32,
4785 		.offset = 44,
4786 		.width = 11,
4787 	},
4788 	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
4789 		.type = VCAP_FIELD_BIT,
4790 		.offset = 55,
4791 		.width = 1,
4792 	},
4793 };
4794 
4795 /* actionfield_set */
4796 static const struct vcap_set is0_actionfield_set[] = {
4797 	[VCAP_AFS_MLBS] = {
4798 		.type_id = 0,
4799 		.sw_per_item = 2,
4800 		.sw_cnt = 6,
4801 	},
4802 	[VCAP_AFS_MLBS_REDUCED] = {
4803 		.type_id = 0,
4804 		.sw_per_item = 1,
4805 		.sw_cnt = 12,
4806 	},
4807 	[VCAP_AFS_CLASSIFICATION] = {
4808 		.type_id = 1,
4809 		.sw_per_item = 2,
4810 		.sw_cnt = 6,
4811 	},
4812 	[VCAP_AFS_FULL] = {
4813 		.type_id = -1,
4814 		.sw_per_item = 3,
4815 		.sw_cnt = 4,
4816 	},
4817 	[VCAP_AFS_CLASS_REDUCED] = {
4818 		.type_id = 1,
4819 		.sw_per_item = 1,
4820 		.sw_cnt = 12,
4821 	},
4822 };
4823 
4824 static const struct vcap_set is2_actionfield_set[] = {
4825 	[VCAP_AFS_BASE_TYPE] = {
4826 		.type_id = -1,
4827 		.sw_per_item = 3,
4828 		.sw_cnt = 4,
4829 	},
4830 };
4831 
4832 static const struct vcap_set es2_actionfield_set[] = {
4833 	[VCAP_AFS_BASE_TYPE] = {
4834 		.type_id = -1,
4835 		.sw_per_item = 3,
4836 		.sw_cnt = 4,
4837 	},
4838 };
4839 
4840 /* actionfield_set map */
4841 static const struct vcap_field *is0_actionfield_set_map[] = {
4842 	[VCAP_AFS_MLBS] = is0_mlbs_actionfield,
4843 	[VCAP_AFS_MLBS_REDUCED] = is0_mlbs_reduced_actionfield,
4844 	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,
4845 	[VCAP_AFS_FULL] = is0_full_actionfield,
4846 	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,
4847 };
4848 
4849 static const struct vcap_field *is2_actionfield_set_map[] = {
4850 	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
4851 };
4852 
4853 static const struct vcap_field *es2_actionfield_set_map[] = {
4854 	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
4855 };
4856 
4857 /* actionfield_set map size */
4858 static int is0_actionfield_set_map_size[] = {
4859 	[VCAP_AFS_MLBS] = ARRAY_SIZE(is0_mlbs_actionfield),
4860 	[VCAP_AFS_MLBS_REDUCED] = ARRAY_SIZE(is0_mlbs_reduced_actionfield),
4861 	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),
4862 	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),
4863 	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),
4864 };
4865 
4866 static int is2_actionfield_set_map_size[] = {
4867 	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
4868 };
4869 
4870 static int es2_actionfield_set_map_size[] = {
4871 	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
4872 };
4873 
4874 /* Type Groups */
4875 static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {
4876 	{
4877 		.offset = 0,
4878 		.width = 5,
4879 		.value = 16,
4880 	},
4881 	{
4882 		.offset = 52,
4883 		.width = 1,
4884 		.value = 0,
4885 	},
4886 	{
4887 		.offset = 104,
4888 		.width = 2,
4889 		.value = 0,
4890 	},
4891 	{
4892 		.offset = 156,
4893 		.width = 3,
4894 		.value = 0,
4895 	},
4896 	{
4897 		.offset = 208,
4898 		.width = 2,
4899 		.value = 0,
4900 	},
4901 	{
4902 		.offset = 260,
4903 		.width = 1,
4904 		.value = 0,
4905 	},
4906 	{
4907 		.offset = 312,
4908 		.width = 4,
4909 		.value = 0,
4910 	},
4911 	{
4912 		.offset = 364,
4913 		.width = 1,
4914 		.value = 0,
4915 	},
4916 	{
4917 		.offset = 416,
4918 		.width = 2,
4919 		.value = 0,
4920 	},
4921 	{
4922 		.offset = 468,
4923 		.width = 3,
4924 		.value = 0,
4925 	},
4926 	{
4927 		.offset = 520,
4928 		.width = 2,
4929 		.value = 0,
4930 	},
4931 	{
4932 		.offset = 572,
4933 		.width = 1,
4934 		.value = 0,
4935 	},
4936 	{}
4937 };
4938 
4939 static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {
4940 	{
4941 		.offset = 0,
4942 		.width = 4,
4943 		.value = 8,
4944 	},
4945 	{
4946 		.offset = 52,
4947 		.width = 1,
4948 		.value = 0,
4949 	},
4950 	{
4951 		.offset = 104,
4952 		.width = 2,
4953 		.value = 0,
4954 	},
4955 	{
4956 		.offset = 156,
4957 		.width = 3,
4958 		.value = 0,
4959 	},
4960 	{
4961 		.offset = 208,
4962 		.width = 2,
4963 		.value = 0,
4964 	},
4965 	{
4966 		.offset = 260,
4967 		.width = 1,
4968 		.value = 0,
4969 	},
4970 	{}
4971 };
4972 
4973 static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {
4974 	{
4975 		.offset = 0,
4976 		.width = 3,
4977 		.value = 4,
4978 	},
4979 	{
4980 		.offset = 52,
4981 		.width = 2,
4982 		.value = 0,
4983 	},
4984 	{
4985 		.offset = 104,
4986 		.width = 2,
4987 		.value = 0,
4988 	},
4989 	{}
4990 };
4991 
4992 static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {
4993 	{
4994 		.offset = 0,
4995 		.width = 2,
4996 		.value = 2,
4997 	},
4998 	{
4999 		.offset = 52,
5000 		.width = 1,
5001 		.value = 0,
5002 	},
5003 	{}
5004 };
5005 
5006 static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {
5007 	{}
5008 };
5009 
5010 static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {
5011 	{
5012 		.offset = 0,
5013 		.width = 3,
5014 		.value = 4,
5015 	},
5016 	{
5017 		.offset = 156,
5018 		.width = 1,
5019 		.value = 0,
5020 	},
5021 	{
5022 		.offset = 312,
5023 		.width = 2,
5024 		.value = 0,
5025 	},
5026 	{
5027 		.offset = 468,
5028 		.width = 1,
5029 		.value = 0,
5030 	},
5031 	{}
5032 };
5033 
5034 static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {
5035 	{
5036 		.offset = 0,
5037 		.width = 2,
5038 		.value = 2,
5039 	},
5040 	{
5041 		.offset = 156,
5042 		.width = 1,
5043 		.value = 0,
5044 	},
5045 	{}
5046 };
5047 
5048 static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {
5049 	{}
5050 };
5051 
5052 static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
5053 	{}
5054 };
5055 
5056 static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
5057 	{
5058 		.offset = 0,
5059 		.width = 3,
5060 		.value = 4,
5061 	},
5062 	{
5063 		.offset = 156,
5064 		.width = 1,
5065 		.value = 0,
5066 	},
5067 	{
5068 		.offset = 312,
5069 		.width = 2,
5070 		.value = 0,
5071 	},
5072 	{
5073 		.offset = 468,
5074 		.width = 1,
5075 		.value = 0,
5076 	},
5077 	{}
5078 };
5079 
5080 static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {
5081 	{
5082 		.offset = 0,
5083 		.width = 2,
5084 		.value = 2,
5085 	},
5086 	{
5087 		.offset = 156,
5088 		.width = 1,
5089 		.value = 0,
5090 	},
5091 	{}
5092 };
5093 
5094 static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {
5095 	{
5096 		.offset = 0,
5097 		.width = 1,
5098 		.value = 1,
5099 	},
5100 	{}
5101 };
5102 
5103 static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {
5104 	{}
5105 };
5106 
5107 static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {
5108 	[12] = is0_x12_keyfield_set_typegroups,
5109 	[6] = is0_x6_keyfield_set_typegroups,
5110 	[3] = is0_x3_keyfield_set_typegroups,
5111 	[2] = is0_x2_keyfield_set_typegroups,
5112 	[1] = is0_x1_keyfield_set_typegroups,
5113 	[13] = NULL,
5114 };
5115 
5116 static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
5117 	[12] = is2_x12_keyfield_set_typegroups,
5118 	[6] = is2_x6_keyfield_set_typegroups,
5119 	[3] = is2_x3_keyfield_set_typegroups,
5120 	[1] = is2_x1_keyfield_set_typegroups,
5121 	[13] = NULL,
5122 };
5123 
5124 static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
5125 	[12] = es2_x12_keyfield_set_typegroups,
5126 	[6] = es2_x6_keyfield_set_typegroups,
5127 	[3] = es2_x3_keyfield_set_typegroups,
5128 	[1] = es2_x1_keyfield_set_typegroups,
5129 	[13] = NULL,
5130 };
5131 
5132 static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {
5133 	{
5134 		.offset = 0,
5135 		.width = 3,
5136 		.value = 4,
5137 	},
5138 	{
5139 		.offset = 110,
5140 		.width = 2,
5141 		.value = 0,
5142 	},
5143 	{
5144 		.offset = 220,
5145 		.width = 2,
5146 		.value = 0,
5147 	},
5148 	{}
5149 };
5150 
5151 static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {
5152 	{
5153 		.offset = 0,
5154 		.width = 2,
5155 		.value = 2,
5156 	},
5157 	{
5158 		.offset = 110,
5159 		.width = 1,
5160 		.value = 0,
5161 	},
5162 	{}
5163 };
5164 
5165 static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {
5166 	{
5167 		.offset = 0,
5168 		.width = 1,
5169 		.value = 1,
5170 	},
5171 	{}
5172 };
5173 
5174 static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {
5175 	{
5176 		.offset = 0,
5177 		.width = 2,
5178 		.value = 2,
5179 	},
5180 	{
5181 		.offset = 110,
5182 		.width = 1,
5183 		.value = 0,
5184 	},
5185 	{
5186 		.offset = 220,
5187 		.width = 1,
5188 		.value = 0,
5189 	},
5190 	{}
5191 };
5192 
5193 static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
5194 	{}
5195 };
5196 
5197 static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
5198 	{
5199 		.offset = 0,
5200 		.width = 2,
5201 		.value = 2,
5202 	},
5203 	{
5204 		.offset = 21,
5205 		.width = 1,
5206 		.value = 0,
5207 	},
5208 	{
5209 		.offset = 42,
5210 		.width = 1,
5211 		.value = 0,
5212 	},
5213 	{}
5214 };
5215 
5216 static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {
5217 	{}
5218 };
5219 
5220 static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {
5221 	[3] = is0_x3_actionfield_set_typegroups,
5222 	[2] = is0_x2_actionfield_set_typegroups,
5223 	[1] = is0_x1_actionfield_set_typegroups,
5224 	[13] = NULL,
5225 };
5226 
5227 static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
5228 	[3] = is2_x3_actionfield_set_typegroups,
5229 	[1] = is2_x1_actionfield_set_typegroups,
5230 	[13] = NULL,
5231 };
5232 
5233 static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
5234 	[3] = es2_x3_actionfield_set_typegroups,
5235 	[1] = es2_x1_actionfield_set_typegroups,
5236 	[13] = NULL,
5237 };
5238 
5239 /* Keyfieldset names */
5240 static const char * const vcap_keyfield_set_names[] = {
5241 	[VCAP_KFS_NO_VALUE]                      =  "(None)",
5242 	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",
5243 	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",
5244 	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",
5245 	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",
5246 	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",
5247 	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",
5248 	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",
5249 	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",
5250 	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",
5251 	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",
5252 	[VCAP_KFS_MLL]                           =  "VCAP_KFS_MLL",
5253 	[VCAP_KFS_NORMAL]                        =  "VCAP_KFS_NORMAL",
5254 	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",
5255 	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",
5256 	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",
5257 	[VCAP_KFS_TRI_VID]                       =  "VCAP_KFS_TRI_VID",
5258 };
5259 
5260 /* Actionfieldset names */
5261 static const char * const vcap_actionfield_set_names[] = {
5262 	[VCAP_AFS_NO_VALUE]                      =  "(None)",
5263 	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",
5264 	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",
5265 	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",
5266 	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",
5267 	[VCAP_AFS_MLBS]                          =  "VCAP_AFS_MLBS",
5268 	[VCAP_AFS_MLBS_REDUCED]                  =  "VCAP_AFS_MLBS_REDUCED",
5269 };
5270 
5271 /* Keyfield names */
5272 static const char * const vcap_keyfield_names[] = {
5273 	[VCAP_KF_NO_VALUE]                       =  "(None)",
5274 	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",
5275 	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",
5276 	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",
5277 	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",
5278 	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",
5279 	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",
5280 	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",
5281 	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",
5282 	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",
5283 	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",
5284 	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",
5285 	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",
5286 	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",
5287 	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",
5288 	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",
5289 	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",
5290 	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",
5291 	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",
5292 	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",
5293 	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",
5294 	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",
5295 	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",
5296 	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",
5297 	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",
5298 	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",
5299 	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",
5300 	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",
5301 	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",
5302 	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",
5303 	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",
5304 	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",
5305 	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",
5306 	[VCAP_KF_DST_ENTRY]                      =  "DST_ENTRY",
5307 	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",
5308 	[VCAP_KF_ETYPE]                          =  "ETYPE",
5309 	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",
5310 	[VCAP_KF_ETYPE_MPLS]                     =  "ETYPE_MPLS",
5311 	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",
5312 	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",
5313 	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",
5314 	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",
5315 	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",
5316 	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",
5317 	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",
5318 	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",
5319 	[VCAP_KF_IP4_IS]                         =  "IP4_IS",
5320 	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",
5321 	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",
5322 	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",
5323 	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",
5324 	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",
5325 	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",
5326 	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",
5327 	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",
5328 	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",
5329 	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",
5330 	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",
5331 	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",
5332 	[VCAP_KF_L3_DMAC_DIP_MATCH]              =  "L3_DMAC_DIP_MATCH",
5333 	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",
5334 	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",
5335 	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",
5336 	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",
5337 	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",
5338 	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",
5339 	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",
5340 	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",
5341 	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",
5342 	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",
5343 	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",
5344 	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",
5345 	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",
5346 	[VCAP_KF_L3_SMAC_SIP_MATCH]              =  "L3_SMAC_SIP_MATCH",
5347 	[VCAP_KF_L3_TOS]                         =  "L3_TOS",
5348 	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",
5349 	[VCAP_KF_L4_ACK]                         =  "L4_ACK",
5350 	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",
5351 	[VCAP_KF_L4_FIN]                         =  "L4_FIN",
5352 	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",
5353 	[VCAP_KF_L4_PSH]                         =  "L4_PSH",
5354 	[VCAP_KF_L4_RNG]                         =  "L4_RNG",
5355 	[VCAP_KF_L4_RST]                         =  "L4_RST",
5356 	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",
5357 	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",
5358 	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",
5359 	[VCAP_KF_L4_SYN]                         =  "L4_SYN",
5360 	[VCAP_KF_L4_URG]                         =  "L4_URG",
5361 	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",
5362 	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",
5363 	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",
5364 	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",
5365 	[VCAP_KF_MIRROR_ENA]                     =  "MIRROR_ENA",
5366 	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",
5367 	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",
5368 	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",
5369 	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",
5370 	[VCAP_KF_TCP_IS]                         =  "TCP_IS",
5371 	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",
5372 	[VCAP_KF_TYPE]                           =  "TYPE",
5373 };
5374 
5375 /* Actionfield names */
5376 static const char * const vcap_actionfield_names[] = {
5377 	[VCAP_AF_NO_VALUE]                       =  "(None)",
5378 	[VCAP_AF_ACL_MAC]                        =  "ACL_MAC",
5379 	[VCAP_AF_ACL_RT_MODE]                    =  "ACL_RT_MODE",
5380 	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",
5381 	[VCAP_AF_CNT_ID]                         =  "CNT_ID",
5382 	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",
5383 	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",
5384 	[VCAP_AF_COSID_ENA]                      =  "COSID_ENA",
5385 	[VCAP_AF_COSID_VAL]                      =  "COSID_VAL",
5386 	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",
5387 	[VCAP_AF_CPU_DIS]                        =  "CPU_DIS",
5388 	[VCAP_AF_CPU_ENA]                        =  "CPU_ENA",
5389 	[VCAP_AF_CPU_Q]                          =  "CPU_Q",
5390 	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",
5391 	[VCAP_AF_CUSTOM_ACE_ENA]                 =  "CUSTOM_ACE_ENA",
5392 	[VCAP_AF_CUSTOM_ACE_OFFSET]              =  "CUSTOM_ACE_OFFSET",
5393 	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",
5394 	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",
5395 	[VCAP_AF_DLB_OFFSET]                     =  "DLB_OFFSET",
5396 	[VCAP_AF_DMAC_OFFSET_ENA]                =  "DMAC_OFFSET_ENA",
5397 	[VCAP_AF_DP_ENA]                         =  "DP_ENA",
5398 	[VCAP_AF_DP_VAL]                         =  "DP_VAL",
5399 	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",
5400 	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",
5401 	[VCAP_AF_EGR_ACL_ENA]                    =  "EGR_ACL_ENA",
5402 	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",
5403 	[VCAP_AF_FWD_DIS]                        =  "FWD_DIS",
5404 	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",
5405 	[VCAP_AF_FWD_TYPE]                       =  "FWD_TYPE",
5406 	[VCAP_AF_GVID_ADD_REPLACE_SEL]           =  "GVID_ADD_REPLACE_SEL",
5407 	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",
5408 	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",
5409 	[VCAP_AF_IGR_ACL_ENA]                    =  "IGR_ACL_ENA",
5410 	[VCAP_AF_INJ_MASQ_ENA]                   =  "INJ_MASQ_ENA",
5411 	[VCAP_AF_INJ_MASQ_LPORT]                 =  "INJ_MASQ_LPORT",
5412 	[VCAP_AF_INJ_MASQ_PORT]                  =  "INJ_MASQ_PORT",
5413 	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",
5414 	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",
5415 	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",
5416 	[VCAP_AF_IS_INNER_ACL]                   =  "IS_INNER_ACL",
5417 	[VCAP_AF_L3_MAC_UPDATE_DIS]              =  "L3_MAC_UPDATE_DIS",
5418 	[VCAP_AF_LOG_MSG_INTERVAL]               =  "LOG_MSG_INTERVAL",
5419 	[VCAP_AF_LPM_AFFIX_ENA]                  =  "LPM_AFFIX_ENA",
5420 	[VCAP_AF_LPM_AFFIX_VAL]                  =  "LPM_AFFIX_VAL",
5421 	[VCAP_AF_LPORT_ENA]                      =  "LPORT_ENA",
5422 	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",
5423 	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",
5424 	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",
5425 	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",
5426 	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",
5427 	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",
5428 	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",
5429 	[VCAP_AF_MIP_SEL]                        =  "MIP_SEL",
5430 	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
5431 	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",
5432 	[VCAP_AF_MPLS_IP_CTRL_ENA]               =  "MPLS_IP_CTRL_ENA",
5433 	[VCAP_AF_MPLS_MEP_ENA]                   =  "MPLS_MEP_ENA",
5434 	[VCAP_AF_MPLS_MIP_ENA]                   =  "MPLS_MIP_ENA",
5435 	[VCAP_AF_MPLS_OAM_FLAVOR]                =  "MPLS_OAM_FLAVOR",
5436 	[VCAP_AF_MPLS_OAM_TYPE]                  =  "MPLS_OAM_TYPE",
5437 	[VCAP_AF_NUM_VLD_LABELS]                 =  "NUM_VLD_LABELS",
5438 	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",
5439 	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",
5440 	[VCAP_AF_NXT_KEY_TYPE]                   =  "NXT_KEY_TYPE",
5441 	[VCAP_AF_NXT_NORMALIZE]                  =  "NXT_NORMALIZE",
5442 	[VCAP_AF_NXT_NORM_W16_OFFSET]            =  "NXT_NORM_W16_OFFSET",
5443 	[VCAP_AF_NXT_NORM_W32_OFFSET]            =  "NXT_NORM_W32_OFFSET",
5444 	[VCAP_AF_NXT_OFFSET_FROM_TYPE]           =  "NXT_OFFSET_FROM_TYPE",
5445 	[VCAP_AF_NXT_TYPE_AFTER_OFFSET]          =  "NXT_TYPE_AFTER_OFFSET",
5446 	[VCAP_AF_OAM_IP_BFD_ENA]                 =  "OAM_IP_BFD_ENA",
5447 	[VCAP_AF_OAM_TWAMP_ENA]                  =  "OAM_TWAMP_ENA",
5448 	[VCAP_AF_OAM_Y1731_SEL]                  =  "OAM_Y1731_SEL",
5449 	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",
5450 	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",
5451 	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",
5452 	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",
5453 	[VCAP_AF_PIPELINE_ACT_SEL]               =  "PIPELINE_ACT_SEL",
5454 	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",
5455 	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",
5456 	[VCAP_AF_PIPELINE_PT_REDUCED]            =  "PIPELINE_PT_REDUCED",
5457 	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",
5458 	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",
5459 	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",
5460 	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",
5461 	[VCAP_AF_PTP_MASTER_SEL]                 =  "PTP_MASTER_SEL",
5462 	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",
5463 	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",
5464 	[VCAP_AF_REW_CMD]                        =  "REW_CMD",
5465 	[VCAP_AF_RLEG_DMAC_CHK_DIS]              =  "RLEG_DMAC_CHK_DIS",
5466 	[VCAP_AF_RLEG_STAT_IDX]                  =  "RLEG_STAT_IDX",
5467 	[VCAP_AF_RSDX_ENA]                       =  "RSDX_ENA",
5468 	[VCAP_AF_RSDX_VAL]                       =  "RSDX_VAL",
5469 	[VCAP_AF_RSVD_LBL_VAL]                   =  "RSVD_LBL_VAL",
5470 	[VCAP_AF_RT_DIS]                         =  "RT_DIS",
5471 	[VCAP_AF_RT_SEL]                         =  "RT_SEL",
5472 	[VCAP_AF_S2_KEY_SEL_ENA]                 =  "S2_KEY_SEL_ENA",
5473 	[VCAP_AF_S2_KEY_SEL_IDX]                 =  "S2_KEY_SEL_IDX",
5474 	[VCAP_AF_SAM_SEQ_ENA]                    =  "SAM_SEQ_ENA",
5475 	[VCAP_AF_SIP_IDX]                        =  "SIP_IDX",
5476 	[VCAP_AF_SWAP_MAC_ENA]                   =  "SWAP_MAC_ENA",
5477 	[VCAP_AF_TCP_UDP_DPORT]                  =  "TCP_UDP_DPORT",
5478 	[VCAP_AF_TCP_UDP_ENA]                    =  "TCP_UDP_ENA",
5479 	[VCAP_AF_TCP_UDP_SPORT]                  =  "TCP_UDP_SPORT",
5480 	[VCAP_AF_TC_ENA]                         =  "TC_ENA",
5481 	[VCAP_AF_TC_LABEL]                       =  "TC_LABEL",
5482 	[VCAP_AF_TPID_SEL]                       =  "TPID_SEL",
5483 	[VCAP_AF_TTL_DECR_DIS]                   =  "TTL_DECR_DIS",
5484 	[VCAP_AF_TTL_ENA]                        =  "TTL_ENA",
5485 	[VCAP_AF_TTL_LABEL]                      =  "TTL_LABEL",
5486 	[VCAP_AF_TTL_UPDATE_ENA]                 =  "TTL_UPDATE_ENA",
5487 	[VCAP_AF_TYPE]                           =  "TYPE",
5488 	[VCAP_AF_VID_VAL]                        =  "VID_VAL",
5489 	[VCAP_AF_VLAN_POP_CNT]                   =  "VLAN_POP_CNT",
5490 	[VCAP_AF_VLAN_POP_CNT_ENA]               =  "VLAN_POP_CNT_ENA",
5491 	[VCAP_AF_VLAN_PUSH_CNT]                  =  "VLAN_PUSH_CNT",
5492 	[VCAP_AF_VLAN_PUSH_CNT_ENA]              =  "VLAN_PUSH_CNT_ENA",
5493 	[VCAP_AF_VLAN_WAS_TAGGED]                =  "VLAN_WAS_TAGGED",
5494 };
5495 
5496 /* VCAPs */
5497 const struct vcap_info kunit_test_vcaps[] = {
5498 	[VCAP_TYPE_IS0] = {
5499 		.name = "is0",
5500 		.rows = 1024,
5501 		.sw_count = 12,
5502 		.sw_width = 52,
5503 		.sticky_width = 1,
5504 		.act_width = 110,
5505 		.default_cnt = 140,
5506 		.require_cnt_dis = 0,
5507 		.version = 1,
5508 		.keyfield_set = is0_keyfield_set,
5509 		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),
5510 		.actionfield_set = is0_actionfield_set,
5511 		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),
5512 		.keyfield_set_map = is0_keyfield_set_map,
5513 		.keyfield_set_map_size = is0_keyfield_set_map_size,
5514 		.actionfield_set_map = is0_actionfield_set_map,
5515 		.actionfield_set_map_size = is0_actionfield_set_map_size,
5516 		.keyfield_set_typegroups = is0_keyfield_set_typegroups,
5517 		.actionfield_set_typegroups = is0_actionfield_set_typegroups,
5518 	},
5519 	[VCAP_TYPE_IS2] = {
5520 		.name = "is2",
5521 		.rows = 256,
5522 		.sw_count = 12,
5523 		.sw_width = 52,
5524 		.sticky_width = 1,
5525 		.act_width = 110,
5526 		.default_cnt = 73,
5527 		.require_cnt_dis = 0,
5528 		.version = 1,
5529 		.keyfield_set = is2_keyfield_set,
5530 		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
5531 		.actionfield_set = is2_actionfield_set,
5532 		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
5533 		.keyfield_set_map = is2_keyfield_set_map,
5534 		.keyfield_set_map_size = is2_keyfield_set_map_size,
5535 		.actionfield_set_map = is2_actionfield_set_map,
5536 		.actionfield_set_map_size = is2_actionfield_set_map_size,
5537 		.keyfield_set_typegroups = is2_keyfield_set_typegroups,
5538 		.actionfield_set_typegroups = is2_actionfield_set_typegroups,
5539 	},
5540 	[VCAP_TYPE_ES2] = {
5541 		.name = "es2",
5542 		.rows = 1024,
5543 		.sw_count = 12,
5544 		.sw_width = 52,
5545 		.sticky_width = 1,
5546 		.act_width = 21,
5547 		.default_cnt = 74,
5548 		.require_cnt_dis = 0,
5549 		.version = 1,
5550 		.keyfield_set = es2_keyfield_set,
5551 		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),
5552 		.actionfield_set = es2_actionfield_set,
5553 		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),
5554 		.keyfield_set_map = es2_keyfield_set_map,
5555 		.keyfield_set_map_size = es2_keyfield_set_map_size,
5556 		.actionfield_set_map = es2_actionfield_set_map,
5557 		.actionfield_set_map_size = es2_actionfield_set_map_size,
5558 		.keyfield_set_typegroups = es2_keyfield_set_typegroups,
5559 		.actionfield_set_typegroups = es2_actionfield_set_typegroups,
5560 	},
5561 };
5562 
5563 const struct vcap_statistics kunit_test_vcap_stats = {
5564 	.name = "kunit_test",
5565 	.count = 3,
5566 	.keyfield_set_names = vcap_keyfield_set_names,
5567 	.actionfield_set_names = vcap_actionfield_set_names,
5568 	.keyfield_names = vcap_keyfield_names,
5569 	.actionfield_names = vcap_actionfield_names,
5570 };
5571