1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. 3 * Microchip VCAP API Test VCAP Model Data 4 */ 5 6 #include <linux/types.h> 7 #include <linux/kernel.h> 8 9 #include "vcap_api.h" 10 #include "vcap_model_kunit.h" 11 12 /* keyfields */ 13 static const struct vcap_field is0_ll_full_keyfield[] = { 14 [VCAP_KF_TYPE] = { 15 .type = VCAP_FIELD_U32, 16 .offset = 0, 17 .width = 2, 18 }, 19 [VCAP_KF_LOOKUP_FIRST_IS] = { 20 .type = VCAP_FIELD_BIT, 21 .offset = 2, 22 .width = 1, 23 }, 24 [VCAP_KF_IF_IGR_PORT] = { 25 .type = VCAP_FIELD_U32, 26 .offset = 3, 27 .width = 7, 28 }, 29 [VCAP_KF_8021Q_VLAN_TAGS] = { 30 .type = VCAP_FIELD_U32, 31 .offset = 10, 32 .width = 3, 33 }, 34 [VCAP_KF_8021Q_TPID0] = { 35 .type = VCAP_FIELD_U32, 36 .offset = 13, 37 .width = 3, 38 }, 39 [VCAP_KF_8021Q_PCP0] = { 40 .type = VCAP_FIELD_U32, 41 .offset = 16, 42 .width = 3, 43 }, 44 [VCAP_KF_8021Q_DEI0] = { 45 .type = VCAP_FIELD_BIT, 46 .offset = 19, 47 .width = 1, 48 }, 49 [VCAP_KF_8021Q_VID0] = { 50 .type = VCAP_FIELD_U32, 51 .offset = 20, 52 .width = 12, 53 }, 54 [VCAP_KF_8021Q_TPID1] = { 55 .type = VCAP_FIELD_U32, 56 .offset = 32, 57 .width = 3, 58 }, 59 [VCAP_KF_8021Q_PCP1] = { 60 .type = VCAP_FIELD_U32, 61 .offset = 35, 62 .width = 3, 63 }, 64 [VCAP_KF_8021Q_DEI1] = { 65 .type = VCAP_FIELD_BIT, 66 .offset = 38, 67 .width = 1, 68 }, 69 [VCAP_KF_8021Q_VID1] = { 70 .type = VCAP_FIELD_U32, 71 .offset = 39, 72 .width = 12, 73 }, 74 [VCAP_KF_8021Q_TPID2] = { 75 .type = VCAP_FIELD_U32, 76 .offset = 51, 77 .width = 3, 78 }, 79 [VCAP_KF_8021Q_PCP2] = { 80 .type = VCAP_FIELD_U32, 81 .offset = 54, 82 .width = 3, 83 }, 84 [VCAP_KF_8021Q_DEI2] = { 85 .type = VCAP_FIELD_BIT, 86 .offset = 57, 87 .width = 1, 88 }, 89 [VCAP_KF_8021Q_VID2] = { 90 .type = VCAP_FIELD_U32, 91 .offset = 58, 92 .width = 12, 93 }, 94 [VCAP_KF_L2_DMAC] = { 95 .type = VCAP_FIELD_U48, 96 .offset = 70, 97 .width = 48, 98 }, 99 [VCAP_KF_L2_SMAC] = { 100 .type = VCAP_FIELD_U48, 101 .offset = 118, 102 .width = 48, 103 }, 104 [VCAP_KF_ETYPE_LEN_IS] = { 105 .type = VCAP_FIELD_BIT, 106 .offset = 166, 107 .width = 1, 108 }, 109 [VCAP_KF_ETYPE] = { 110 .type = VCAP_FIELD_U32, 111 .offset = 167, 112 .width = 16, 113 }, 114 [VCAP_KF_IP_SNAP_IS] = { 115 .type = VCAP_FIELD_BIT, 116 .offset = 183, 117 .width = 1, 118 }, 119 [VCAP_KF_IP4_IS] = { 120 .type = VCAP_FIELD_BIT, 121 .offset = 184, 122 .width = 1, 123 }, 124 [VCAP_KF_L3_FRAGMENT_TYPE] = { 125 .type = VCAP_FIELD_U32, 126 .offset = 185, 127 .width = 2, 128 }, 129 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 130 .type = VCAP_FIELD_BIT, 131 .offset = 187, 132 .width = 1, 133 }, 134 [VCAP_KF_L3_OPTIONS_IS] = { 135 .type = VCAP_FIELD_BIT, 136 .offset = 188, 137 .width = 1, 138 }, 139 [VCAP_KF_L3_DSCP] = { 140 .type = VCAP_FIELD_U32, 141 .offset = 189, 142 .width = 6, 143 }, 144 [VCAP_KF_L3_IP4_DIP] = { 145 .type = VCAP_FIELD_U32, 146 .offset = 195, 147 .width = 32, 148 }, 149 [VCAP_KF_L3_IP4_SIP] = { 150 .type = VCAP_FIELD_U32, 151 .offset = 227, 152 .width = 32, 153 }, 154 [VCAP_KF_TCP_UDP_IS] = { 155 .type = VCAP_FIELD_BIT, 156 .offset = 259, 157 .width = 1, 158 }, 159 [VCAP_KF_TCP_IS] = { 160 .type = VCAP_FIELD_BIT, 161 .offset = 260, 162 .width = 1, 163 }, 164 [VCAP_KF_L4_SPORT] = { 165 .type = VCAP_FIELD_U32, 166 .offset = 261, 167 .width = 16, 168 }, 169 [VCAP_KF_L4_RNG] = { 170 .type = VCAP_FIELD_U32, 171 .offset = 277, 172 .width = 8, 173 }, 174 }; 175 176 static const struct vcap_field is0_normal_7tuple_keyfield[] = { 177 [VCAP_KF_TYPE] = { 178 .type = VCAP_FIELD_BIT, 179 .offset = 0, 180 .width = 1, 181 }, 182 [VCAP_KF_LOOKUP_FIRST_IS] = { 183 .type = VCAP_FIELD_BIT, 184 .offset = 1, 185 .width = 1, 186 }, 187 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { 188 .type = VCAP_FIELD_U32, 189 .offset = 2, 190 .width = 2, 191 }, 192 [VCAP_KF_LOOKUP_GEN_IDX] = { 193 .type = VCAP_FIELD_U32, 194 .offset = 4, 195 .width = 12, 196 }, 197 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 198 .type = VCAP_FIELD_U32, 199 .offset = 16, 200 .width = 2, 201 }, 202 [VCAP_KF_IF_IGR_PORT_MASK] = { 203 .type = VCAP_FIELD_U72, 204 .offset = 18, 205 .width = 65, 206 }, 207 [VCAP_KF_L2_MC_IS] = { 208 .type = VCAP_FIELD_BIT, 209 .offset = 83, 210 .width = 1, 211 }, 212 [VCAP_KF_L2_BC_IS] = { 213 .type = VCAP_FIELD_BIT, 214 .offset = 84, 215 .width = 1, 216 }, 217 [VCAP_KF_8021Q_VLAN_TAGS] = { 218 .type = VCAP_FIELD_U32, 219 .offset = 85, 220 .width = 3, 221 }, 222 [VCAP_KF_8021Q_TPID0] = { 223 .type = VCAP_FIELD_U32, 224 .offset = 88, 225 .width = 3, 226 }, 227 [VCAP_KF_8021Q_PCP0] = { 228 .type = VCAP_FIELD_U32, 229 .offset = 91, 230 .width = 3, 231 }, 232 [VCAP_KF_8021Q_DEI0] = { 233 .type = VCAP_FIELD_BIT, 234 .offset = 94, 235 .width = 1, 236 }, 237 [VCAP_KF_8021Q_VID0] = { 238 .type = VCAP_FIELD_U32, 239 .offset = 95, 240 .width = 12, 241 }, 242 [VCAP_KF_8021Q_TPID1] = { 243 .type = VCAP_FIELD_U32, 244 .offset = 107, 245 .width = 3, 246 }, 247 [VCAP_KF_8021Q_PCP1] = { 248 .type = VCAP_FIELD_U32, 249 .offset = 110, 250 .width = 3, 251 }, 252 [VCAP_KF_8021Q_DEI1] = { 253 .type = VCAP_FIELD_BIT, 254 .offset = 113, 255 .width = 1, 256 }, 257 [VCAP_KF_8021Q_VID1] = { 258 .type = VCAP_FIELD_U32, 259 .offset = 114, 260 .width = 12, 261 }, 262 [VCAP_KF_8021Q_TPID2] = { 263 .type = VCAP_FIELD_U32, 264 .offset = 126, 265 .width = 3, 266 }, 267 [VCAP_KF_8021Q_PCP2] = { 268 .type = VCAP_FIELD_U32, 269 .offset = 129, 270 .width = 3, 271 }, 272 [VCAP_KF_8021Q_DEI2] = { 273 .type = VCAP_FIELD_BIT, 274 .offset = 132, 275 .width = 1, 276 }, 277 [VCAP_KF_8021Q_VID2] = { 278 .type = VCAP_FIELD_U32, 279 .offset = 133, 280 .width = 12, 281 }, 282 [VCAP_KF_L2_DMAC] = { 283 .type = VCAP_FIELD_U48, 284 .offset = 145, 285 .width = 48, 286 }, 287 [VCAP_KF_L2_SMAC] = { 288 .type = VCAP_FIELD_U48, 289 .offset = 193, 290 .width = 48, 291 }, 292 [VCAP_KF_IP_MC_IS] = { 293 .type = VCAP_FIELD_BIT, 294 .offset = 241, 295 .width = 1, 296 }, 297 [VCAP_KF_ETYPE_LEN_IS] = { 298 .type = VCAP_FIELD_BIT, 299 .offset = 242, 300 .width = 1, 301 }, 302 [VCAP_KF_ETYPE] = { 303 .type = VCAP_FIELD_U32, 304 .offset = 243, 305 .width = 16, 306 }, 307 [VCAP_KF_IP_SNAP_IS] = { 308 .type = VCAP_FIELD_BIT, 309 .offset = 259, 310 .width = 1, 311 }, 312 [VCAP_KF_IP4_IS] = { 313 .type = VCAP_FIELD_BIT, 314 .offset = 260, 315 .width = 1, 316 }, 317 [VCAP_KF_L3_FRAGMENT_TYPE] = { 318 .type = VCAP_FIELD_U32, 319 .offset = 261, 320 .width = 2, 321 }, 322 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 323 .type = VCAP_FIELD_BIT, 324 .offset = 263, 325 .width = 1, 326 }, 327 [VCAP_KF_L3_OPTIONS_IS] = { 328 .type = VCAP_FIELD_BIT, 329 .offset = 264, 330 .width = 1, 331 }, 332 [VCAP_KF_L3_DSCP] = { 333 .type = VCAP_FIELD_U32, 334 .offset = 265, 335 .width = 6, 336 }, 337 [VCAP_KF_L3_IP6_DIP] = { 338 .type = VCAP_FIELD_U128, 339 .offset = 271, 340 .width = 128, 341 }, 342 [VCAP_KF_L3_IP6_SIP] = { 343 .type = VCAP_FIELD_U128, 344 .offset = 399, 345 .width = 128, 346 }, 347 [VCAP_KF_TCP_UDP_IS] = { 348 .type = VCAP_FIELD_BIT, 349 .offset = 527, 350 .width = 1, 351 }, 352 [VCAP_KF_TCP_IS] = { 353 .type = VCAP_FIELD_BIT, 354 .offset = 528, 355 .width = 1, 356 }, 357 [VCAP_KF_L4_SPORT] = { 358 .type = VCAP_FIELD_U32, 359 .offset = 529, 360 .width = 16, 361 }, 362 [VCAP_KF_L4_RNG] = { 363 .type = VCAP_FIELD_U32, 364 .offset = 545, 365 .width = 8, 366 }, 367 }; 368 369 static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { 370 [VCAP_KF_TYPE] = { 371 .type = VCAP_FIELD_U32, 372 .offset = 0, 373 .width = 2, 374 }, 375 [VCAP_KF_LOOKUP_FIRST_IS] = { 376 .type = VCAP_FIELD_BIT, 377 .offset = 2, 378 .width = 1, 379 }, 380 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { 381 .type = VCAP_FIELD_U32, 382 .offset = 3, 383 .width = 2, 384 }, 385 [VCAP_KF_LOOKUP_GEN_IDX] = { 386 .type = VCAP_FIELD_U32, 387 .offset = 5, 388 .width = 12, 389 }, 390 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 391 .type = VCAP_FIELD_U32, 392 .offset = 17, 393 .width = 2, 394 }, 395 [VCAP_KF_IF_IGR_PORT_MASK] = { 396 .type = VCAP_FIELD_U72, 397 .offset = 19, 398 .width = 65, 399 }, 400 [VCAP_KF_L2_MC_IS] = { 401 .type = VCAP_FIELD_BIT, 402 .offset = 84, 403 .width = 1, 404 }, 405 [VCAP_KF_L2_BC_IS] = { 406 .type = VCAP_FIELD_BIT, 407 .offset = 85, 408 .width = 1, 409 }, 410 [VCAP_KF_8021Q_VLAN_TAGS] = { 411 .type = VCAP_FIELD_U32, 412 .offset = 86, 413 .width = 3, 414 }, 415 [VCAP_KF_8021Q_TPID0] = { 416 .type = VCAP_FIELD_U32, 417 .offset = 89, 418 .width = 3, 419 }, 420 [VCAP_KF_8021Q_PCP0] = { 421 .type = VCAP_FIELD_U32, 422 .offset = 92, 423 .width = 3, 424 }, 425 [VCAP_KF_8021Q_DEI0] = { 426 .type = VCAP_FIELD_BIT, 427 .offset = 95, 428 .width = 1, 429 }, 430 [VCAP_KF_8021Q_VID0] = { 431 .type = VCAP_FIELD_U32, 432 .offset = 96, 433 .width = 12, 434 }, 435 [VCAP_KF_8021Q_TPID1] = { 436 .type = VCAP_FIELD_U32, 437 .offset = 108, 438 .width = 3, 439 }, 440 [VCAP_KF_8021Q_PCP1] = { 441 .type = VCAP_FIELD_U32, 442 .offset = 111, 443 .width = 3, 444 }, 445 [VCAP_KF_8021Q_DEI1] = { 446 .type = VCAP_FIELD_BIT, 447 .offset = 114, 448 .width = 1, 449 }, 450 [VCAP_KF_8021Q_VID1] = { 451 .type = VCAP_FIELD_U32, 452 .offset = 115, 453 .width = 12, 454 }, 455 [VCAP_KF_8021Q_TPID2] = { 456 .type = VCAP_FIELD_U32, 457 .offset = 127, 458 .width = 3, 459 }, 460 [VCAP_KF_8021Q_PCP2] = { 461 .type = VCAP_FIELD_U32, 462 .offset = 130, 463 .width = 3, 464 }, 465 [VCAP_KF_8021Q_DEI2] = { 466 .type = VCAP_FIELD_BIT, 467 .offset = 133, 468 .width = 1, 469 }, 470 [VCAP_KF_8021Q_VID2] = { 471 .type = VCAP_FIELD_U32, 472 .offset = 134, 473 .width = 12, 474 }, 475 [VCAP_KF_IP_MC_IS] = { 476 .type = VCAP_FIELD_BIT, 477 .offset = 146, 478 .width = 1, 479 }, 480 [VCAP_KF_IP4_IS] = { 481 .type = VCAP_FIELD_BIT, 482 .offset = 147, 483 .width = 1, 484 }, 485 [VCAP_KF_L3_FRAGMENT_TYPE] = { 486 .type = VCAP_FIELD_U32, 487 .offset = 148, 488 .width = 2, 489 }, 490 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 491 .type = VCAP_FIELD_BIT, 492 .offset = 150, 493 .width = 1, 494 }, 495 [VCAP_KF_L3_OPTIONS_IS] = { 496 .type = VCAP_FIELD_BIT, 497 .offset = 151, 498 .width = 1, 499 }, 500 [VCAP_KF_L3_DSCP] = { 501 .type = VCAP_FIELD_U32, 502 .offset = 152, 503 .width = 6, 504 }, 505 [VCAP_KF_L3_IP4_DIP] = { 506 .type = VCAP_FIELD_U32, 507 .offset = 158, 508 .width = 32, 509 }, 510 [VCAP_KF_L3_IP4_SIP] = { 511 .type = VCAP_FIELD_U32, 512 .offset = 190, 513 .width = 32, 514 }, 515 [VCAP_KF_L3_IP_PROTO] = { 516 .type = VCAP_FIELD_U32, 517 .offset = 222, 518 .width = 8, 519 }, 520 [VCAP_KF_TCP_UDP_IS] = { 521 .type = VCAP_FIELD_BIT, 522 .offset = 230, 523 .width = 1, 524 }, 525 [VCAP_KF_TCP_IS] = { 526 .type = VCAP_FIELD_BIT, 527 .offset = 231, 528 .width = 1, 529 }, 530 [VCAP_KF_L4_RNG] = { 531 .type = VCAP_FIELD_U32, 532 .offset = 232, 533 .width = 8, 534 }, 535 [VCAP_KF_IP_PAYLOAD_5TUPLE] = { 536 .type = VCAP_FIELD_U32, 537 .offset = 240, 538 .width = 32, 539 }, 540 }; 541 542 static const struct vcap_field is0_pure_5tuple_ip4_keyfield[] = { 543 [VCAP_KF_TYPE] = { 544 .type = VCAP_FIELD_U32, 545 .offset = 0, 546 .width = 2, 547 }, 548 [VCAP_KF_LOOKUP_FIRST_IS] = { 549 .type = VCAP_FIELD_BIT, 550 .offset = 2, 551 .width = 1, 552 }, 553 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { 554 .type = VCAP_FIELD_U32, 555 .offset = 3, 556 .width = 2, 557 }, 558 [VCAP_KF_LOOKUP_GEN_IDX] = { 559 .type = VCAP_FIELD_U32, 560 .offset = 5, 561 .width = 12, 562 }, 563 [VCAP_KF_L3_FRAGMENT_TYPE] = { 564 .type = VCAP_FIELD_U32, 565 .offset = 17, 566 .width = 2, 567 }, 568 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 569 .type = VCAP_FIELD_BIT, 570 .offset = 19, 571 .width = 1, 572 }, 573 [VCAP_KF_L3_OPTIONS_IS] = { 574 .type = VCAP_FIELD_BIT, 575 .offset = 20, 576 .width = 1, 577 }, 578 [VCAP_KF_L3_DSCP] = { 579 .type = VCAP_FIELD_U32, 580 .offset = 21, 581 .width = 6, 582 }, 583 [VCAP_KF_L3_IP4_DIP] = { 584 .type = VCAP_FIELD_U32, 585 .offset = 27, 586 .width = 32, 587 }, 588 [VCAP_KF_L3_IP4_SIP] = { 589 .type = VCAP_FIELD_U32, 590 .offset = 59, 591 .width = 32, 592 }, 593 [VCAP_KF_L3_IP_PROTO] = { 594 .type = VCAP_FIELD_U32, 595 .offset = 91, 596 .width = 8, 597 }, 598 [VCAP_KF_L4_RNG] = { 599 .type = VCAP_FIELD_U32, 600 .offset = 99, 601 .width = 8, 602 }, 603 [VCAP_KF_IP_PAYLOAD_5TUPLE] = { 604 .type = VCAP_FIELD_U32, 605 .offset = 107, 606 .width = 32, 607 }, 608 }; 609 610 static const struct vcap_field is0_etag_keyfield[] = { 611 [VCAP_KF_TYPE] = { 612 .type = VCAP_FIELD_U32, 613 .offset = 0, 614 .width = 2, 615 }, 616 [VCAP_KF_LOOKUP_FIRST_IS] = { 617 .type = VCAP_FIELD_BIT, 618 .offset = 2, 619 .width = 1, 620 }, 621 [VCAP_KF_IF_IGR_PORT] = { 622 .type = VCAP_FIELD_U32, 623 .offset = 3, 624 .width = 7, 625 }, 626 [VCAP_KF_8021BR_E_TAGGED] = { 627 .type = VCAP_FIELD_BIT, 628 .offset = 10, 629 .width = 1, 630 }, 631 [VCAP_KF_8021BR_GRP] = { 632 .type = VCAP_FIELD_U32, 633 .offset = 11, 634 .width = 2, 635 }, 636 [VCAP_KF_8021BR_ECID_EXT] = { 637 .type = VCAP_FIELD_U32, 638 .offset = 13, 639 .width = 8, 640 }, 641 [VCAP_KF_8021BR_ECID_BASE] = { 642 .type = VCAP_FIELD_U32, 643 .offset = 21, 644 .width = 12, 645 }, 646 [VCAP_KF_8021BR_IGR_ECID_EXT] = { 647 .type = VCAP_FIELD_U32, 648 .offset = 33, 649 .width = 8, 650 }, 651 [VCAP_KF_8021BR_IGR_ECID_BASE] = { 652 .type = VCAP_FIELD_U32, 653 .offset = 41, 654 .width = 12, 655 }, 656 }; 657 658 static const struct vcap_field is2_mac_etype_keyfield[] = { 659 [VCAP_KF_TYPE] = { 660 .type = VCAP_FIELD_U32, 661 .offset = 0, 662 .width = 4, 663 }, 664 [VCAP_KF_LOOKUP_FIRST_IS] = { 665 .type = VCAP_FIELD_BIT, 666 .offset = 4, 667 .width = 1, 668 }, 669 [VCAP_KF_LOOKUP_PAG] = { 670 .type = VCAP_FIELD_U32, 671 .offset = 5, 672 .width = 8, 673 }, 674 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 675 .type = VCAP_FIELD_BIT, 676 .offset = 13, 677 .width = 1, 678 }, 679 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 680 .type = VCAP_FIELD_U32, 681 .offset = 14, 682 .width = 4, 683 }, 684 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 685 .type = VCAP_FIELD_U32, 686 .offset = 18, 687 .width = 2, 688 }, 689 [VCAP_KF_IF_IGR_PORT_MASK] = { 690 .type = VCAP_FIELD_U32, 691 .offset = 20, 692 .width = 32, 693 }, 694 [VCAP_KF_L2_MC_IS] = { 695 .type = VCAP_FIELD_BIT, 696 .offset = 52, 697 .width = 1, 698 }, 699 [VCAP_KF_L2_BC_IS] = { 700 .type = VCAP_FIELD_BIT, 701 .offset = 53, 702 .width = 1, 703 }, 704 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 705 .type = VCAP_FIELD_BIT, 706 .offset = 54, 707 .width = 1, 708 }, 709 [VCAP_KF_ISDX_GT0_IS] = { 710 .type = VCAP_FIELD_BIT, 711 .offset = 55, 712 .width = 1, 713 }, 714 [VCAP_KF_ISDX_CLS] = { 715 .type = VCAP_FIELD_U32, 716 .offset = 56, 717 .width = 12, 718 }, 719 [VCAP_KF_8021Q_VID_CLS] = { 720 .type = VCAP_FIELD_U32, 721 .offset = 68, 722 .width = 13, 723 }, 724 [VCAP_KF_8021Q_DEI_CLS] = { 725 .type = VCAP_FIELD_BIT, 726 .offset = 81, 727 .width = 1, 728 }, 729 [VCAP_KF_8021Q_PCP_CLS] = { 730 .type = VCAP_FIELD_U32, 731 .offset = 82, 732 .width = 3, 733 }, 734 [VCAP_KF_L2_FWD_IS] = { 735 .type = VCAP_FIELD_BIT, 736 .offset = 85, 737 .width = 1, 738 }, 739 [VCAP_KF_L3_RT_IS] = { 740 .type = VCAP_FIELD_BIT, 741 .offset = 88, 742 .width = 1, 743 }, 744 [VCAP_KF_L3_DST_IS] = { 745 .type = VCAP_FIELD_BIT, 746 .offset = 89, 747 .width = 1, 748 }, 749 [VCAP_KF_L2_DMAC] = { 750 .type = VCAP_FIELD_U48, 751 .offset = 90, 752 .width = 48, 753 }, 754 [VCAP_KF_L2_SMAC] = { 755 .type = VCAP_FIELD_U48, 756 .offset = 138, 757 .width = 48, 758 }, 759 [VCAP_KF_ETYPE_LEN_IS] = { 760 .type = VCAP_FIELD_BIT, 761 .offset = 186, 762 .width = 1, 763 }, 764 [VCAP_KF_ETYPE] = { 765 .type = VCAP_FIELD_U32, 766 .offset = 187, 767 .width = 16, 768 }, 769 [VCAP_KF_L2_PAYLOAD_ETYPE] = { 770 .type = VCAP_FIELD_U64, 771 .offset = 203, 772 .width = 64, 773 }, 774 [VCAP_KF_L4_RNG] = { 775 .type = VCAP_FIELD_U32, 776 .offset = 267, 777 .width = 16, 778 }, 779 [VCAP_KF_OAM_CCM_CNTS_EQ0] = { 780 .type = VCAP_FIELD_BIT, 781 .offset = 283, 782 .width = 1, 783 }, 784 [VCAP_KF_OAM_Y1731_IS] = { 785 .type = VCAP_FIELD_BIT, 786 .offset = 284, 787 .width = 1, 788 }, 789 }; 790 791 static const struct vcap_field is2_arp_keyfield[] = { 792 [VCAP_KF_TYPE] = { 793 .type = VCAP_FIELD_U32, 794 .offset = 0, 795 .width = 4, 796 }, 797 [VCAP_KF_LOOKUP_FIRST_IS] = { 798 .type = VCAP_FIELD_BIT, 799 .offset = 4, 800 .width = 1, 801 }, 802 [VCAP_KF_LOOKUP_PAG] = { 803 .type = VCAP_FIELD_U32, 804 .offset = 5, 805 .width = 8, 806 }, 807 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 808 .type = VCAP_FIELD_BIT, 809 .offset = 13, 810 .width = 1, 811 }, 812 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 813 .type = VCAP_FIELD_U32, 814 .offset = 14, 815 .width = 4, 816 }, 817 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 818 .type = VCAP_FIELD_U32, 819 .offset = 18, 820 .width = 2, 821 }, 822 [VCAP_KF_IF_IGR_PORT_MASK] = { 823 .type = VCAP_FIELD_U32, 824 .offset = 20, 825 .width = 32, 826 }, 827 [VCAP_KF_L2_MC_IS] = { 828 .type = VCAP_FIELD_BIT, 829 .offset = 52, 830 .width = 1, 831 }, 832 [VCAP_KF_L2_BC_IS] = { 833 .type = VCAP_FIELD_BIT, 834 .offset = 53, 835 .width = 1, 836 }, 837 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 838 .type = VCAP_FIELD_BIT, 839 .offset = 54, 840 .width = 1, 841 }, 842 [VCAP_KF_ISDX_GT0_IS] = { 843 .type = VCAP_FIELD_BIT, 844 .offset = 55, 845 .width = 1, 846 }, 847 [VCAP_KF_ISDX_CLS] = { 848 .type = VCAP_FIELD_U32, 849 .offset = 56, 850 .width = 12, 851 }, 852 [VCAP_KF_8021Q_VID_CLS] = { 853 .type = VCAP_FIELD_U32, 854 .offset = 68, 855 .width = 13, 856 }, 857 [VCAP_KF_8021Q_DEI_CLS] = { 858 .type = VCAP_FIELD_BIT, 859 .offset = 81, 860 .width = 1, 861 }, 862 [VCAP_KF_8021Q_PCP_CLS] = { 863 .type = VCAP_FIELD_U32, 864 .offset = 82, 865 .width = 3, 866 }, 867 [VCAP_KF_L2_FWD_IS] = { 868 .type = VCAP_FIELD_BIT, 869 .offset = 85, 870 .width = 1, 871 }, 872 [VCAP_KF_L2_SMAC] = { 873 .type = VCAP_FIELD_U48, 874 .offset = 86, 875 .width = 48, 876 }, 877 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { 878 .type = VCAP_FIELD_BIT, 879 .offset = 134, 880 .width = 1, 881 }, 882 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { 883 .type = VCAP_FIELD_BIT, 884 .offset = 135, 885 .width = 1, 886 }, 887 [VCAP_KF_ARP_LEN_OK_IS] = { 888 .type = VCAP_FIELD_BIT, 889 .offset = 136, 890 .width = 1, 891 }, 892 [VCAP_KF_ARP_TGT_MATCH_IS] = { 893 .type = VCAP_FIELD_BIT, 894 .offset = 137, 895 .width = 1, 896 }, 897 [VCAP_KF_ARP_SENDER_MATCH_IS] = { 898 .type = VCAP_FIELD_BIT, 899 .offset = 138, 900 .width = 1, 901 }, 902 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { 903 .type = VCAP_FIELD_BIT, 904 .offset = 139, 905 .width = 1, 906 }, 907 [VCAP_KF_ARP_OPCODE] = { 908 .type = VCAP_FIELD_U32, 909 .offset = 140, 910 .width = 2, 911 }, 912 [VCAP_KF_L3_IP4_DIP] = { 913 .type = VCAP_FIELD_U32, 914 .offset = 142, 915 .width = 32, 916 }, 917 [VCAP_KF_L3_IP4_SIP] = { 918 .type = VCAP_FIELD_U32, 919 .offset = 174, 920 .width = 32, 921 }, 922 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 923 .type = VCAP_FIELD_BIT, 924 .offset = 206, 925 .width = 1, 926 }, 927 [VCAP_KF_L4_RNG] = { 928 .type = VCAP_FIELD_U32, 929 .offset = 207, 930 .width = 16, 931 }, 932 }; 933 934 static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { 935 [VCAP_KF_TYPE] = { 936 .type = VCAP_FIELD_U32, 937 .offset = 0, 938 .width = 4, 939 }, 940 [VCAP_KF_LOOKUP_FIRST_IS] = { 941 .type = VCAP_FIELD_BIT, 942 .offset = 4, 943 .width = 1, 944 }, 945 [VCAP_KF_LOOKUP_PAG] = { 946 .type = VCAP_FIELD_U32, 947 .offset = 5, 948 .width = 8, 949 }, 950 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 951 .type = VCAP_FIELD_BIT, 952 .offset = 13, 953 .width = 1, 954 }, 955 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 956 .type = VCAP_FIELD_U32, 957 .offset = 14, 958 .width = 4, 959 }, 960 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 961 .type = VCAP_FIELD_U32, 962 .offset = 18, 963 .width = 2, 964 }, 965 [VCAP_KF_IF_IGR_PORT_MASK] = { 966 .type = VCAP_FIELD_U32, 967 .offset = 20, 968 .width = 32, 969 }, 970 [VCAP_KF_L2_MC_IS] = { 971 .type = VCAP_FIELD_BIT, 972 .offset = 52, 973 .width = 1, 974 }, 975 [VCAP_KF_L2_BC_IS] = { 976 .type = VCAP_FIELD_BIT, 977 .offset = 53, 978 .width = 1, 979 }, 980 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 981 .type = VCAP_FIELD_BIT, 982 .offset = 54, 983 .width = 1, 984 }, 985 [VCAP_KF_ISDX_GT0_IS] = { 986 .type = VCAP_FIELD_BIT, 987 .offset = 55, 988 .width = 1, 989 }, 990 [VCAP_KF_ISDX_CLS] = { 991 .type = VCAP_FIELD_U32, 992 .offset = 56, 993 .width = 12, 994 }, 995 [VCAP_KF_8021Q_VID_CLS] = { 996 .type = VCAP_FIELD_U32, 997 .offset = 68, 998 .width = 13, 999 }, 1000 [VCAP_KF_8021Q_DEI_CLS] = { 1001 .type = VCAP_FIELD_BIT, 1002 .offset = 81, 1003 .width = 1, 1004 }, 1005 [VCAP_KF_8021Q_PCP_CLS] = { 1006 .type = VCAP_FIELD_U32, 1007 .offset = 82, 1008 .width = 3, 1009 }, 1010 [VCAP_KF_L2_FWD_IS] = { 1011 .type = VCAP_FIELD_BIT, 1012 .offset = 85, 1013 .width = 1, 1014 }, 1015 [VCAP_KF_L3_RT_IS] = { 1016 .type = VCAP_FIELD_BIT, 1017 .offset = 88, 1018 .width = 1, 1019 }, 1020 [VCAP_KF_L3_DST_IS] = { 1021 .type = VCAP_FIELD_BIT, 1022 .offset = 89, 1023 .width = 1, 1024 }, 1025 [VCAP_KF_IP4_IS] = { 1026 .type = VCAP_FIELD_BIT, 1027 .offset = 90, 1028 .width = 1, 1029 }, 1030 [VCAP_KF_L3_FRAGMENT_TYPE] = { 1031 .type = VCAP_FIELD_U32, 1032 .offset = 91, 1033 .width = 2, 1034 }, 1035 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 1036 .type = VCAP_FIELD_BIT, 1037 .offset = 93, 1038 .width = 1, 1039 }, 1040 [VCAP_KF_L3_OPTIONS_IS] = { 1041 .type = VCAP_FIELD_BIT, 1042 .offset = 94, 1043 .width = 1, 1044 }, 1045 [VCAP_KF_L3_TTL_GT0] = { 1046 .type = VCAP_FIELD_BIT, 1047 .offset = 95, 1048 .width = 1, 1049 }, 1050 [VCAP_KF_L3_TOS] = { 1051 .type = VCAP_FIELD_U32, 1052 .offset = 96, 1053 .width = 8, 1054 }, 1055 [VCAP_KF_L3_IP4_DIP] = { 1056 .type = VCAP_FIELD_U32, 1057 .offset = 104, 1058 .width = 32, 1059 }, 1060 [VCAP_KF_L3_IP4_SIP] = { 1061 .type = VCAP_FIELD_U32, 1062 .offset = 136, 1063 .width = 32, 1064 }, 1065 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1066 .type = VCAP_FIELD_BIT, 1067 .offset = 168, 1068 .width = 1, 1069 }, 1070 [VCAP_KF_TCP_IS] = { 1071 .type = VCAP_FIELD_BIT, 1072 .offset = 169, 1073 .width = 1, 1074 }, 1075 [VCAP_KF_L4_DPORT] = { 1076 .type = VCAP_FIELD_U32, 1077 .offset = 170, 1078 .width = 16, 1079 }, 1080 [VCAP_KF_L4_SPORT] = { 1081 .type = VCAP_FIELD_U32, 1082 .offset = 186, 1083 .width = 16, 1084 }, 1085 [VCAP_KF_L4_RNG] = { 1086 .type = VCAP_FIELD_U32, 1087 .offset = 202, 1088 .width = 16, 1089 }, 1090 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 1091 .type = VCAP_FIELD_BIT, 1092 .offset = 218, 1093 .width = 1, 1094 }, 1095 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 1096 .type = VCAP_FIELD_BIT, 1097 .offset = 219, 1098 .width = 1, 1099 }, 1100 [VCAP_KF_L4_FIN] = { 1101 .type = VCAP_FIELD_BIT, 1102 .offset = 220, 1103 .width = 1, 1104 }, 1105 [VCAP_KF_L4_SYN] = { 1106 .type = VCAP_FIELD_BIT, 1107 .offset = 221, 1108 .width = 1, 1109 }, 1110 [VCAP_KF_L4_RST] = { 1111 .type = VCAP_FIELD_BIT, 1112 .offset = 222, 1113 .width = 1, 1114 }, 1115 [VCAP_KF_L4_PSH] = { 1116 .type = VCAP_FIELD_BIT, 1117 .offset = 223, 1118 .width = 1, 1119 }, 1120 [VCAP_KF_L4_ACK] = { 1121 .type = VCAP_FIELD_BIT, 1122 .offset = 224, 1123 .width = 1, 1124 }, 1125 [VCAP_KF_L4_URG] = { 1126 .type = VCAP_FIELD_BIT, 1127 .offset = 225, 1128 .width = 1, 1129 }, 1130 [VCAP_KF_L4_PAYLOAD] = { 1131 .type = VCAP_FIELD_U64, 1132 .offset = 226, 1133 .width = 64, 1134 }, 1135 }; 1136 1137 static const struct vcap_field is2_ip4_other_keyfield[] = { 1138 [VCAP_KF_TYPE] = { 1139 .type = VCAP_FIELD_U32, 1140 .offset = 0, 1141 .width = 4, 1142 }, 1143 [VCAP_KF_LOOKUP_FIRST_IS] = { 1144 .type = VCAP_FIELD_BIT, 1145 .offset = 4, 1146 .width = 1, 1147 }, 1148 [VCAP_KF_LOOKUP_PAG] = { 1149 .type = VCAP_FIELD_U32, 1150 .offset = 5, 1151 .width = 8, 1152 }, 1153 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 1154 .type = VCAP_FIELD_BIT, 1155 .offset = 13, 1156 .width = 1, 1157 }, 1158 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 1159 .type = VCAP_FIELD_U32, 1160 .offset = 14, 1161 .width = 4, 1162 }, 1163 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 1164 .type = VCAP_FIELD_U32, 1165 .offset = 18, 1166 .width = 2, 1167 }, 1168 [VCAP_KF_IF_IGR_PORT_MASK] = { 1169 .type = VCAP_FIELD_U32, 1170 .offset = 20, 1171 .width = 32, 1172 }, 1173 [VCAP_KF_L2_MC_IS] = { 1174 .type = VCAP_FIELD_BIT, 1175 .offset = 52, 1176 .width = 1, 1177 }, 1178 [VCAP_KF_L2_BC_IS] = { 1179 .type = VCAP_FIELD_BIT, 1180 .offset = 53, 1181 .width = 1, 1182 }, 1183 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1184 .type = VCAP_FIELD_BIT, 1185 .offset = 54, 1186 .width = 1, 1187 }, 1188 [VCAP_KF_ISDX_GT0_IS] = { 1189 .type = VCAP_FIELD_BIT, 1190 .offset = 55, 1191 .width = 1, 1192 }, 1193 [VCAP_KF_ISDX_CLS] = { 1194 .type = VCAP_FIELD_U32, 1195 .offset = 56, 1196 .width = 12, 1197 }, 1198 [VCAP_KF_8021Q_VID_CLS] = { 1199 .type = VCAP_FIELD_U32, 1200 .offset = 68, 1201 .width = 13, 1202 }, 1203 [VCAP_KF_8021Q_DEI_CLS] = { 1204 .type = VCAP_FIELD_BIT, 1205 .offset = 81, 1206 .width = 1, 1207 }, 1208 [VCAP_KF_8021Q_PCP_CLS] = { 1209 .type = VCAP_FIELD_U32, 1210 .offset = 82, 1211 .width = 3, 1212 }, 1213 [VCAP_KF_L2_FWD_IS] = { 1214 .type = VCAP_FIELD_BIT, 1215 .offset = 85, 1216 .width = 1, 1217 }, 1218 [VCAP_KF_L3_RT_IS] = { 1219 .type = VCAP_FIELD_BIT, 1220 .offset = 88, 1221 .width = 1, 1222 }, 1223 [VCAP_KF_L3_DST_IS] = { 1224 .type = VCAP_FIELD_BIT, 1225 .offset = 89, 1226 .width = 1, 1227 }, 1228 [VCAP_KF_IP4_IS] = { 1229 .type = VCAP_FIELD_BIT, 1230 .offset = 90, 1231 .width = 1, 1232 }, 1233 [VCAP_KF_L3_FRAGMENT_TYPE] = { 1234 .type = VCAP_FIELD_U32, 1235 .offset = 91, 1236 .width = 2, 1237 }, 1238 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 1239 .type = VCAP_FIELD_BIT, 1240 .offset = 93, 1241 .width = 1, 1242 }, 1243 [VCAP_KF_L3_OPTIONS_IS] = { 1244 .type = VCAP_FIELD_BIT, 1245 .offset = 94, 1246 .width = 1, 1247 }, 1248 [VCAP_KF_L3_TTL_GT0] = { 1249 .type = VCAP_FIELD_BIT, 1250 .offset = 95, 1251 .width = 1, 1252 }, 1253 [VCAP_KF_L3_TOS] = { 1254 .type = VCAP_FIELD_U32, 1255 .offset = 96, 1256 .width = 8, 1257 }, 1258 [VCAP_KF_L3_IP4_DIP] = { 1259 .type = VCAP_FIELD_U32, 1260 .offset = 104, 1261 .width = 32, 1262 }, 1263 [VCAP_KF_L3_IP4_SIP] = { 1264 .type = VCAP_FIELD_U32, 1265 .offset = 136, 1266 .width = 32, 1267 }, 1268 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1269 .type = VCAP_FIELD_BIT, 1270 .offset = 168, 1271 .width = 1, 1272 }, 1273 [VCAP_KF_L3_IP_PROTO] = { 1274 .type = VCAP_FIELD_U32, 1275 .offset = 169, 1276 .width = 8, 1277 }, 1278 [VCAP_KF_L4_RNG] = { 1279 .type = VCAP_FIELD_U32, 1280 .offset = 177, 1281 .width = 16, 1282 }, 1283 [VCAP_KF_L3_PAYLOAD] = { 1284 .type = VCAP_FIELD_U112, 1285 .offset = 193, 1286 .width = 96, 1287 }, 1288 }; 1289 1290 static const struct vcap_field is2_ip6_std_keyfield[] = { 1291 [VCAP_KF_TYPE] = { 1292 .type = VCAP_FIELD_U32, 1293 .offset = 0, 1294 .width = 4, 1295 }, 1296 [VCAP_KF_LOOKUP_FIRST_IS] = { 1297 .type = VCAP_FIELD_BIT, 1298 .offset = 4, 1299 .width = 1, 1300 }, 1301 [VCAP_KF_LOOKUP_PAG] = { 1302 .type = VCAP_FIELD_U32, 1303 .offset = 5, 1304 .width = 8, 1305 }, 1306 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 1307 .type = VCAP_FIELD_BIT, 1308 .offset = 13, 1309 .width = 1, 1310 }, 1311 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 1312 .type = VCAP_FIELD_U32, 1313 .offset = 14, 1314 .width = 4, 1315 }, 1316 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 1317 .type = VCAP_FIELD_U32, 1318 .offset = 18, 1319 .width = 2, 1320 }, 1321 [VCAP_KF_IF_IGR_PORT_MASK] = { 1322 .type = VCAP_FIELD_U32, 1323 .offset = 20, 1324 .width = 32, 1325 }, 1326 [VCAP_KF_L2_MC_IS] = { 1327 .type = VCAP_FIELD_BIT, 1328 .offset = 52, 1329 .width = 1, 1330 }, 1331 [VCAP_KF_L2_BC_IS] = { 1332 .type = VCAP_FIELD_BIT, 1333 .offset = 53, 1334 .width = 1, 1335 }, 1336 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1337 .type = VCAP_FIELD_BIT, 1338 .offset = 54, 1339 .width = 1, 1340 }, 1341 [VCAP_KF_ISDX_GT0_IS] = { 1342 .type = VCAP_FIELD_BIT, 1343 .offset = 55, 1344 .width = 1, 1345 }, 1346 [VCAP_KF_ISDX_CLS] = { 1347 .type = VCAP_FIELD_U32, 1348 .offset = 56, 1349 .width = 12, 1350 }, 1351 [VCAP_KF_8021Q_VID_CLS] = { 1352 .type = VCAP_FIELD_U32, 1353 .offset = 68, 1354 .width = 13, 1355 }, 1356 [VCAP_KF_8021Q_DEI_CLS] = { 1357 .type = VCAP_FIELD_BIT, 1358 .offset = 81, 1359 .width = 1, 1360 }, 1361 [VCAP_KF_8021Q_PCP_CLS] = { 1362 .type = VCAP_FIELD_U32, 1363 .offset = 82, 1364 .width = 3, 1365 }, 1366 [VCAP_KF_L2_FWD_IS] = { 1367 .type = VCAP_FIELD_BIT, 1368 .offset = 85, 1369 .width = 1, 1370 }, 1371 [VCAP_KF_L3_RT_IS] = { 1372 .type = VCAP_FIELD_BIT, 1373 .offset = 88, 1374 .width = 1, 1375 }, 1376 [VCAP_KF_L3_TTL_GT0] = { 1377 .type = VCAP_FIELD_BIT, 1378 .offset = 90, 1379 .width = 1, 1380 }, 1381 [VCAP_KF_L3_IP6_SIP] = { 1382 .type = VCAP_FIELD_U128, 1383 .offset = 91, 1384 .width = 128, 1385 }, 1386 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1387 .type = VCAP_FIELD_BIT, 1388 .offset = 219, 1389 .width = 1, 1390 }, 1391 [VCAP_KF_L3_IP_PROTO] = { 1392 .type = VCAP_FIELD_U32, 1393 .offset = 220, 1394 .width = 8, 1395 }, 1396 [VCAP_KF_L4_RNG] = { 1397 .type = VCAP_FIELD_U32, 1398 .offset = 228, 1399 .width = 16, 1400 }, 1401 [VCAP_KF_L3_PAYLOAD] = { 1402 .type = VCAP_FIELD_U48, 1403 .offset = 244, 1404 .width = 40, 1405 }, 1406 }; 1407 1408 static const struct vcap_field is2_ip_7tuple_keyfield[] = { 1409 [VCAP_KF_TYPE] = { 1410 .type = VCAP_FIELD_U32, 1411 .offset = 0, 1412 .width = 2, 1413 }, 1414 [VCAP_KF_LOOKUP_FIRST_IS] = { 1415 .type = VCAP_FIELD_BIT, 1416 .offset = 2, 1417 .width = 1, 1418 }, 1419 [VCAP_KF_LOOKUP_PAG] = { 1420 .type = VCAP_FIELD_U32, 1421 .offset = 3, 1422 .width = 8, 1423 }, 1424 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 1425 .type = VCAP_FIELD_BIT, 1426 .offset = 11, 1427 .width = 1, 1428 }, 1429 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 1430 .type = VCAP_FIELD_U32, 1431 .offset = 12, 1432 .width = 4, 1433 }, 1434 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 1435 .type = VCAP_FIELD_U32, 1436 .offset = 16, 1437 .width = 2, 1438 }, 1439 [VCAP_KF_IF_IGR_PORT_MASK] = { 1440 .type = VCAP_FIELD_U72, 1441 .offset = 18, 1442 .width = 65, 1443 }, 1444 [VCAP_KF_L2_MC_IS] = { 1445 .type = VCAP_FIELD_BIT, 1446 .offset = 83, 1447 .width = 1, 1448 }, 1449 [VCAP_KF_L2_BC_IS] = { 1450 .type = VCAP_FIELD_BIT, 1451 .offset = 84, 1452 .width = 1, 1453 }, 1454 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1455 .type = VCAP_FIELD_BIT, 1456 .offset = 85, 1457 .width = 1, 1458 }, 1459 [VCAP_KF_ISDX_GT0_IS] = { 1460 .type = VCAP_FIELD_BIT, 1461 .offset = 86, 1462 .width = 1, 1463 }, 1464 [VCAP_KF_ISDX_CLS] = { 1465 .type = VCAP_FIELD_U32, 1466 .offset = 87, 1467 .width = 12, 1468 }, 1469 [VCAP_KF_8021Q_VID_CLS] = { 1470 .type = VCAP_FIELD_U32, 1471 .offset = 99, 1472 .width = 13, 1473 }, 1474 [VCAP_KF_8021Q_DEI_CLS] = { 1475 .type = VCAP_FIELD_BIT, 1476 .offset = 112, 1477 .width = 1, 1478 }, 1479 [VCAP_KF_8021Q_PCP_CLS] = { 1480 .type = VCAP_FIELD_U32, 1481 .offset = 113, 1482 .width = 3, 1483 }, 1484 [VCAP_KF_L2_FWD_IS] = { 1485 .type = VCAP_FIELD_BIT, 1486 .offset = 116, 1487 .width = 1, 1488 }, 1489 [VCAP_KF_L3_RT_IS] = { 1490 .type = VCAP_FIELD_BIT, 1491 .offset = 119, 1492 .width = 1, 1493 }, 1494 [VCAP_KF_L3_DST_IS] = { 1495 .type = VCAP_FIELD_BIT, 1496 .offset = 120, 1497 .width = 1, 1498 }, 1499 [VCAP_KF_L2_DMAC] = { 1500 .type = VCAP_FIELD_U48, 1501 .offset = 121, 1502 .width = 48, 1503 }, 1504 [VCAP_KF_L2_SMAC] = { 1505 .type = VCAP_FIELD_U48, 1506 .offset = 169, 1507 .width = 48, 1508 }, 1509 [VCAP_KF_IP4_IS] = { 1510 .type = VCAP_FIELD_BIT, 1511 .offset = 217, 1512 .width = 1, 1513 }, 1514 [VCAP_KF_L3_TTL_GT0] = { 1515 .type = VCAP_FIELD_BIT, 1516 .offset = 218, 1517 .width = 1, 1518 }, 1519 [VCAP_KF_L3_TOS] = { 1520 .type = VCAP_FIELD_U32, 1521 .offset = 219, 1522 .width = 8, 1523 }, 1524 [VCAP_KF_L3_IP6_DIP] = { 1525 .type = VCAP_FIELD_U128, 1526 .offset = 227, 1527 .width = 128, 1528 }, 1529 [VCAP_KF_L3_IP6_SIP] = { 1530 .type = VCAP_FIELD_U128, 1531 .offset = 355, 1532 .width = 128, 1533 }, 1534 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1535 .type = VCAP_FIELD_BIT, 1536 .offset = 483, 1537 .width = 1, 1538 }, 1539 [VCAP_KF_TCP_UDP_IS] = { 1540 .type = VCAP_FIELD_BIT, 1541 .offset = 484, 1542 .width = 1, 1543 }, 1544 [VCAP_KF_TCP_IS] = { 1545 .type = VCAP_FIELD_BIT, 1546 .offset = 485, 1547 .width = 1, 1548 }, 1549 [VCAP_KF_L4_DPORT] = { 1550 .type = VCAP_FIELD_U32, 1551 .offset = 486, 1552 .width = 16, 1553 }, 1554 [VCAP_KF_L4_SPORT] = { 1555 .type = VCAP_FIELD_U32, 1556 .offset = 502, 1557 .width = 16, 1558 }, 1559 [VCAP_KF_L4_RNG] = { 1560 .type = VCAP_FIELD_U32, 1561 .offset = 518, 1562 .width = 16, 1563 }, 1564 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 1565 .type = VCAP_FIELD_BIT, 1566 .offset = 534, 1567 .width = 1, 1568 }, 1569 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 1570 .type = VCAP_FIELD_BIT, 1571 .offset = 535, 1572 .width = 1, 1573 }, 1574 [VCAP_KF_L4_FIN] = { 1575 .type = VCAP_FIELD_BIT, 1576 .offset = 536, 1577 .width = 1, 1578 }, 1579 [VCAP_KF_L4_SYN] = { 1580 .type = VCAP_FIELD_BIT, 1581 .offset = 537, 1582 .width = 1, 1583 }, 1584 [VCAP_KF_L4_RST] = { 1585 .type = VCAP_FIELD_BIT, 1586 .offset = 538, 1587 .width = 1, 1588 }, 1589 [VCAP_KF_L4_PSH] = { 1590 .type = VCAP_FIELD_BIT, 1591 .offset = 539, 1592 .width = 1, 1593 }, 1594 [VCAP_KF_L4_ACK] = { 1595 .type = VCAP_FIELD_BIT, 1596 .offset = 540, 1597 .width = 1, 1598 }, 1599 [VCAP_KF_L4_URG] = { 1600 .type = VCAP_FIELD_BIT, 1601 .offset = 541, 1602 .width = 1, 1603 }, 1604 [VCAP_KF_L4_PAYLOAD] = { 1605 .type = VCAP_FIELD_U64, 1606 .offset = 542, 1607 .width = 64, 1608 }, 1609 }; 1610 1611 static const struct vcap_field es2_mac_etype_keyfield[] = { 1612 [VCAP_KF_TYPE] = { 1613 .type = VCAP_FIELD_U32, 1614 .offset = 0, 1615 .width = 3, 1616 }, 1617 [VCAP_KF_LOOKUP_FIRST_IS] = { 1618 .type = VCAP_FIELD_BIT, 1619 .offset = 3, 1620 .width = 1, 1621 }, 1622 [VCAP_KF_ACL_GRP_ID] = { 1623 .type = VCAP_FIELD_U32, 1624 .offset = 4, 1625 .width = 8, 1626 }, 1627 [VCAP_KF_PROT_ACTIVE] = { 1628 .type = VCAP_FIELD_BIT, 1629 .offset = 12, 1630 .width = 1, 1631 }, 1632 [VCAP_KF_L2_MC_IS] = { 1633 .type = VCAP_FIELD_BIT, 1634 .offset = 13, 1635 .width = 1, 1636 }, 1637 [VCAP_KF_L2_BC_IS] = { 1638 .type = VCAP_FIELD_BIT, 1639 .offset = 14, 1640 .width = 1, 1641 }, 1642 [VCAP_KF_ISDX_GT0_IS] = { 1643 .type = VCAP_FIELD_BIT, 1644 .offset = 15, 1645 .width = 1, 1646 }, 1647 [VCAP_KF_ISDX_CLS] = { 1648 .type = VCAP_FIELD_U32, 1649 .offset = 16, 1650 .width = 12, 1651 }, 1652 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1653 .type = VCAP_FIELD_BIT, 1654 .offset = 28, 1655 .width = 1, 1656 }, 1657 [VCAP_KF_8021Q_VID_CLS] = { 1658 .type = VCAP_FIELD_U32, 1659 .offset = 29, 1660 .width = 13, 1661 }, 1662 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1663 .type = VCAP_FIELD_U32, 1664 .offset = 42, 1665 .width = 3, 1666 }, 1667 [VCAP_KF_IF_EGR_PORT_MASK] = { 1668 .type = VCAP_FIELD_U32, 1669 .offset = 45, 1670 .width = 32, 1671 }, 1672 [VCAP_KF_IF_IGR_PORT_SEL] = { 1673 .type = VCAP_FIELD_BIT, 1674 .offset = 77, 1675 .width = 1, 1676 }, 1677 [VCAP_KF_IF_IGR_PORT] = { 1678 .type = VCAP_FIELD_U32, 1679 .offset = 78, 1680 .width = 9, 1681 }, 1682 [VCAP_KF_8021Q_PCP_CLS] = { 1683 .type = VCAP_FIELD_U32, 1684 .offset = 87, 1685 .width = 3, 1686 }, 1687 [VCAP_KF_8021Q_DEI_CLS] = { 1688 .type = VCAP_FIELD_BIT, 1689 .offset = 90, 1690 .width = 1, 1691 }, 1692 [VCAP_KF_COSID_CLS] = { 1693 .type = VCAP_FIELD_U32, 1694 .offset = 91, 1695 .width = 3, 1696 }, 1697 [VCAP_KF_L3_DPL_CLS] = { 1698 .type = VCAP_FIELD_BIT, 1699 .offset = 94, 1700 .width = 1, 1701 }, 1702 [VCAP_KF_L3_RT_IS] = { 1703 .type = VCAP_FIELD_BIT, 1704 .offset = 95, 1705 .width = 1, 1706 }, 1707 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 1708 .type = VCAP_FIELD_BIT, 1709 .offset = 96, 1710 .width = 1, 1711 }, 1712 [VCAP_KF_MIRROR_PROBE] = { 1713 .type = VCAP_FIELD_U32, 1714 .offset = 97, 1715 .width = 2, 1716 }, 1717 [VCAP_KF_L2_DMAC] = { 1718 .type = VCAP_FIELD_U48, 1719 .offset = 99, 1720 .width = 48, 1721 }, 1722 [VCAP_KF_L2_SMAC] = { 1723 .type = VCAP_FIELD_U48, 1724 .offset = 147, 1725 .width = 48, 1726 }, 1727 [VCAP_KF_ETYPE_LEN_IS] = { 1728 .type = VCAP_FIELD_BIT, 1729 .offset = 195, 1730 .width = 1, 1731 }, 1732 [VCAP_KF_ETYPE] = { 1733 .type = VCAP_FIELD_U32, 1734 .offset = 196, 1735 .width = 16, 1736 }, 1737 [VCAP_KF_L2_PAYLOAD_ETYPE] = { 1738 .type = VCAP_FIELD_U64, 1739 .offset = 212, 1740 .width = 64, 1741 }, 1742 [VCAP_KF_OAM_CCM_CNTS_EQ0] = { 1743 .type = VCAP_FIELD_BIT, 1744 .offset = 276, 1745 .width = 1, 1746 }, 1747 [VCAP_KF_OAM_Y1731_IS] = { 1748 .type = VCAP_FIELD_BIT, 1749 .offset = 277, 1750 .width = 1, 1751 }, 1752 }; 1753 1754 static const struct vcap_field es2_arp_keyfield[] = { 1755 [VCAP_KF_TYPE] = { 1756 .type = VCAP_FIELD_U32, 1757 .offset = 0, 1758 .width = 3, 1759 }, 1760 [VCAP_KF_LOOKUP_FIRST_IS] = { 1761 .type = VCAP_FIELD_BIT, 1762 .offset = 3, 1763 .width = 1, 1764 }, 1765 [VCAP_KF_ACL_GRP_ID] = { 1766 .type = VCAP_FIELD_U32, 1767 .offset = 4, 1768 .width = 8, 1769 }, 1770 [VCAP_KF_PROT_ACTIVE] = { 1771 .type = VCAP_FIELD_BIT, 1772 .offset = 12, 1773 .width = 1, 1774 }, 1775 [VCAP_KF_L2_MC_IS] = { 1776 .type = VCAP_FIELD_BIT, 1777 .offset = 13, 1778 .width = 1, 1779 }, 1780 [VCAP_KF_L2_BC_IS] = { 1781 .type = VCAP_FIELD_BIT, 1782 .offset = 14, 1783 .width = 1, 1784 }, 1785 [VCAP_KF_ISDX_GT0_IS] = { 1786 .type = VCAP_FIELD_BIT, 1787 .offset = 15, 1788 .width = 1, 1789 }, 1790 [VCAP_KF_ISDX_CLS] = { 1791 .type = VCAP_FIELD_U32, 1792 .offset = 16, 1793 .width = 12, 1794 }, 1795 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1796 .type = VCAP_FIELD_BIT, 1797 .offset = 28, 1798 .width = 1, 1799 }, 1800 [VCAP_KF_8021Q_VID_CLS] = { 1801 .type = VCAP_FIELD_U32, 1802 .offset = 29, 1803 .width = 13, 1804 }, 1805 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1806 .type = VCAP_FIELD_U32, 1807 .offset = 42, 1808 .width = 3, 1809 }, 1810 [VCAP_KF_IF_EGR_PORT_MASK] = { 1811 .type = VCAP_FIELD_U32, 1812 .offset = 45, 1813 .width = 32, 1814 }, 1815 [VCAP_KF_IF_IGR_PORT_SEL] = { 1816 .type = VCAP_FIELD_BIT, 1817 .offset = 77, 1818 .width = 1, 1819 }, 1820 [VCAP_KF_IF_IGR_PORT] = { 1821 .type = VCAP_FIELD_U32, 1822 .offset = 78, 1823 .width = 9, 1824 }, 1825 [VCAP_KF_8021Q_PCP_CLS] = { 1826 .type = VCAP_FIELD_U32, 1827 .offset = 87, 1828 .width = 3, 1829 }, 1830 [VCAP_KF_8021Q_DEI_CLS] = { 1831 .type = VCAP_FIELD_BIT, 1832 .offset = 90, 1833 .width = 1, 1834 }, 1835 [VCAP_KF_COSID_CLS] = { 1836 .type = VCAP_FIELD_U32, 1837 .offset = 91, 1838 .width = 3, 1839 }, 1840 [VCAP_KF_L3_DPL_CLS] = { 1841 .type = VCAP_FIELD_BIT, 1842 .offset = 94, 1843 .width = 1, 1844 }, 1845 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 1846 .type = VCAP_FIELD_BIT, 1847 .offset = 95, 1848 .width = 1, 1849 }, 1850 [VCAP_KF_MIRROR_PROBE] = { 1851 .type = VCAP_FIELD_U32, 1852 .offset = 96, 1853 .width = 2, 1854 }, 1855 [VCAP_KF_L2_SMAC] = { 1856 .type = VCAP_FIELD_U48, 1857 .offset = 98, 1858 .width = 48, 1859 }, 1860 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { 1861 .type = VCAP_FIELD_BIT, 1862 .offset = 146, 1863 .width = 1, 1864 }, 1865 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { 1866 .type = VCAP_FIELD_BIT, 1867 .offset = 147, 1868 .width = 1, 1869 }, 1870 [VCAP_KF_ARP_LEN_OK_IS] = { 1871 .type = VCAP_FIELD_BIT, 1872 .offset = 148, 1873 .width = 1, 1874 }, 1875 [VCAP_KF_ARP_TGT_MATCH_IS] = { 1876 .type = VCAP_FIELD_BIT, 1877 .offset = 149, 1878 .width = 1, 1879 }, 1880 [VCAP_KF_ARP_SENDER_MATCH_IS] = { 1881 .type = VCAP_FIELD_BIT, 1882 .offset = 150, 1883 .width = 1, 1884 }, 1885 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { 1886 .type = VCAP_FIELD_BIT, 1887 .offset = 151, 1888 .width = 1, 1889 }, 1890 [VCAP_KF_ARP_OPCODE] = { 1891 .type = VCAP_FIELD_U32, 1892 .offset = 152, 1893 .width = 2, 1894 }, 1895 [VCAP_KF_L3_IP4_DIP] = { 1896 .type = VCAP_FIELD_U32, 1897 .offset = 154, 1898 .width = 32, 1899 }, 1900 [VCAP_KF_L3_IP4_SIP] = { 1901 .type = VCAP_FIELD_U32, 1902 .offset = 186, 1903 .width = 32, 1904 }, 1905 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1906 .type = VCAP_FIELD_BIT, 1907 .offset = 218, 1908 .width = 1, 1909 }, 1910 }; 1911 1912 static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { 1913 [VCAP_KF_TYPE] = { 1914 .type = VCAP_FIELD_U32, 1915 .offset = 0, 1916 .width = 3, 1917 }, 1918 [VCAP_KF_LOOKUP_FIRST_IS] = { 1919 .type = VCAP_FIELD_BIT, 1920 .offset = 3, 1921 .width = 1, 1922 }, 1923 [VCAP_KF_ACL_GRP_ID] = { 1924 .type = VCAP_FIELD_U32, 1925 .offset = 4, 1926 .width = 8, 1927 }, 1928 [VCAP_KF_PROT_ACTIVE] = { 1929 .type = VCAP_FIELD_BIT, 1930 .offset = 12, 1931 .width = 1, 1932 }, 1933 [VCAP_KF_L2_MC_IS] = { 1934 .type = VCAP_FIELD_BIT, 1935 .offset = 13, 1936 .width = 1, 1937 }, 1938 [VCAP_KF_L2_BC_IS] = { 1939 .type = VCAP_FIELD_BIT, 1940 .offset = 14, 1941 .width = 1, 1942 }, 1943 [VCAP_KF_ISDX_GT0_IS] = { 1944 .type = VCAP_FIELD_BIT, 1945 .offset = 15, 1946 .width = 1, 1947 }, 1948 [VCAP_KF_ISDX_CLS] = { 1949 .type = VCAP_FIELD_U32, 1950 .offset = 16, 1951 .width = 12, 1952 }, 1953 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1954 .type = VCAP_FIELD_BIT, 1955 .offset = 28, 1956 .width = 1, 1957 }, 1958 [VCAP_KF_8021Q_VID_CLS] = { 1959 .type = VCAP_FIELD_U32, 1960 .offset = 29, 1961 .width = 13, 1962 }, 1963 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1964 .type = VCAP_FIELD_U32, 1965 .offset = 42, 1966 .width = 3, 1967 }, 1968 [VCAP_KF_IF_EGR_PORT_MASK] = { 1969 .type = VCAP_FIELD_U32, 1970 .offset = 45, 1971 .width = 32, 1972 }, 1973 [VCAP_KF_IF_IGR_PORT_SEL] = { 1974 .type = VCAP_FIELD_BIT, 1975 .offset = 77, 1976 .width = 1, 1977 }, 1978 [VCAP_KF_IF_IGR_PORT] = { 1979 .type = VCAP_FIELD_U32, 1980 .offset = 78, 1981 .width = 9, 1982 }, 1983 [VCAP_KF_8021Q_PCP_CLS] = { 1984 .type = VCAP_FIELD_U32, 1985 .offset = 87, 1986 .width = 3, 1987 }, 1988 [VCAP_KF_8021Q_DEI_CLS] = { 1989 .type = VCAP_FIELD_BIT, 1990 .offset = 90, 1991 .width = 1, 1992 }, 1993 [VCAP_KF_COSID_CLS] = { 1994 .type = VCAP_FIELD_U32, 1995 .offset = 91, 1996 .width = 3, 1997 }, 1998 [VCAP_KF_L3_DPL_CLS] = { 1999 .type = VCAP_FIELD_BIT, 2000 .offset = 94, 2001 .width = 1, 2002 }, 2003 [VCAP_KF_L3_RT_IS] = { 2004 .type = VCAP_FIELD_BIT, 2005 .offset = 95, 2006 .width = 1, 2007 }, 2008 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 2009 .type = VCAP_FIELD_BIT, 2010 .offset = 96, 2011 .width = 1, 2012 }, 2013 [VCAP_KF_MIRROR_PROBE] = { 2014 .type = VCAP_FIELD_U32, 2015 .offset = 97, 2016 .width = 2, 2017 }, 2018 [VCAP_KF_IP4_IS] = { 2019 .type = VCAP_FIELD_BIT, 2020 .offset = 99, 2021 .width = 1, 2022 }, 2023 [VCAP_KF_L3_FRAGMENT_TYPE] = { 2024 .type = VCAP_FIELD_U32, 2025 .offset = 100, 2026 .width = 2, 2027 }, 2028 [VCAP_KF_L3_OPTIONS_IS] = { 2029 .type = VCAP_FIELD_BIT, 2030 .offset = 102, 2031 .width = 1, 2032 }, 2033 [VCAP_KF_L3_TTL_GT0] = { 2034 .type = VCAP_FIELD_BIT, 2035 .offset = 103, 2036 .width = 1, 2037 }, 2038 [VCAP_KF_L3_TOS] = { 2039 .type = VCAP_FIELD_U32, 2040 .offset = 104, 2041 .width = 8, 2042 }, 2043 [VCAP_KF_L3_IP4_DIP] = { 2044 .type = VCAP_FIELD_U32, 2045 .offset = 112, 2046 .width = 32, 2047 }, 2048 [VCAP_KF_L3_IP4_SIP] = { 2049 .type = VCAP_FIELD_U32, 2050 .offset = 144, 2051 .width = 32, 2052 }, 2053 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 2054 .type = VCAP_FIELD_BIT, 2055 .offset = 176, 2056 .width = 1, 2057 }, 2058 [VCAP_KF_TCP_IS] = { 2059 .type = VCAP_FIELD_BIT, 2060 .offset = 177, 2061 .width = 1, 2062 }, 2063 [VCAP_KF_L4_DPORT] = { 2064 .type = VCAP_FIELD_U32, 2065 .offset = 178, 2066 .width = 16, 2067 }, 2068 [VCAP_KF_L4_SPORT] = { 2069 .type = VCAP_FIELD_U32, 2070 .offset = 194, 2071 .width = 16, 2072 }, 2073 [VCAP_KF_L4_RNG] = { 2074 .type = VCAP_FIELD_U32, 2075 .offset = 210, 2076 .width = 16, 2077 }, 2078 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 2079 .type = VCAP_FIELD_BIT, 2080 .offset = 226, 2081 .width = 1, 2082 }, 2083 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 2084 .type = VCAP_FIELD_BIT, 2085 .offset = 227, 2086 .width = 1, 2087 }, 2088 [VCAP_KF_L4_FIN] = { 2089 .type = VCAP_FIELD_BIT, 2090 .offset = 228, 2091 .width = 1, 2092 }, 2093 [VCAP_KF_L4_SYN] = { 2094 .type = VCAP_FIELD_BIT, 2095 .offset = 229, 2096 .width = 1, 2097 }, 2098 [VCAP_KF_L4_RST] = { 2099 .type = VCAP_FIELD_BIT, 2100 .offset = 230, 2101 .width = 1, 2102 }, 2103 [VCAP_KF_L4_PSH] = { 2104 .type = VCAP_FIELD_BIT, 2105 .offset = 231, 2106 .width = 1, 2107 }, 2108 [VCAP_KF_L4_ACK] = { 2109 .type = VCAP_FIELD_BIT, 2110 .offset = 232, 2111 .width = 1, 2112 }, 2113 [VCAP_KF_L4_URG] = { 2114 .type = VCAP_FIELD_BIT, 2115 .offset = 233, 2116 .width = 1, 2117 }, 2118 [VCAP_KF_L4_PAYLOAD] = { 2119 .type = VCAP_FIELD_U64, 2120 .offset = 234, 2121 .width = 64, 2122 }, 2123 }; 2124 2125 static const struct vcap_field es2_ip4_other_keyfield[] = { 2126 [VCAP_KF_TYPE] = { 2127 .type = VCAP_FIELD_U32, 2128 .offset = 0, 2129 .width = 3, 2130 }, 2131 [VCAP_KF_LOOKUP_FIRST_IS] = { 2132 .type = VCAP_FIELD_BIT, 2133 .offset = 3, 2134 .width = 1, 2135 }, 2136 [VCAP_KF_ACL_GRP_ID] = { 2137 .type = VCAP_FIELD_U32, 2138 .offset = 4, 2139 .width = 8, 2140 }, 2141 [VCAP_KF_PROT_ACTIVE] = { 2142 .type = VCAP_FIELD_BIT, 2143 .offset = 12, 2144 .width = 1, 2145 }, 2146 [VCAP_KF_L2_MC_IS] = { 2147 .type = VCAP_FIELD_BIT, 2148 .offset = 13, 2149 .width = 1, 2150 }, 2151 [VCAP_KF_L2_BC_IS] = { 2152 .type = VCAP_FIELD_BIT, 2153 .offset = 14, 2154 .width = 1, 2155 }, 2156 [VCAP_KF_ISDX_GT0_IS] = { 2157 .type = VCAP_FIELD_BIT, 2158 .offset = 15, 2159 .width = 1, 2160 }, 2161 [VCAP_KF_ISDX_CLS] = { 2162 .type = VCAP_FIELD_U32, 2163 .offset = 16, 2164 .width = 12, 2165 }, 2166 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 2167 .type = VCAP_FIELD_BIT, 2168 .offset = 28, 2169 .width = 1, 2170 }, 2171 [VCAP_KF_8021Q_VID_CLS] = { 2172 .type = VCAP_FIELD_U32, 2173 .offset = 29, 2174 .width = 13, 2175 }, 2176 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 2177 .type = VCAP_FIELD_U32, 2178 .offset = 42, 2179 .width = 3, 2180 }, 2181 [VCAP_KF_IF_EGR_PORT_MASK] = { 2182 .type = VCAP_FIELD_U32, 2183 .offset = 45, 2184 .width = 32, 2185 }, 2186 [VCAP_KF_IF_IGR_PORT_SEL] = { 2187 .type = VCAP_FIELD_BIT, 2188 .offset = 77, 2189 .width = 1, 2190 }, 2191 [VCAP_KF_IF_IGR_PORT] = { 2192 .type = VCAP_FIELD_U32, 2193 .offset = 78, 2194 .width = 9, 2195 }, 2196 [VCAP_KF_8021Q_PCP_CLS] = { 2197 .type = VCAP_FIELD_U32, 2198 .offset = 87, 2199 .width = 3, 2200 }, 2201 [VCAP_KF_8021Q_DEI_CLS] = { 2202 .type = VCAP_FIELD_BIT, 2203 .offset = 90, 2204 .width = 1, 2205 }, 2206 [VCAP_KF_COSID_CLS] = { 2207 .type = VCAP_FIELD_U32, 2208 .offset = 91, 2209 .width = 3, 2210 }, 2211 [VCAP_KF_L3_DPL_CLS] = { 2212 .type = VCAP_FIELD_BIT, 2213 .offset = 94, 2214 .width = 1, 2215 }, 2216 [VCAP_KF_L3_RT_IS] = { 2217 .type = VCAP_FIELD_BIT, 2218 .offset = 95, 2219 .width = 1, 2220 }, 2221 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 2222 .type = VCAP_FIELD_BIT, 2223 .offset = 96, 2224 .width = 1, 2225 }, 2226 [VCAP_KF_MIRROR_PROBE] = { 2227 .type = VCAP_FIELD_U32, 2228 .offset = 97, 2229 .width = 2, 2230 }, 2231 [VCAP_KF_IP4_IS] = { 2232 .type = VCAP_FIELD_BIT, 2233 .offset = 99, 2234 .width = 1, 2235 }, 2236 [VCAP_KF_L3_FRAGMENT_TYPE] = { 2237 .type = VCAP_FIELD_U32, 2238 .offset = 100, 2239 .width = 2, 2240 }, 2241 [VCAP_KF_L3_OPTIONS_IS] = { 2242 .type = VCAP_FIELD_BIT, 2243 .offset = 102, 2244 .width = 1, 2245 }, 2246 [VCAP_KF_L3_TTL_GT0] = { 2247 .type = VCAP_FIELD_BIT, 2248 .offset = 103, 2249 .width = 1, 2250 }, 2251 [VCAP_KF_L3_TOS] = { 2252 .type = VCAP_FIELD_U32, 2253 .offset = 104, 2254 .width = 8, 2255 }, 2256 [VCAP_KF_L3_IP4_DIP] = { 2257 .type = VCAP_FIELD_U32, 2258 .offset = 112, 2259 .width = 32, 2260 }, 2261 [VCAP_KF_L3_IP4_SIP] = { 2262 .type = VCAP_FIELD_U32, 2263 .offset = 144, 2264 .width = 32, 2265 }, 2266 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 2267 .type = VCAP_FIELD_BIT, 2268 .offset = 176, 2269 .width = 1, 2270 }, 2271 [VCAP_KF_L3_IP_PROTO] = { 2272 .type = VCAP_FIELD_U32, 2273 .offset = 177, 2274 .width = 8, 2275 }, 2276 [VCAP_KF_L3_PAYLOAD] = { 2277 .type = VCAP_FIELD_U112, 2278 .offset = 185, 2279 .width = 96, 2280 }, 2281 }; 2282 2283 static const struct vcap_field es2_ip_7tuple_keyfield[] = { 2284 [VCAP_KF_LOOKUP_FIRST_IS] = { 2285 .type = VCAP_FIELD_BIT, 2286 .offset = 0, 2287 .width = 1, 2288 }, 2289 [VCAP_KF_ACL_GRP_ID] = { 2290 .type = VCAP_FIELD_U32, 2291 .offset = 1, 2292 .width = 8, 2293 }, 2294 [VCAP_KF_PROT_ACTIVE] = { 2295 .type = VCAP_FIELD_BIT, 2296 .offset = 9, 2297 .width = 1, 2298 }, 2299 [VCAP_KF_L2_MC_IS] = { 2300 .type = VCAP_FIELD_BIT, 2301 .offset = 10, 2302 .width = 1, 2303 }, 2304 [VCAP_KF_L2_BC_IS] = { 2305 .type = VCAP_FIELD_BIT, 2306 .offset = 11, 2307 .width = 1, 2308 }, 2309 [VCAP_KF_ISDX_GT0_IS] = { 2310 .type = VCAP_FIELD_BIT, 2311 .offset = 12, 2312 .width = 1, 2313 }, 2314 [VCAP_KF_ISDX_CLS] = { 2315 .type = VCAP_FIELD_U32, 2316 .offset = 13, 2317 .width = 12, 2318 }, 2319 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 2320 .type = VCAP_FIELD_BIT, 2321 .offset = 25, 2322 .width = 1, 2323 }, 2324 [VCAP_KF_8021Q_VID_CLS] = { 2325 .type = VCAP_FIELD_U32, 2326 .offset = 26, 2327 .width = 13, 2328 }, 2329 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 2330 .type = VCAP_FIELD_U32, 2331 .offset = 39, 2332 .width = 3, 2333 }, 2334 [VCAP_KF_IF_EGR_PORT_MASK] = { 2335 .type = VCAP_FIELD_U32, 2336 .offset = 42, 2337 .width = 32, 2338 }, 2339 [VCAP_KF_IF_IGR_PORT_SEL] = { 2340 .type = VCAP_FIELD_BIT, 2341 .offset = 74, 2342 .width = 1, 2343 }, 2344 [VCAP_KF_IF_IGR_PORT] = { 2345 .type = VCAP_FIELD_U32, 2346 .offset = 75, 2347 .width = 9, 2348 }, 2349 [VCAP_KF_8021Q_PCP_CLS] = { 2350 .type = VCAP_FIELD_U32, 2351 .offset = 84, 2352 .width = 3, 2353 }, 2354 [VCAP_KF_8021Q_DEI_CLS] = { 2355 .type = VCAP_FIELD_BIT, 2356 .offset = 87, 2357 .width = 1, 2358 }, 2359 [VCAP_KF_COSID_CLS] = { 2360 .type = VCAP_FIELD_U32, 2361 .offset = 88, 2362 .width = 3, 2363 }, 2364 [VCAP_KF_L3_DPL_CLS] = { 2365 .type = VCAP_FIELD_BIT, 2366 .offset = 91, 2367 .width = 1, 2368 }, 2369 [VCAP_KF_L3_RT_IS] = { 2370 .type = VCAP_FIELD_BIT, 2371 .offset = 92, 2372 .width = 1, 2373 }, 2374 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 2375 .type = VCAP_FIELD_BIT, 2376 .offset = 93, 2377 .width = 1, 2378 }, 2379 [VCAP_KF_MIRROR_PROBE] = { 2380 .type = VCAP_FIELD_U32, 2381 .offset = 94, 2382 .width = 2, 2383 }, 2384 [VCAP_KF_L2_DMAC] = { 2385 .type = VCAP_FIELD_U48, 2386 .offset = 96, 2387 .width = 48, 2388 }, 2389 [VCAP_KF_L2_SMAC] = { 2390 .type = VCAP_FIELD_U48, 2391 .offset = 144, 2392 .width = 48, 2393 }, 2394 [VCAP_KF_IP4_IS] = { 2395 .type = VCAP_FIELD_BIT, 2396 .offset = 192, 2397 .width = 1, 2398 }, 2399 [VCAP_KF_L3_TTL_GT0] = { 2400 .type = VCAP_FIELD_BIT, 2401 .offset = 193, 2402 .width = 1, 2403 }, 2404 [VCAP_KF_L3_TOS] = { 2405 .type = VCAP_FIELD_U32, 2406 .offset = 194, 2407 .width = 8, 2408 }, 2409 [VCAP_KF_L3_IP6_DIP] = { 2410 .type = VCAP_FIELD_U128, 2411 .offset = 202, 2412 .width = 128, 2413 }, 2414 [VCAP_KF_L3_IP6_SIP] = { 2415 .type = VCAP_FIELD_U128, 2416 .offset = 330, 2417 .width = 128, 2418 }, 2419 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 2420 .type = VCAP_FIELD_BIT, 2421 .offset = 458, 2422 .width = 1, 2423 }, 2424 [VCAP_KF_TCP_UDP_IS] = { 2425 .type = VCAP_FIELD_BIT, 2426 .offset = 459, 2427 .width = 1, 2428 }, 2429 [VCAP_KF_TCP_IS] = { 2430 .type = VCAP_FIELD_BIT, 2431 .offset = 460, 2432 .width = 1, 2433 }, 2434 [VCAP_KF_L4_DPORT] = { 2435 .type = VCAP_FIELD_U32, 2436 .offset = 461, 2437 .width = 16, 2438 }, 2439 [VCAP_KF_L4_SPORT] = { 2440 .type = VCAP_FIELD_U32, 2441 .offset = 477, 2442 .width = 16, 2443 }, 2444 [VCAP_KF_L4_RNG] = { 2445 .type = VCAP_FIELD_U32, 2446 .offset = 493, 2447 .width = 16, 2448 }, 2449 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 2450 .type = VCAP_FIELD_BIT, 2451 .offset = 509, 2452 .width = 1, 2453 }, 2454 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 2455 .type = VCAP_FIELD_BIT, 2456 .offset = 510, 2457 .width = 1, 2458 }, 2459 [VCAP_KF_L4_FIN] = { 2460 .type = VCAP_FIELD_BIT, 2461 .offset = 511, 2462 .width = 1, 2463 }, 2464 [VCAP_KF_L4_SYN] = { 2465 .type = VCAP_FIELD_BIT, 2466 .offset = 512, 2467 .width = 1, 2468 }, 2469 [VCAP_KF_L4_RST] = { 2470 .type = VCAP_FIELD_BIT, 2471 .offset = 513, 2472 .width = 1, 2473 }, 2474 [VCAP_KF_L4_PSH] = { 2475 .type = VCAP_FIELD_BIT, 2476 .offset = 514, 2477 .width = 1, 2478 }, 2479 [VCAP_KF_L4_ACK] = { 2480 .type = VCAP_FIELD_BIT, 2481 .offset = 515, 2482 .width = 1, 2483 }, 2484 [VCAP_KF_L4_URG] = { 2485 .type = VCAP_FIELD_BIT, 2486 .offset = 516, 2487 .width = 1, 2488 }, 2489 [VCAP_KF_L4_PAYLOAD] = { 2490 .type = VCAP_FIELD_U64, 2491 .offset = 517, 2492 .width = 64, 2493 }, 2494 }; 2495 2496 static const struct vcap_field es2_ip4_vid_keyfield[] = { 2497 [VCAP_KF_LOOKUP_FIRST_IS] = { 2498 .type = VCAP_FIELD_BIT, 2499 .offset = 0, 2500 .width = 1, 2501 }, 2502 [VCAP_KF_ACL_GRP_ID] = { 2503 .type = VCAP_FIELD_U32, 2504 .offset = 1, 2505 .width = 8, 2506 }, 2507 [VCAP_KF_PROT_ACTIVE] = { 2508 .type = VCAP_FIELD_BIT, 2509 .offset = 9, 2510 .width = 1, 2511 }, 2512 [VCAP_KF_L2_MC_IS] = { 2513 .type = VCAP_FIELD_BIT, 2514 .offset = 10, 2515 .width = 1, 2516 }, 2517 [VCAP_KF_L2_BC_IS] = { 2518 .type = VCAP_FIELD_BIT, 2519 .offset = 11, 2520 .width = 1, 2521 }, 2522 [VCAP_KF_ISDX_GT0_IS] = { 2523 .type = VCAP_FIELD_BIT, 2524 .offset = 12, 2525 .width = 1, 2526 }, 2527 [VCAP_KF_ISDX_CLS] = { 2528 .type = VCAP_FIELD_U32, 2529 .offset = 13, 2530 .width = 12, 2531 }, 2532 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 2533 .type = VCAP_FIELD_BIT, 2534 .offset = 25, 2535 .width = 1, 2536 }, 2537 [VCAP_KF_8021Q_VID_CLS] = { 2538 .type = VCAP_FIELD_U32, 2539 .offset = 26, 2540 .width = 13, 2541 }, 2542 [VCAP_KF_8021Q_PCP_CLS] = { 2543 .type = VCAP_FIELD_U32, 2544 .offset = 39, 2545 .width = 3, 2546 }, 2547 [VCAP_KF_8021Q_DEI_CLS] = { 2548 .type = VCAP_FIELD_BIT, 2549 .offset = 42, 2550 .width = 1, 2551 }, 2552 [VCAP_KF_COSID_CLS] = { 2553 .type = VCAP_FIELD_U32, 2554 .offset = 43, 2555 .width = 3, 2556 }, 2557 [VCAP_KF_L3_DPL_CLS] = { 2558 .type = VCAP_FIELD_BIT, 2559 .offset = 46, 2560 .width = 1, 2561 }, 2562 [VCAP_KF_L3_RT_IS] = { 2563 .type = VCAP_FIELD_BIT, 2564 .offset = 47, 2565 .width = 1, 2566 }, 2567 [VCAP_KF_ES0_ISDX_KEY_ENA] = { 2568 .type = VCAP_FIELD_BIT, 2569 .offset = 48, 2570 .width = 1, 2571 }, 2572 [VCAP_KF_MIRROR_PROBE] = { 2573 .type = VCAP_FIELD_U32, 2574 .offset = 49, 2575 .width = 2, 2576 }, 2577 [VCAP_KF_IP4_IS] = { 2578 .type = VCAP_FIELD_BIT, 2579 .offset = 51, 2580 .width = 1, 2581 }, 2582 [VCAP_KF_L3_IP4_DIP] = { 2583 .type = VCAP_FIELD_U32, 2584 .offset = 52, 2585 .width = 32, 2586 }, 2587 [VCAP_KF_L3_IP4_SIP] = { 2588 .type = VCAP_FIELD_U32, 2589 .offset = 84, 2590 .width = 32, 2591 }, 2592 [VCAP_KF_L4_RNG] = { 2593 .type = VCAP_FIELD_U32, 2594 .offset = 116, 2595 .width = 16, 2596 }, 2597 }; 2598 2599 static const struct vcap_field es2_ip6_vid_keyfield[] = { 2600 [VCAP_KF_TYPE] = { 2601 .type = VCAP_FIELD_U32, 2602 .offset = 0, 2603 .width = 3, 2604 }, 2605 [VCAP_KF_LOOKUP_FIRST_IS] = { 2606 .type = VCAP_FIELD_BIT, 2607 .offset = 3, 2608 .width = 1, 2609 }, 2610 [VCAP_KF_ACL_GRP_ID] = { 2611 .type = VCAP_FIELD_U32, 2612 .offset = 4, 2613 .width = 8, 2614 }, 2615 [VCAP_KF_PROT_ACTIVE] = { 2616 .type = VCAP_FIELD_BIT, 2617 .offset = 12, 2618 .width = 1, 2619 }, 2620 [VCAP_KF_L2_MC_IS] = { 2621 .type = VCAP_FIELD_BIT, 2622 .offset = 13, 2623 .width = 1, 2624 }, 2625 [VCAP_KF_L2_BC_IS] = { 2626 .type = VCAP_FIELD_BIT, 2627 .offset = 14, 2628 .width = 1, 2629 }, 2630 [VCAP_KF_ISDX_GT0_IS] = { 2631 .type = VCAP_FIELD_BIT, 2632 .offset = 15, 2633 .width = 1, 2634 }, 2635 [VCAP_KF_ISDX_CLS] = { 2636 .type = VCAP_FIELD_U32, 2637 .offset = 16, 2638 .width = 12, 2639 }, 2640 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 2641 .type = VCAP_FIELD_BIT, 2642 .offset = 28, 2643 .width = 1, 2644 }, 2645 [VCAP_KF_8021Q_VID_CLS] = { 2646 .type = VCAP_FIELD_U32, 2647 .offset = 29, 2648 .width = 13, 2649 }, 2650 [VCAP_KF_L3_RT_IS] = { 2651 .type = VCAP_FIELD_BIT, 2652 .offset = 42, 2653 .width = 1, 2654 }, 2655 [VCAP_KF_L3_IP6_DIP] = { 2656 .type = VCAP_FIELD_U128, 2657 .offset = 43, 2658 .width = 128, 2659 }, 2660 [VCAP_KF_L3_IP6_SIP] = { 2661 .type = VCAP_FIELD_U128, 2662 .offset = 171, 2663 .width = 128, 2664 }, 2665 }; 2666 2667 /* keyfield_set */ 2668 static const struct vcap_set is0_keyfield_set[] = { 2669 [VCAP_KFS_LL_FULL] = { 2670 .type_id = 0, 2671 .sw_per_item = 6, 2672 .sw_cnt = 2, 2673 }, 2674 [VCAP_KFS_NORMAL_7TUPLE] = { 2675 .type_id = 0, 2676 .sw_per_item = 12, 2677 .sw_cnt = 1, 2678 }, 2679 [VCAP_KFS_NORMAL_5TUPLE_IP4] = { 2680 .type_id = 2, 2681 .sw_per_item = 6, 2682 .sw_cnt = 2, 2683 }, 2684 [VCAP_KFS_PURE_5TUPLE_IP4] = { 2685 .type_id = 2, 2686 .sw_per_item = 3, 2687 .sw_cnt = 4, 2688 }, 2689 [VCAP_KFS_ETAG] = { 2690 .type_id = 3, 2691 .sw_per_item = 2, 2692 .sw_cnt = 6, 2693 }, 2694 }; 2695 2696 static const struct vcap_set is2_keyfield_set[] = { 2697 [VCAP_KFS_MAC_ETYPE] = { 2698 .type_id = 0, 2699 .sw_per_item = 6, 2700 .sw_cnt = 2, 2701 }, 2702 [VCAP_KFS_ARP] = { 2703 .type_id = 3, 2704 .sw_per_item = 6, 2705 .sw_cnt = 2, 2706 }, 2707 [VCAP_KFS_IP4_TCP_UDP] = { 2708 .type_id = 4, 2709 .sw_per_item = 6, 2710 .sw_cnt = 2, 2711 }, 2712 [VCAP_KFS_IP4_OTHER] = { 2713 .type_id = 5, 2714 .sw_per_item = 6, 2715 .sw_cnt = 2, 2716 }, 2717 [VCAP_KFS_IP6_STD] = { 2718 .type_id = 6, 2719 .sw_per_item = 6, 2720 .sw_cnt = 2, 2721 }, 2722 [VCAP_KFS_IP_7TUPLE] = { 2723 .type_id = 1, 2724 .sw_per_item = 12, 2725 .sw_cnt = 1, 2726 }, 2727 }; 2728 2729 static const struct vcap_set es2_keyfield_set[] = { 2730 [VCAP_KFS_MAC_ETYPE] = { 2731 .type_id = 0, 2732 .sw_per_item = 6, 2733 .sw_cnt = 2, 2734 }, 2735 [VCAP_KFS_ARP] = { 2736 .type_id = 1, 2737 .sw_per_item = 6, 2738 .sw_cnt = 2, 2739 }, 2740 [VCAP_KFS_IP4_TCP_UDP] = { 2741 .type_id = 2, 2742 .sw_per_item = 6, 2743 .sw_cnt = 2, 2744 }, 2745 [VCAP_KFS_IP4_OTHER] = { 2746 .type_id = 3, 2747 .sw_per_item = 6, 2748 .sw_cnt = 2, 2749 }, 2750 [VCAP_KFS_IP_7TUPLE] = { 2751 .type_id = -1, 2752 .sw_per_item = 12, 2753 .sw_cnt = 1, 2754 }, 2755 [VCAP_KFS_IP4_VID] = { 2756 .type_id = -1, 2757 .sw_per_item = 3, 2758 .sw_cnt = 4, 2759 }, 2760 [VCAP_KFS_IP6_VID] = { 2761 .type_id = 5, 2762 .sw_per_item = 6, 2763 .sw_cnt = 2, 2764 }, 2765 }; 2766 2767 /* keyfield_set map */ 2768 static const struct vcap_field *is0_keyfield_set_map[] = { 2769 [VCAP_KFS_LL_FULL] = is0_ll_full_keyfield, 2770 [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, 2771 [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, 2772 [VCAP_KFS_PURE_5TUPLE_IP4] = is0_pure_5tuple_ip4_keyfield, 2773 [VCAP_KFS_ETAG] = is0_etag_keyfield, 2774 }; 2775 2776 static const struct vcap_field *is2_keyfield_set_map[] = { 2777 [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, 2778 [VCAP_KFS_ARP] = is2_arp_keyfield, 2779 [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, 2780 [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, 2781 [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, 2782 [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, 2783 }; 2784 2785 static const struct vcap_field *es2_keyfield_set_map[] = { 2786 [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, 2787 [VCAP_KFS_ARP] = es2_arp_keyfield, 2788 [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, 2789 [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, 2790 [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, 2791 [VCAP_KFS_IP4_VID] = es2_ip4_vid_keyfield, 2792 [VCAP_KFS_IP6_VID] = es2_ip6_vid_keyfield, 2793 }; 2794 2795 /* keyfield_set map sizes */ 2796 static int is0_keyfield_set_map_size[] = { 2797 [VCAP_KFS_LL_FULL] = ARRAY_SIZE(is0_ll_full_keyfield), 2798 [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), 2799 [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), 2800 [VCAP_KFS_PURE_5TUPLE_IP4] = ARRAY_SIZE(is0_pure_5tuple_ip4_keyfield), 2801 [VCAP_KFS_ETAG] = ARRAY_SIZE(is0_etag_keyfield), 2802 }; 2803 2804 static int is2_keyfield_set_map_size[] = { 2805 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), 2806 [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), 2807 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), 2808 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), 2809 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), 2810 [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), 2811 }; 2812 2813 static int es2_keyfield_set_map_size[] = { 2814 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), 2815 [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), 2816 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), 2817 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), 2818 [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), 2819 [VCAP_KFS_IP4_VID] = ARRAY_SIZE(es2_ip4_vid_keyfield), 2820 [VCAP_KFS_IP6_VID] = ARRAY_SIZE(es2_ip6_vid_keyfield), 2821 }; 2822 2823 /* actionfields */ 2824 static const struct vcap_field is0_classification_actionfield[] = { 2825 [VCAP_AF_TYPE] = { 2826 .type = VCAP_FIELD_BIT, 2827 .offset = 0, 2828 .width = 1, 2829 }, 2830 [VCAP_AF_DSCP_ENA] = { 2831 .type = VCAP_FIELD_BIT, 2832 .offset = 1, 2833 .width = 1, 2834 }, 2835 [VCAP_AF_DSCP_VAL] = { 2836 .type = VCAP_FIELD_U32, 2837 .offset = 2, 2838 .width = 6, 2839 }, 2840 [VCAP_AF_QOS_ENA] = { 2841 .type = VCAP_FIELD_BIT, 2842 .offset = 12, 2843 .width = 1, 2844 }, 2845 [VCAP_AF_QOS_VAL] = { 2846 .type = VCAP_FIELD_U32, 2847 .offset = 13, 2848 .width = 3, 2849 }, 2850 [VCAP_AF_DP_ENA] = { 2851 .type = VCAP_FIELD_BIT, 2852 .offset = 16, 2853 .width = 1, 2854 }, 2855 [VCAP_AF_DP_VAL] = { 2856 .type = VCAP_FIELD_U32, 2857 .offset = 17, 2858 .width = 2, 2859 }, 2860 [VCAP_AF_DEI_ENA] = { 2861 .type = VCAP_FIELD_BIT, 2862 .offset = 19, 2863 .width = 1, 2864 }, 2865 [VCAP_AF_DEI_VAL] = { 2866 .type = VCAP_FIELD_BIT, 2867 .offset = 20, 2868 .width = 1, 2869 }, 2870 [VCAP_AF_PCP_ENA] = { 2871 .type = VCAP_FIELD_BIT, 2872 .offset = 21, 2873 .width = 1, 2874 }, 2875 [VCAP_AF_PCP_VAL] = { 2876 .type = VCAP_FIELD_U32, 2877 .offset = 22, 2878 .width = 3, 2879 }, 2880 [VCAP_AF_MAP_LOOKUP_SEL] = { 2881 .type = VCAP_FIELD_U32, 2882 .offset = 25, 2883 .width = 2, 2884 }, 2885 [VCAP_AF_MAP_KEY] = { 2886 .type = VCAP_FIELD_U32, 2887 .offset = 27, 2888 .width = 3, 2889 }, 2890 [VCAP_AF_MAP_IDX] = { 2891 .type = VCAP_FIELD_U32, 2892 .offset = 30, 2893 .width = 9, 2894 }, 2895 [VCAP_AF_CLS_VID_SEL] = { 2896 .type = VCAP_FIELD_U32, 2897 .offset = 39, 2898 .width = 3, 2899 }, 2900 [VCAP_AF_VID_VAL] = { 2901 .type = VCAP_FIELD_U32, 2902 .offset = 45, 2903 .width = 13, 2904 }, 2905 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 2906 .type = VCAP_FIELD_BIT, 2907 .offset = 68, 2908 .width = 1, 2909 }, 2910 [VCAP_AF_ISDX_VAL] = { 2911 .type = VCAP_FIELD_U32, 2912 .offset = 69, 2913 .width = 12, 2914 }, 2915 [VCAP_AF_PAG_OVERRIDE_MASK] = { 2916 .type = VCAP_FIELD_U32, 2917 .offset = 109, 2918 .width = 8, 2919 }, 2920 [VCAP_AF_PAG_VAL] = { 2921 .type = VCAP_FIELD_U32, 2922 .offset = 117, 2923 .width = 8, 2924 }, 2925 [VCAP_AF_NXT_IDX_CTRL] = { 2926 .type = VCAP_FIELD_U32, 2927 .offset = 171, 2928 .width = 3, 2929 }, 2930 [VCAP_AF_NXT_IDX] = { 2931 .type = VCAP_FIELD_U32, 2932 .offset = 174, 2933 .width = 12, 2934 }, 2935 }; 2936 2937 static const struct vcap_field is0_full_actionfield[] = { 2938 [VCAP_AF_DSCP_ENA] = { 2939 .type = VCAP_FIELD_BIT, 2940 .offset = 0, 2941 .width = 1, 2942 }, 2943 [VCAP_AF_DSCP_VAL] = { 2944 .type = VCAP_FIELD_U32, 2945 .offset = 1, 2946 .width = 6, 2947 }, 2948 [VCAP_AF_QOS_ENA] = { 2949 .type = VCAP_FIELD_BIT, 2950 .offset = 11, 2951 .width = 1, 2952 }, 2953 [VCAP_AF_QOS_VAL] = { 2954 .type = VCAP_FIELD_U32, 2955 .offset = 12, 2956 .width = 3, 2957 }, 2958 [VCAP_AF_DP_ENA] = { 2959 .type = VCAP_FIELD_BIT, 2960 .offset = 15, 2961 .width = 1, 2962 }, 2963 [VCAP_AF_DP_VAL] = { 2964 .type = VCAP_FIELD_U32, 2965 .offset = 16, 2966 .width = 2, 2967 }, 2968 [VCAP_AF_DEI_ENA] = { 2969 .type = VCAP_FIELD_BIT, 2970 .offset = 18, 2971 .width = 1, 2972 }, 2973 [VCAP_AF_DEI_VAL] = { 2974 .type = VCAP_FIELD_BIT, 2975 .offset = 19, 2976 .width = 1, 2977 }, 2978 [VCAP_AF_PCP_ENA] = { 2979 .type = VCAP_FIELD_BIT, 2980 .offset = 20, 2981 .width = 1, 2982 }, 2983 [VCAP_AF_PCP_VAL] = { 2984 .type = VCAP_FIELD_U32, 2985 .offset = 21, 2986 .width = 3, 2987 }, 2988 [VCAP_AF_MAP_LOOKUP_SEL] = { 2989 .type = VCAP_FIELD_U32, 2990 .offset = 24, 2991 .width = 2, 2992 }, 2993 [VCAP_AF_MAP_KEY] = { 2994 .type = VCAP_FIELD_U32, 2995 .offset = 26, 2996 .width = 3, 2997 }, 2998 [VCAP_AF_MAP_IDX] = { 2999 .type = VCAP_FIELD_U32, 3000 .offset = 29, 3001 .width = 9, 3002 }, 3003 [VCAP_AF_CLS_VID_SEL] = { 3004 .type = VCAP_FIELD_U32, 3005 .offset = 38, 3006 .width = 3, 3007 }, 3008 [VCAP_AF_VID_VAL] = { 3009 .type = VCAP_FIELD_U32, 3010 .offset = 44, 3011 .width = 13, 3012 }, 3013 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 3014 .type = VCAP_FIELD_BIT, 3015 .offset = 67, 3016 .width = 1, 3017 }, 3018 [VCAP_AF_ISDX_VAL] = { 3019 .type = VCAP_FIELD_U32, 3020 .offset = 68, 3021 .width = 12, 3022 }, 3023 [VCAP_AF_MASK_MODE] = { 3024 .type = VCAP_FIELD_U32, 3025 .offset = 80, 3026 .width = 3, 3027 }, 3028 [VCAP_AF_PORT_MASK] = { 3029 .type = VCAP_FIELD_U72, 3030 .offset = 83, 3031 .width = 65, 3032 }, 3033 [VCAP_AF_PAG_OVERRIDE_MASK] = { 3034 .type = VCAP_FIELD_U32, 3035 .offset = 204, 3036 .width = 8, 3037 }, 3038 [VCAP_AF_PAG_VAL] = { 3039 .type = VCAP_FIELD_U32, 3040 .offset = 212, 3041 .width = 8, 3042 }, 3043 [VCAP_AF_NXT_IDX_CTRL] = { 3044 .type = VCAP_FIELD_U32, 3045 .offset = 298, 3046 .width = 3, 3047 }, 3048 [VCAP_AF_NXT_IDX] = { 3049 .type = VCAP_FIELD_U32, 3050 .offset = 301, 3051 .width = 12, 3052 }, 3053 }; 3054 3055 static const struct vcap_field is0_class_reduced_actionfield[] = { 3056 [VCAP_AF_TYPE] = { 3057 .type = VCAP_FIELD_BIT, 3058 .offset = 0, 3059 .width = 1, 3060 }, 3061 [VCAP_AF_QOS_ENA] = { 3062 .type = VCAP_FIELD_BIT, 3063 .offset = 5, 3064 .width = 1, 3065 }, 3066 [VCAP_AF_QOS_VAL] = { 3067 .type = VCAP_FIELD_U32, 3068 .offset = 6, 3069 .width = 3, 3070 }, 3071 [VCAP_AF_DP_ENA] = { 3072 .type = VCAP_FIELD_BIT, 3073 .offset = 9, 3074 .width = 1, 3075 }, 3076 [VCAP_AF_DP_VAL] = { 3077 .type = VCAP_FIELD_U32, 3078 .offset = 10, 3079 .width = 2, 3080 }, 3081 [VCAP_AF_MAP_LOOKUP_SEL] = { 3082 .type = VCAP_FIELD_U32, 3083 .offset = 12, 3084 .width = 2, 3085 }, 3086 [VCAP_AF_MAP_KEY] = { 3087 .type = VCAP_FIELD_U32, 3088 .offset = 14, 3089 .width = 3, 3090 }, 3091 [VCAP_AF_CLS_VID_SEL] = { 3092 .type = VCAP_FIELD_U32, 3093 .offset = 17, 3094 .width = 3, 3095 }, 3096 [VCAP_AF_VID_VAL] = { 3097 .type = VCAP_FIELD_U32, 3098 .offset = 23, 3099 .width = 13, 3100 }, 3101 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 3102 .type = VCAP_FIELD_BIT, 3103 .offset = 46, 3104 .width = 1, 3105 }, 3106 [VCAP_AF_ISDX_VAL] = { 3107 .type = VCAP_FIELD_U32, 3108 .offset = 47, 3109 .width = 12, 3110 }, 3111 [VCAP_AF_NXT_IDX_CTRL] = { 3112 .type = VCAP_FIELD_U32, 3113 .offset = 90, 3114 .width = 3, 3115 }, 3116 [VCAP_AF_NXT_IDX] = { 3117 .type = VCAP_FIELD_U32, 3118 .offset = 93, 3119 .width = 12, 3120 }, 3121 }; 3122 3123 static const struct vcap_field is2_base_type_actionfield[] = { 3124 [VCAP_AF_PIPELINE_FORCE_ENA] = { 3125 .type = VCAP_FIELD_BIT, 3126 .offset = 1, 3127 .width = 1, 3128 }, 3129 [VCAP_AF_PIPELINE_PT] = { 3130 .type = VCAP_FIELD_U32, 3131 .offset = 2, 3132 .width = 5, 3133 }, 3134 [VCAP_AF_HIT_ME_ONCE] = { 3135 .type = VCAP_FIELD_BIT, 3136 .offset = 7, 3137 .width = 1, 3138 }, 3139 [VCAP_AF_INTR_ENA] = { 3140 .type = VCAP_FIELD_BIT, 3141 .offset = 8, 3142 .width = 1, 3143 }, 3144 [VCAP_AF_CPU_COPY_ENA] = { 3145 .type = VCAP_FIELD_BIT, 3146 .offset = 9, 3147 .width = 1, 3148 }, 3149 [VCAP_AF_CPU_QUEUE_NUM] = { 3150 .type = VCAP_FIELD_U32, 3151 .offset = 10, 3152 .width = 3, 3153 }, 3154 [VCAP_AF_LRN_DIS] = { 3155 .type = VCAP_FIELD_BIT, 3156 .offset = 14, 3157 .width = 1, 3158 }, 3159 [VCAP_AF_RT_DIS] = { 3160 .type = VCAP_FIELD_BIT, 3161 .offset = 15, 3162 .width = 1, 3163 }, 3164 [VCAP_AF_POLICE_ENA] = { 3165 .type = VCAP_FIELD_BIT, 3166 .offset = 16, 3167 .width = 1, 3168 }, 3169 [VCAP_AF_POLICE_IDX] = { 3170 .type = VCAP_FIELD_U32, 3171 .offset = 17, 3172 .width = 6, 3173 }, 3174 [VCAP_AF_IGNORE_PIPELINE_CTRL] = { 3175 .type = VCAP_FIELD_BIT, 3176 .offset = 23, 3177 .width = 1, 3178 }, 3179 [VCAP_AF_MASK_MODE] = { 3180 .type = VCAP_FIELD_U32, 3181 .offset = 27, 3182 .width = 3, 3183 }, 3184 [VCAP_AF_PORT_MASK] = { 3185 .type = VCAP_FIELD_U72, 3186 .offset = 30, 3187 .width = 68, 3188 }, 3189 [VCAP_AF_MIRROR_PROBE] = { 3190 .type = VCAP_FIELD_U32, 3191 .offset = 111, 3192 .width = 2, 3193 }, 3194 [VCAP_AF_MATCH_ID] = { 3195 .type = VCAP_FIELD_U32, 3196 .offset = 159, 3197 .width = 16, 3198 }, 3199 [VCAP_AF_MATCH_ID_MASK] = { 3200 .type = VCAP_FIELD_U32, 3201 .offset = 175, 3202 .width = 16, 3203 }, 3204 [VCAP_AF_CNT_ID] = { 3205 .type = VCAP_FIELD_U32, 3206 .offset = 191, 3207 .width = 12, 3208 }, 3209 }; 3210 3211 static const struct vcap_field es2_base_type_actionfield[] = { 3212 [VCAP_AF_HIT_ME_ONCE] = { 3213 .type = VCAP_FIELD_BIT, 3214 .offset = 0, 3215 .width = 1, 3216 }, 3217 [VCAP_AF_INTR_ENA] = { 3218 .type = VCAP_FIELD_BIT, 3219 .offset = 1, 3220 .width = 1, 3221 }, 3222 [VCAP_AF_FWD_MODE] = { 3223 .type = VCAP_FIELD_U32, 3224 .offset = 2, 3225 .width = 2, 3226 }, 3227 [VCAP_AF_COPY_QUEUE_NUM] = { 3228 .type = VCAP_FIELD_U32, 3229 .offset = 4, 3230 .width = 16, 3231 }, 3232 [VCAP_AF_COPY_PORT_NUM] = { 3233 .type = VCAP_FIELD_U32, 3234 .offset = 20, 3235 .width = 7, 3236 }, 3237 [VCAP_AF_MIRROR_PROBE_ID] = { 3238 .type = VCAP_FIELD_U32, 3239 .offset = 27, 3240 .width = 2, 3241 }, 3242 [VCAP_AF_CPU_COPY_ENA] = { 3243 .type = VCAP_FIELD_BIT, 3244 .offset = 29, 3245 .width = 1, 3246 }, 3247 [VCAP_AF_CPU_QUEUE_NUM] = { 3248 .type = VCAP_FIELD_U32, 3249 .offset = 30, 3250 .width = 3, 3251 }, 3252 [VCAP_AF_POLICE_ENA] = { 3253 .type = VCAP_FIELD_BIT, 3254 .offset = 33, 3255 .width = 1, 3256 }, 3257 [VCAP_AF_POLICE_REMARK] = { 3258 .type = VCAP_FIELD_BIT, 3259 .offset = 34, 3260 .width = 1, 3261 }, 3262 [VCAP_AF_POLICE_IDX] = { 3263 .type = VCAP_FIELD_U32, 3264 .offset = 35, 3265 .width = 6, 3266 }, 3267 [VCAP_AF_ES2_REW_CMD] = { 3268 .type = VCAP_FIELD_U32, 3269 .offset = 41, 3270 .width = 3, 3271 }, 3272 [VCAP_AF_CNT_ID] = { 3273 .type = VCAP_FIELD_U32, 3274 .offset = 44, 3275 .width = 11, 3276 }, 3277 [VCAP_AF_IGNORE_PIPELINE_CTRL] = { 3278 .type = VCAP_FIELD_BIT, 3279 .offset = 55, 3280 .width = 1, 3281 }, 3282 }; 3283 3284 /* actionfield_set */ 3285 static const struct vcap_set is0_actionfield_set[] = { 3286 [VCAP_AFS_CLASSIFICATION] = { 3287 .type_id = 1, 3288 .sw_per_item = 2, 3289 .sw_cnt = 6, 3290 }, 3291 [VCAP_AFS_FULL] = { 3292 .type_id = -1, 3293 .sw_per_item = 3, 3294 .sw_cnt = 4, 3295 }, 3296 [VCAP_AFS_CLASS_REDUCED] = { 3297 .type_id = 1, 3298 .sw_per_item = 1, 3299 .sw_cnt = 12, 3300 }, 3301 }; 3302 3303 static const struct vcap_set is2_actionfield_set[] = { 3304 [VCAP_AFS_BASE_TYPE] = { 3305 .type_id = -1, 3306 .sw_per_item = 3, 3307 .sw_cnt = 4, 3308 }, 3309 }; 3310 3311 static const struct vcap_set es2_actionfield_set[] = { 3312 [VCAP_AFS_BASE_TYPE] = { 3313 .type_id = -1, 3314 .sw_per_item = 3, 3315 .sw_cnt = 4, 3316 }, 3317 }; 3318 3319 /* actionfield_set map */ 3320 static const struct vcap_field *is0_actionfield_set_map[] = { 3321 [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, 3322 [VCAP_AFS_FULL] = is0_full_actionfield, 3323 [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, 3324 }; 3325 3326 static const struct vcap_field *is2_actionfield_set_map[] = { 3327 [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, 3328 }; 3329 3330 static const struct vcap_field *es2_actionfield_set_map[] = { 3331 [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, 3332 }; 3333 3334 /* actionfield_set map size */ 3335 static int is0_actionfield_set_map_size[] = { 3336 [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), 3337 [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), 3338 [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), 3339 }; 3340 3341 static int is2_actionfield_set_map_size[] = { 3342 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), 3343 }; 3344 3345 static int es2_actionfield_set_map_size[] = { 3346 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), 3347 }; 3348 3349 /* Type Groups */ 3350 static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { 3351 { 3352 .offset = 0, 3353 .width = 5, 3354 .value = 16, 3355 }, 3356 { 3357 .offset = 52, 3358 .width = 1, 3359 .value = 0, 3360 }, 3361 { 3362 .offset = 104, 3363 .width = 2, 3364 .value = 0, 3365 }, 3366 { 3367 .offset = 156, 3368 .width = 3, 3369 .value = 0, 3370 }, 3371 { 3372 .offset = 208, 3373 .width = 2, 3374 .value = 0, 3375 }, 3376 { 3377 .offset = 260, 3378 .width = 1, 3379 .value = 0, 3380 }, 3381 { 3382 .offset = 312, 3383 .width = 4, 3384 .value = 0, 3385 }, 3386 { 3387 .offset = 364, 3388 .width = 1, 3389 .value = 0, 3390 }, 3391 { 3392 .offset = 416, 3393 .width = 2, 3394 .value = 0, 3395 }, 3396 { 3397 .offset = 468, 3398 .width = 3, 3399 .value = 0, 3400 }, 3401 { 3402 .offset = 520, 3403 .width = 2, 3404 .value = 0, 3405 }, 3406 { 3407 .offset = 572, 3408 .width = 1, 3409 .value = 0, 3410 }, 3411 {} 3412 }; 3413 3414 static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { 3415 { 3416 .offset = 0, 3417 .width = 4, 3418 .value = 8, 3419 }, 3420 { 3421 .offset = 52, 3422 .width = 1, 3423 .value = 0, 3424 }, 3425 { 3426 .offset = 104, 3427 .width = 2, 3428 .value = 0, 3429 }, 3430 { 3431 .offset = 156, 3432 .width = 3, 3433 .value = 0, 3434 }, 3435 { 3436 .offset = 208, 3437 .width = 2, 3438 .value = 0, 3439 }, 3440 { 3441 .offset = 260, 3442 .width = 1, 3443 .value = 0, 3444 }, 3445 {} 3446 }; 3447 3448 static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { 3449 { 3450 .offset = 0, 3451 .width = 3, 3452 .value = 4, 3453 }, 3454 { 3455 .offset = 52, 3456 .width = 2, 3457 .value = 0, 3458 }, 3459 { 3460 .offset = 104, 3461 .width = 2, 3462 .value = 0, 3463 }, 3464 {} 3465 }; 3466 3467 static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { 3468 { 3469 .offset = 0, 3470 .width = 2, 3471 .value = 2, 3472 }, 3473 { 3474 .offset = 52, 3475 .width = 1, 3476 .value = 0, 3477 }, 3478 {} 3479 }; 3480 3481 static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { 3482 {} 3483 }; 3484 3485 static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { 3486 { 3487 .offset = 0, 3488 .width = 3, 3489 .value = 4, 3490 }, 3491 { 3492 .offset = 156, 3493 .width = 1, 3494 .value = 0, 3495 }, 3496 { 3497 .offset = 312, 3498 .width = 2, 3499 .value = 0, 3500 }, 3501 { 3502 .offset = 468, 3503 .width = 1, 3504 .value = 0, 3505 }, 3506 {} 3507 }; 3508 3509 static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { 3510 { 3511 .offset = 0, 3512 .width = 2, 3513 .value = 2, 3514 }, 3515 { 3516 .offset = 156, 3517 .width = 1, 3518 .value = 0, 3519 }, 3520 {} 3521 }; 3522 3523 static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { 3524 {} 3525 }; 3526 3527 static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { 3528 {} 3529 }; 3530 3531 static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { 3532 { 3533 .offset = 0, 3534 .width = 3, 3535 .value = 4, 3536 }, 3537 { 3538 .offset = 156, 3539 .width = 1, 3540 .value = 0, 3541 }, 3542 { 3543 .offset = 312, 3544 .width = 2, 3545 .value = 0, 3546 }, 3547 { 3548 .offset = 468, 3549 .width = 1, 3550 .value = 0, 3551 }, 3552 {} 3553 }; 3554 3555 static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { 3556 { 3557 .offset = 0, 3558 .width = 2, 3559 .value = 2, 3560 }, 3561 { 3562 .offset = 156, 3563 .width = 1, 3564 .value = 0, 3565 }, 3566 {} 3567 }; 3568 3569 static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { 3570 { 3571 .offset = 0, 3572 .width = 1, 3573 .value = 1, 3574 }, 3575 {} 3576 }; 3577 3578 static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { 3579 {} 3580 }; 3581 3582 static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { 3583 [12] = is0_x12_keyfield_set_typegroups, 3584 [6] = is0_x6_keyfield_set_typegroups, 3585 [3] = is0_x3_keyfield_set_typegroups, 3586 [2] = is0_x2_keyfield_set_typegroups, 3587 [1] = is0_x1_keyfield_set_typegroups, 3588 [13] = NULL, 3589 }; 3590 3591 static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { 3592 [12] = is2_x12_keyfield_set_typegroups, 3593 [6] = is2_x6_keyfield_set_typegroups, 3594 [3] = is2_x3_keyfield_set_typegroups, 3595 [1] = is2_x1_keyfield_set_typegroups, 3596 [13] = NULL, 3597 }; 3598 3599 static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { 3600 [12] = es2_x12_keyfield_set_typegroups, 3601 [6] = es2_x6_keyfield_set_typegroups, 3602 [3] = es2_x3_keyfield_set_typegroups, 3603 [1] = es2_x1_keyfield_set_typegroups, 3604 [13] = NULL, 3605 }; 3606 3607 static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { 3608 { 3609 .offset = 0, 3610 .width = 3, 3611 .value = 4, 3612 }, 3613 { 3614 .offset = 110, 3615 .width = 2, 3616 .value = 0, 3617 }, 3618 { 3619 .offset = 220, 3620 .width = 2, 3621 .value = 0, 3622 }, 3623 {} 3624 }; 3625 3626 static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { 3627 { 3628 .offset = 0, 3629 .width = 2, 3630 .value = 2, 3631 }, 3632 { 3633 .offset = 110, 3634 .width = 1, 3635 .value = 0, 3636 }, 3637 {} 3638 }; 3639 3640 static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { 3641 { 3642 .offset = 0, 3643 .width = 1, 3644 .value = 1, 3645 }, 3646 {} 3647 }; 3648 3649 static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { 3650 { 3651 .offset = 0, 3652 .width = 2, 3653 .value = 2, 3654 }, 3655 { 3656 .offset = 110, 3657 .width = 1, 3658 .value = 0, 3659 }, 3660 { 3661 .offset = 220, 3662 .width = 1, 3663 .value = 0, 3664 }, 3665 {} 3666 }; 3667 3668 static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { 3669 {} 3670 }; 3671 3672 static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { 3673 { 3674 .offset = 0, 3675 .width = 2, 3676 .value = 2, 3677 }, 3678 { 3679 .offset = 21, 3680 .width = 1, 3681 .value = 0, 3682 }, 3683 { 3684 .offset = 42, 3685 .width = 1, 3686 .value = 0, 3687 }, 3688 {} 3689 }; 3690 3691 static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { 3692 {} 3693 }; 3694 3695 static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { 3696 [3] = is0_x3_actionfield_set_typegroups, 3697 [2] = is0_x2_actionfield_set_typegroups, 3698 [1] = is0_x1_actionfield_set_typegroups, 3699 [13] = NULL, 3700 }; 3701 3702 static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { 3703 [3] = is2_x3_actionfield_set_typegroups, 3704 [1] = is2_x1_actionfield_set_typegroups, 3705 [13] = NULL, 3706 }; 3707 3708 static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { 3709 [3] = es2_x3_actionfield_set_typegroups, 3710 [1] = es2_x1_actionfield_set_typegroups, 3711 [13] = NULL, 3712 }; 3713 3714 /* Keyfieldset names */ 3715 static const char * const vcap_keyfield_set_names[] = { 3716 [VCAP_KFS_NO_VALUE] = "(None)", 3717 [VCAP_KFS_ARP] = "VCAP_KFS_ARP", 3718 [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", 3719 [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", 3720 [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", 3721 [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", 3722 [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", 3723 [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", 3724 [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", 3725 [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", 3726 [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", 3727 [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", 3728 [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", 3729 [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", 3730 [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", 3731 [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", 3732 [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", 3733 [VCAP_KFS_OAM] = "VCAP_KFS_OAM", 3734 [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", 3735 [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", 3736 [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", 3737 }; 3738 3739 /* Actionfieldset names */ 3740 static const char * const vcap_actionfield_set_names[] = { 3741 [VCAP_AFS_NO_VALUE] = "(None)", 3742 [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", 3743 [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", 3744 [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", 3745 [VCAP_AFS_FULL] = "VCAP_AFS_FULL", 3746 [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", 3747 }; 3748 3749 /* Keyfield names */ 3750 static const char * const vcap_keyfield_names[] = { 3751 [VCAP_KF_NO_VALUE] = "(None)", 3752 [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", 3753 [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", 3754 [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", 3755 [VCAP_KF_8021BR_GRP] = "8021BR_GRP", 3756 [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", 3757 [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", 3758 [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", 3759 [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", 3760 [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", 3761 [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", 3762 [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", 3763 [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", 3764 [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", 3765 [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", 3766 [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", 3767 [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", 3768 [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", 3769 [VCAP_KF_8021Q_VID0] = "8021Q_VID0", 3770 [VCAP_KF_8021Q_VID1] = "8021Q_VID1", 3771 [VCAP_KF_8021Q_VID2] = "8021Q_VID2", 3772 [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", 3773 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", 3774 [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", 3775 [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", 3776 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", 3777 [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", 3778 [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", 3779 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", 3780 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", 3781 [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", 3782 [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", 3783 [VCAP_KF_COSID_CLS] = "COSID_CLS", 3784 [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", 3785 [VCAP_KF_ETYPE] = "ETYPE", 3786 [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", 3787 [VCAP_KF_HOST_MATCH] = "HOST_MATCH", 3788 [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", 3789 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", 3790 [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", 3791 [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", 3792 [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", 3793 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", 3794 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", 3795 [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", 3796 [VCAP_KF_IP4_IS] = "IP4_IS", 3797 [VCAP_KF_IP_MC_IS] = "IP_MC_IS", 3798 [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", 3799 [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", 3800 [VCAP_KF_ISDX_CLS] = "ISDX_CLS", 3801 [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", 3802 [VCAP_KF_L2_BC_IS] = "L2_BC_IS", 3803 [VCAP_KF_L2_DMAC] = "L2_DMAC", 3804 [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", 3805 [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", 3806 [VCAP_KF_L2_LLC] = "L2_LLC", 3807 [VCAP_KF_L2_MC_IS] = "L2_MC_IS", 3808 [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", 3809 [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", 3810 [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", 3811 [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", 3812 [VCAP_KF_L2_SMAC] = "L2_SMAC", 3813 [VCAP_KF_L2_SNAP] = "L2_SNAP", 3814 [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", 3815 [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", 3816 [VCAP_KF_L3_DSCP] = "L3_DSCP", 3817 [VCAP_KF_L3_DST_IS] = "L3_DST_IS", 3818 [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", 3819 [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", 3820 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", 3821 [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", 3822 [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", 3823 [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", 3824 [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", 3825 [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", 3826 [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", 3827 [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", 3828 [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", 3829 [VCAP_KF_L3_RT_IS] = "L3_RT_IS", 3830 [VCAP_KF_L3_TOS] = "L3_TOS", 3831 [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", 3832 [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", 3833 [VCAP_KF_L4_1588_VER] = "L4_1588_VER", 3834 [VCAP_KF_L4_ACK] = "L4_ACK", 3835 [VCAP_KF_L4_DPORT] = "L4_DPORT", 3836 [VCAP_KF_L4_FIN] = "L4_FIN", 3837 [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", 3838 [VCAP_KF_L4_PSH] = "L4_PSH", 3839 [VCAP_KF_L4_RNG] = "L4_RNG", 3840 [VCAP_KF_L4_RST] = "L4_RST", 3841 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", 3842 [VCAP_KF_L4_SPORT] = "L4_SPORT", 3843 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", 3844 [VCAP_KF_L4_SYN] = "L4_SYN", 3845 [VCAP_KF_L4_URG] = "L4_URG", 3846 [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", 3847 [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", 3848 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", 3849 [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", 3850 [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", 3851 [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", 3852 [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", 3853 [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", 3854 [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", 3855 [VCAP_KF_OAM_MEPID] = "OAM_MEPID", 3856 [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", 3857 [VCAP_KF_OAM_VER] = "OAM_VER", 3858 [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", 3859 [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", 3860 [VCAP_KF_TCP_IS] = "TCP_IS", 3861 [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", 3862 [VCAP_KF_TYPE] = "TYPE", 3863 }; 3864 3865 /* Actionfield names */ 3866 static const char * const vcap_actionfield_names[] = { 3867 [VCAP_AF_NO_VALUE] = "(None)", 3868 [VCAP_AF_ACL_ID] = "ACL_ID", 3869 [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", 3870 [VCAP_AF_CNT_ID] = "CNT_ID", 3871 [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", 3872 [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", 3873 [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", 3874 [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", 3875 [VCAP_AF_DEI_ENA] = "DEI_ENA", 3876 [VCAP_AF_DEI_VAL] = "DEI_VAL", 3877 [VCAP_AF_DP_ENA] = "DP_ENA", 3878 [VCAP_AF_DP_VAL] = "DP_VAL", 3879 [VCAP_AF_DSCP_ENA] = "DSCP_ENA", 3880 [VCAP_AF_DSCP_VAL] = "DSCP_VAL", 3881 [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", 3882 [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", 3883 [VCAP_AF_FWD_MODE] = "FWD_MODE", 3884 [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", 3885 [VCAP_AF_HOST_MATCH] = "HOST_MATCH", 3886 [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", 3887 [VCAP_AF_INTR_ENA] = "INTR_ENA", 3888 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", 3889 [VCAP_AF_ISDX_ENA] = "ISDX_ENA", 3890 [VCAP_AF_ISDX_VAL] = "ISDX_VAL", 3891 [VCAP_AF_LRN_DIS] = "LRN_DIS", 3892 [VCAP_AF_MAP_IDX] = "MAP_IDX", 3893 [VCAP_AF_MAP_KEY] = "MAP_KEY", 3894 [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", 3895 [VCAP_AF_MASK_MODE] = "MASK_MODE", 3896 [VCAP_AF_MATCH_ID] = "MATCH_ID", 3897 [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", 3898 [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", 3899 [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", 3900 [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", 3901 [VCAP_AF_NXT_IDX] = "NXT_IDX", 3902 [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", 3903 [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", 3904 [VCAP_AF_PAG_VAL] = "PAG_VAL", 3905 [VCAP_AF_PCP_ENA] = "PCP_ENA", 3906 [VCAP_AF_PCP_VAL] = "PCP_VAL", 3907 [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", 3908 [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", 3909 [VCAP_AF_POLICE_ENA] = "POLICE_ENA", 3910 [VCAP_AF_POLICE_IDX] = "POLICE_IDX", 3911 [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", 3912 [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", 3913 [VCAP_AF_PORT_MASK] = "PORT_MASK", 3914 [VCAP_AF_QOS_ENA] = "QOS_ENA", 3915 [VCAP_AF_QOS_VAL] = "QOS_VAL", 3916 [VCAP_AF_REW_OP] = "REW_OP", 3917 [VCAP_AF_RT_DIS] = "RT_DIS", 3918 [VCAP_AF_TYPE] = "TYPE", 3919 [VCAP_AF_VID_VAL] = "VID_VAL", 3920 }; 3921 3922 /* VCAPs */ 3923 const struct vcap_info kunit_test_vcaps[] = { 3924 [VCAP_TYPE_IS0] = { 3925 .name = "is0", 3926 .rows = 1024, 3927 .sw_count = 12, 3928 .sw_width = 52, 3929 .sticky_width = 1, 3930 .act_width = 110, 3931 .default_cnt = 140, 3932 .require_cnt_dis = 0, 3933 .version = 1, 3934 .keyfield_set = is0_keyfield_set, 3935 .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), 3936 .actionfield_set = is0_actionfield_set, 3937 .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), 3938 .keyfield_set_map = is0_keyfield_set_map, 3939 .keyfield_set_map_size = is0_keyfield_set_map_size, 3940 .actionfield_set_map = is0_actionfield_set_map, 3941 .actionfield_set_map_size = is0_actionfield_set_map_size, 3942 .keyfield_set_typegroups = is0_keyfield_set_typegroups, 3943 .actionfield_set_typegroups = is0_actionfield_set_typegroups, 3944 }, 3945 [VCAP_TYPE_IS2] = { 3946 .name = "is2", 3947 .rows = 256, 3948 .sw_count = 12, 3949 .sw_width = 52, 3950 .sticky_width = 1, 3951 .act_width = 110, 3952 .default_cnt = 73, 3953 .require_cnt_dis = 0, 3954 .version = 1, 3955 .keyfield_set = is2_keyfield_set, 3956 .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), 3957 .actionfield_set = is2_actionfield_set, 3958 .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), 3959 .keyfield_set_map = is2_keyfield_set_map, 3960 .keyfield_set_map_size = is2_keyfield_set_map_size, 3961 .actionfield_set_map = is2_actionfield_set_map, 3962 .actionfield_set_map_size = is2_actionfield_set_map_size, 3963 .keyfield_set_typegroups = is2_keyfield_set_typegroups, 3964 .actionfield_set_typegroups = is2_actionfield_set_typegroups, 3965 }, 3966 [VCAP_TYPE_ES2] = { 3967 .name = "es2", 3968 .rows = 1024, 3969 .sw_count = 12, 3970 .sw_width = 52, 3971 .sticky_width = 1, 3972 .act_width = 21, 3973 .default_cnt = 74, 3974 .require_cnt_dis = 0, 3975 .version = 1, 3976 .keyfield_set = es2_keyfield_set, 3977 .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), 3978 .actionfield_set = es2_actionfield_set, 3979 .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), 3980 .keyfield_set_map = es2_keyfield_set_map, 3981 .keyfield_set_map_size = es2_keyfield_set_map_size, 3982 .actionfield_set_map = es2_actionfield_set_map, 3983 .actionfield_set_map_size = es2_actionfield_set_map_size, 3984 .keyfield_set_typegroups = es2_keyfield_set_typegroups, 3985 .actionfield_set_typegroups = es2_actionfield_set_typegroups, 3986 }, 3987 }; 3988 3989 const struct vcap_statistics kunit_test_vcap_stats = { 3990 .name = "kunit_test", 3991 .count = 3, 3992 .keyfield_set_names = vcap_keyfield_set_names, 3993 .actionfield_set_names = vcap_actionfield_set_names, 3994 .keyfield_names = vcap_keyfield_names, 3995 .actionfield_names = vcap_actionfield_names, 3996 }; 3997