1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. 3 * Microchip VCAP API 4 */ 5 6 /* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200. 7 * Commit ID: fd7cafd175899f0672c73afb3a30fc872500ae86 8 */ 9 10 #ifndef __VCAP_AG_API__ 11 #define __VCAP_AG_API__ 12 13 enum vcap_type { 14 VCAP_TYPE_IS2, 15 VCAP_TYPE_MAX 16 }; 17 18 /* Keyfieldset names with origin information */ 19 enum vcap_keyfield_set { 20 VCAP_KFS_NO_VALUE, /* initial value */ 21 VCAP_KFS_ARP, /* sparx5 is2 X6 */ 22 VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6 */ 23 VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6 */ 24 VCAP_KFS_IP6_STD, /* sparx5 is2 X6 */ 25 VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12 */ 26 VCAP_KFS_MAC_ETYPE, /* sparx5 is2 X6 */ 27 }; 28 29 /* List of keyfields with description 30 * 31 * Keys ending in _IS are booleans derived from frame data 32 * Keys ending in _CLS are classified frame data 33 * 34 * VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2 35 * Classified DEI 36 * VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2 37 * Classified PCP 38 * VCAP_KF_8021Q_VID_CLS: W13, sparx5: is2 39 * Classified VID 40 * VCAP_KF_8021Q_VLAN_TAGGED_IS: W1, sparx5: is2 41 * Sparx5: Set if frame was received with a VLAN tag, LAN966x: Set if frame has 42 * one or more Q-tags. Independent of port VLAN awareness 43 * VCAP_KF_ARP_ADDR_SPACE_OK_IS: W1, sparx5: is2 44 * Set if hardware address is Ethernet 45 * VCAP_KF_ARP_LEN_OK_IS: W1, sparx5: is2 46 * Set if hardware address length = 6 (Ethernet) and IP address length = 4 (IP). 47 * VCAP_KF_ARP_OPCODE: W2, sparx5: is2 48 * ARP opcode 49 * VCAP_KF_ARP_OPCODE_UNKNOWN_IS: W1, sparx5: is2 50 * Set if not one of the codes defined in VCAP_KF_ARP_OPCODE 51 * VCAP_KF_ARP_PROTO_SPACE_OK_IS: W1, sparx5: is2 52 * Set if protocol address space is 0x0800 53 * VCAP_KF_ARP_SENDER_MATCH_IS: W1, sparx5: is2 54 * Sender Hardware Address = SMAC (ARP) 55 * VCAP_KF_ARP_TGT_MATCH_IS: W1, sparx5: is2 56 * Target Hardware Address = SMAC (RARP) 57 * VCAP_KF_ETYPE: W16, sparx5: is2 58 * Ethernet type 59 * VCAP_KF_ETYPE_LEN_IS: W1, sparx5: is2 60 * Set if frame has EtherType >= 0x600 61 * VCAP_KF_IF_IGR_PORT_MASK: sparx5 is2 W32, sparx5 is2 W65 62 * Ingress port mask, one bit per port/erleg 63 * VCAP_KF_IF_IGR_PORT_MASK_L3: W1, sparx5: is2 64 * If set, IF_IGR_PORT_MASK, IF_IGR_PORT_MASK_RNG, and IF_IGR_PORT_MASK_SEL are 65 * used to specify L3 interfaces 66 * VCAP_KF_IF_IGR_PORT_MASK_RNG: W4, sparx5: is2 67 * Range selector for IF_IGR_PORT_MASK. Specifies which group of 32 ports are 68 * available in IF_IGR_PORT_MASK 69 * VCAP_KF_IF_IGR_PORT_MASK_SEL: W2, sparx5: is2 70 * Mode selector for IF_IGR_PORT_MASK, applicable when IF_IGR_PORT_MASK_L3 == 0. 71 * Mapping: 0: DEFAULT 1: LOOPBACK 2: MASQUERADE 3: CPU_VD 72 * VCAP_KF_IP4_IS: W1, sparx5: is2 73 * Set if frame has EtherType = 0x800 and IP version = 4 74 * VCAP_KF_ISDX_CLS: W12, sparx5: is2 75 * Classified ISDX 76 * VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2 77 * Set if classified ISDX > 0 78 * VCAP_KF_L2_BC_IS: W1, sparx5: is2 79 * Set if frame’s destination MAC address is the broadcast address 80 * (FF-FF-FF-FF-FF-FF). 81 * VCAP_KF_L2_DMAC: W48, sparx5: is2 82 * Destination MAC address 83 * VCAP_KF_L2_FWD_IS: W1, sparx5: is2 84 * Set if the frame is allowed to be forwarded to front ports 85 * VCAP_KF_L2_MC_IS: W1, sparx5: is2 86 * Set if frame’s destination MAC address is a multicast address (bit 40 = 1). 87 * VCAP_KF_L2_PAYLOAD_ETYPE: W64, sparx5: is2 88 * Byte 0-7 of L2 payload after Type/Len field and overloading for OAM 89 * VCAP_KF_L2_SMAC: W48, sparx5: is2 90 * Source MAC address 91 * VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2 92 * Set if Src IP matches Dst IP address 93 * VCAP_KF_L3_DST_IS: W1, sparx5: is2 94 * Set if lookup is done for egress router leg 95 * VCAP_KF_L3_FRAGMENT_TYPE: W2, sparx5: is2 96 * L3 Fragmentation type (none, initial, suspicious, valid follow up) 97 * VCAP_KF_L3_FRAG_INVLD_L4_LEN: W1, sparx5: is2 98 * Set if frame's L4 length is less than ANA_CL:COMMON:CLM_FRAGMENT_CFG.L4_MIN_L 99 * EN 100 * VCAP_KF_L3_IP4_DIP: W32, sparx5: is2 101 * Destination IPv4 Address 102 * VCAP_KF_L3_IP4_SIP: W32, sparx5: is2 103 * Source IPv4 Address 104 * VCAP_KF_L3_IP6_DIP: W128, sparx5: is2 105 * Sparx5: Full IPv6 DIP, LAN966x: Either Full IPv6 DIP or a subset depending on 106 * frame type 107 * VCAP_KF_L3_IP6_SIP: W128, sparx5: is2 108 * Sparx5: Full IPv6 SIP, LAN966x: Either Full IPv6 SIP or a subset depending on 109 * frame type 110 * VCAP_KF_L3_IP_PROTO: W8, sparx5: is2 111 * IPv4 frames: IP protocol. IPv6 frames: Next header, same as for IPV4 112 * VCAP_KF_L3_OPTIONS_IS: W1, sparx5: is2 113 * Set if IPv4 frame contains options (IP len > 5) 114 * VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40 115 * Sparx5: Payload bytes after IP header. IPv4: IPv4 options are not parsed so 116 * payload is always taken 20 bytes after the start of the IPv4 header, LAN966x: 117 * Bytes 0-6 after IP header 118 * VCAP_KF_L3_RT_IS: W1, sparx5: is2 119 * Set if frame has hit a router leg 120 * VCAP_KF_L3_TOS: W8, sparx5: is2 121 * Sparx5: Frame's IPv4/IPv6 DSCP and ECN fields, LAN966x: IP TOS field 122 * VCAP_KF_L3_TTL_GT0: W1, sparx5: is2 123 * Set if IPv4 TTL / IPv6 hop limit is greater than 0 124 * VCAP_KF_L4_ACK: W1, sparx5: is2 125 * Sparx5 and LAN966x: TCP flag ACK, LAN966x only: PTP over UDP: flagField bit 2 126 * (unicastFlag) 127 * VCAP_KF_L4_DPORT: W16, sparx5: is2 128 * Sparx5: TCP/UDP destination port. Overloading for IP_7TUPLE: Non-TCP/UDP IP 129 * frames: L4_DPORT = L3_IP_PROTO, LAN966x: TCP/UDP destination port 130 * VCAP_KF_L4_FIN: W1, sparx5: is2 131 * TCP flag FIN, LAN966x: TCP flag FIN, and for PTP over UDP: messageType bit 1 132 * VCAP_KF_L4_PAYLOAD: W64, sparx5: is2 133 * Payload bytes after TCP/UDP header Overloading for IP_7TUPLE: Non TCP/UDP 134 * frames: Payload bytes 0–7 after IP header. IPv4 options are not parsed so 135 * payload is always taken 20 bytes after the start of the IPv4 header for non 136 * TCP/UDP IPv4 frames 137 * VCAP_KF_L4_PSH: W1, sparx5: is2 138 * Sparx5: TCP flag PSH, LAN966x: TCP: TCP flag PSH. PTP over UDP: flagField bit 139 * 1 (twoStepFlag) 140 * VCAP_KF_L4_RNG: W16, sparx5: is2 141 * Range checker bitmask (one for each range checker). Input into range checkers 142 * is taken from classified results (VID, DSCP) and frame (SPORT, DPORT, ETYPE, 143 * outer VID, inner VID) 144 * VCAP_KF_L4_RST: W1, sparx5: is2 145 * Sparx5: TCP flag RST , LAN966x: TCP: TCP flag RST. PTP over UDP: messageType 146 * bit 3 147 * VCAP_KF_L4_SEQUENCE_EQ0_IS: W1, sparx5: is2 148 * Set if TCP sequence number is 0, LAN966x: Overlayed with PTP over UDP: 149 * messageType bit 0 150 * VCAP_KF_L4_SPORT: W16, sparx5: is2 151 * TCP/UDP source port 152 * VCAP_KF_L4_SPORT_EQ_DPORT_IS: W1, sparx5: is2 153 * Set if UDP or TCP source port equals UDP or TCP destination port 154 * VCAP_KF_L4_SYN: W1, sparx5: is2 155 * Sparx5: TCP flag SYN, LAN966x: TCP: TCP flag SYN. PTP over UDP: messageType 156 * bit 2 157 * VCAP_KF_L4_URG: W1, sparx5: is2 158 * Sparx5: TCP flag URG, LAN966x: TCP: TCP flag URG. PTP over UDP: flagField bit 159 * 7 (reserved) 160 * VCAP_KF_LOOKUP_FIRST_IS: W1, sparx5: is2 161 * Selects between entries relevant for first and second lookup. Set for first 162 * lookup, cleared for second lookup. 163 * VCAP_KF_LOOKUP_PAG: W8, sparx5: is2 164 * Classified Policy Association Group: chains rules from IS1/CLM to IS2 165 * VCAP_KF_OAM_CCM_CNTS_EQ0: W1, sparx5: is2 166 * Dual-ended loss measurement counters in CCM frames are all zero 167 * VCAP_KF_OAM_Y1731_IS: W1, sparx5: is2 168 * Set if frame’s EtherType = 0x8902 169 * VCAP_KF_TCP_IS: W1, sparx5: is2 170 * Set if frame is IPv4 TCP frame (IP protocol = 6) or IPv6 TCP frames (Next 171 * header = 6) 172 * VCAP_KF_TCP_UDP_IS: W1, sparx5: is2 173 * Set if frame is IPv4/IPv6 TCP or UDP frame (IP protocol/next header equals 6 174 * or 17) 175 * VCAP_KF_TYPE: sparx5 is2 W4, sparx5 is2 W2 176 * Keyset type id - set by the API 177 */ 178 179 /* Keyfield names */ 180 enum vcap_key_field { 181 VCAP_KF_NO_VALUE, /* initial value */ 182 VCAP_KF_8021Q_DEI_CLS, 183 VCAP_KF_8021Q_PCP_CLS, 184 VCAP_KF_8021Q_VID_CLS, 185 VCAP_KF_8021Q_VLAN_TAGGED_IS, 186 VCAP_KF_ARP_ADDR_SPACE_OK_IS, 187 VCAP_KF_ARP_LEN_OK_IS, 188 VCAP_KF_ARP_OPCODE, 189 VCAP_KF_ARP_OPCODE_UNKNOWN_IS, 190 VCAP_KF_ARP_PROTO_SPACE_OK_IS, 191 VCAP_KF_ARP_SENDER_MATCH_IS, 192 VCAP_KF_ARP_TGT_MATCH_IS, 193 VCAP_KF_ETYPE, 194 VCAP_KF_ETYPE_LEN_IS, 195 VCAP_KF_IF_IGR_PORT_MASK, 196 VCAP_KF_IF_IGR_PORT_MASK_L3, 197 VCAP_KF_IF_IGR_PORT_MASK_RNG, 198 VCAP_KF_IF_IGR_PORT_MASK_SEL, 199 VCAP_KF_IP4_IS, 200 VCAP_KF_ISDX_CLS, 201 VCAP_KF_ISDX_GT0_IS, 202 VCAP_KF_L2_BC_IS, 203 VCAP_KF_L2_DMAC, 204 VCAP_KF_L2_FWD_IS, 205 VCAP_KF_L2_MC_IS, 206 VCAP_KF_L2_PAYLOAD_ETYPE, 207 VCAP_KF_L2_SMAC, 208 VCAP_KF_L3_DIP_EQ_SIP_IS, 209 VCAP_KF_L3_DST_IS, 210 VCAP_KF_L3_FRAGMENT_TYPE, 211 VCAP_KF_L3_FRAG_INVLD_L4_LEN, 212 VCAP_KF_L3_IP4_DIP, 213 VCAP_KF_L3_IP4_SIP, 214 VCAP_KF_L3_IP6_DIP, 215 VCAP_KF_L3_IP6_SIP, 216 VCAP_KF_L3_IP_PROTO, 217 VCAP_KF_L3_OPTIONS_IS, 218 VCAP_KF_L3_PAYLOAD, 219 VCAP_KF_L3_RT_IS, 220 VCAP_KF_L3_TOS, 221 VCAP_KF_L3_TTL_GT0, 222 VCAP_KF_L4_ACK, 223 VCAP_KF_L4_DPORT, 224 VCAP_KF_L4_FIN, 225 VCAP_KF_L4_PAYLOAD, 226 VCAP_KF_L4_PSH, 227 VCAP_KF_L4_RNG, 228 VCAP_KF_L4_RST, 229 VCAP_KF_L4_SEQUENCE_EQ0_IS, 230 VCAP_KF_L4_SPORT, 231 VCAP_KF_L4_SPORT_EQ_DPORT_IS, 232 VCAP_KF_L4_SYN, 233 VCAP_KF_L4_URG, 234 VCAP_KF_LOOKUP_FIRST_IS, 235 VCAP_KF_LOOKUP_PAG, 236 VCAP_KF_OAM_CCM_CNTS_EQ0, 237 VCAP_KF_OAM_Y1731_IS, 238 VCAP_KF_TCP_IS, 239 VCAP_KF_TCP_UDP_IS, 240 VCAP_KF_TYPE, 241 }; 242 243 /* Actionset names with origin information */ 244 enum vcap_actionfield_set { 245 VCAP_AFS_NO_VALUE, /* initial value */ 246 VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3 */ 247 }; 248 249 /* List of actionfields with description 250 * 251 * VCAP_AF_CNT_ID: W12, sparx5: is2 252 * Counter ID, used per lookup to index the 4K frame counters (ANA_ACL:CNT_TBL). 253 * Multiple VCAP IS2 entries can use the same counter. 254 * VCAP_AF_CPU_COPY_ENA: W1, sparx5: is2 255 * Setting this bit to 1 causes all frames that hit this action to be copied to 256 * the CPU extraction queue specified in CPU_QUEUE_NUM. 257 * VCAP_AF_CPU_QUEUE_NUM: W3, sparx5: is2 258 * CPU queue number. Used when CPU_COPY_ENA is set. 259 * VCAP_AF_HIT_ME_ONCE: W1, sparx5: is2 260 * Setting this bit to 1 causes the first frame that hits this action where the 261 * HIT_CNT counter is zero to be copied to the CPU extraction queue specified in 262 * CPU_QUEUE_NUM. The HIT_CNT counter is then incremented and any frames that 263 * hit this action later are not copied to the CPU. To re-enable the HIT_ME_ONCE 264 * functionality, the HIT_CNT counter must be cleared. 265 * VCAP_AF_IGNORE_PIPELINE_CTRL: W1, sparx5: is2 266 * Ignore ingress pipeline control. This enforces the use of the VCAP IS2 action 267 * even when the pipeline control has terminated the frame before VCAP IS2. 268 * VCAP_AF_INTR_ENA: W1, sparx5: is2 269 * If set, an interrupt is triggered when this rule is hit 270 * VCAP_AF_LRN_DIS: W1, sparx5: is2 271 * Setting this bit to 1 disables learning of frames hitting this action. 272 * VCAP_AF_MASK_MODE: W3, sparx5: is2 273 * Controls the PORT_MASK use. Sparx5: 0: OR_DSTMASK, 1: AND_VLANMASK, 2: 274 * REPLACE_PGID, 3: REPLACE_ALL, 4: REDIR_PGID, 5: OR_PGID_MASK, 6: VSTAX, 7: 275 * Not applicable. LAN966X: 0: No action, 1: Permit/deny (AND), 2: Policy 276 * forwarding (DMAC lookup), 3: Redirect. The CPU port is untouched by 277 * MASK_MODE. 278 * VCAP_AF_MATCH_ID: W16, sparx5: is2 279 * Logical ID for the entry. The MATCH_ID is extracted together with the frame 280 * if the frame is forwarded to the CPU (CPU_COPY_ENA). The result is placed in 281 * IFH.CL_RSLT. 282 * VCAP_AF_MATCH_ID_MASK: W16, sparx5: is2 283 * Mask used by MATCH_ID. 284 * VCAP_AF_MIRROR_PROBE: W2, sparx5: is2 285 * Mirroring performed according to configuration of a mirror probe. 0: No 286 * mirroring. 1: Mirror probe 0. 2: Mirror probe 1. 3: Mirror probe 2 287 * VCAP_AF_PIPELINE_FORCE_ENA: W1, sparx5: is2 288 * If set, use PIPELINE_PT unconditionally and set PIPELINE_ACT = NONE if 289 * PIPELINE_PT == NONE. Overrules previous settings of pipeline point. 290 * VCAP_AF_PIPELINE_PT: W5, sparx5: is2 291 * Pipeline point used if PIPELINE_FORCE_ENA is set 292 * VCAP_AF_POLICE_ENA: W1, sparx5: is2 293 * Setting this bit to 1 causes frames that hit this action to be policed by the 294 * ACL policer specified in POLICE_IDX. Only applies to the first lookup. 295 * VCAP_AF_POLICE_IDX: W6, sparx5: is2 296 * Selects VCAP policer used when policing frames (POLICE_ENA) 297 * VCAP_AF_PORT_MASK: W68, sparx5: is2 298 * Port mask applied to the forwarding decision based on MASK_MODE. 299 * VCAP_AF_RT_DIS: W1, sparx5: is2 300 * If set, routing is disallowed. Only applies when IS_INNER_ACL is 0. See also 301 * IGR_ACL_ENA, EGR_ACL_ENA, and RLEG_STAT_IDX. 302 */ 303 304 /* Actionfield names */ 305 enum vcap_action_field { 306 VCAP_AF_NO_VALUE, /* initial value */ 307 VCAP_AF_CNT_ID, 308 VCAP_AF_CPU_COPY_ENA, 309 VCAP_AF_CPU_QUEUE_NUM, 310 VCAP_AF_HIT_ME_ONCE, 311 VCAP_AF_IGNORE_PIPELINE_CTRL, 312 VCAP_AF_INTR_ENA, 313 VCAP_AF_LRN_DIS, 314 VCAP_AF_MASK_MODE, 315 VCAP_AF_MATCH_ID, 316 VCAP_AF_MATCH_ID_MASK, 317 VCAP_AF_MIRROR_PROBE, 318 VCAP_AF_PIPELINE_FORCE_ENA, 319 VCAP_AF_PIPELINE_PT, 320 VCAP_AF_POLICE_ENA, 321 VCAP_AF_POLICE_IDX, 322 VCAP_AF_PORT_MASK, 323 VCAP_AF_RT_DIS, 324 }; 325 326 #endif /* __VCAP_AG_API__ */ 327