1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries. 3 * Microchip VCAP API 4 */ 5 6 /* This file is autogenerated by cml-utils 2023-01-17 16:55:38 +0100. 7 * Commit ID: cc027a9bd71002aebf074df5ad8584fe1545e05e 8 */ 9 10 #include <linux/types.h> 11 #include <linux/kernel.h> 12 13 #include "vcap_api.h" 14 #include "sparx5_vcap_ag_api.h" 15 16 /* keyfields */ 17 static const struct vcap_field is0_normal_7tuple_keyfield[] = { 18 [VCAP_KF_TYPE] = { 19 .type = VCAP_FIELD_BIT, 20 .offset = 0, 21 .width = 1, 22 }, 23 [VCAP_KF_LOOKUP_FIRST_IS] = { 24 .type = VCAP_FIELD_BIT, 25 .offset = 1, 26 .width = 1, 27 }, 28 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { 29 .type = VCAP_FIELD_U32, 30 .offset = 2, 31 .width = 2, 32 }, 33 [VCAP_KF_LOOKUP_GEN_IDX] = { 34 .type = VCAP_FIELD_U32, 35 .offset = 4, 36 .width = 12, 37 }, 38 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 39 .type = VCAP_FIELD_U32, 40 .offset = 16, 41 .width = 2, 42 }, 43 [VCAP_KF_IF_IGR_PORT_MASK] = { 44 .type = VCAP_FIELD_U72, 45 .offset = 18, 46 .width = 65, 47 }, 48 [VCAP_KF_L2_MC_IS] = { 49 .type = VCAP_FIELD_BIT, 50 .offset = 83, 51 .width = 1, 52 }, 53 [VCAP_KF_L2_BC_IS] = { 54 .type = VCAP_FIELD_BIT, 55 .offset = 84, 56 .width = 1, 57 }, 58 [VCAP_KF_8021Q_VLAN_TAGS] = { 59 .type = VCAP_FIELD_U32, 60 .offset = 85, 61 .width = 3, 62 }, 63 [VCAP_KF_8021Q_TPID0] = { 64 .type = VCAP_FIELD_U32, 65 .offset = 88, 66 .width = 3, 67 }, 68 [VCAP_KF_8021Q_PCP0] = { 69 .type = VCAP_FIELD_U32, 70 .offset = 91, 71 .width = 3, 72 }, 73 [VCAP_KF_8021Q_DEI0] = { 74 .type = VCAP_FIELD_BIT, 75 .offset = 94, 76 .width = 1, 77 }, 78 [VCAP_KF_8021Q_VID0] = { 79 .type = VCAP_FIELD_U32, 80 .offset = 95, 81 .width = 12, 82 }, 83 [VCAP_KF_8021Q_TPID1] = { 84 .type = VCAP_FIELD_U32, 85 .offset = 107, 86 .width = 3, 87 }, 88 [VCAP_KF_8021Q_PCP1] = { 89 .type = VCAP_FIELD_U32, 90 .offset = 110, 91 .width = 3, 92 }, 93 [VCAP_KF_8021Q_DEI1] = { 94 .type = VCAP_FIELD_BIT, 95 .offset = 113, 96 .width = 1, 97 }, 98 [VCAP_KF_8021Q_VID1] = { 99 .type = VCAP_FIELD_U32, 100 .offset = 114, 101 .width = 12, 102 }, 103 [VCAP_KF_8021Q_TPID2] = { 104 .type = VCAP_FIELD_U32, 105 .offset = 126, 106 .width = 3, 107 }, 108 [VCAP_KF_8021Q_PCP2] = { 109 .type = VCAP_FIELD_U32, 110 .offset = 129, 111 .width = 3, 112 }, 113 [VCAP_KF_8021Q_DEI2] = { 114 .type = VCAP_FIELD_BIT, 115 .offset = 132, 116 .width = 1, 117 }, 118 [VCAP_KF_8021Q_VID2] = { 119 .type = VCAP_FIELD_U32, 120 .offset = 133, 121 .width = 12, 122 }, 123 [VCAP_KF_L2_DMAC] = { 124 .type = VCAP_FIELD_U48, 125 .offset = 145, 126 .width = 48, 127 }, 128 [VCAP_KF_L2_SMAC] = { 129 .type = VCAP_FIELD_U48, 130 .offset = 193, 131 .width = 48, 132 }, 133 [VCAP_KF_IP_MC_IS] = { 134 .type = VCAP_FIELD_BIT, 135 .offset = 241, 136 .width = 1, 137 }, 138 [VCAP_KF_ETYPE_LEN_IS] = { 139 .type = VCAP_FIELD_BIT, 140 .offset = 242, 141 .width = 1, 142 }, 143 [VCAP_KF_ETYPE] = { 144 .type = VCAP_FIELD_U32, 145 .offset = 243, 146 .width = 16, 147 }, 148 [VCAP_KF_IP_SNAP_IS] = { 149 .type = VCAP_FIELD_BIT, 150 .offset = 259, 151 .width = 1, 152 }, 153 [VCAP_KF_IP4_IS] = { 154 .type = VCAP_FIELD_BIT, 155 .offset = 260, 156 .width = 1, 157 }, 158 [VCAP_KF_L3_FRAGMENT_TYPE] = { 159 .type = VCAP_FIELD_U32, 160 .offset = 261, 161 .width = 2, 162 }, 163 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 164 .type = VCAP_FIELD_BIT, 165 .offset = 263, 166 .width = 1, 167 }, 168 [VCAP_KF_L3_OPTIONS_IS] = { 169 .type = VCAP_FIELD_BIT, 170 .offset = 264, 171 .width = 1, 172 }, 173 [VCAP_KF_L3_DSCP] = { 174 .type = VCAP_FIELD_U32, 175 .offset = 265, 176 .width = 6, 177 }, 178 [VCAP_KF_L3_IP6_DIP] = { 179 .type = VCAP_FIELD_U128, 180 .offset = 271, 181 .width = 128, 182 }, 183 [VCAP_KF_L3_IP6_SIP] = { 184 .type = VCAP_FIELD_U128, 185 .offset = 399, 186 .width = 128, 187 }, 188 [VCAP_KF_TCP_UDP_IS] = { 189 .type = VCAP_FIELD_BIT, 190 .offset = 527, 191 .width = 1, 192 }, 193 [VCAP_KF_TCP_IS] = { 194 .type = VCAP_FIELD_BIT, 195 .offset = 528, 196 .width = 1, 197 }, 198 [VCAP_KF_L4_SPORT] = { 199 .type = VCAP_FIELD_U32, 200 .offset = 529, 201 .width = 16, 202 }, 203 [VCAP_KF_L4_RNG] = { 204 .type = VCAP_FIELD_U32, 205 .offset = 545, 206 .width = 8, 207 }, 208 }; 209 210 static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { 211 [VCAP_KF_TYPE] = { 212 .type = VCAP_FIELD_U32, 213 .offset = 0, 214 .width = 2, 215 }, 216 [VCAP_KF_LOOKUP_FIRST_IS] = { 217 .type = VCAP_FIELD_BIT, 218 .offset = 2, 219 .width = 1, 220 }, 221 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { 222 .type = VCAP_FIELD_U32, 223 .offset = 3, 224 .width = 2, 225 }, 226 [VCAP_KF_LOOKUP_GEN_IDX] = { 227 .type = VCAP_FIELD_U32, 228 .offset = 5, 229 .width = 12, 230 }, 231 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 232 .type = VCAP_FIELD_U32, 233 .offset = 17, 234 .width = 2, 235 }, 236 [VCAP_KF_IF_IGR_PORT_MASK] = { 237 .type = VCAP_FIELD_U72, 238 .offset = 19, 239 .width = 65, 240 }, 241 [VCAP_KF_L2_MC_IS] = { 242 .type = VCAP_FIELD_BIT, 243 .offset = 84, 244 .width = 1, 245 }, 246 [VCAP_KF_L2_BC_IS] = { 247 .type = VCAP_FIELD_BIT, 248 .offset = 85, 249 .width = 1, 250 }, 251 [VCAP_KF_8021Q_VLAN_TAGS] = { 252 .type = VCAP_FIELD_U32, 253 .offset = 86, 254 .width = 3, 255 }, 256 [VCAP_KF_8021Q_TPID0] = { 257 .type = VCAP_FIELD_U32, 258 .offset = 89, 259 .width = 3, 260 }, 261 [VCAP_KF_8021Q_PCP0] = { 262 .type = VCAP_FIELD_U32, 263 .offset = 92, 264 .width = 3, 265 }, 266 [VCAP_KF_8021Q_DEI0] = { 267 .type = VCAP_FIELD_BIT, 268 .offset = 95, 269 .width = 1, 270 }, 271 [VCAP_KF_8021Q_VID0] = { 272 .type = VCAP_FIELD_U32, 273 .offset = 96, 274 .width = 12, 275 }, 276 [VCAP_KF_8021Q_TPID1] = { 277 .type = VCAP_FIELD_U32, 278 .offset = 108, 279 .width = 3, 280 }, 281 [VCAP_KF_8021Q_PCP1] = { 282 .type = VCAP_FIELD_U32, 283 .offset = 111, 284 .width = 3, 285 }, 286 [VCAP_KF_8021Q_DEI1] = { 287 .type = VCAP_FIELD_BIT, 288 .offset = 114, 289 .width = 1, 290 }, 291 [VCAP_KF_8021Q_VID1] = { 292 .type = VCAP_FIELD_U32, 293 .offset = 115, 294 .width = 12, 295 }, 296 [VCAP_KF_8021Q_TPID2] = { 297 .type = VCAP_FIELD_U32, 298 .offset = 127, 299 .width = 3, 300 }, 301 [VCAP_KF_8021Q_PCP2] = { 302 .type = VCAP_FIELD_U32, 303 .offset = 130, 304 .width = 3, 305 }, 306 [VCAP_KF_8021Q_DEI2] = { 307 .type = VCAP_FIELD_BIT, 308 .offset = 133, 309 .width = 1, 310 }, 311 [VCAP_KF_8021Q_VID2] = { 312 .type = VCAP_FIELD_U32, 313 .offset = 134, 314 .width = 12, 315 }, 316 [VCAP_KF_IP_MC_IS] = { 317 .type = VCAP_FIELD_BIT, 318 .offset = 146, 319 .width = 1, 320 }, 321 [VCAP_KF_IP4_IS] = { 322 .type = VCAP_FIELD_BIT, 323 .offset = 147, 324 .width = 1, 325 }, 326 [VCAP_KF_L3_FRAGMENT_TYPE] = { 327 .type = VCAP_FIELD_U32, 328 .offset = 148, 329 .width = 2, 330 }, 331 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 332 .type = VCAP_FIELD_BIT, 333 .offset = 150, 334 .width = 1, 335 }, 336 [VCAP_KF_L3_OPTIONS_IS] = { 337 .type = VCAP_FIELD_BIT, 338 .offset = 151, 339 .width = 1, 340 }, 341 [VCAP_KF_L3_DSCP] = { 342 .type = VCAP_FIELD_U32, 343 .offset = 152, 344 .width = 6, 345 }, 346 [VCAP_KF_L3_IP4_DIP] = { 347 .type = VCAP_FIELD_U32, 348 .offset = 158, 349 .width = 32, 350 }, 351 [VCAP_KF_L3_IP4_SIP] = { 352 .type = VCAP_FIELD_U32, 353 .offset = 190, 354 .width = 32, 355 }, 356 [VCAP_KF_L3_IP_PROTO] = { 357 .type = VCAP_FIELD_U32, 358 .offset = 222, 359 .width = 8, 360 }, 361 [VCAP_KF_TCP_UDP_IS] = { 362 .type = VCAP_FIELD_BIT, 363 .offset = 230, 364 .width = 1, 365 }, 366 [VCAP_KF_TCP_IS] = { 367 .type = VCAP_FIELD_BIT, 368 .offset = 231, 369 .width = 1, 370 }, 371 [VCAP_KF_L4_RNG] = { 372 .type = VCAP_FIELD_U32, 373 .offset = 232, 374 .width = 8, 375 }, 376 [VCAP_KF_IP_PAYLOAD_5TUPLE] = { 377 .type = VCAP_FIELD_U32, 378 .offset = 240, 379 .width = 32, 380 }, 381 }; 382 383 static const struct vcap_field is2_mac_etype_keyfield[] = { 384 [VCAP_KF_TYPE] = { 385 .type = VCAP_FIELD_U32, 386 .offset = 0, 387 .width = 4, 388 }, 389 [VCAP_KF_LOOKUP_FIRST_IS] = { 390 .type = VCAP_FIELD_BIT, 391 .offset = 4, 392 .width = 1, 393 }, 394 [VCAP_KF_LOOKUP_PAG] = { 395 .type = VCAP_FIELD_U32, 396 .offset = 5, 397 .width = 8, 398 }, 399 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 400 .type = VCAP_FIELD_BIT, 401 .offset = 13, 402 .width = 1, 403 }, 404 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 405 .type = VCAP_FIELD_U32, 406 .offset = 14, 407 .width = 4, 408 }, 409 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 410 .type = VCAP_FIELD_U32, 411 .offset = 18, 412 .width = 2, 413 }, 414 [VCAP_KF_IF_IGR_PORT_MASK] = { 415 .type = VCAP_FIELD_U32, 416 .offset = 20, 417 .width = 32, 418 }, 419 [VCAP_KF_L2_MC_IS] = { 420 .type = VCAP_FIELD_BIT, 421 .offset = 52, 422 .width = 1, 423 }, 424 [VCAP_KF_L2_BC_IS] = { 425 .type = VCAP_FIELD_BIT, 426 .offset = 53, 427 .width = 1, 428 }, 429 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 430 .type = VCAP_FIELD_BIT, 431 .offset = 54, 432 .width = 1, 433 }, 434 [VCAP_KF_ISDX_GT0_IS] = { 435 .type = VCAP_FIELD_BIT, 436 .offset = 55, 437 .width = 1, 438 }, 439 [VCAP_KF_ISDX_CLS] = { 440 .type = VCAP_FIELD_U32, 441 .offset = 56, 442 .width = 12, 443 }, 444 [VCAP_KF_8021Q_VID_CLS] = { 445 .type = VCAP_FIELD_U32, 446 .offset = 68, 447 .width = 13, 448 }, 449 [VCAP_KF_8021Q_DEI_CLS] = { 450 .type = VCAP_FIELD_BIT, 451 .offset = 81, 452 .width = 1, 453 }, 454 [VCAP_KF_8021Q_PCP_CLS] = { 455 .type = VCAP_FIELD_U32, 456 .offset = 82, 457 .width = 3, 458 }, 459 [VCAP_KF_L2_FWD_IS] = { 460 .type = VCAP_FIELD_BIT, 461 .offset = 85, 462 .width = 1, 463 }, 464 [VCAP_KF_L3_RT_IS] = { 465 .type = VCAP_FIELD_BIT, 466 .offset = 88, 467 .width = 1, 468 }, 469 [VCAP_KF_L3_DST_IS] = { 470 .type = VCAP_FIELD_BIT, 471 .offset = 89, 472 .width = 1, 473 }, 474 [VCAP_KF_L2_DMAC] = { 475 .type = VCAP_FIELD_U48, 476 .offset = 90, 477 .width = 48, 478 }, 479 [VCAP_KF_L2_SMAC] = { 480 .type = VCAP_FIELD_U48, 481 .offset = 138, 482 .width = 48, 483 }, 484 [VCAP_KF_ETYPE_LEN_IS] = { 485 .type = VCAP_FIELD_BIT, 486 .offset = 186, 487 .width = 1, 488 }, 489 [VCAP_KF_ETYPE] = { 490 .type = VCAP_FIELD_U32, 491 .offset = 187, 492 .width = 16, 493 }, 494 [VCAP_KF_L2_PAYLOAD_ETYPE] = { 495 .type = VCAP_FIELD_U64, 496 .offset = 203, 497 .width = 64, 498 }, 499 [VCAP_KF_L4_RNG] = { 500 .type = VCAP_FIELD_U32, 501 .offset = 267, 502 .width = 16, 503 }, 504 [VCAP_KF_OAM_CCM_CNTS_EQ0] = { 505 .type = VCAP_FIELD_BIT, 506 .offset = 283, 507 .width = 1, 508 }, 509 [VCAP_KF_OAM_Y1731_IS] = { 510 .type = VCAP_FIELD_BIT, 511 .offset = 284, 512 .width = 1, 513 }, 514 }; 515 516 static const struct vcap_field is2_arp_keyfield[] = { 517 [VCAP_KF_TYPE] = { 518 .type = VCAP_FIELD_U32, 519 .offset = 0, 520 .width = 4, 521 }, 522 [VCAP_KF_LOOKUP_FIRST_IS] = { 523 .type = VCAP_FIELD_BIT, 524 .offset = 4, 525 .width = 1, 526 }, 527 [VCAP_KF_LOOKUP_PAG] = { 528 .type = VCAP_FIELD_U32, 529 .offset = 5, 530 .width = 8, 531 }, 532 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 533 .type = VCAP_FIELD_BIT, 534 .offset = 13, 535 .width = 1, 536 }, 537 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 538 .type = VCAP_FIELD_U32, 539 .offset = 14, 540 .width = 4, 541 }, 542 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 543 .type = VCAP_FIELD_U32, 544 .offset = 18, 545 .width = 2, 546 }, 547 [VCAP_KF_IF_IGR_PORT_MASK] = { 548 .type = VCAP_FIELD_U32, 549 .offset = 20, 550 .width = 32, 551 }, 552 [VCAP_KF_L2_MC_IS] = { 553 .type = VCAP_FIELD_BIT, 554 .offset = 52, 555 .width = 1, 556 }, 557 [VCAP_KF_L2_BC_IS] = { 558 .type = VCAP_FIELD_BIT, 559 .offset = 53, 560 .width = 1, 561 }, 562 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 563 .type = VCAP_FIELD_BIT, 564 .offset = 54, 565 .width = 1, 566 }, 567 [VCAP_KF_ISDX_GT0_IS] = { 568 .type = VCAP_FIELD_BIT, 569 .offset = 55, 570 .width = 1, 571 }, 572 [VCAP_KF_ISDX_CLS] = { 573 .type = VCAP_FIELD_U32, 574 .offset = 56, 575 .width = 12, 576 }, 577 [VCAP_KF_8021Q_VID_CLS] = { 578 .type = VCAP_FIELD_U32, 579 .offset = 68, 580 .width = 13, 581 }, 582 [VCAP_KF_8021Q_DEI_CLS] = { 583 .type = VCAP_FIELD_BIT, 584 .offset = 81, 585 .width = 1, 586 }, 587 [VCAP_KF_8021Q_PCP_CLS] = { 588 .type = VCAP_FIELD_U32, 589 .offset = 82, 590 .width = 3, 591 }, 592 [VCAP_KF_L2_FWD_IS] = { 593 .type = VCAP_FIELD_BIT, 594 .offset = 85, 595 .width = 1, 596 }, 597 [VCAP_KF_L2_SMAC] = { 598 .type = VCAP_FIELD_U48, 599 .offset = 86, 600 .width = 48, 601 }, 602 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { 603 .type = VCAP_FIELD_BIT, 604 .offset = 134, 605 .width = 1, 606 }, 607 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { 608 .type = VCAP_FIELD_BIT, 609 .offset = 135, 610 .width = 1, 611 }, 612 [VCAP_KF_ARP_LEN_OK_IS] = { 613 .type = VCAP_FIELD_BIT, 614 .offset = 136, 615 .width = 1, 616 }, 617 [VCAP_KF_ARP_TGT_MATCH_IS] = { 618 .type = VCAP_FIELD_BIT, 619 .offset = 137, 620 .width = 1, 621 }, 622 [VCAP_KF_ARP_SENDER_MATCH_IS] = { 623 .type = VCAP_FIELD_BIT, 624 .offset = 138, 625 .width = 1, 626 }, 627 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { 628 .type = VCAP_FIELD_BIT, 629 .offset = 139, 630 .width = 1, 631 }, 632 [VCAP_KF_ARP_OPCODE] = { 633 .type = VCAP_FIELD_U32, 634 .offset = 140, 635 .width = 2, 636 }, 637 [VCAP_KF_L3_IP4_DIP] = { 638 .type = VCAP_FIELD_U32, 639 .offset = 142, 640 .width = 32, 641 }, 642 [VCAP_KF_L3_IP4_SIP] = { 643 .type = VCAP_FIELD_U32, 644 .offset = 174, 645 .width = 32, 646 }, 647 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 648 .type = VCAP_FIELD_BIT, 649 .offset = 206, 650 .width = 1, 651 }, 652 [VCAP_KF_L4_RNG] = { 653 .type = VCAP_FIELD_U32, 654 .offset = 207, 655 .width = 16, 656 }, 657 }; 658 659 static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { 660 [VCAP_KF_TYPE] = { 661 .type = VCAP_FIELD_U32, 662 .offset = 0, 663 .width = 4, 664 }, 665 [VCAP_KF_LOOKUP_FIRST_IS] = { 666 .type = VCAP_FIELD_BIT, 667 .offset = 4, 668 .width = 1, 669 }, 670 [VCAP_KF_LOOKUP_PAG] = { 671 .type = VCAP_FIELD_U32, 672 .offset = 5, 673 .width = 8, 674 }, 675 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 676 .type = VCAP_FIELD_BIT, 677 .offset = 13, 678 .width = 1, 679 }, 680 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 681 .type = VCAP_FIELD_U32, 682 .offset = 14, 683 .width = 4, 684 }, 685 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 686 .type = VCAP_FIELD_U32, 687 .offset = 18, 688 .width = 2, 689 }, 690 [VCAP_KF_IF_IGR_PORT_MASK] = { 691 .type = VCAP_FIELD_U32, 692 .offset = 20, 693 .width = 32, 694 }, 695 [VCAP_KF_L2_MC_IS] = { 696 .type = VCAP_FIELD_BIT, 697 .offset = 52, 698 .width = 1, 699 }, 700 [VCAP_KF_L2_BC_IS] = { 701 .type = VCAP_FIELD_BIT, 702 .offset = 53, 703 .width = 1, 704 }, 705 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 706 .type = VCAP_FIELD_BIT, 707 .offset = 54, 708 .width = 1, 709 }, 710 [VCAP_KF_ISDX_GT0_IS] = { 711 .type = VCAP_FIELD_BIT, 712 .offset = 55, 713 .width = 1, 714 }, 715 [VCAP_KF_ISDX_CLS] = { 716 .type = VCAP_FIELD_U32, 717 .offset = 56, 718 .width = 12, 719 }, 720 [VCAP_KF_8021Q_VID_CLS] = { 721 .type = VCAP_FIELD_U32, 722 .offset = 68, 723 .width = 13, 724 }, 725 [VCAP_KF_8021Q_DEI_CLS] = { 726 .type = VCAP_FIELD_BIT, 727 .offset = 81, 728 .width = 1, 729 }, 730 [VCAP_KF_8021Q_PCP_CLS] = { 731 .type = VCAP_FIELD_U32, 732 .offset = 82, 733 .width = 3, 734 }, 735 [VCAP_KF_L2_FWD_IS] = { 736 .type = VCAP_FIELD_BIT, 737 .offset = 85, 738 .width = 1, 739 }, 740 [VCAP_KF_L3_RT_IS] = { 741 .type = VCAP_FIELD_BIT, 742 .offset = 88, 743 .width = 1, 744 }, 745 [VCAP_KF_L3_DST_IS] = { 746 .type = VCAP_FIELD_BIT, 747 .offset = 89, 748 .width = 1, 749 }, 750 [VCAP_KF_IP4_IS] = { 751 .type = VCAP_FIELD_BIT, 752 .offset = 90, 753 .width = 1, 754 }, 755 [VCAP_KF_L3_FRAGMENT_TYPE] = { 756 .type = VCAP_FIELD_U32, 757 .offset = 91, 758 .width = 2, 759 }, 760 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 761 .type = VCAP_FIELD_BIT, 762 .offset = 93, 763 .width = 1, 764 }, 765 [VCAP_KF_L3_OPTIONS_IS] = { 766 .type = VCAP_FIELD_BIT, 767 .offset = 94, 768 .width = 1, 769 }, 770 [VCAP_KF_L3_TTL_GT0] = { 771 .type = VCAP_FIELD_BIT, 772 .offset = 95, 773 .width = 1, 774 }, 775 [VCAP_KF_L3_TOS] = { 776 .type = VCAP_FIELD_U32, 777 .offset = 96, 778 .width = 8, 779 }, 780 [VCAP_KF_L3_IP4_DIP] = { 781 .type = VCAP_FIELD_U32, 782 .offset = 104, 783 .width = 32, 784 }, 785 [VCAP_KF_L3_IP4_SIP] = { 786 .type = VCAP_FIELD_U32, 787 .offset = 136, 788 .width = 32, 789 }, 790 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 791 .type = VCAP_FIELD_BIT, 792 .offset = 168, 793 .width = 1, 794 }, 795 [VCAP_KF_TCP_IS] = { 796 .type = VCAP_FIELD_BIT, 797 .offset = 169, 798 .width = 1, 799 }, 800 [VCAP_KF_L4_DPORT] = { 801 .type = VCAP_FIELD_U32, 802 .offset = 170, 803 .width = 16, 804 }, 805 [VCAP_KF_L4_SPORT] = { 806 .type = VCAP_FIELD_U32, 807 .offset = 186, 808 .width = 16, 809 }, 810 [VCAP_KF_L4_RNG] = { 811 .type = VCAP_FIELD_U32, 812 .offset = 202, 813 .width = 16, 814 }, 815 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 816 .type = VCAP_FIELD_BIT, 817 .offset = 218, 818 .width = 1, 819 }, 820 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 821 .type = VCAP_FIELD_BIT, 822 .offset = 219, 823 .width = 1, 824 }, 825 [VCAP_KF_L4_FIN] = { 826 .type = VCAP_FIELD_BIT, 827 .offset = 220, 828 .width = 1, 829 }, 830 [VCAP_KF_L4_SYN] = { 831 .type = VCAP_FIELD_BIT, 832 .offset = 221, 833 .width = 1, 834 }, 835 [VCAP_KF_L4_RST] = { 836 .type = VCAP_FIELD_BIT, 837 .offset = 222, 838 .width = 1, 839 }, 840 [VCAP_KF_L4_PSH] = { 841 .type = VCAP_FIELD_BIT, 842 .offset = 223, 843 .width = 1, 844 }, 845 [VCAP_KF_L4_ACK] = { 846 .type = VCAP_FIELD_BIT, 847 .offset = 224, 848 .width = 1, 849 }, 850 [VCAP_KF_L4_URG] = { 851 .type = VCAP_FIELD_BIT, 852 .offset = 225, 853 .width = 1, 854 }, 855 [VCAP_KF_L4_PAYLOAD] = { 856 .type = VCAP_FIELD_U64, 857 .offset = 226, 858 .width = 64, 859 }, 860 }; 861 862 static const struct vcap_field is2_ip4_other_keyfield[] = { 863 [VCAP_KF_TYPE] = { 864 .type = VCAP_FIELD_U32, 865 .offset = 0, 866 .width = 4, 867 }, 868 [VCAP_KF_LOOKUP_FIRST_IS] = { 869 .type = VCAP_FIELD_BIT, 870 .offset = 4, 871 .width = 1, 872 }, 873 [VCAP_KF_LOOKUP_PAG] = { 874 .type = VCAP_FIELD_U32, 875 .offset = 5, 876 .width = 8, 877 }, 878 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 879 .type = VCAP_FIELD_BIT, 880 .offset = 13, 881 .width = 1, 882 }, 883 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 884 .type = VCAP_FIELD_U32, 885 .offset = 14, 886 .width = 4, 887 }, 888 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 889 .type = VCAP_FIELD_U32, 890 .offset = 18, 891 .width = 2, 892 }, 893 [VCAP_KF_IF_IGR_PORT_MASK] = { 894 .type = VCAP_FIELD_U32, 895 .offset = 20, 896 .width = 32, 897 }, 898 [VCAP_KF_L2_MC_IS] = { 899 .type = VCAP_FIELD_BIT, 900 .offset = 52, 901 .width = 1, 902 }, 903 [VCAP_KF_L2_BC_IS] = { 904 .type = VCAP_FIELD_BIT, 905 .offset = 53, 906 .width = 1, 907 }, 908 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 909 .type = VCAP_FIELD_BIT, 910 .offset = 54, 911 .width = 1, 912 }, 913 [VCAP_KF_ISDX_GT0_IS] = { 914 .type = VCAP_FIELD_BIT, 915 .offset = 55, 916 .width = 1, 917 }, 918 [VCAP_KF_ISDX_CLS] = { 919 .type = VCAP_FIELD_U32, 920 .offset = 56, 921 .width = 12, 922 }, 923 [VCAP_KF_8021Q_VID_CLS] = { 924 .type = VCAP_FIELD_U32, 925 .offset = 68, 926 .width = 13, 927 }, 928 [VCAP_KF_8021Q_DEI_CLS] = { 929 .type = VCAP_FIELD_BIT, 930 .offset = 81, 931 .width = 1, 932 }, 933 [VCAP_KF_8021Q_PCP_CLS] = { 934 .type = VCAP_FIELD_U32, 935 .offset = 82, 936 .width = 3, 937 }, 938 [VCAP_KF_L2_FWD_IS] = { 939 .type = VCAP_FIELD_BIT, 940 .offset = 85, 941 .width = 1, 942 }, 943 [VCAP_KF_L3_RT_IS] = { 944 .type = VCAP_FIELD_BIT, 945 .offset = 88, 946 .width = 1, 947 }, 948 [VCAP_KF_L3_DST_IS] = { 949 .type = VCAP_FIELD_BIT, 950 .offset = 89, 951 .width = 1, 952 }, 953 [VCAP_KF_IP4_IS] = { 954 .type = VCAP_FIELD_BIT, 955 .offset = 90, 956 .width = 1, 957 }, 958 [VCAP_KF_L3_FRAGMENT_TYPE] = { 959 .type = VCAP_FIELD_U32, 960 .offset = 91, 961 .width = 2, 962 }, 963 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { 964 .type = VCAP_FIELD_BIT, 965 .offset = 93, 966 .width = 1, 967 }, 968 [VCAP_KF_L3_OPTIONS_IS] = { 969 .type = VCAP_FIELD_BIT, 970 .offset = 94, 971 .width = 1, 972 }, 973 [VCAP_KF_L3_TTL_GT0] = { 974 .type = VCAP_FIELD_BIT, 975 .offset = 95, 976 .width = 1, 977 }, 978 [VCAP_KF_L3_TOS] = { 979 .type = VCAP_FIELD_U32, 980 .offset = 96, 981 .width = 8, 982 }, 983 [VCAP_KF_L3_IP4_DIP] = { 984 .type = VCAP_FIELD_U32, 985 .offset = 104, 986 .width = 32, 987 }, 988 [VCAP_KF_L3_IP4_SIP] = { 989 .type = VCAP_FIELD_U32, 990 .offset = 136, 991 .width = 32, 992 }, 993 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 994 .type = VCAP_FIELD_BIT, 995 .offset = 168, 996 .width = 1, 997 }, 998 [VCAP_KF_L3_IP_PROTO] = { 999 .type = VCAP_FIELD_U32, 1000 .offset = 169, 1001 .width = 8, 1002 }, 1003 [VCAP_KF_L4_RNG] = { 1004 .type = VCAP_FIELD_U32, 1005 .offset = 177, 1006 .width = 16, 1007 }, 1008 [VCAP_KF_L3_PAYLOAD] = { 1009 .type = VCAP_FIELD_U112, 1010 .offset = 193, 1011 .width = 96, 1012 }, 1013 }; 1014 1015 static const struct vcap_field is2_ip6_std_keyfield[] = { 1016 [VCAP_KF_TYPE] = { 1017 .type = VCAP_FIELD_U32, 1018 .offset = 0, 1019 .width = 4, 1020 }, 1021 [VCAP_KF_LOOKUP_FIRST_IS] = { 1022 .type = VCAP_FIELD_BIT, 1023 .offset = 4, 1024 .width = 1, 1025 }, 1026 [VCAP_KF_LOOKUP_PAG] = { 1027 .type = VCAP_FIELD_U32, 1028 .offset = 5, 1029 .width = 8, 1030 }, 1031 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 1032 .type = VCAP_FIELD_BIT, 1033 .offset = 13, 1034 .width = 1, 1035 }, 1036 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 1037 .type = VCAP_FIELD_U32, 1038 .offset = 14, 1039 .width = 4, 1040 }, 1041 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 1042 .type = VCAP_FIELD_U32, 1043 .offset = 18, 1044 .width = 2, 1045 }, 1046 [VCAP_KF_IF_IGR_PORT_MASK] = { 1047 .type = VCAP_FIELD_U32, 1048 .offset = 20, 1049 .width = 32, 1050 }, 1051 [VCAP_KF_L2_MC_IS] = { 1052 .type = VCAP_FIELD_BIT, 1053 .offset = 52, 1054 .width = 1, 1055 }, 1056 [VCAP_KF_L2_BC_IS] = { 1057 .type = VCAP_FIELD_BIT, 1058 .offset = 53, 1059 .width = 1, 1060 }, 1061 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1062 .type = VCAP_FIELD_BIT, 1063 .offset = 54, 1064 .width = 1, 1065 }, 1066 [VCAP_KF_ISDX_GT0_IS] = { 1067 .type = VCAP_FIELD_BIT, 1068 .offset = 55, 1069 .width = 1, 1070 }, 1071 [VCAP_KF_ISDX_CLS] = { 1072 .type = VCAP_FIELD_U32, 1073 .offset = 56, 1074 .width = 12, 1075 }, 1076 [VCAP_KF_8021Q_VID_CLS] = { 1077 .type = VCAP_FIELD_U32, 1078 .offset = 68, 1079 .width = 13, 1080 }, 1081 [VCAP_KF_8021Q_DEI_CLS] = { 1082 .type = VCAP_FIELD_BIT, 1083 .offset = 81, 1084 .width = 1, 1085 }, 1086 [VCAP_KF_8021Q_PCP_CLS] = { 1087 .type = VCAP_FIELD_U32, 1088 .offset = 82, 1089 .width = 3, 1090 }, 1091 [VCAP_KF_L2_FWD_IS] = { 1092 .type = VCAP_FIELD_BIT, 1093 .offset = 85, 1094 .width = 1, 1095 }, 1096 [VCAP_KF_L3_RT_IS] = { 1097 .type = VCAP_FIELD_BIT, 1098 .offset = 88, 1099 .width = 1, 1100 }, 1101 [VCAP_KF_L3_TTL_GT0] = { 1102 .type = VCAP_FIELD_BIT, 1103 .offset = 90, 1104 .width = 1, 1105 }, 1106 [VCAP_KF_L3_IP6_SIP] = { 1107 .type = VCAP_FIELD_U128, 1108 .offset = 91, 1109 .width = 128, 1110 }, 1111 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1112 .type = VCAP_FIELD_BIT, 1113 .offset = 219, 1114 .width = 1, 1115 }, 1116 [VCAP_KF_L3_IP_PROTO] = { 1117 .type = VCAP_FIELD_U32, 1118 .offset = 220, 1119 .width = 8, 1120 }, 1121 [VCAP_KF_L4_RNG] = { 1122 .type = VCAP_FIELD_U32, 1123 .offset = 228, 1124 .width = 16, 1125 }, 1126 [VCAP_KF_L3_PAYLOAD] = { 1127 .type = VCAP_FIELD_U48, 1128 .offset = 244, 1129 .width = 40, 1130 }, 1131 }; 1132 1133 static const struct vcap_field is2_ip_7tuple_keyfield[] = { 1134 [VCAP_KF_TYPE] = { 1135 .type = VCAP_FIELD_U32, 1136 .offset = 0, 1137 .width = 2, 1138 }, 1139 [VCAP_KF_LOOKUP_FIRST_IS] = { 1140 .type = VCAP_FIELD_BIT, 1141 .offset = 2, 1142 .width = 1, 1143 }, 1144 [VCAP_KF_LOOKUP_PAG] = { 1145 .type = VCAP_FIELD_U32, 1146 .offset = 3, 1147 .width = 8, 1148 }, 1149 [VCAP_KF_IF_IGR_PORT_MASK_L3] = { 1150 .type = VCAP_FIELD_BIT, 1151 .offset = 11, 1152 .width = 1, 1153 }, 1154 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { 1155 .type = VCAP_FIELD_U32, 1156 .offset = 12, 1157 .width = 4, 1158 }, 1159 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { 1160 .type = VCAP_FIELD_U32, 1161 .offset = 16, 1162 .width = 2, 1163 }, 1164 [VCAP_KF_IF_IGR_PORT_MASK] = { 1165 .type = VCAP_FIELD_U72, 1166 .offset = 18, 1167 .width = 65, 1168 }, 1169 [VCAP_KF_L2_MC_IS] = { 1170 .type = VCAP_FIELD_BIT, 1171 .offset = 83, 1172 .width = 1, 1173 }, 1174 [VCAP_KF_L2_BC_IS] = { 1175 .type = VCAP_FIELD_BIT, 1176 .offset = 84, 1177 .width = 1, 1178 }, 1179 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1180 .type = VCAP_FIELD_BIT, 1181 .offset = 85, 1182 .width = 1, 1183 }, 1184 [VCAP_KF_ISDX_GT0_IS] = { 1185 .type = VCAP_FIELD_BIT, 1186 .offset = 86, 1187 .width = 1, 1188 }, 1189 [VCAP_KF_ISDX_CLS] = { 1190 .type = VCAP_FIELD_U32, 1191 .offset = 87, 1192 .width = 12, 1193 }, 1194 [VCAP_KF_8021Q_VID_CLS] = { 1195 .type = VCAP_FIELD_U32, 1196 .offset = 99, 1197 .width = 13, 1198 }, 1199 [VCAP_KF_8021Q_DEI_CLS] = { 1200 .type = VCAP_FIELD_BIT, 1201 .offset = 112, 1202 .width = 1, 1203 }, 1204 [VCAP_KF_8021Q_PCP_CLS] = { 1205 .type = VCAP_FIELD_U32, 1206 .offset = 113, 1207 .width = 3, 1208 }, 1209 [VCAP_KF_L2_FWD_IS] = { 1210 .type = VCAP_FIELD_BIT, 1211 .offset = 116, 1212 .width = 1, 1213 }, 1214 [VCAP_KF_L3_RT_IS] = { 1215 .type = VCAP_FIELD_BIT, 1216 .offset = 119, 1217 .width = 1, 1218 }, 1219 [VCAP_KF_L3_DST_IS] = { 1220 .type = VCAP_FIELD_BIT, 1221 .offset = 120, 1222 .width = 1, 1223 }, 1224 [VCAP_KF_L2_DMAC] = { 1225 .type = VCAP_FIELD_U48, 1226 .offset = 121, 1227 .width = 48, 1228 }, 1229 [VCAP_KF_L2_SMAC] = { 1230 .type = VCAP_FIELD_U48, 1231 .offset = 169, 1232 .width = 48, 1233 }, 1234 [VCAP_KF_IP4_IS] = { 1235 .type = VCAP_FIELD_BIT, 1236 .offset = 217, 1237 .width = 1, 1238 }, 1239 [VCAP_KF_L3_TTL_GT0] = { 1240 .type = VCAP_FIELD_BIT, 1241 .offset = 218, 1242 .width = 1, 1243 }, 1244 [VCAP_KF_L3_TOS] = { 1245 .type = VCAP_FIELD_U32, 1246 .offset = 219, 1247 .width = 8, 1248 }, 1249 [VCAP_KF_L3_IP6_DIP] = { 1250 .type = VCAP_FIELD_U128, 1251 .offset = 227, 1252 .width = 128, 1253 }, 1254 [VCAP_KF_L3_IP6_SIP] = { 1255 .type = VCAP_FIELD_U128, 1256 .offset = 355, 1257 .width = 128, 1258 }, 1259 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1260 .type = VCAP_FIELD_BIT, 1261 .offset = 483, 1262 .width = 1, 1263 }, 1264 [VCAP_KF_TCP_UDP_IS] = { 1265 .type = VCAP_FIELD_BIT, 1266 .offset = 484, 1267 .width = 1, 1268 }, 1269 [VCAP_KF_TCP_IS] = { 1270 .type = VCAP_FIELD_BIT, 1271 .offset = 485, 1272 .width = 1, 1273 }, 1274 [VCAP_KF_L4_DPORT] = { 1275 .type = VCAP_FIELD_U32, 1276 .offset = 486, 1277 .width = 16, 1278 }, 1279 [VCAP_KF_L4_SPORT] = { 1280 .type = VCAP_FIELD_U32, 1281 .offset = 502, 1282 .width = 16, 1283 }, 1284 [VCAP_KF_L4_RNG] = { 1285 .type = VCAP_FIELD_U32, 1286 .offset = 518, 1287 .width = 16, 1288 }, 1289 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 1290 .type = VCAP_FIELD_BIT, 1291 .offset = 534, 1292 .width = 1, 1293 }, 1294 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 1295 .type = VCAP_FIELD_BIT, 1296 .offset = 535, 1297 .width = 1, 1298 }, 1299 [VCAP_KF_L4_FIN] = { 1300 .type = VCAP_FIELD_BIT, 1301 .offset = 536, 1302 .width = 1, 1303 }, 1304 [VCAP_KF_L4_SYN] = { 1305 .type = VCAP_FIELD_BIT, 1306 .offset = 537, 1307 .width = 1, 1308 }, 1309 [VCAP_KF_L4_RST] = { 1310 .type = VCAP_FIELD_BIT, 1311 .offset = 538, 1312 .width = 1, 1313 }, 1314 [VCAP_KF_L4_PSH] = { 1315 .type = VCAP_FIELD_BIT, 1316 .offset = 539, 1317 .width = 1, 1318 }, 1319 [VCAP_KF_L4_ACK] = { 1320 .type = VCAP_FIELD_BIT, 1321 .offset = 540, 1322 .width = 1, 1323 }, 1324 [VCAP_KF_L4_URG] = { 1325 .type = VCAP_FIELD_BIT, 1326 .offset = 541, 1327 .width = 1, 1328 }, 1329 [VCAP_KF_L4_PAYLOAD] = { 1330 .type = VCAP_FIELD_U64, 1331 .offset = 542, 1332 .width = 64, 1333 }, 1334 }; 1335 1336 static const struct vcap_field es2_mac_etype_keyfield[] = { 1337 [VCAP_KF_TYPE] = { 1338 .type = VCAP_FIELD_U32, 1339 .offset = 0, 1340 .width = 3, 1341 }, 1342 [VCAP_KF_LOOKUP_FIRST_IS] = { 1343 .type = VCAP_FIELD_BIT, 1344 .offset = 3, 1345 .width = 1, 1346 }, 1347 [VCAP_KF_L2_MC_IS] = { 1348 .type = VCAP_FIELD_BIT, 1349 .offset = 13, 1350 .width = 1, 1351 }, 1352 [VCAP_KF_L2_BC_IS] = { 1353 .type = VCAP_FIELD_BIT, 1354 .offset = 14, 1355 .width = 1, 1356 }, 1357 [VCAP_KF_ISDX_GT0_IS] = { 1358 .type = VCAP_FIELD_BIT, 1359 .offset = 15, 1360 .width = 1, 1361 }, 1362 [VCAP_KF_ISDX_CLS] = { 1363 .type = VCAP_FIELD_U32, 1364 .offset = 16, 1365 .width = 12, 1366 }, 1367 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1368 .type = VCAP_FIELD_BIT, 1369 .offset = 28, 1370 .width = 1, 1371 }, 1372 [VCAP_KF_8021Q_VID_CLS] = { 1373 .type = VCAP_FIELD_U32, 1374 .offset = 29, 1375 .width = 13, 1376 }, 1377 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1378 .type = VCAP_FIELD_U32, 1379 .offset = 42, 1380 .width = 3, 1381 }, 1382 [VCAP_KF_IF_EGR_PORT_MASK] = { 1383 .type = VCAP_FIELD_U32, 1384 .offset = 45, 1385 .width = 32, 1386 }, 1387 [VCAP_KF_IF_IGR_PORT_SEL] = { 1388 .type = VCAP_FIELD_BIT, 1389 .offset = 77, 1390 .width = 1, 1391 }, 1392 [VCAP_KF_IF_IGR_PORT] = { 1393 .type = VCAP_FIELD_U32, 1394 .offset = 78, 1395 .width = 9, 1396 }, 1397 [VCAP_KF_8021Q_PCP_CLS] = { 1398 .type = VCAP_FIELD_U32, 1399 .offset = 87, 1400 .width = 3, 1401 }, 1402 [VCAP_KF_8021Q_DEI_CLS] = { 1403 .type = VCAP_FIELD_BIT, 1404 .offset = 90, 1405 .width = 1, 1406 }, 1407 [VCAP_KF_COSID_CLS] = { 1408 .type = VCAP_FIELD_U32, 1409 .offset = 91, 1410 .width = 3, 1411 }, 1412 [VCAP_KF_L3_DPL_CLS] = { 1413 .type = VCAP_FIELD_BIT, 1414 .offset = 94, 1415 .width = 1, 1416 }, 1417 [VCAP_KF_L3_RT_IS] = { 1418 .type = VCAP_FIELD_BIT, 1419 .offset = 95, 1420 .width = 1, 1421 }, 1422 [VCAP_KF_L2_DMAC] = { 1423 .type = VCAP_FIELD_U48, 1424 .offset = 99, 1425 .width = 48, 1426 }, 1427 [VCAP_KF_L2_SMAC] = { 1428 .type = VCAP_FIELD_U48, 1429 .offset = 147, 1430 .width = 48, 1431 }, 1432 [VCAP_KF_ETYPE_LEN_IS] = { 1433 .type = VCAP_FIELD_BIT, 1434 .offset = 195, 1435 .width = 1, 1436 }, 1437 [VCAP_KF_ETYPE] = { 1438 .type = VCAP_FIELD_U32, 1439 .offset = 196, 1440 .width = 16, 1441 }, 1442 [VCAP_KF_L2_PAYLOAD_ETYPE] = { 1443 .type = VCAP_FIELD_U64, 1444 .offset = 212, 1445 .width = 64, 1446 }, 1447 [VCAP_KF_OAM_CCM_CNTS_EQ0] = { 1448 .type = VCAP_FIELD_BIT, 1449 .offset = 276, 1450 .width = 1, 1451 }, 1452 [VCAP_KF_OAM_Y1731_IS] = { 1453 .type = VCAP_FIELD_BIT, 1454 .offset = 277, 1455 .width = 1, 1456 }, 1457 }; 1458 1459 static const struct vcap_field es2_arp_keyfield[] = { 1460 [VCAP_KF_TYPE] = { 1461 .type = VCAP_FIELD_U32, 1462 .offset = 0, 1463 .width = 3, 1464 }, 1465 [VCAP_KF_LOOKUP_FIRST_IS] = { 1466 .type = VCAP_FIELD_BIT, 1467 .offset = 3, 1468 .width = 1, 1469 }, 1470 [VCAP_KF_L2_MC_IS] = { 1471 .type = VCAP_FIELD_BIT, 1472 .offset = 13, 1473 .width = 1, 1474 }, 1475 [VCAP_KF_L2_BC_IS] = { 1476 .type = VCAP_FIELD_BIT, 1477 .offset = 14, 1478 .width = 1, 1479 }, 1480 [VCAP_KF_ISDX_GT0_IS] = { 1481 .type = VCAP_FIELD_BIT, 1482 .offset = 15, 1483 .width = 1, 1484 }, 1485 [VCAP_KF_ISDX_CLS] = { 1486 .type = VCAP_FIELD_U32, 1487 .offset = 16, 1488 .width = 12, 1489 }, 1490 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1491 .type = VCAP_FIELD_BIT, 1492 .offset = 28, 1493 .width = 1, 1494 }, 1495 [VCAP_KF_8021Q_VID_CLS] = { 1496 .type = VCAP_FIELD_U32, 1497 .offset = 29, 1498 .width = 13, 1499 }, 1500 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1501 .type = VCAP_FIELD_U32, 1502 .offset = 42, 1503 .width = 3, 1504 }, 1505 [VCAP_KF_IF_EGR_PORT_MASK] = { 1506 .type = VCAP_FIELD_U32, 1507 .offset = 45, 1508 .width = 32, 1509 }, 1510 [VCAP_KF_IF_IGR_PORT_SEL] = { 1511 .type = VCAP_FIELD_BIT, 1512 .offset = 77, 1513 .width = 1, 1514 }, 1515 [VCAP_KF_IF_IGR_PORT] = { 1516 .type = VCAP_FIELD_U32, 1517 .offset = 78, 1518 .width = 9, 1519 }, 1520 [VCAP_KF_8021Q_PCP_CLS] = { 1521 .type = VCAP_FIELD_U32, 1522 .offset = 87, 1523 .width = 3, 1524 }, 1525 [VCAP_KF_8021Q_DEI_CLS] = { 1526 .type = VCAP_FIELD_BIT, 1527 .offset = 90, 1528 .width = 1, 1529 }, 1530 [VCAP_KF_COSID_CLS] = { 1531 .type = VCAP_FIELD_U32, 1532 .offset = 91, 1533 .width = 3, 1534 }, 1535 [VCAP_KF_L3_DPL_CLS] = { 1536 .type = VCAP_FIELD_BIT, 1537 .offset = 94, 1538 .width = 1, 1539 }, 1540 [VCAP_KF_L2_SMAC] = { 1541 .type = VCAP_FIELD_U48, 1542 .offset = 98, 1543 .width = 48, 1544 }, 1545 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { 1546 .type = VCAP_FIELD_BIT, 1547 .offset = 146, 1548 .width = 1, 1549 }, 1550 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { 1551 .type = VCAP_FIELD_BIT, 1552 .offset = 147, 1553 .width = 1, 1554 }, 1555 [VCAP_KF_ARP_LEN_OK_IS] = { 1556 .type = VCAP_FIELD_BIT, 1557 .offset = 148, 1558 .width = 1, 1559 }, 1560 [VCAP_KF_ARP_TGT_MATCH_IS] = { 1561 .type = VCAP_FIELD_BIT, 1562 .offset = 149, 1563 .width = 1, 1564 }, 1565 [VCAP_KF_ARP_SENDER_MATCH_IS] = { 1566 .type = VCAP_FIELD_BIT, 1567 .offset = 150, 1568 .width = 1, 1569 }, 1570 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { 1571 .type = VCAP_FIELD_BIT, 1572 .offset = 151, 1573 .width = 1, 1574 }, 1575 [VCAP_KF_ARP_OPCODE] = { 1576 .type = VCAP_FIELD_U32, 1577 .offset = 152, 1578 .width = 2, 1579 }, 1580 [VCAP_KF_L3_IP4_DIP] = { 1581 .type = VCAP_FIELD_U32, 1582 .offset = 154, 1583 .width = 32, 1584 }, 1585 [VCAP_KF_L3_IP4_SIP] = { 1586 .type = VCAP_FIELD_U32, 1587 .offset = 186, 1588 .width = 32, 1589 }, 1590 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1591 .type = VCAP_FIELD_BIT, 1592 .offset = 218, 1593 .width = 1, 1594 }, 1595 }; 1596 1597 static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { 1598 [VCAP_KF_TYPE] = { 1599 .type = VCAP_FIELD_U32, 1600 .offset = 0, 1601 .width = 3, 1602 }, 1603 [VCAP_KF_LOOKUP_FIRST_IS] = { 1604 .type = VCAP_FIELD_BIT, 1605 .offset = 3, 1606 .width = 1, 1607 }, 1608 [VCAP_KF_L2_MC_IS] = { 1609 .type = VCAP_FIELD_BIT, 1610 .offset = 13, 1611 .width = 1, 1612 }, 1613 [VCAP_KF_L2_BC_IS] = { 1614 .type = VCAP_FIELD_BIT, 1615 .offset = 14, 1616 .width = 1, 1617 }, 1618 [VCAP_KF_ISDX_GT0_IS] = { 1619 .type = VCAP_FIELD_BIT, 1620 .offset = 15, 1621 .width = 1, 1622 }, 1623 [VCAP_KF_ISDX_CLS] = { 1624 .type = VCAP_FIELD_U32, 1625 .offset = 16, 1626 .width = 12, 1627 }, 1628 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1629 .type = VCAP_FIELD_BIT, 1630 .offset = 28, 1631 .width = 1, 1632 }, 1633 [VCAP_KF_8021Q_VID_CLS] = { 1634 .type = VCAP_FIELD_U32, 1635 .offset = 29, 1636 .width = 13, 1637 }, 1638 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1639 .type = VCAP_FIELD_U32, 1640 .offset = 42, 1641 .width = 3, 1642 }, 1643 [VCAP_KF_IF_EGR_PORT_MASK] = { 1644 .type = VCAP_FIELD_U32, 1645 .offset = 45, 1646 .width = 32, 1647 }, 1648 [VCAP_KF_IF_IGR_PORT_SEL] = { 1649 .type = VCAP_FIELD_BIT, 1650 .offset = 77, 1651 .width = 1, 1652 }, 1653 [VCAP_KF_IF_IGR_PORT] = { 1654 .type = VCAP_FIELD_U32, 1655 .offset = 78, 1656 .width = 9, 1657 }, 1658 [VCAP_KF_8021Q_PCP_CLS] = { 1659 .type = VCAP_FIELD_U32, 1660 .offset = 87, 1661 .width = 3, 1662 }, 1663 [VCAP_KF_8021Q_DEI_CLS] = { 1664 .type = VCAP_FIELD_BIT, 1665 .offset = 90, 1666 .width = 1, 1667 }, 1668 [VCAP_KF_COSID_CLS] = { 1669 .type = VCAP_FIELD_U32, 1670 .offset = 91, 1671 .width = 3, 1672 }, 1673 [VCAP_KF_L3_DPL_CLS] = { 1674 .type = VCAP_FIELD_BIT, 1675 .offset = 94, 1676 .width = 1, 1677 }, 1678 [VCAP_KF_L3_RT_IS] = { 1679 .type = VCAP_FIELD_BIT, 1680 .offset = 95, 1681 .width = 1, 1682 }, 1683 [VCAP_KF_IP4_IS] = { 1684 .type = VCAP_FIELD_BIT, 1685 .offset = 99, 1686 .width = 1, 1687 }, 1688 [VCAP_KF_L3_FRAGMENT_TYPE] = { 1689 .type = VCAP_FIELD_U32, 1690 .offset = 100, 1691 .width = 2, 1692 }, 1693 [VCAP_KF_L3_OPTIONS_IS] = { 1694 .type = VCAP_FIELD_BIT, 1695 .offset = 102, 1696 .width = 1, 1697 }, 1698 [VCAP_KF_L3_TTL_GT0] = { 1699 .type = VCAP_FIELD_BIT, 1700 .offset = 103, 1701 .width = 1, 1702 }, 1703 [VCAP_KF_L3_TOS] = { 1704 .type = VCAP_FIELD_U32, 1705 .offset = 104, 1706 .width = 8, 1707 }, 1708 [VCAP_KF_L3_IP4_DIP] = { 1709 .type = VCAP_FIELD_U32, 1710 .offset = 112, 1711 .width = 32, 1712 }, 1713 [VCAP_KF_L3_IP4_SIP] = { 1714 .type = VCAP_FIELD_U32, 1715 .offset = 144, 1716 .width = 32, 1717 }, 1718 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1719 .type = VCAP_FIELD_BIT, 1720 .offset = 176, 1721 .width = 1, 1722 }, 1723 [VCAP_KF_TCP_IS] = { 1724 .type = VCAP_FIELD_BIT, 1725 .offset = 177, 1726 .width = 1, 1727 }, 1728 [VCAP_KF_L4_DPORT] = { 1729 .type = VCAP_FIELD_U32, 1730 .offset = 178, 1731 .width = 16, 1732 }, 1733 [VCAP_KF_L4_SPORT] = { 1734 .type = VCAP_FIELD_U32, 1735 .offset = 194, 1736 .width = 16, 1737 }, 1738 [VCAP_KF_L4_RNG] = { 1739 .type = VCAP_FIELD_U32, 1740 .offset = 210, 1741 .width = 16, 1742 }, 1743 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 1744 .type = VCAP_FIELD_BIT, 1745 .offset = 226, 1746 .width = 1, 1747 }, 1748 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 1749 .type = VCAP_FIELD_BIT, 1750 .offset = 227, 1751 .width = 1, 1752 }, 1753 [VCAP_KF_L4_FIN] = { 1754 .type = VCAP_FIELD_BIT, 1755 .offset = 228, 1756 .width = 1, 1757 }, 1758 [VCAP_KF_L4_SYN] = { 1759 .type = VCAP_FIELD_BIT, 1760 .offset = 229, 1761 .width = 1, 1762 }, 1763 [VCAP_KF_L4_RST] = { 1764 .type = VCAP_FIELD_BIT, 1765 .offset = 230, 1766 .width = 1, 1767 }, 1768 [VCAP_KF_L4_PSH] = { 1769 .type = VCAP_FIELD_BIT, 1770 .offset = 231, 1771 .width = 1, 1772 }, 1773 [VCAP_KF_L4_ACK] = { 1774 .type = VCAP_FIELD_BIT, 1775 .offset = 232, 1776 .width = 1, 1777 }, 1778 [VCAP_KF_L4_URG] = { 1779 .type = VCAP_FIELD_BIT, 1780 .offset = 233, 1781 .width = 1, 1782 }, 1783 [VCAP_KF_L4_PAYLOAD] = { 1784 .type = VCAP_FIELD_U64, 1785 .offset = 234, 1786 .width = 64, 1787 }, 1788 }; 1789 1790 static const struct vcap_field es2_ip4_other_keyfield[] = { 1791 [VCAP_KF_TYPE] = { 1792 .type = VCAP_FIELD_U32, 1793 .offset = 0, 1794 .width = 3, 1795 }, 1796 [VCAP_KF_LOOKUP_FIRST_IS] = { 1797 .type = VCAP_FIELD_BIT, 1798 .offset = 3, 1799 .width = 1, 1800 }, 1801 [VCAP_KF_L2_MC_IS] = { 1802 .type = VCAP_FIELD_BIT, 1803 .offset = 13, 1804 .width = 1, 1805 }, 1806 [VCAP_KF_L2_BC_IS] = { 1807 .type = VCAP_FIELD_BIT, 1808 .offset = 14, 1809 .width = 1, 1810 }, 1811 [VCAP_KF_ISDX_GT0_IS] = { 1812 .type = VCAP_FIELD_BIT, 1813 .offset = 15, 1814 .width = 1, 1815 }, 1816 [VCAP_KF_ISDX_CLS] = { 1817 .type = VCAP_FIELD_U32, 1818 .offset = 16, 1819 .width = 12, 1820 }, 1821 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1822 .type = VCAP_FIELD_BIT, 1823 .offset = 28, 1824 .width = 1, 1825 }, 1826 [VCAP_KF_8021Q_VID_CLS] = { 1827 .type = VCAP_FIELD_U32, 1828 .offset = 29, 1829 .width = 13, 1830 }, 1831 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1832 .type = VCAP_FIELD_U32, 1833 .offset = 42, 1834 .width = 3, 1835 }, 1836 [VCAP_KF_IF_EGR_PORT_MASK] = { 1837 .type = VCAP_FIELD_U32, 1838 .offset = 45, 1839 .width = 32, 1840 }, 1841 [VCAP_KF_IF_IGR_PORT_SEL] = { 1842 .type = VCAP_FIELD_BIT, 1843 .offset = 77, 1844 .width = 1, 1845 }, 1846 [VCAP_KF_IF_IGR_PORT] = { 1847 .type = VCAP_FIELD_U32, 1848 .offset = 78, 1849 .width = 9, 1850 }, 1851 [VCAP_KF_8021Q_PCP_CLS] = { 1852 .type = VCAP_FIELD_U32, 1853 .offset = 87, 1854 .width = 3, 1855 }, 1856 [VCAP_KF_8021Q_DEI_CLS] = { 1857 .type = VCAP_FIELD_BIT, 1858 .offset = 90, 1859 .width = 1, 1860 }, 1861 [VCAP_KF_COSID_CLS] = { 1862 .type = VCAP_FIELD_U32, 1863 .offset = 91, 1864 .width = 3, 1865 }, 1866 [VCAP_KF_L3_DPL_CLS] = { 1867 .type = VCAP_FIELD_BIT, 1868 .offset = 94, 1869 .width = 1, 1870 }, 1871 [VCAP_KF_L3_RT_IS] = { 1872 .type = VCAP_FIELD_BIT, 1873 .offset = 95, 1874 .width = 1, 1875 }, 1876 [VCAP_KF_IP4_IS] = { 1877 .type = VCAP_FIELD_BIT, 1878 .offset = 99, 1879 .width = 1, 1880 }, 1881 [VCAP_KF_L3_FRAGMENT_TYPE] = { 1882 .type = VCAP_FIELD_U32, 1883 .offset = 100, 1884 .width = 2, 1885 }, 1886 [VCAP_KF_L3_OPTIONS_IS] = { 1887 .type = VCAP_FIELD_BIT, 1888 .offset = 102, 1889 .width = 1, 1890 }, 1891 [VCAP_KF_L3_TTL_GT0] = { 1892 .type = VCAP_FIELD_BIT, 1893 .offset = 103, 1894 .width = 1, 1895 }, 1896 [VCAP_KF_L3_TOS] = { 1897 .type = VCAP_FIELD_U32, 1898 .offset = 104, 1899 .width = 8, 1900 }, 1901 [VCAP_KF_L3_IP4_DIP] = { 1902 .type = VCAP_FIELD_U32, 1903 .offset = 112, 1904 .width = 32, 1905 }, 1906 [VCAP_KF_L3_IP4_SIP] = { 1907 .type = VCAP_FIELD_U32, 1908 .offset = 144, 1909 .width = 32, 1910 }, 1911 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 1912 .type = VCAP_FIELD_BIT, 1913 .offset = 176, 1914 .width = 1, 1915 }, 1916 [VCAP_KF_L3_IP_PROTO] = { 1917 .type = VCAP_FIELD_U32, 1918 .offset = 177, 1919 .width = 8, 1920 }, 1921 [VCAP_KF_L3_PAYLOAD] = { 1922 .type = VCAP_FIELD_U112, 1923 .offset = 185, 1924 .width = 96, 1925 }, 1926 }; 1927 1928 static const struct vcap_field es2_ip_7tuple_keyfield[] = { 1929 [VCAP_KF_LOOKUP_FIRST_IS] = { 1930 .type = VCAP_FIELD_BIT, 1931 .offset = 0, 1932 .width = 1, 1933 }, 1934 [VCAP_KF_L2_MC_IS] = { 1935 .type = VCAP_FIELD_BIT, 1936 .offset = 10, 1937 .width = 1, 1938 }, 1939 [VCAP_KF_L2_BC_IS] = { 1940 .type = VCAP_FIELD_BIT, 1941 .offset = 11, 1942 .width = 1, 1943 }, 1944 [VCAP_KF_ISDX_GT0_IS] = { 1945 .type = VCAP_FIELD_BIT, 1946 .offset = 12, 1947 .width = 1, 1948 }, 1949 [VCAP_KF_ISDX_CLS] = { 1950 .type = VCAP_FIELD_U32, 1951 .offset = 13, 1952 .width = 12, 1953 }, 1954 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 1955 .type = VCAP_FIELD_BIT, 1956 .offset = 25, 1957 .width = 1, 1958 }, 1959 [VCAP_KF_8021Q_VID_CLS] = { 1960 .type = VCAP_FIELD_U32, 1961 .offset = 26, 1962 .width = 13, 1963 }, 1964 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 1965 .type = VCAP_FIELD_U32, 1966 .offset = 39, 1967 .width = 3, 1968 }, 1969 [VCAP_KF_IF_EGR_PORT_MASK] = { 1970 .type = VCAP_FIELD_U32, 1971 .offset = 42, 1972 .width = 32, 1973 }, 1974 [VCAP_KF_IF_IGR_PORT_SEL] = { 1975 .type = VCAP_FIELD_BIT, 1976 .offset = 74, 1977 .width = 1, 1978 }, 1979 [VCAP_KF_IF_IGR_PORT] = { 1980 .type = VCAP_FIELD_U32, 1981 .offset = 75, 1982 .width = 9, 1983 }, 1984 [VCAP_KF_8021Q_PCP_CLS] = { 1985 .type = VCAP_FIELD_U32, 1986 .offset = 84, 1987 .width = 3, 1988 }, 1989 [VCAP_KF_8021Q_DEI_CLS] = { 1990 .type = VCAP_FIELD_BIT, 1991 .offset = 87, 1992 .width = 1, 1993 }, 1994 [VCAP_KF_COSID_CLS] = { 1995 .type = VCAP_FIELD_U32, 1996 .offset = 88, 1997 .width = 3, 1998 }, 1999 [VCAP_KF_L3_DPL_CLS] = { 2000 .type = VCAP_FIELD_BIT, 2001 .offset = 91, 2002 .width = 1, 2003 }, 2004 [VCAP_KF_L3_RT_IS] = { 2005 .type = VCAP_FIELD_BIT, 2006 .offset = 92, 2007 .width = 1, 2008 }, 2009 [VCAP_KF_L2_DMAC] = { 2010 .type = VCAP_FIELD_U48, 2011 .offset = 96, 2012 .width = 48, 2013 }, 2014 [VCAP_KF_L2_SMAC] = { 2015 .type = VCAP_FIELD_U48, 2016 .offset = 144, 2017 .width = 48, 2018 }, 2019 [VCAP_KF_IP4_IS] = { 2020 .type = VCAP_FIELD_BIT, 2021 .offset = 192, 2022 .width = 1, 2023 }, 2024 [VCAP_KF_L3_TTL_GT0] = { 2025 .type = VCAP_FIELD_BIT, 2026 .offset = 193, 2027 .width = 1, 2028 }, 2029 [VCAP_KF_L3_TOS] = { 2030 .type = VCAP_FIELD_U32, 2031 .offset = 194, 2032 .width = 8, 2033 }, 2034 [VCAP_KF_L3_IP6_DIP] = { 2035 .type = VCAP_FIELD_U128, 2036 .offset = 202, 2037 .width = 128, 2038 }, 2039 [VCAP_KF_L3_IP6_SIP] = { 2040 .type = VCAP_FIELD_U128, 2041 .offset = 330, 2042 .width = 128, 2043 }, 2044 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 2045 .type = VCAP_FIELD_BIT, 2046 .offset = 458, 2047 .width = 1, 2048 }, 2049 [VCAP_KF_TCP_UDP_IS] = { 2050 .type = VCAP_FIELD_BIT, 2051 .offset = 459, 2052 .width = 1, 2053 }, 2054 [VCAP_KF_TCP_IS] = { 2055 .type = VCAP_FIELD_BIT, 2056 .offset = 460, 2057 .width = 1, 2058 }, 2059 [VCAP_KF_L4_DPORT] = { 2060 .type = VCAP_FIELD_U32, 2061 .offset = 461, 2062 .width = 16, 2063 }, 2064 [VCAP_KF_L4_SPORT] = { 2065 .type = VCAP_FIELD_U32, 2066 .offset = 477, 2067 .width = 16, 2068 }, 2069 [VCAP_KF_L4_RNG] = { 2070 .type = VCAP_FIELD_U32, 2071 .offset = 493, 2072 .width = 16, 2073 }, 2074 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { 2075 .type = VCAP_FIELD_BIT, 2076 .offset = 509, 2077 .width = 1, 2078 }, 2079 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { 2080 .type = VCAP_FIELD_BIT, 2081 .offset = 510, 2082 .width = 1, 2083 }, 2084 [VCAP_KF_L4_FIN] = { 2085 .type = VCAP_FIELD_BIT, 2086 .offset = 511, 2087 .width = 1, 2088 }, 2089 [VCAP_KF_L4_SYN] = { 2090 .type = VCAP_FIELD_BIT, 2091 .offset = 512, 2092 .width = 1, 2093 }, 2094 [VCAP_KF_L4_RST] = { 2095 .type = VCAP_FIELD_BIT, 2096 .offset = 513, 2097 .width = 1, 2098 }, 2099 [VCAP_KF_L4_PSH] = { 2100 .type = VCAP_FIELD_BIT, 2101 .offset = 514, 2102 .width = 1, 2103 }, 2104 [VCAP_KF_L4_ACK] = { 2105 .type = VCAP_FIELD_BIT, 2106 .offset = 515, 2107 .width = 1, 2108 }, 2109 [VCAP_KF_L4_URG] = { 2110 .type = VCAP_FIELD_BIT, 2111 .offset = 516, 2112 .width = 1, 2113 }, 2114 [VCAP_KF_L4_PAYLOAD] = { 2115 .type = VCAP_FIELD_U64, 2116 .offset = 517, 2117 .width = 64, 2118 }, 2119 }; 2120 2121 static const struct vcap_field es2_ip6_std_keyfield[] = { 2122 [VCAP_KF_TYPE] = { 2123 .type = VCAP_FIELD_U32, 2124 .offset = 0, 2125 .width = 3, 2126 }, 2127 [VCAP_KF_LOOKUP_FIRST_IS] = { 2128 .type = VCAP_FIELD_BIT, 2129 .offset = 3, 2130 .width = 1, 2131 }, 2132 [VCAP_KF_L2_MC_IS] = { 2133 .type = VCAP_FIELD_BIT, 2134 .offset = 13, 2135 .width = 1, 2136 }, 2137 [VCAP_KF_L2_BC_IS] = { 2138 .type = VCAP_FIELD_BIT, 2139 .offset = 14, 2140 .width = 1, 2141 }, 2142 [VCAP_KF_ISDX_GT0_IS] = { 2143 .type = VCAP_FIELD_BIT, 2144 .offset = 15, 2145 .width = 1, 2146 }, 2147 [VCAP_KF_ISDX_CLS] = { 2148 .type = VCAP_FIELD_U32, 2149 .offset = 16, 2150 .width = 12, 2151 }, 2152 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { 2153 .type = VCAP_FIELD_BIT, 2154 .offset = 28, 2155 .width = 1, 2156 }, 2157 [VCAP_KF_8021Q_VID_CLS] = { 2158 .type = VCAP_FIELD_U32, 2159 .offset = 29, 2160 .width = 13, 2161 }, 2162 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { 2163 .type = VCAP_FIELD_U32, 2164 .offset = 42, 2165 .width = 3, 2166 }, 2167 [VCAP_KF_IF_EGR_PORT_MASK] = { 2168 .type = VCAP_FIELD_U32, 2169 .offset = 45, 2170 .width = 32, 2171 }, 2172 [VCAP_KF_IF_IGR_PORT_SEL] = { 2173 .type = VCAP_FIELD_BIT, 2174 .offset = 77, 2175 .width = 1, 2176 }, 2177 [VCAP_KF_IF_IGR_PORT] = { 2178 .type = VCAP_FIELD_U32, 2179 .offset = 78, 2180 .width = 9, 2181 }, 2182 [VCAP_KF_8021Q_PCP_CLS] = { 2183 .type = VCAP_FIELD_U32, 2184 .offset = 87, 2185 .width = 3, 2186 }, 2187 [VCAP_KF_8021Q_DEI_CLS] = { 2188 .type = VCAP_FIELD_BIT, 2189 .offset = 90, 2190 .width = 1, 2191 }, 2192 [VCAP_KF_COSID_CLS] = { 2193 .type = VCAP_FIELD_U32, 2194 .offset = 91, 2195 .width = 3, 2196 }, 2197 [VCAP_KF_L3_DPL_CLS] = { 2198 .type = VCAP_FIELD_BIT, 2199 .offset = 94, 2200 .width = 1, 2201 }, 2202 [VCAP_KF_L3_RT_IS] = { 2203 .type = VCAP_FIELD_BIT, 2204 .offset = 95, 2205 .width = 1, 2206 }, 2207 [VCAP_KF_L3_TTL_GT0] = { 2208 .type = VCAP_FIELD_BIT, 2209 .offset = 99, 2210 .width = 1, 2211 }, 2212 [VCAP_KF_L3_IP6_SIP] = { 2213 .type = VCAP_FIELD_U128, 2214 .offset = 100, 2215 .width = 128, 2216 }, 2217 [VCAP_KF_L3_DIP_EQ_SIP_IS] = { 2218 .type = VCAP_FIELD_BIT, 2219 .offset = 228, 2220 .width = 1, 2221 }, 2222 [VCAP_KF_L3_IP_PROTO] = { 2223 .type = VCAP_FIELD_U32, 2224 .offset = 229, 2225 .width = 8, 2226 }, 2227 [VCAP_KF_L4_RNG] = { 2228 .type = VCAP_FIELD_U32, 2229 .offset = 237, 2230 .width = 16, 2231 }, 2232 [VCAP_KF_L3_PAYLOAD] = { 2233 .type = VCAP_FIELD_U48, 2234 .offset = 253, 2235 .width = 40, 2236 }, 2237 }; 2238 2239 /* keyfield_set */ 2240 static const struct vcap_set is0_keyfield_set[] = { 2241 [VCAP_KFS_NORMAL_7TUPLE] = { 2242 .type_id = 0, 2243 .sw_per_item = 12, 2244 .sw_cnt = 1, 2245 }, 2246 [VCAP_KFS_NORMAL_5TUPLE_IP4] = { 2247 .type_id = 2, 2248 .sw_per_item = 6, 2249 .sw_cnt = 2, 2250 }, 2251 }; 2252 2253 static const struct vcap_set is2_keyfield_set[] = { 2254 [VCAP_KFS_MAC_ETYPE] = { 2255 .type_id = 0, 2256 .sw_per_item = 6, 2257 .sw_cnt = 2, 2258 }, 2259 [VCAP_KFS_ARP] = { 2260 .type_id = 3, 2261 .sw_per_item = 6, 2262 .sw_cnt = 2, 2263 }, 2264 [VCAP_KFS_IP4_TCP_UDP] = { 2265 .type_id = 4, 2266 .sw_per_item = 6, 2267 .sw_cnt = 2, 2268 }, 2269 [VCAP_KFS_IP4_OTHER] = { 2270 .type_id = 5, 2271 .sw_per_item = 6, 2272 .sw_cnt = 2, 2273 }, 2274 [VCAP_KFS_IP6_STD] = { 2275 .type_id = 6, 2276 .sw_per_item = 6, 2277 .sw_cnt = 2, 2278 }, 2279 [VCAP_KFS_IP_7TUPLE] = { 2280 .type_id = 1, 2281 .sw_per_item = 12, 2282 .sw_cnt = 1, 2283 }, 2284 }; 2285 2286 static const struct vcap_set es2_keyfield_set[] = { 2287 [VCAP_KFS_MAC_ETYPE] = { 2288 .type_id = 0, 2289 .sw_per_item = 6, 2290 .sw_cnt = 2, 2291 }, 2292 [VCAP_KFS_ARP] = { 2293 .type_id = 1, 2294 .sw_per_item = 6, 2295 .sw_cnt = 2, 2296 }, 2297 [VCAP_KFS_IP4_TCP_UDP] = { 2298 .type_id = 2, 2299 .sw_per_item = 6, 2300 .sw_cnt = 2, 2301 }, 2302 [VCAP_KFS_IP4_OTHER] = { 2303 .type_id = 3, 2304 .sw_per_item = 6, 2305 .sw_cnt = 2, 2306 }, 2307 [VCAP_KFS_IP_7TUPLE] = { 2308 .type_id = -1, 2309 .sw_per_item = 12, 2310 .sw_cnt = 1, 2311 }, 2312 [VCAP_KFS_IP6_STD] = { 2313 .type_id = 4, 2314 .sw_per_item = 6, 2315 .sw_cnt = 2, 2316 }, 2317 }; 2318 2319 /* keyfield_set map */ 2320 static const struct vcap_field *is0_keyfield_set_map[] = { 2321 [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, 2322 [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, 2323 }; 2324 2325 static const struct vcap_field *is2_keyfield_set_map[] = { 2326 [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, 2327 [VCAP_KFS_ARP] = is2_arp_keyfield, 2328 [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, 2329 [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, 2330 [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, 2331 [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, 2332 }; 2333 2334 static const struct vcap_field *es2_keyfield_set_map[] = { 2335 [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, 2336 [VCAP_KFS_ARP] = es2_arp_keyfield, 2337 [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, 2338 [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, 2339 [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, 2340 [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, 2341 }; 2342 2343 /* keyfield_set map sizes */ 2344 static int is0_keyfield_set_map_size[] = { 2345 [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), 2346 [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), 2347 }; 2348 2349 static int is2_keyfield_set_map_size[] = { 2350 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), 2351 [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), 2352 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), 2353 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), 2354 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), 2355 [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), 2356 }; 2357 2358 static int es2_keyfield_set_map_size[] = { 2359 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), 2360 [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), 2361 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), 2362 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), 2363 [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), 2364 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), 2365 }; 2366 2367 /* actionfields */ 2368 static const struct vcap_field is0_classification_actionfield[] = { 2369 [VCAP_AF_TYPE] = { 2370 .type = VCAP_FIELD_BIT, 2371 .offset = 0, 2372 .width = 1, 2373 }, 2374 [VCAP_AF_DSCP_ENA] = { 2375 .type = VCAP_FIELD_BIT, 2376 .offset = 1, 2377 .width = 1, 2378 }, 2379 [VCAP_AF_DSCP_VAL] = { 2380 .type = VCAP_FIELD_U32, 2381 .offset = 2, 2382 .width = 6, 2383 }, 2384 [VCAP_AF_QOS_ENA] = { 2385 .type = VCAP_FIELD_BIT, 2386 .offset = 12, 2387 .width = 1, 2388 }, 2389 [VCAP_AF_QOS_VAL] = { 2390 .type = VCAP_FIELD_U32, 2391 .offset = 13, 2392 .width = 3, 2393 }, 2394 [VCAP_AF_DP_ENA] = { 2395 .type = VCAP_FIELD_BIT, 2396 .offset = 16, 2397 .width = 1, 2398 }, 2399 [VCAP_AF_DP_VAL] = { 2400 .type = VCAP_FIELD_U32, 2401 .offset = 17, 2402 .width = 2, 2403 }, 2404 [VCAP_AF_DEI_ENA] = { 2405 .type = VCAP_FIELD_BIT, 2406 .offset = 19, 2407 .width = 1, 2408 }, 2409 [VCAP_AF_DEI_VAL] = { 2410 .type = VCAP_FIELD_BIT, 2411 .offset = 20, 2412 .width = 1, 2413 }, 2414 [VCAP_AF_PCP_ENA] = { 2415 .type = VCAP_FIELD_BIT, 2416 .offset = 21, 2417 .width = 1, 2418 }, 2419 [VCAP_AF_PCP_VAL] = { 2420 .type = VCAP_FIELD_U32, 2421 .offset = 22, 2422 .width = 3, 2423 }, 2424 [VCAP_AF_MAP_LOOKUP_SEL] = { 2425 .type = VCAP_FIELD_U32, 2426 .offset = 25, 2427 .width = 2, 2428 }, 2429 [VCAP_AF_MAP_KEY] = { 2430 .type = VCAP_FIELD_U32, 2431 .offset = 27, 2432 .width = 3, 2433 }, 2434 [VCAP_AF_MAP_IDX] = { 2435 .type = VCAP_FIELD_U32, 2436 .offset = 30, 2437 .width = 9, 2438 }, 2439 [VCAP_AF_CLS_VID_SEL] = { 2440 .type = VCAP_FIELD_U32, 2441 .offset = 39, 2442 .width = 3, 2443 }, 2444 [VCAP_AF_VID_VAL] = { 2445 .type = VCAP_FIELD_U32, 2446 .offset = 45, 2447 .width = 13, 2448 }, 2449 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 2450 .type = VCAP_FIELD_BIT, 2451 .offset = 68, 2452 .width = 1, 2453 }, 2454 [VCAP_AF_ISDX_VAL] = { 2455 .type = VCAP_FIELD_U32, 2456 .offset = 69, 2457 .width = 12, 2458 }, 2459 [VCAP_AF_PAG_OVERRIDE_MASK] = { 2460 .type = VCAP_FIELD_U32, 2461 .offset = 109, 2462 .width = 8, 2463 }, 2464 [VCAP_AF_PAG_VAL] = { 2465 .type = VCAP_FIELD_U32, 2466 .offset = 117, 2467 .width = 8, 2468 }, 2469 [VCAP_AF_NXT_IDX_CTRL] = { 2470 .type = VCAP_FIELD_U32, 2471 .offset = 171, 2472 .width = 3, 2473 }, 2474 [VCAP_AF_NXT_IDX] = { 2475 .type = VCAP_FIELD_U32, 2476 .offset = 174, 2477 .width = 12, 2478 }, 2479 }; 2480 2481 static const struct vcap_field is0_full_actionfield[] = { 2482 [VCAP_AF_DSCP_ENA] = { 2483 .type = VCAP_FIELD_BIT, 2484 .offset = 0, 2485 .width = 1, 2486 }, 2487 [VCAP_AF_DSCP_VAL] = { 2488 .type = VCAP_FIELD_U32, 2489 .offset = 1, 2490 .width = 6, 2491 }, 2492 [VCAP_AF_QOS_ENA] = { 2493 .type = VCAP_FIELD_BIT, 2494 .offset = 11, 2495 .width = 1, 2496 }, 2497 [VCAP_AF_QOS_VAL] = { 2498 .type = VCAP_FIELD_U32, 2499 .offset = 12, 2500 .width = 3, 2501 }, 2502 [VCAP_AF_DP_ENA] = { 2503 .type = VCAP_FIELD_BIT, 2504 .offset = 15, 2505 .width = 1, 2506 }, 2507 [VCAP_AF_DP_VAL] = { 2508 .type = VCAP_FIELD_U32, 2509 .offset = 16, 2510 .width = 2, 2511 }, 2512 [VCAP_AF_DEI_ENA] = { 2513 .type = VCAP_FIELD_BIT, 2514 .offset = 18, 2515 .width = 1, 2516 }, 2517 [VCAP_AF_DEI_VAL] = { 2518 .type = VCAP_FIELD_BIT, 2519 .offset = 19, 2520 .width = 1, 2521 }, 2522 [VCAP_AF_PCP_ENA] = { 2523 .type = VCAP_FIELD_BIT, 2524 .offset = 20, 2525 .width = 1, 2526 }, 2527 [VCAP_AF_PCP_VAL] = { 2528 .type = VCAP_FIELD_U32, 2529 .offset = 21, 2530 .width = 3, 2531 }, 2532 [VCAP_AF_MAP_LOOKUP_SEL] = { 2533 .type = VCAP_FIELD_U32, 2534 .offset = 24, 2535 .width = 2, 2536 }, 2537 [VCAP_AF_MAP_KEY] = { 2538 .type = VCAP_FIELD_U32, 2539 .offset = 26, 2540 .width = 3, 2541 }, 2542 [VCAP_AF_MAP_IDX] = { 2543 .type = VCAP_FIELD_U32, 2544 .offset = 29, 2545 .width = 9, 2546 }, 2547 [VCAP_AF_CLS_VID_SEL] = { 2548 .type = VCAP_FIELD_U32, 2549 .offset = 38, 2550 .width = 3, 2551 }, 2552 [VCAP_AF_VID_VAL] = { 2553 .type = VCAP_FIELD_U32, 2554 .offset = 44, 2555 .width = 13, 2556 }, 2557 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 2558 .type = VCAP_FIELD_BIT, 2559 .offset = 67, 2560 .width = 1, 2561 }, 2562 [VCAP_AF_ISDX_VAL] = { 2563 .type = VCAP_FIELD_U32, 2564 .offset = 68, 2565 .width = 12, 2566 }, 2567 [VCAP_AF_MASK_MODE] = { 2568 .type = VCAP_FIELD_U32, 2569 .offset = 80, 2570 .width = 3, 2571 }, 2572 [VCAP_AF_PORT_MASK] = { 2573 .type = VCAP_FIELD_U72, 2574 .offset = 83, 2575 .width = 65, 2576 }, 2577 [VCAP_AF_PAG_OVERRIDE_MASK] = { 2578 .type = VCAP_FIELD_U32, 2579 .offset = 204, 2580 .width = 8, 2581 }, 2582 [VCAP_AF_PAG_VAL] = { 2583 .type = VCAP_FIELD_U32, 2584 .offset = 212, 2585 .width = 8, 2586 }, 2587 [VCAP_AF_NXT_IDX_CTRL] = { 2588 .type = VCAP_FIELD_U32, 2589 .offset = 298, 2590 .width = 3, 2591 }, 2592 [VCAP_AF_NXT_IDX] = { 2593 .type = VCAP_FIELD_U32, 2594 .offset = 301, 2595 .width = 12, 2596 }, 2597 }; 2598 2599 static const struct vcap_field is0_class_reduced_actionfield[] = { 2600 [VCAP_AF_TYPE] = { 2601 .type = VCAP_FIELD_BIT, 2602 .offset = 0, 2603 .width = 1, 2604 }, 2605 [VCAP_AF_QOS_ENA] = { 2606 .type = VCAP_FIELD_BIT, 2607 .offset = 5, 2608 .width = 1, 2609 }, 2610 [VCAP_AF_QOS_VAL] = { 2611 .type = VCAP_FIELD_U32, 2612 .offset = 6, 2613 .width = 3, 2614 }, 2615 [VCAP_AF_DP_ENA] = { 2616 .type = VCAP_FIELD_BIT, 2617 .offset = 9, 2618 .width = 1, 2619 }, 2620 [VCAP_AF_DP_VAL] = { 2621 .type = VCAP_FIELD_U32, 2622 .offset = 10, 2623 .width = 2, 2624 }, 2625 [VCAP_AF_MAP_LOOKUP_SEL] = { 2626 .type = VCAP_FIELD_U32, 2627 .offset = 12, 2628 .width = 2, 2629 }, 2630 [VCAP_AF_MAP_KEY] = { 2631 .type = VCAP_FIELD_U32, 2632 .offset = 14, 2633 .width = 3, 2634 }, 2635 [VCAP_AF_CLS_VID_SEL] = { 2636 .type = VCAP_FIELD_U32, 2637 .offset = 17, 2638 .width = 3, 2639 }, 2640 [VCAP_AF_VID_VAL] = { 2641 .type = VCAP_FIELD_U32, 2642 .offset = 23, 2643 .width = 13, 2644 }, 2645 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { 2646 .type = VCAP_FIELD_BIT, 2647 .offset = 46, 2648 .width = 1, 2649 }, 2650 [VCAP_AF_ISDX_VAL] = { 2651 .type = VCAP_FIELD_U32, 2652 .offset = 47, 2653 .width = 12, 2654 }, 2655 [VCAP_AF_NXT_IDX_CTRL] = { 2656 .type = VCAP_FIELD_U32, 2657 .offset = 90, 2658 .width = 3, 2659 }, 2660 [VCAP_AF_NXT_IDX] = { 2661 .type = VCAP_FIELD_U32, 2662 .offset = 93, 2663 .width = 12, 2664 }, 2665 }; 2666 2667 static const struct vcap_field is2_base_type_actionfield[] = { 2668 [VCAP_AF_PIPELINE_FORCE_ENA] = { 2669 .type = VCAP_FIELD_BIT, 2670 .offset = 1, 2671 .width = 1, 2672 }, 2673 [VCAP_AF_PIPELINE_PT] = { 2674 .type = VCAP_FIELD_U32, 2675 .offset = 2, 2676 .width = 5, 2677 }, 2678 [VCAP_AF_HIT_ME_ONCE] = { 2679 .type = VCAP_FIELD_BIT, 2680 .offset = 7, 2681 .width = 1, 2682 }, 2683 [VCAP_AF_INTR_ENA] = { 2684 .type = VCAP_FIELD_BIT, 2685 .offset = 8, 2686 .width = 1, 2687 }, 2688 [VCAP_AF_CPU_COPY_ENA] = { 2689 .type = VCAP_FIELD_BIT, 2690 .offset = 9, 2691 .width = 1, 2692 }, 2693 [VCAP_AF_CPU_QUEUE_NUM] = { 2694 .type = VCAP_FIELD_U32, 2695 .offset = 10, 2696 .width = 3, 2697 }, 2698 [VCAP_AF_LRN_DIS] = { 2699 .type = VCAP_FIELD_BIT, 2700 .offset = 14, 2701 .width = 1, 2702 }, 2703 [VCAP_AF_RT_DIS] = { 2704 .type = VCAP_FIELD_BIT, 2705 .offset = 15, 2706 .width = 1, 2707 }, 2708 [VCAP_AF_POLICE_ENA] = { 2709 .type = VCAP_FIELD_BIT, 2710 .offset = 16, 2711 .width = 1, 2712 }, 2713 [VCAP_AF_POLICE_IDX] = { 2714 .type = VCAP_FIELD_U32, 2715 .offset = 17, 2716 .width = 6, 2717 }, 2718 [VCAP_AF_IGNORE_PIPELINE_CTRL] = { 2719 .type = VCAP_FIELD_BIT, 2720 .offset = 23, 2721 .width = 1, 2722 }, 2723 [VCAP_AF_MASK_MODE] = { 2724 .type = VCAP_FIELD_U32, 2725 .offset = 27, 2726 .width = 3, 2727 }, 2728 [VCAP_AF_PORT_MASK] = { 2729 .type = VCAP_FIELD_U72, 2730 .offset = 30, 2731 .width = 68, 2732 }, 2733 [VCAP_AF_MIRROR_PROBE] = { 2734 .type = VCAP_FIELD_U32, 2735 .offset = 111, 2736 .width = 2, 2737 }, 2738 [VCAP_AF_MATCH_ID] = { 2739 .type = VCAP_FIELD_U32, 2740 .offset = 159, 2741 .width = 16, 2742 }, 2743 [VCAP_AF_MATCH_ID_MASK] = { 2744 .type = VCAP_FIELD_U32, 2745 .offset = 175, 2746 .width = 16, 2747 }, 2748 [VCAP_AF_CNT_ID] = { 2749 .type = VCAP_FIELD_U32, 2750 .offset = 191, 2751 .width = 12, 2752 }, 2753 }; 2754 2755 static const struct vcap_field es2_base_type_actionfield[] = { 2756 [VCAP_AF_HIT_ME_ONCE] = { 2757 .type = VCAP_FIELD_BIT, 2758 .offset = 0, 2759 .width = 1, 2760 }, 2761 [VCAP_AF_INTR_ENA] = { 2762 .type = VCAP_FIELD_BIT, 2763 .offset = 1, 2764 .width = 1, 2765 }, 2766 [VCAP_AF_FWD_MODE] = { 2767 .type = VCAP_FIELD_U32, 2768 .offset = 2, 2769 .width = 2, 2770 }, 2771 [VCAP_AF_COPY_QUEUE_NUM] = { 2772 .type = VCAP_FIELD_U32, 2773 .offset = 4, 2774 .width = 16, 2775 }, 2776 [VCAP_AF_COPY_PORT_NUM] = { 2777 .type = VCAP_FIELD_U32, 2778 .offset = 20, 2779 .width = 7, 2780 }, 2781 [VCAP_AF_MIRROR_PROBE_ID] = { 2782 .type = VCAP_FIELD_U32, 2783 .offset = 27, 2784 .width = 2, 2785 }, 2786 [VCAP_AF_CPU_COPY_ENA] = { 2787 .type = VCAP_FIELD_BIT, 2788 .offset = 29, 2789 .width = 1, 2790 }, 2791 [VCAP_AF_CPU_QUEUE_NUM] = { 2792 .type = VCAP_FIELD_U32, 2793 .offset = 30, 2794 .width = 3, 2795 }, 2796 [VCAP_AF_POLICE_ENA] = { 2797 .type = VCAP_FIELD_BIT, 2798 .offset = 33, 2799 .width = 1, 2800 }, 2801 [VCAP_AF_POLICE_REMARK] = { 2802 .type = VCAP_FIELD_BIT, 2803 .offset = 34, 2804 .width = 1, 2805 }, 2806 [VCAP_AF_POLICE_IDX] = { 2807 .type = VCAP_FIELD_U32, 2808 .offset = 35, 2809 .width = 6, 2810 }, 2811 [VCAP_AF_ES2_REW_CMD] = { 2812 .type = VCAP_FIELD_U32, 2813 .offset = 41, 2814 .width = 3, 2815 }, 2816 [VCAP_AF_CNT_ID] = { 2817 .type = VCAP_FIELD_U32, 2818 .offset = 44, 2819 .width = 11, 2820 }, 2821 [VCAP_AF_IGNORE_PIPELINE_CTRL] = { 2822 .type = VCAP_FIELD_BIT, 2823 .offset = 55, 2824 .width = 1, 2825 }, 2826 }; 2827 2828 /* actionfield_set */ 2829 static const struct vcap_set is0_actionfield_set[] = { 2830 [VCAP_AFS_CLASSIFICATION] = { 2831 .type_id = 1, 2832 .sw_per_item = 2, 2833 .sw_cnt = 6, 2834 }, 2835 [VCAP_AFS_FULL] = { 2836 .type_id = -1, 2837 .sw_per_item = 3, 2838 .sw_cnt = 4, 2839 }, 2840 [VCAP_AFS_CLASS_REDUCED] = { 2841 .type_id = 1, 2842 .sw_per_item = 1, 2843 .sw_cnt = 12, 2844 }, 2845 }; 2846 2847 static const struct vcap_set is2_actionfield_set[] = { 2848 [VCAP_AFS_BASE_TYPE] = { 2849 .type_id = -1, 2850 .sw_per_item = 3, 2851 .sw_cnt = 4, 2852 }, 2853 }; 2854 2855 static const struct vcap_set es2_actionfield_set[] = { 2856 [VCAP_AFS_BASE_TYPE] = { 2857 .type_id = -1, 2858 .sw_per_item = 3, 2859 .sw_cnt = 4, 2860 }, 2861 }; 2862 2863 /* actionfield_set map */ 2864 static const struct vcap_field *is0_actionfield_set_map[] = { 2865 [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, 2866 [VCAP_AFS_FULL] = is0_full_actionfield, 2867 [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, 2868 }; 2869 2870 static const struct vcap_field *is2_actionfield_set_map[] = { 2871 [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, 2872 }; 2873 2874 static const struct vcap_field *es2_actionfield_set_map[] = { 2875 [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, 2876 }; 2877 2878 /* actionfield_set map size */ 2879 static int is0_actionfield_set_map_size[] = { 2880 [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), 2881 [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), 2882 [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), 2883 }; 2884 2885 static int is2_actionfield_set_map_size[] = { 2886 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), 2887 }; 2888 2889 static int es2_actionfield_set_map_size[] = { 2890 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), 2891 }; 2892 2893 /* Type Groups */ 2894 static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { 2895 { 2896 .offset = 0, 2897 .width = 5, 2898 .value = 16, 2899 }, 2900 { 2901 .offset = 52, 2902 .width = 1, 2903 .value = 0, 2904 }, 2905 { 2906 .offset = 104, 2907 .width = 2, 2908 .value = 0, 2909 }, 2910 { 2911 .offset = 156, 2912 .width = 3, 2913 .value = 0, 2914 }, 2915 { 2916 .offset = 208, 2917 .width = 2, 2918 .value = 0, 2919 }, 2920 { 2921 .offset = 260, 2922 .width = 1, 2923 .value = 0, 2924 }, 2925 { 2926 .offset = 312, 2927 .width = 4, 2928 .value = 0, 2929 }, 2930 { 2931 .offset = 364, 2932 .width = 1, 2933 .value = 0, 2934 }, 2935 { 2936 .offset = 416, 2937 .width = 2, 2938 .value = 0, 2939 }, 2940 { 2941 .offset = 468, 2942 .width = 3, 2943 .value = 0, 2944 }, 2945 { 2946 .offset = 520, 2947 .width = 2, 2948 .value = 0, 2949 }, 2950 { 2951 .offset = 572, 2952 .width = 1, 2953 .value = 0, 2954 }, 2955 {} 2956 }; 2957 2958 static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { 2959 { 2960 .offset = 0, 2961 .width = 4, 2962 .value = 8, 2963 }, 2964 { 2965 .offset = 52, 2966 .width = 1, 2967 .value = 0, 2968 }, 2969 { 2970 .offset = 104, 2971 .width = 2, 2972 .value = 0, 2973 }, 2974 { 2975 .offset = 156, 2976 .width = 3, 2977 .value = 0, 2978 }, 2979 { 2980 .offset = 208, 2981 .width = 2, 2982 .value = 0, 2983 }, 2984 { 2985 .offset = 260, 2986 .width = 1, 2987 .value = 0, 2988 }, 2989 {} 2990 }; 2991 2992 static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { 2993 {} 2994 }; 2995 2996 static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { 2997 {} 2998 }; 2999 3000 static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { 3001 {} 3002 }; 3003 3004 static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { 3005 { 3006 .offset = 0, 3007 .width = 3, 3008 .value = 4, 3009 }, 3010 { 3011 .offset = 156, 3012 .width = 1, 3013 .value = 0, 3014 }, 3015 { 3016 .offset = 312, 3017 .width = 2, 3018 .value = 0, 3019 }, 3020 { 3021 .offset = 468, 3022 .width = 1, 3023 .value = 0, 3024 }, 3025 {} 3026 }; 3027 3028 static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { 3029 { 3030 .offset = 0, 3031 .width = 2, 3032 .value = 2, 3033 }, 3034 { 3035 .offset = 156, 3036 .width = 1, 3037 .value = 0, 3038 }, 3039 {} 3040 }; 3041 3042 static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { 3043 {} 3044 }; 3045 3046 static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { 3047 {} 3048 }; 3049 3050 static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { 3051 { 3052 .offset = 0, 3053 .width = 3, 3054 .value = 4, 3055 }, 3056 { 3057 .offset = 156, 3058 .width = 1, 3059 .value = 0, 3060 }, 3061 { 3062 .offset = 312, 3063 .width = 2, 3064 .value = 0, 3065 }, 3066 { 3067 .offset = 468, 3068 .width = 1, 3069 .value = 0, 3070 }, 3071 {} 3072 }; 3073 3074 static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { 3075 { 3076 .offset = 0, 3077 .width = 2, 3078 .value = 2, 3079 }, 3080 { 3081 .offset = 156, 3082 .width = 1, 3083 .value = 0, 3084 }, 3085 {} 3086 }; 3087 3088 static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { 3089 {} 3090 }; 3091 3092 static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { 3093 {} 3094 }; 3095 3096 static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { 3097 [12] = is0_x12_keyfield_set_typegroups, 3098 [6] = is0_x6_keyfield_set_typegroups, 3099 [3] = is0_x3_keyfield_set_typegroups, 3100 [2] = is0_x2_keyfield_set_typegroups, 3101 [1] = is0_x1_keyfield_set_typegroups, 3102 [13] = NULL, 3103 }; 3104 3105 static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { 3106 [12] = is2_x12_keyfield_set_typegroups, 3107 [6] = is2_x6_keyfield_set_typegroups, 3108 [3] = is2_x3_keyfield_set_typegroups, 3109 [1] = is2_x1_keyfield_set_typegroups, 3110 [13] = NULL, 3111 }; 3112 3113 static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { 3114 [12] = es2_x12_keyfield_set_typegroups, 3115 [6] = es2_x6_keyfield_set_typegroups, 3116 [3] = es2_x3_keyfield_set_typegroups, 3117 [1] = es2_x1_keyfield_set_typegroups, 3118 [13] = NULL, 3119 }; 3120 3121 static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { 3122 { 3123 .offset = 0, 3124 .width = 3, 3125 .value = 4, 3126 }, 3127 { 3128 .offset = 110, 3129 .width = 2, 3130 .value = 0, 3131 }, 3132 { 3133 .offset = 220, 3134 .width = 2, 3135 .value = 0, 3136 }, 3137 {} 3138 }; 3139 3140 static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { 3141 { 3142 .offset = 0, 3143 .width = 2, 3144 .value = 2, 3145 }, 3146 { 3147 .offset = 110, 3148 .width = 1, 3149 .value = 0, 3150 }, 3151 {} 3152 }; 3153 3154 static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { 3155 { 3156 .offset = 0, 3157 .width = 1, 3158 .value = 1, 3159 }, 3160 {} 3161 }; 3162 3163 static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { 3164 { 3165 .offset = 0, 3166 .width = 2, 3167 .value = 2, 3168 }, 3169 { 3170 .offset = 110, 3171 .width = 1, 3172 .value = 0, 3173 }, 3174 { 3175 .offset = 220, 3176 .width = 1, 3177 .value = 0, 3178 }, 3179 {} 3180 }; 3181 3182 static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { 3183 {} 3184 }; 3185 3186 static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { 3187 { 3188 .offset = 0, 3189 .width = 2, 3190 .value = 2, 3191 }, 3192 { 3193 .offset = 21, 3194 .width = 1, 3195 .value = 0, 3196 }, 3197 { 3198 .offset = 42, 3199 .width = 1, 3200 .value = 0, 3201 }, 3202 {} 3203 }; 3204 3205 static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { 3206 {} 3207 }; 3208 3209 static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { 3210 [3] = is0_x3_actionfield_set_typegroups, 3211 [2] = is0_x2_actionfield_set_typegroups, 3212 [1] = is0_x1_actionfield_set_typegroups, 3213 [13] = NULL, 3214 }; 3215 3216 static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { 3217 [3] = is2_x3_actionfield_set_typegroups, 3218 [1] = is2_x1_actionfield_set_typegroups, 3219 [13] = NULL, 3220 }; 3221 3222 static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { 3223 [3] = es2_x3_actionfield_set_typegroups, 3224 [1] = es2_x1_actionfield_set_typegroups, 3225 [13] = NULL, 3226 }; 3227 3228 /* Keyfieldset names */ 3229 static const char * const vcap_keyfield_set_names[] = { 3230 [VCAP_KFS_NO_VALUE] = "(None)", 3231 [VCAP_KFS_ARP] = "VCAP_KFS_ARP", 3232 [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", 3233 [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", 3234 [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", 3235 [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", 3236 [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", 3237 [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", 3238 [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", 3239 [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", 3240 [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", 3241 [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", 3242 [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", 3243 [VCAP_KFS_OAM] = "VCAP_KFS_OAM", 3244 [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", 3245 [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", 3246 }; 3247 3248 /* Actionfieldset names */ 3249 static const char * const vcap_actionfield_set_names[] = { 3250 [VCAP_AFS_NO_VALUE] = "(None)", 3251 [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", 3252 [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", 3253 [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", 3254 [VCAP_AFS_FULL] = "VCAP_AFS_FULL", 3255 [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", 3256 }; 3257 3258 /* Keyfield names */ 3259 static const char * const vcap_keyfield_names[] = { 3260 [VCAP_KF_NO_VALUE] = "(None)", 3261 [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", 3262 [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", 3263 [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", 3264 [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", 3265 [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", 3266 [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", 3267 [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", 3268 [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", 3269 [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", 3270 [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", 3271 [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", 3272 [VCAP_KF_8021Q_VID0] = "8021Q_VID0", 3273 [VCAP_KF_8021Q_VID1] = "8021Q_VID1", 3274 [VCAP_KF_8021Q_VID2] = "8021Q_VID2", 3275 [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", 3276 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", 3277 [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", 3278 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", 3279 [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", 3280 [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", 3281 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", 3282 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", 3283 [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", 3284 [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", 3285 [VCAP_KF_COSID_CLS] = "COSID_CLS", 3286 [VCAP_KF_ETYPE] = "ETYPE", 3287 [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", 3288 [VCAP_KF_HOST_MATCH] = "HOST_MATCH", 3289 [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", 3290 [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", 3291 [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", 3292 [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", 3293 [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", 3294 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", 3295 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", 3296 [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", 3297 [VCAP_KF_IP4_IS] = "IP4_IS", 3298 [VCAP_KF_IP_MC_IS] = "IP_MC_IS", 3299 [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", 3300 [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", 3301 [VCAP_KF_ISDX_CLS] = "ISDX_CLS", 3302 [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", 3303 [VCAP_KF_L2_BC_IS] = "L2_BC_IS", 3304 [VCAP_KF_L2_DMAC] = "L2_DMAC", 3305 [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", 3306 [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", 3307 [VCAP_KF_L2_LLC] = "L2_LLC", 3308 [VCAP_KF_L2_MC_IS] = "L2_MC_IS", 3309 [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", 3310 [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", 3311 [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", 3312 [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", 3313 [VCAP_KF_L2_SMAC] = "L2_SMAC", 3314 [VCAP_KF_L2_SNAP] = "L2_SNAP", 3315 [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", 3316 [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", 3317 [VCAP_KF_L3_DSCP] = "L3_DSCP", 3318 [VCAP_KF_L3_DST_IS] = "L3_DST_IS", 3319 [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", 3320 [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", 3321 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", 3322 [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", 3323 [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", 3324 [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", 3325 [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", 3326 [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", 3327 [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", 3328 [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", 3329 [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", 3330 [VCAP_KF_L3_RT_IS] = "L3_RT_IS", 3331 [VCAP_KF_L3_TOS] = "L3_TOS", 3332 [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", 3333 [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", 3334 [VCAP_KF_L4_1588_VER] = "L4_1588_VER", 3335 [VCAP_KF_L4_ACK] = "L4_ACK", 3336 [VCAP_KF_L4_DPORT] = "L4_DPORT", 3337 [VCAP_KF_L4_FIN] = "L4_FIN", 3338 [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", 3339 [VCAP_KF_L4_PSH] = "L4_PSH", 3340 [VCAP_KF_L4_RNG] = "L4_RNG", 3341 [VCAP_KF_L4_RST] = "L4_RST", 3342 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", 3343 [VCAP_KF_L4_SPORT] = "L4_SPORT", 3344 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", 3345 [VCAP_KF_L4_SYN] = "L4_SYN", 3346 [VCAP_KF_L4_URG] = "L4_URG", 3347 [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", 3348 [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", 3349 [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", 3350 [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", 3351 [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", 3352 [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", 3353 [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", 3354 [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", 3355 [VCAP_KF_OAM_MEPID] = "OAM_MEPID", 3356 [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", 3357 [VCAP_KF_OAM_VER] = "OAM_VER", 3358 [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", 3359 [VCAP_KF_TCP_IS] = "TCP_IS", 3360 [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", 3361 [VCAP_KF_TYPE] = "TYPE", 3362 }; 3363 3364 /* Actionfield names */ 3365 static const char * const vcap_actionfield_names[] = { 3366 [VCAP_AF_NO_VALUE] = "(None)", 3367 [VCAP_AF_ACL_ID] = "ACL_ID", 3368 [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", 3369 [VCAP_AF_CNT_ID] = "CNT_ID", 3370 [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", 3371 [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", 3372 [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", 3373 [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", 3374 [VCAP_AF_DEI_ENA] = "DEI_ENA", 3375 [VCAP_AF_DEI_VAL] = "DEI_VAL", 3376 [VCAP_AF_DP_ENA] = "DP_ENA", 3377 [VCAP_AF_DP_VAL] = "DP_VAL", 3378 [VCAP_AF_DSCP_ENA] = "DSCP_ENA", 3379 [VCAP_AF_DSCP_VAL] = "DSCP_VAL", 3380 [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", 3381 [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", 3382 [VCAP_AF_FWD_MODE] = "FWD_MODE", 3383 [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", 3384 [VCAP_AF_HOST_MATCH] = "HOST_MATCH", 3385 [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", 3386 [VCAP_AF_INTR_ENA] = "INTR_ENA", 3387 [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", 3388 [VCAP_AF_ISDX_ENA] = "ISDX_ENA", 3389 [VCAP_AF_ISDX_VAL] = "ISDX_VAL", 3390 [VCAP_AF_LRN_DIS] = "LRN_DIS", 3391 [VCAP_AF_MAP_IDX] = "MAP_IDX", 3392 [VCAP_AF_MAP_KEY] = "MAP_KEY", 3393 [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", 3394 [VCAP_AF_MASK_MODE] = "MASK_MODE", 3395 [VCAP_AF_MATCH_ID] = "MATCH_ID", 3396 [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", 3397 [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", 3398 [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", 3399 [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", 3400 [VCAP_AF_NXT_IDX] = "NXT_IDX", 3401 [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", 3402 [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", 3403 [VCAP_AF_PAG_VAL] = "PAG_VAL", 3404 [VCAP_AF_PCP_ENA] = "PCP_ENA", 3405 [VCAP_AF_PCP_VAL] = "PCP_VAL", 3406 [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", 3407 [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", 3408 [VCAP_AF_POLICE_ENA] = "POLICE_ENA", 3409 [VCAP_AF_POLICE_IDX] = "POLICE_IDX", 3410 [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", 3411 [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", 3412 [VCAP_AF_PORT_MASK] = "PORT_MASK", 3413 [VCAP_AF_QOS_ENA] = "QOS_ENA", 3414 [VCAP_AF_QOS_VAL] = "QOS_VAL", 3415 [VCAP_AF_REW_OP] = "REW_OP", 3416 [VCAP_AF_RT_DIS] = "RT_DIS", 3417 [VCAP_AF_TYPE] = "TYPE", 3418 [VCAP_AF_VID_VAL] = "VID_VAL", 3419 }; 3420 3421 /* VCAPs */ 3422 const struct vcap_info sparx5_vcaps[] = { 3423 [VCAP_TYPE_IS0] = { 3424 .name = "is0", 3425 .rows = 1024, 3426 .sw_count = 12, 3427 .sw_width = 52, 3428 .sticky_width = 1, 3429 .act_width = 110, 3430 .default_cnt = 140, 3431 .require_cnt_dis = 0, 3432 .version = 1, 3433 .keyfield_set = is0_keyfield_set, 3434 .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), 3435 .actionfield_set = is0_actionfield_set, 3436 .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), 3437 .keyfield_set_map = is0_keyfield_set_map, 3438 .keyfield_set_map_size = is0_keyfield_set_map_size, 3439 .actionfield_set_map = is0_actionfield_set_map, 3440 .actionfield_set_map_size = is0_actionfield_set_map_size, 3441 .keyfield_set_typegroups = is0_keyfield_set_typegroups, 3442 .actionfield_set_typegroups = is0_actionfield_set_typegroups, 3443 }, 3444 [VCAP_TYPE_IS2] = { 3445 .name = "is2", 3446 .rows = 256, 3447 .sw_count = 12, 3448 .sw_width = 52, 3449 .sticky_width = 1, 3450 .act_width = 110, 3451 .default_cnt = 73, 3452 .require_cnt_dis = 0, 3453 .version = 1, 3454 .keyfield_set = is2_keyfield_set, 3455 .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), 3456 .actionfield_set = is2_actionfield_set, 3457 .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), 3458 .keyfield_set_map = is2_keyfield_set_map, 3459 .keyfield_set_map_size = is2_keyfield_set_map_size, 3460 .actionfield_set_map = is2_actionfield_set_map, 3461 .actionfield_set_map_size = is2_actionfield_set_map_size, 3462 .keyfield_set_typegroups = is2_keyfield_set_typegroups, 3463 .actionfield_set_typegroups = is2_actionfield_set_typegroups, 3464 }, 3465 [VCAP_TYPE_ES2] = { 3466 .name = "es2", 3467 .rows = 1024, 3468 .sw_count = 12, 3469 .sw_width = 52, 3470 .sticky_width = 1, 3471 .act_width = 21, 3472 .default_cnt = 74, 3473 .require_cnt_dis = 0, 3474 .version = 1, 3475 .keyfield_set = es2_keyfield_set, 3476 .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), 3477 .actionfield_set = es2_actionfield_set, 3478 .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), 3479 .keyfield_set_map = es2_keyfield_set_map, 3480 .keyfield_set_map_size = es2_keyfield_set_map_size, 3481 .actionfield_set_map = es2_actionfield_set_map, 3482 .actionfield_set_map_size = es2_actionfield_set_map_size, 3483 .keyfield_set_typegroups = es2_keyfield_set_typegroups, 3484 .actionfield_set_typegroups = es2_actionfield_set_typegroups, 3485 }, 3486 }; 3487 3488 const struct vcap_statistics sparx5_vcap_stats = { 3489 .name = "sparx5", 3490 .count = 3, 3491 .keyfield_set_names = vcap_keyfield_set_names, 3492 .actionfield_set_names = vcap_actionfield_set_names, 3493 .keyfield_names = vcap_keyfield_names, 3494 .actionfield_names = vcap_actionfield_names, 3495 }; 3496