1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #include "sparx5_main_regs.h" 8 #include "sparx5_main.h" 9 10 #define SPX5_PSFP_SF_CNT 1024 11 #define SPX5_PSFP_SG_CONFIG_CHANGE_SLEEP 1000 12 #define SPX5_PSFP_SG_CONFIG_CHANGE_TIMEO 100000 13 14 /* Pool of available service policers */ 15 static struct sparx5_pool_entry sparx5_psfp_fm_pool[SPX5_SDLB_CNT]; 16 17 /* Pool of available stream gates */ 18 static struct sparx5_pool_entry sparx5_psfp_sg_pool[SPX5_PSFP_SG_CNT]; 19 20 /* Pool of available stream filters */ 21 static struct sparx5_pool_entry sparx5_psfp_sf_pool[SPX5_PSFP_SF_CNT]; 22 23 static int sparx5_psfp_sf_get(u32 *id) 24 { 25 return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); 26 } 27 28 static int sparx5_psfp_sf_put(u32 id) 29 { 30 return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); 31 } 32 33 static int sparx5_psfp_sg_get(u32 idx, u32 *id) 34 { 35 return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, 36 idx, id); 37 } 38 39 static int sparx5_psfp_sg_put(u32 id) 40 { 41 return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); 42 } 43 44 static int sparx5_psfp_fm_get(u32 idx, u32 *id) 45 { 46 return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, 47 id); 48 } 49 50 static int sparx5_psfp_fm_put(u32 id) 51 { 52 return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); 53 } 54 55 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) 56 { 57 return ANA_L2_TSN_CFG_TSN_SFID_GET(spx5_rd(sparx5, 58 ANA_L2_TSN_CFG(isdx))); 59 } 60 61 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx) 62 { 63 return ANA_L2_DLB_CFG_DLB_IDX_GET(spx5_rd(sparx5, 64 ANA_L2_DLB_CFG(isdx))); 65 } 66 67 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid) 68 { 69 return ANA_AC_TSN_SF_CFG_TSN_SGID_GET(spx5_rd(sparx5, 70 ANA_AC_TSN_SF_CFG(sfid))); 71 } 72 73 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid) 74 { 75 spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID, 76 sparx5, ANA_L2_TSN_CFG(isdx)); 77 78 spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX, 79 sparx5, ANA_L2_DLB_CFG(isdx)); 80 } 81 82 /* Internal priority value to internal priority selector */ 83 static u32 sparx5_psfp_ipv_to_ips(s32 ipv) 84 { 85 return ipv > 0 ? (ipv | BIT(3)) : 0; 86 } 87 88 static int sparx5_psfp_sgid_get_status(struct sparx5 *sparx5) 89 { 90 return spx5_rd(sparx5, ANA_AC_SG_ACCESS_CTRL); 91 } 92 93 static int sparx5_psfp_sgid_wait_for_completion(struct sparx5 *sparx5) 94 { 95 u32 val; 96 97 return readx_poll_timeout(sparx5_psfp_sgid_get_status, sparx5, val, 98 !ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(val), 99 SPX5_PSFP_SG_CONFIG_CHANGE_SLEEP, 100 SPX5_PSFP_SG_CONFIG_CHANGE_TIMEO); 101 } 102 103 static void sparx5_psfp_sg_config_change(struct sparx5 *sparx5, u32 id) 104 { 105 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, 106 ANA_AC_SG_ACCESS_CTRL); 107 108 spx5_wr(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(1) | 109 ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), 110 sparx5, ANA_AC_SG_ACCESS_CTRL); 111 112 if (sparx5_psfp_sgid_wait_for_completion(sparx5) < 0) 113 pr_debug("%s:%d timed out waiting for sgid completion", 114 __func__, __LINE__); 115 } 116 117 static void sparx5_psfp_sf_set(struct sparx5 *sparx5, u32 id, 118 const struct sparx5_psfp_sf *sf) 119 { 120 /* Configure stream gate*/ 121 spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) | 122 ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(sf->max_sdu) | 123 ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(sf->sblock_osize) | 124 ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(sf->sblock_osize_ena), 125 ANA_AC_TSN_SF_CFG_TSN_SGID | ANA_AC_TSN_SF_CFG_TSN_MAX_SDU | 126 ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE | 127 ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, 128 sparx5, ANA_AC_TSN_SF_CFG(id)); 129 } 130 131 static int sparx5_psfp_sg_set(struct sparx5 *sparx5, u32 id, 132 const struct sparx5_psfp_sg *sg) 133 { 134 u32 ips, base_lsb, base_msb, accum_time_interval = 0; 135 const struct sparx5_psfp_gce *gce; 136 int i; 137 138 ips = sparx5_psfp_ipv_to_ips(sg->ipv); 139 base_lsb = sg->basetime.tv_sec & 0xffffffff; 140 base_msb = sg->basetime.tv_sec >> 32; 141 142 /* Set stream gate id */ 143 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, 144 ANA_AC_SG_ACCESS_CTRL); 145 146 /* Write AdminPSFP values */ 147 spx5_wr(sg->basetime.tv_nsec, sparx5, ANA_AC_SG_CONFIG_REG_1); 148 spx5_wr(base_lsb, sparx5, ANA_AC_SG_CONFIG_REG_2); 149 150 spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) | 151 ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(ips) | 152 ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(sg->num_entries) | 153 ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(sg->gate_state) | 154 ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(1), 155 ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB | 156 ANA_AC_SG_CONFIG_REG_3_INIT_IPS | 157 ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH | 158 ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE | 159 ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, 160 sparx5, ANA_AC_SG_CONFIG_REG_3); 161 162 spx5_wr(sg->cycletime, sparx5, ANA_AC_SG_CONFIG_REG_4); 163 spx5_wr(sg->cycletimeext, sparx5, ANA_AC_SG_CONFIG_REG_5); 164 165 /* For each scheduling entry */ 166 for (i = 0; i < sg->num_entries; i++) { 167 gce = &sg->gce[i]; 168 ips = sparx5_psfp_ipv_to_ips(gce->ipv); 169 /* hardware needs TimeInterval to be cumulative */ 170 accum_time_interval += gce->interval; 171 /* Set gate state */ 172 spx5_wr(ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(ips) | 173 ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(gce->gate_state), 174 sparx5, ANA_AC_SG_GCL_GS_CONFIG(i)); 175 176 /* Set time interval */ 177 spx5_wr(accum_time_interval, sparx5, 178 ANA_AC_SG_GCL_TI_CONFIG(i)); 179 180 /* Set maximum octets */ 181 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); 182 } 183 184 return 0; 185 } 186 187 static int sparx5_sdlb_conf_set(struct sparx5 *sparx5, 188 struct sparx5_psfp_fm *fm) 189 { 190 int (*sparx5_sdlb_group_action)(struct sparx5 *sparx5, u32 group, 191 u32 idx); 192 193 if (!fm->pol.rate && !fm->pol.burst) 194 sparx5_sdlb_group_action = &sparx5_sdlb_group_del; 195 else 196 sparx5_sdlb_group_action = &sparx5_sdlb_group_add; 197 198 sparx5_policer_conf_set(sparx5, &fm->pol); 199 200 return sparx5_sdlb_group_action(sparx5, fm->pol.group, fm->pol.idx); 201 } 202 203 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, 204 u32 *id) 205 { 206 int ret; 207 208 ret = sparx5_psfp_sf_get(id); 209 if (ret < 0) 210 return ret; 211 212 sparx5_psfp_sf_set(sparx5, *id, sf); 213 214 return 0; 215 } 216 217 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id) 218 { 219 const struct sparx5_psfp_sf sf = { 0 }; 220 221 sparx5_psfp_sf_set(sparx5, id, &sf); 222 223 return sparx5_psfp_sf_put(id); 224 } 225 226 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, 227 struct sparx5_psfp_sg *sg, u32 *id) 228 { 229 ktime_t basetime; 230 int ret; 231 232 ret = sparx5_psfp_sg_get(uidx, id); 233 if (ret < 0) 234 return ret; 235 /* Was already in use, no need to reconfigure */ 236 if (ret > 1) 237 return 0; 238 239 /* Calculate basetime for this stream gate */ 240 sparx5_new_base_time(sparx5, sg->cycletime, 0, &basetime); 241 sg->basetime = ktime_to_timespec64(basetime); 242 243 sparx5_psfp_sg_set(sparx5, *id, sg); 244 245 /* Signal hardware to copy AdminPSFP values into OperPSFP values */ 246 sparx5_psfp_sg_config_change(sparx5, *id); 247 248 return 0; 249 } 250 251 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id) 252 { 253 const struct sparx5_psfp_sg sg = { 0 }; 254 int ret; 255 256 ret = sparx5_psfp_sg_put(id); 257 if (ret < 0) 258 return ret; 259 /* Stream gate still in use ? */ 260 if (ret > 0) 261 return 0; 262 263 return sparx5_psfp_sg_set(sparx5, id, &sg); 264 } 265 266 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, 267 struct sparx5_psfp_fm *fm, u32 *id) 268 { 269 struct sparx5_policer *pol = &fm->pol; 270 int ret; 271 272 /* Get flow meter */ 273 ret = sparx5_psfp_fm_get(uidx, &fm->pol.idx); 274 if (ret < 0) 275 return ret; 276 /* Was already in use, no need to reconfigure */ 277 if (ret > 1) 278 return 0; 279 280 ret = sparx5_sdlb_group_get_by_rate(sparx5, pol->rate, pol->burst); 281 if (ret < 0) 282 return ret; 283 284 fm->pol.group = ret; 285 286 ret = sparx5_sdlb_conf_set(sparx5, fm); 287 if (ret < 0) 288 return ret; 289 290 *id = fm->pol.idx; 291 292 return 0; 293 } 294 295 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id) 296 { 297 struct sparx5_psfp_fm fm = { .pol.idx = id, 298 .pol.type = SPX5_POL_SERVICE }; 299 int ret; 300 301 /* Find the group that this lb belongs to */ 302 ret = sparx5_sdlb_group_get_by_index(sparx5, id, &fm.pol.group); 303 if (ret < 0) 304 return ret; 305 306 ret = sparx5_psfp_fm_put(id); 307 if (ret < 0) 308 return ret; 309 /* Do not reset flow-meter if still in use. */ 310 if (ret > 0) 311 return 0; 312 313 return sparx5_sdlb_conf_set(sparx5, &fm); 314 } 315 316 void sparx5_psfp_init(struct sparx5 *sparx5) 317 { 318 const struct sparx5_sdlb_group *group; 319 int i; 320 321 for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { 322 group = &sdlb_groups[i]; 323 sparx5_sdlb_group_init(sparx5, group->max_rate, 324 group->min_burst, group->frame_size, i); 325 } 326 327 spx5_wr(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(1), 328 sparx5, ANA_AC_SG_CYCLETIME_UPDATE_PERIOD); 329 330 spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1), 331 ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, sparx5, ANA_L2_FWD_CFG); 332 } 333