1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #include "sparx5_main_regs.h" 8 #include "sparx5_main.h" 9 #include "sparx5_port.h" 10 11 /* The IFH bit position of the first VSTAX bit. This is because the 12 * VSTAX bit positions in Data sheet is starting from zero. 13 */ 14 #define VSTAX 73 15 16 static void ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width) 17 { 18 u8 *ifh_hdr = ifh; 19 /* Calculate the Start IFH byte position of this IFH bit position */ 20 u32 byte = (35 - (pos / 8)); 21 /* Calculate the Start bit position in the Start IFH byte */ 22 u32 bit = (pos % 8); 23 u64 encode = GENMASK(bit + width - 1, bit) & (value << bit); 24 25 /* Max width is 5 bytes - 40 bits. In worst case this will 26 * spread over 6 bytes - 48 bits 27 */ 28 compiletime_assert(width <= 40, "Unsupported width, must be <= 40"); 29 30 /* The b0-b7 goes into the start IFH byte */ 31 if (encode & 0xFF) 32 ifh_hdr[byte] |= (u8)((encode & 0xFF)); 33 /* The b8-b15 goes into the next IFH byte */ 34 if (encode & 0xFF00) 35 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); 36 /* The b16-b23 goes into the next IFH byte */ 37 if (encode & 0xFF0000) 38 ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16); 39 /* The b24-b31 goes into the next IFH byte */ 40 if (encode & 0xFF000000) 41 ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24); 42 /* The b32-b39 goes into the next IFH byte */ 43 if (encode & 0xFF00000000) 44 ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32); 45 /* The b40-b47 goes into the next IFH byte */ 46 if (encode & 0xFF0000000000) 47 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); 48 } 49 50 static void sparx5_set_port_ifh(void *ifh_hdr, u16 portno) 51 { 52 /* VSTAX.RSV = 1. MSBit must be 1 */ 53 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); 54 /* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */ 55 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55, 1); 56 /* MISC.CPU_MASK/DPORT = Destination port */ 57 ifh_encode_bitfield(ifh_hdr, portno, 29, 8); 58 /* MISC.PIPELINE_PT */ 59 ifh_encode_bitfield(ifh_hdr, 16, 37, 5); 60 /* MISC.PIPELINE_ACT */ 61 ifh_encode_bitfield(ifh_hdr, 1, 42, 3); 62 /* FWD.SRC_PORT = CPU */ 63 ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7); 64 /* FWD.SFLOW_ID (disable SFlow sampling) */ 65 ifh_encode_bitfield(ifh_hdr, 124, 57, 7); 66 /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ 67 ifh_encode_bitfield(ifh_hdr, 1, 67, 1); 68 } 69 70 static int sparx5_port_open(struct net_device *ndev) 71 { 72 struct sparx5_port *port = netdev_priv(ndev); 73 int err = 0; 74 75 sparx5_port_enable(port, true); 76 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 77 if (err) { 78 netdev_err(ndev, "Could not attach to PHY\n"); 79 return err; 80 } 81 82 phylink_start(port->phylink); 83 84 if (!ndev->phydev) { 85 /* power up serdes */ 86 port->conf.power_down = false; 87 if (port->conf.serdes_reset) 88 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 89 else 90 err = phy_power_on(port->serdes); 91 if (err) 92 netdev_err(ndev, "%s failed\n", __func__); 93 } 94 95 return err; 96 } 97 98 static int sparx5_port_stop(struct net_device *ndev) 99 { 100 struct sparx5_port *port = netdev_priv(ndev); 101 int err = 0; 102 103 sparx5_port_enable(port, false); 104 phylink_stop(port->phylink); 105 phylink_disconnect_phy(port->phylink); 106 107 if (!ndev->phydev) { 108 /* power down serdes */ 109 port->conf.power_down = true; 110 if (port->conf.serdes_reset) 111 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 112 else 113 err = phy_power_off(port->serdes); 114 if (err) 115 netdev_err(ndev, "%s failed\n", __func__); 116 } 117 return 0; 118 } 119 120 static void sparx5_set_rx_mode(struct net_device *dev) 121 { 122 struct sparx5_port *port = netdev_priv(dev); 123 struct sparx5 *sparx5 = port->sparx5; 124 125 if (!test_bit(port->portno, sparx5->bridge_mask)) 126 __dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync); 127 } 128 129 static int sparx5_port_get_phys_port_name(struct net_device *dev, 130 char *buf, size_t len) 131 { 132 struct sparx5_port *port = netdev_priv(dev); 133 int ret; 134 135 ret = snprintf(buf, len, "p%d", port->portno); 136 if (ret >= len) 137 return -EINVAL; 138 139 return 0; 140 } 141 142 static int sparx5_set_mac_address(struct net_device *dev, void *p) 143 { 144 struct sparx5_port *port = netdev_priv(dev); 145 struct sparx5 *sparx5 = port->sparx5; 146 const struct sockaddr *addr = p; 147 148 if (!is_valid_ether_addr(addr->sa_data)) 149 return -EADDRNOTAVAIL; 150 151 /* Remove current */ 152 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); 153 154 /* Add new */ 155 sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); 156 157 /* Record the address */ 158 ether_addr_copy(dev->dev_addr, addr->sa_data); 159 160 return 0; 161 } 162 163 static int sparx5_get_port_parent_id(struct net_device *dev, 164 struct netdev_phys_item_id *ppid) 165 { 166 struct sparx5_port *sparx5_port = netdev_priv(dev); 167 struct sparx5 *sparx5 = sparx5_port->sparx5; 168 169 ppid->id_len = sizeof(sparx5->base_mac); 170 memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len); 171 172 return 0; 173 } 174 175 static const struct net_device_ops sparx5_port_netdev_ops = { 176 .ndo_open = sparx5_port_open, 177 .ndo_stop = sparx5_port_stop, 178 .ndo_start_xmit = sparx5_port_xmit_impl, 179 .ndo_set_rx_mode = sparx5_set_rx_mode, 180 .ndo_get_phys_port_name = sparx5_port_get_phys_port_name, 181 .ndo_set_mac_address = sparx5_set_mac_address, 182 .ndo_validate_addr = eth_validate_addr, 183 .ndo_get_stats64 = sparx5_get_stats64, 184 .ndo_get_port_parent_id = sparx5_get_port_parent_id, 185 }; 186 187 bool sparx5_netdevice_check(const struct net_device *dev) 188 { 189 return dev && (dev->netdev_ops == &sparx5_port_netdev_ops); 190 } 191 192 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno) 193 { 194 struct sparx5_port *spx5_port; 195 struct net_device *ndev; 196 u64 val; 197 198 ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct sparx5_port)); 199 if (!ndev) 200 return ERR_PTR(-ENOMEM); 201 202 SET_NETDEV_DEV(ndev, sparx5->dev); 203 spx5_port = netdev_priv(ndev); 204 spx5_port->ndev = ndev; 205 spx5_port->sparx5 = sparx5; 206 spx5_port->portno = portno; 207 sparx5_set_port_ifh(spx5_port->ifh, portno); 208 209 ndev->netdev_ops = &sparx5_port_netdev_ops; 210 ndev->ethtool_ops = &sparx5_ethtool_ops; 211 212 val = ether_addr_to_u64(sparx5->base_mac) + portno + 1; 213 u64_to_ether_addr(val, ndev->dev_addr); 214 215 return ndev; 216 } 217 218 int sparx5_register_netdevs(struct sparx5 *sparx5) 219 { 220 int portno; 221 int err; 222 223 for (portno = 0; portno < SPX5_PORTS; portno++) 224 if (sparx5->ports[portno]) { 225 err = register_netdev(sparx5->ports[portno]->ndev); 226 if (err) { 227 dev_err(sparx5->dev, 228 "port: %02u: netdev registration failed\n", 229 portno); 230 return err; 231 } 232 sparx5_port_inj_timer_setup(sparx5->ports[portno]); 233 } 234 return 0; 235 } 236 237 void sparx5_destroy_netdevs(struct sparx5 *sparx5) 238 { 239 struct sparx5_port *port; 240 int portno; 241 242 for (portno = 0; portno < SPX5_PORTS; portno++) { 243 port = sparx5->ports[portno]; 244 if (port && port->phylink) { 245 /* Disconnect the phy */ 246 rtnl_lock(); 247 sparx5_port_stop(port->ndev); 248 phylink_disconnect_phy(port->phylink); 249 rtnl_unlock(); 250 phylink_destroy(port->phylink); 251 port->phylink = NULL; 252 } 253 } 254 } 255 256 void sparx5_unregister_netdevs(struct sparx5 *sparx5) 257 { 258 int portno; 259 260 for (portno = 0; portno < SPX5_PORTS; portno++) 261 if (sparx5->ports[portno]) 262 unregister_netdev(sparx5->ports[portno]->ndev); 263 } 264 265