1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #include "sparx5_main_regs.h" 8 #include "sparx5_main.h" 9 #include "sparx5_port.h" 10 11 /* The IFH bit position of the first VSTAX bit. This is because the 12 * VSTAX bit positions in Data sheet is starting from zero. 13 */ 14 #define VSTAX 73 15 16 #define ifh_encode_bitfield(ifh, value, pos, _width) \ 17 ({ \ 18 u32 width = (_width); \ 19 \ 20 /* Max width is 5 bytes - 40 bits. In worst case this will 21 * spread over 6 bytes - 48 bits 22 */ \ 23 compiletime_assert(width <= 40, \ 24 "Unsupported width, must be <= 40"); \ 25 __ifh_encode_bitfield((ifh), (value), (pos), width); \ 26 }) 27 28 static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width) 29 { 30 u8 *ifh_hdr = ifh; 31 /* Calculate the Start IFH byte position of this IFH bit position */ 32 u32 byte = (35 - (pos / 8)); 33 /* Calculate the Start bit position in the Start IFH byte */ 34 u32 bit = (pos % 8); 35 u64 encode = GENMASK(bit + width - 1, bit) & (value << bit); 36 37 /* The b0-b7 goes into the start IFH byte */ 38 if (encode & 0xFF) 39 ifh_hdr[byte] |= (u8)((encode & 0xFF)); 40 /* The b8-b15 goes into the next IFH byte */ 41 if (encode & 0xFF00) 42 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); 43 /* The b16-b23 goes into the next IFH byte */ 44 if (encode & 0xFF0000) 45 ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16); 46 /* The b24-b31 goes into the next IFH byte */ 47 if (encode & 0xFF000000) 48 ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24); 49 /* The b32-b39 goes into the next IFH byte */ 50 if (encode & 0xFF00000000) 51 ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32); 52 /* The b40-b47 goes into the next IFH byte */ 53 if (encode & 0xFF0000000000) 54 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); 55 } 56 57 static void sparx5_set_port_ifh(void *ifh_hdr, u16 portno) 58 { 59 /* VSTAX.RSV = 1. MSBit must be 1 */ 60 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); 61 /* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */ 62 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55, 1); 63 /* MISC.CPU_MASK/DPORT = Destination port */ 64 ifh_encode_bitfield(ifh_hdr, portno, 29, 8); 65 /* MISC.PIPELINE_PT */ 66 ifh_encode_bitfield(ifh_hdr, 16, 37, 5); 67 /* MISC.PIPELINE_ACT */ 68 ifh_encode_bitfield(ifh_hdr, 1, 42, 3); 69 /* FWD.SRC_PORT = CPU */ 70 ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7); 71 /* FWD.SFLOW_ID (disable SFlow sampling) */ 72 ifh_encode_bitfield(ifh_hdr, 124, 57, 7); 73 /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ 74 ifh_encode_bitfield(ifh_hdr, 1, 67, 1); 75 } 76 77 static int sparx5_port_open(struct net_device *ndev) 78 { 79 struct sparx5_port *port = netdev_priv(ndev); 80 int err = 0; 81 82 sparx5_port_enable(port, true); 83 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 84 if (err) { 85 netdev_err(ndev, "Could not attach to PHY\n"); 86 return err; 87 } 88 89 phylink_start(port->phylink); 90 91 if (!ndev->phydev) { 92 /* power up serdes */ 93 port->conf.power_down = false; 94 if (port->conf.serdes_reset) 95 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 96 else 97 err = phy_power_on(port->serdes); 98 if (err) 99 netdev_err(ndev, "%s failed\n", __func__); 100 } 101 102 return err; 103 } 104 105 static int sparx5_port_stop(struct net_device *ndev) 106 { 107 struct sparx5_port *port = netdev_priv(ndev); 108 int err = 0; 109 110 sparx5_port_enable(port, false); 111 phylink_stop(port->phylink); 112 phylink_disconnect_phy(port->phylink); 113 114 if (!ndev->phydev) { 115 /* power down serdes */ 116 port->conf.power_down = true; 117 if (port->conf.serdes_reset) 118 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 119 else 120 err = phy_power_off(port->serdes); 121 if (err) 122 netdev_err(ndev, "%s failed\n", __func__); 123 } 124 return 0; 125 } 126 127 static void sparx5_set_rx_mode(struct net_device *dev) 128 { 129 struct sparx5_port *port = netdev_priv(dev); 130 struct sparx5 *sparx5 = port->sparx5; 131 132 if (!test_bit(port->portno, sparx5->bridge_mask)) 133 __dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync); 134 } 135 136 static int sparx5_port_get_phys_port_name(struct net_device *dev, 137 char *buf, size_t len) 138 { 139 struct sparx5_port *port = netdev_priv(dev); 140 int ret; 141 142 ret = snprintf(buf, len, "p%d", port->portno); 143 if (ret >= len) 144 return -EINVAL; 145 146 return 0; 147 } 148 149 static int sparx5_set_mac_address(struct net_device *dev, void *p) 150 { 151 struct sparx5_port *port = netdev_priv(dev); 152 struct sparx5 *sparx5 = port->sparx5; 153 const struct sockaddr *addr = p; 154 155 if (!is_valid_ether_addr(addr->sa_data)) 156 return -EADDRNOTAVAIL; 157 158 /* Remove current */ 159 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); 160 161 /* Add new */ 162 sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); 163 164 /* Record the address */ 165 ether_addr_copy(dev->dev_addr, addr->sa_data); 166 167 return 0; 168 } 169 170 static int sparx5_get_port_parent_id(struct net_device *dev, 171 struct netdev_phys_item_id *ppid) 172 { 173 struct sparx5_port *sparx5_port = netdev_priv(dev); 174 struct sparx5 *sparx5 = sparx5_port->sparx5; 175 176 ppid->id_len = sizeof(sparx5->base_mac); 177 memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len); 178 179 return 0; 180 } 181 182 static const struct net_device_ops sparx5_port_netdev_ops = { 183 .ndo_open = sparx5_port_open, 184 .ndo_stop = sparx5_port_stop, 185 .ndo_start_xmit = sparx5_port_xmit_impl, 186 .ndo_set_rx_mode = sparx5_set_rx_mode, 187 .ndo_get_phys_port_name = sparx5_port_get_phys_port_name, 188 .ndo_set_mac_address = sparx5_set_mac_address, 189 .ndo_validate_addr = eth_validate_addr, 190 .ndo_get_stats64 = sparx5_get_stats64, 191 .ndo_get_port_parent_id = sparx5_get_port_parent_id, 192 }; 193 194 bool sparx5_netdevice_check(const struct net_device *dev) 195 { 196 return dev && (dev->netdev_ops == &sparx5_port_netdev_ops); 197 } 198 199 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno) 200 { 201 struct sparx5_port *spx5_port; 202 struct net_device *ndev; 203 u64 val; 204 205 ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct sparx5_port)); 206 if (!ndev) 207 return ERR_PTR(-ENOMEM); 208 209 SET_NETDEV_DEV(ndev, sparx5->dev); 210 spx5_port = netdev_priv(ndev); 211 spx5_port->ndev = ndev; 212 spx5_port->sparx5 = sparx5; 213 spx5_port->portno = portno; 214 sparx5_set_port_ifh(spx5_port->ifh, portno); 215 216 ndev->netdev_ops = &sparx5_port_netdev_ops; 217 ndev->ethtool_ops = &sparx5_ethtool_ops; 218 219 val = ether_addr_to_u64(sparx5->base_mac) + portno + 1; 220 u64_to_ether_addr(val, ndev->dev_addr); 221 222 return ndev; 223 } 224 225 int sparx5_register_netdevs(struct sparx5 *sparx5) 226 { 227 int portno; 228 int err; 229 230 for (portno = 0; portno < SPX5_PORTS; portno++) 231 if (sparx5->ports[portno]) { 232 err = register_netdev(sparx5->ports[portno]->ndev); 233 if (err) { 234 dev_err(sparx5->dev, 235 "port: %02u: netdev registration failed\n", 236 portno); 237 return err; 238 } 239 sparx5_port_inj_timer_setup(sparx5->ports[portno]); 240 } 241 return 0; 242 } 243 244 void sparx5_destroy_netdevs(struct sparx5 *sparx5) 245 { 246 struct sparx5_port *port; 247 int portno; 248 249 for (portno = 0; portno < SPX5_PORTS; portno++) { 250 port = sparx5->ports[portno]; 251 if (port && port->phylink) { 252 /* Disconnect the phy */ 253 rtnl_lock(); 254 sparx5_port_stop(port->ndev); 255 phylink_disconnect_phy(port->phylink); 256 rtnl_unlock(); 257 phylink_destroy(port->phylink); 258 port->phylink = NULL; 259 } 260 } 261 } 262 263 void sparx5_unregister_netdevs(struct sparx5 *sparx5) 264 { 265 int portno; 266 267 for (portno = 0; portno < SPX5_PORTS; portno++) 268 if (sparx5->ports[portno]) 269 unregister_netdev(sparx5->ports[portno]->ndev); 270 } 271 272