1 /* SPDX-License-Identifier: GPL-2.0+
2  * Microchip Sparx5 Switch driver
3  *
4  * Copyright (c) 2021 Microchip Technology Inc.
5  */
6 
7 /* This file is autogenerated by cml-utils 2022-02-26 14:15:01 +0100.
8  * Commit ID: 98bdd3d171cc2a1afd30d241d41a4281d471a48c (dirty)
9  */
10 
11 #ifndef _SPARX5_MAIN_REGS_H_
12 #define _SPARX5_MAIN_REGS_H_
13 
14 #include <linux/bitfield.h>
15 #include <linux/types.h>
16 #include <linux/bug.h>
17 
18 enum sparx5_target {
19 	TARGET_ANA_AC = 1,
20 	TARGET_ANA_ACL = 2,
21 	TARGET_ANA_AC_POL = 4,
22 	TARGET_ANA_CL = 6,
23 	TARGET_ANA_L2 = 7,
24 	TARGET_ANA_L3 = 8,
25 	TARGET_ASM = 9,
26 	TARGET_CLKGEN = 11,
27 	TARGET_CPU = 12,
28 	TARGET_DEV10G = 17,
29 	TARGET_DEV25G = 29,
30 	TARGET_DEV2G5 = 37,
31 	TARGET_DEV5G = 102,
32 	TARGET_DSM = 115,
33 	TARGET_EACL = 116,
34 	TARGET_FDMA = 117,
35 	TARGET_GCB = 118,
36 	TARGET_HSCH = 119,
37 	TARGET_LRN = 122,
38 	TARGET_PCEP = 129,
39 	TARGET_PCS10G_BR = 132,
40 	TARGET_PCS25G_BR = 144,
41 	TARGET_PCS5G_BR = 160,
42 	TARGET_PORT_CONF = 173,
43 	TARGET_PTP = 174,
44 	TARGET_QFWD = 175,
45 	TARGET_QRES = 176,
46 	TARGET_QS = 177,
47 	TARGET_QSYS = 178,
48 	TARGET_REW = 179,
49 	TARGET_VCAP_SUPER = 326,
50 	TARGET_VOP = 327,
51 	TARGET_XQS = 331,
52 	NUM_TARGETS = 332
53 };
54 
55 #define __REG(...)    __VA_ARGS__
56 
57 /*      ANA_AC:RAM_CTRL:RAM_INIT */
58 #define ANA_AC_RAM_INIT           __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
59 
60 #define ANA_AC_RAM_INIT_RAM_INIT                 BIT(1)
61 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
62 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
63 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
64 	FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
65 
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK             BIT(0)
67 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
68 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
69 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
70 	FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
71 
72 /*      ANA_AC:PS_COMMON:OWN_UPSID */
73 #define ANA_AC_OWN_UPSID(r)       __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
74 
75 #define ANA_AC_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
76 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
77 	FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
78 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
79 	FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
80 
81 /*      ANA_AC:SRC:SRC_CFG */
82 #define ANA_AC_SRC_CFG(g)         __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
83 
84 /*      ANA_AC:SRC:SRC_CFG1 */
85 #define ANA_AC_SRC_CFG1(g)        __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
86 
87 /*      ANA_AC:SRC:SRC_CFG2 */
88 #define ANA_AC_SRC_CFG2(g)        __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
89 
90 #define ANA_AC_SRC_CFG2_PORT_MASK2               BIT(0)
91 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
92 	FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
93 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
94 	FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
95 
96 /*      ANA_AC:PGID:PGID_CFG */
97 #define ANA_AC_PGID_CFG(g)        __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
98 
99 /*      ANA_AC:PGID:PGID_CFG1 */
100 #define ANA_AC_PGID_CFG1(g)       __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
101 
102 /*      ANA_AC:PGID:PGID_CFG2 */
103 #define ANA_AC_PGID_CFG2(g)       __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
104 
105 #define ANA_AC_PGID_CFG2_PORT_MASK2              BIT(0)
106 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
107 	FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
108 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
109 	FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
110 
111 /*      ANA_AC:PGID:PGID_MISC_CFG */
112 #define ANA_AC_PGID_MISC_CFG(g)   __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
113 
114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU         GENMASK(6, 4)
115 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
116 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
117 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
118 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
119 
120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA      BIT(1)
121 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
122 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
123 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
124 	FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
125 
126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA   BIT(0)
127 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
128 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
129 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
130 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
131 
132 /*      ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */
133 #define ANA_AC_PORT_SGE_CFG(r)    __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
134 
135 #define ANA_AC_PORT_SGE_CFG_MASK                 GENMASK(15, 0)
136 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
137 	FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
138 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
139 	FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
140 
141 /*      ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
142 #define ANA_AC_STAT_RESET         __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
143 
144 #define ANA_AC_STAT_RESET_RESET                  BIT(0)
145 #define ANA_AC_STAT_RESET_RESET_SET(x)\
146 	FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
147 #define ANA_AC_STAT_RESET_RESET_GET(x)\
148 	FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
149 
150 /*      ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */
151 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
152 
153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK       GENMASK(11, 4)
154 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
155 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
156 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
157 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
158 
159 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE    GENMASK(3, 1)
160 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
161 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
162 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
163 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
164 
165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE        BIT(0)
166 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
167 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
168 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
169 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
170 
171 /*      ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */
172 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
173 
174 /*      ANA_ACL:COMMON:OWN_UPSID */
175 #define ANA_ACL_OWN_UPSID(r)      __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
176 
177 #define ANA_ACL_OWN_UPSID_OWN_UPSID              GENMASK(4, 0)
178 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
179 	FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
180 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
181 	FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
182 
183 /*      ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */
184 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
185 
186 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT   GENMASK(9, 0)
187 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
188 	FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
189 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
190 	FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
191 
192 /*      ANA_AC_POL:COMMON_BDLB:DLB_CTRL */
193 #define ANA_AC_POL_BDLB_DLB_CTRL  __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
194 
195 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
196 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
197 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
198 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
199 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
200 
201 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT   GENMASK(18, 4)
202 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
203 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
204 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
205 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
206 
207 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA        BIT(1)
208 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
209 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
210 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
211 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
212 
213 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA     BIT(0)
214 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
215 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
216 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
217 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
218 
219 /*      ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */
220 #define ANA_AC_POL_SLB_DLB_CTRL   __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
221 
222 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS  GENMASK(26, 19)
223 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
224 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
225 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
226 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
227 
228 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT    GENMASK(18, 4)
229 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
230 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
231 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
232 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
233 
234 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA         BIT(1)
235 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
236 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
237 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
238 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
239 
240 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA      BIT(0)
241 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
242 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
243 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
244 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
245 
246 /*      ANA_CL:PORT:FILTER_CTRL */
247 #define ANA_CL_FILTER_CTRL(g)     __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
248 
249 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS    BIT(2)
250 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
251 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
252 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
253 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
254 
255 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS   BIT(1)
256 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
257 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
258 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
259 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
260 
261 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA  BIT(0)
262 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
263 	FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
264 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
265 	FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
266 
267 /*      ANA_CL:PORT:VLAN_FILTER_CTRL */
268 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
269 
270 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10)
271 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
272 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
273 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
274 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
275 
276 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS    BIT(9)
277 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
278 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
279 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
280 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
281 
282 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS         BIT(8)
283 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
284 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
285 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
286 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
287 
288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS    BIT(7)
289 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
290 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
291 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
292 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
293 
294 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6)
295 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
296 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
297 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
298 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
299 
300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5)
301 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
302 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
303 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
304 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
305 
306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
307 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
308 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
309 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
310 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
311 
312 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS         BIT(3)
313 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
314 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
315 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
316 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
317 
318 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS   BIT(2)
319 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
320 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
321 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
322 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
323 
324 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS   BIT(1)
325 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
326 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
327 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
328 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
329 
330 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS   BIT(0)
331 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
332 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
333 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
334 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
335 
336 /*      ANA_CL:PORT:ETAG_FILTER_CTRL */
337 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
338 
339 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
340 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
341 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
342 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
343 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
344 
345 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS         BIT(0)
346 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
347 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
348 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
349 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
350 
351 /*      ANA_CL:PORT:VLAN_CTRL */
352 #define ANA_CL_VLAN_CTRL(g)       __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
353 
354 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)
355 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
356 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
357 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
358 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
359 
360 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP    GENMASK(25, 23)
361 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
362 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
363 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
364 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
365 
366 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI    BIT(22)
367 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
368 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
369 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
370 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
371 
372 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA  BIT(21)
373 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
374 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
375 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
376 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
377 
378 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL            BIT(20)
379 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
380 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
381 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
382 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
383 
384 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA          BIT(19)
385 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
386 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
387 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
388 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
389 
390 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT            GENMASK(18, 17)
391 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
392 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
393 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
394 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
395 
396 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE           BIT(16)
397 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
398 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
399 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
400 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
401 
402 #define ANA_CL_VLAN_CTRL_PORT_PCP                GENMASK(15, 13)
403 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
404 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
405 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
406 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
407 
408 #define ANA_CL_VLAN_CTRL_PORT_DEI                BIT(12)
409 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
410 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
411 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
412 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
413 
414 #define ANA_CL_VLAN_CTRL_PORT_VID                GENMASK(11, 0)
415 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
416 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
417 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
418 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
419 
420 /*      ANA_CL:PORT:VLAN_CTRL_2 */
421 #define ANA_CL_VLAN_CTRL_2(g)     __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
422 
423 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT         GENMASK(1, 0)
424 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
425 	FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
426 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
427 	FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
428 
429 /*      ANA_CL:PORT:CAPTURE_BPDU_CFG */
430 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
431 
432 /*      ANA_CL:COMMON:OWN_UPSID */
433 #define ANA_CL_OWN_UPSID(r)       __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
434 
435 #define ANA_CL_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
436 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\
437 	FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
438 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\
439 	FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
440 
441 /*      ANA_L2:COMMON:AUTO_LRN_CFG */
442 #define ANA_L2_AUTO_LRN_CFG       __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
443 
444 /*      ANA_L2:COMMON:AUTO_LRN_CFG1 */
445 #define ANA_L2_AUTO_LRN_CFG1      __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
446 
447 /*      ANA_L2:COMMON:AUTO_LRN_CFG2 */
448 #define ANA_L2_AUTO_LRN_CFG2      __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
449 
450 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2       BIT(0)
451 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\
452 	FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
453 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\
454 	FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
455 
456 /*      ANA_L2:COMMON:OWN_UPSID */
457 #define ANA_L2_OWN_UPSID(r)       __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
458 
459 #define ANA_L2_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
460 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\
461 	FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
462 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\
463 	FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
464 
465 /*      ANA_L3:COMMON:VLAN_CTRL */
466 #define ANA_L3_VLAN_CTRL          __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
467 
468 #define ANA_L3_VLAN_CTRL_VLAN_ENA                BIT(0)
469 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\
470 	FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
471 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\
472 	FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
473 
474 /*      ANA_L3:VLAN:VLAN_CFG */
475 #define ANA_L3_VLAN_CFG(g)        __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
476 
477 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR            GENMASK(30, 24)
478 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\
479 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
480 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\
481 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
482 
483 #define ANA_L3_VLAN_CFG_VLAN_FID                 GENMASK(20, 8)
484 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\
485 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
486 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\
487 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
488 
489 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA      BIT(6)
490 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\
491 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
492 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\
493 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
494 
495 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA         BIT(5)
496 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\
497 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
498 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\
499 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
500 
501 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS           BIT(4)
502 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\
503 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
504 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\
505 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
506 
507 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS             BIT(3)
508 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\
509 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
510 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\
511 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
512 
513 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA            BIT(2)
514 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\
515 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
516 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\
517 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
518 
519 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA         BIT(1)
520 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\
521 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
522 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\
523 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
524 
525 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA          BIT(0)
526 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\
527 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
528 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\
529 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
530 
531 /*      ANA_L3:VLAN:VLAN_MASK_CFG */
532 #define ANA_L3_VLAN_MASK_CFG(g)   __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
533 
534 /*      ANA_L3:VLAN:VLAN_MASK_CFG1 */
535 #define ANA_L3_VLAN_MASK_CFG1(g)  __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
536 
537 /*      ANA_L3:VLAN:VLAN_MASK_CFG2 */
538 #define ANA_L3_VLAN_MASK_CFG2(g)  __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
539 
540 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2    BIT(0)
541 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\
542 	FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
543 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\
544 	FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
545 
546 /*      ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */
547 #define ASM_RX_IN_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
548 
549 /*      ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */
550 #define ASM_RX_SYMBOL_ERR_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
551 
552 /*      ASM:DEV_STATISTICS:RX_PAUSE_CNT */
553 #define ASM_RX_PAUSE_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
554 
555 /*      ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */
556 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
557 
558 /*      ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */
559 #define ASM_RX_OK_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
560 
561 /*      ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */
562 #define ASM_RX_BAD_BYTES_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
563 
564 /*      ASM:DEV_STATISTICS:RX_UC_CNT */
565 #define ASM_RX_UC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
566 
567 /*      ASM:DEV_STATISTICS:RX_MC_CNT */
568 #define ASM_RX_MC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
569 
570 /*      ASM:DEV_STATISTICS:RX_BC_CNT */
571 #define ASM_RX_BC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
572 
573 /*      ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */
574 #define ASM_RX_CRC_ERR_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
575 
576 /*      ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */
577 #define ASM_RX_UNDERSIZE_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
578 
579 /*      ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */
580 #define ASM_RX_FRAGMENTS_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
581 
582 /*      ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */
583 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
584 
585 /*      ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */
586 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
587 
588 /*      ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */
589 #define ASM_RX_OVERSIZE_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
590 
591 /*      ASM:DEV_STATISTICS:RX_JABBERS_CNT */
592 #define ASM_RX_JABBERS_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
593 
594 /*      ASM:DEV_STATISTICS:RX_SIZE64_CNT */
595 #define ASM_RX_SIZE64_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
596 
597 /*      ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */
598 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
599 
600 /*      ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */
601 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
602 
603 /*      ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */
604 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
605 
606 /*      ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */
607 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
608 
609 /*      ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */
610 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
611 
612 /*      ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */
613 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
614 
615 /*      ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */
616 #define ASM_RX_IPG_SHRINK_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
617 
618 /*      ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */
619 #define ASM_TX_OUT_BYTES_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
620 
621 /*      ASM:DEV_STATISTICS:TX_PAUSE_CNT */
622 #define ASM_TX_PAUSE_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
623 
624 /*      ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */
625 #define ASM_TX_OK_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
626 
627 /*      ASM:DEV_STATISTICS:TX_UC_CNT */
628 #define ASM_TX_UC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
629 
630 /*      ASM:DEV_STATISTICS:TX_MC_CNT */
631 #define ASM_TX_MC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
632 
633 /*      ASM:DEV_STATISTICS:TX_BC_CNT */
634 #define ASM_TX_BC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
635 
636 /*      ASM:DEV_STATISTICS:TX_SIZE64_CNT */
637 #define ASM_TX_SIZE64_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
638 
639 /*      ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */
640 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
641 
642 /*      ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */
643 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
644 
645 /*      ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */
646 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
647 
648 /*      ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */
649 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
650 
651 /*      ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */
652 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
653 
654 /*      ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */
655 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
656 
657 /*      ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */
658 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
659 
660 /*      ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */
661 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
662 
663 /*      ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */
664 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
665 
666 /*      ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */
667 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
668 
669 /*      ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */
670 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
671 
672 /*      ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */
673 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
674 
675 /*      ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */
676 #define ASM_PMAC_RX_PAUSE_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
677 
678 /*      ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */
679 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
680 
681 /*      ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */
682 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
683 
684 /*      ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */
685 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
686 
687 /*      ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */
688 #define ASM_PMAC_RX_UC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
689 
690 /*      ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */
691 #define ASM_PMAC_RX_MC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
692 
693 /*      ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */
694 #define ASM_PMAC_RX_BC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
695 
696 /*      ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */
697 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
698 
699 /*      ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */
700 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
701 
702 /*      ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */
703 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
704 
705 /*      ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
706 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
707 
708 /*      ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
709 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
710 
711 /*      ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */
712 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
713 
714 /*      ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */
715 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
716 
717 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */
718 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
719 
720 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */
721 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
722 
723 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */
724 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
725 
726 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */
727 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
728 
729 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */
730 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
731 
732 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */
733 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
734 
735 /*      ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */
736 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
737 
738 /*      ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */
739 #define ASM_PMAC_TX_PAUSE_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
740 
741 /*      ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */
742 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
743 
744 /*      ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */
745 #define ASM_PMAC_TX_UC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
746 
747 /*      ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */
748 #define ASM_PMAC_TX_MC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
749 
750 /*      ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */
751 #define ASM_PMAC_TX_BC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
752 
753 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */
754 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
755 
756 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */
757 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
758 
759 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */
760 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
761 
762 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */
763 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
764 
765 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */
766 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
767 
768 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */
769 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
770 
771 /*      ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */
772 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
773 
774 /*      ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */
775 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
776 
777 /*      ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */
778 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
779 
780 /*      ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */
781 #define ASM_MM_RX_SMD_ERR_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
782 
783 /*      ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */
784 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
785 
786 /*      ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */
787 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
788 
789 /*      ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */
790 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
791 
792 /*      ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */
793 #define ASM_TX_MULTI_COLL_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
794 
795 /*      ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */
796 #define ASM_TX_LATE_COLL_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
797 
798 /*      ASM:DEV_STATISTICS:TX_XCOLL_CNT */
799 #define ASM_TX_XCOLL_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
800 
801 /*      ASM:DEV_STATISTICS:TX_DEFER_CNT */
802 #define ASM_TX_DEFER_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
803 
804 /*      ASM:DEV_STATISTICS:TX_XDEFER_CNT */
805 #define ASM_TX_XDEFER_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
806 
807 /*      ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */
808 #define ASM_TX_BACKOFF1_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
809 
810 /*      ASM:DEV_STATISTICS:TX_CSENSE_CNT */
811 #define ASM_TX_CSENSE_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
812 
813 /*      ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */
814 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
815 
816 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0)
817 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
818 	FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
819 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
820 	FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
821 
822 /*      ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */
823 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
824 
825 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
826 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
827 	FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
828 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
829 	FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
830 
831 /*      ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */
832 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
833 
834 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
835 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
836 	FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
837 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
838 	FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
839 
840 /*      ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */
841 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
842 
843 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
844 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
845 	FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
846 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
847 	FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
848 
849 /*      ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */
850 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
851 
852 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
853 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
854 	FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
855 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
856 	FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
857 
858 /*      ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */
859 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
860 
861 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0)
862 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
863 	FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
864 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
865 	FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
866 
867 /*      ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */
868 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
869 
870 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
871 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
872 	FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
873 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
874 	FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
875 
876 /*      ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */
877 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
878 
879 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
880 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
881 	FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
882 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
883 	FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
884 
885 /*      ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */
886 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
887 
888 /*      ASM:CFG:STAT_CFG */
889 #define ASM_STAT_CFG              __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
890 
891 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT           BIT(0)
892 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\
893 	FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
894 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\
895 	FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
896 
897 /*      ASM:CFG:PORT_CFG */
898 #define ASM_PORT_CFG(r)           __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
899 
900 #define ASM_PORT_CFG_CSC_STAT_DIS                BIT(12)
901 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\
902 	FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
903 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\
904 	FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
905 
906 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA      BIT(11)
907 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\
908 	FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
909 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\
910 	FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
911 
912 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA          BIT(10)
913 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\
914 	FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
915 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\
916 	FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
917 
918 #define ASM_PORT_CFG_NO_PREAMBLE_ENA             BIT(9)
919 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\
920 	FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
921 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\
922 	FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
923 
924 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA           BIT(8)
925 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\
926 	FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
927 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\
928 	FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
929 
930 #define ASM_PORT_CFG_FRM_AGING_DIS               BIT(7)
931 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\
932 	FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
933 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\
934 	FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
935 
936 #define ASM_PORT_CFG_PAD_ENA                     BIT(6)
937 #define ASM_PORT_CFG_PAD_ENA_SET(x)\
938 	FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
939 #define ASM_PORT_CFG_PAD_ENA_GET(x)\
940 	FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
941 
942 #define ASM_PORT_CFG_INJ_DISCARD_CFG             GENMASK(5, 4)
943 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\
944 	FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
945 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\
946 	FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
947 
948 #define ASM_PORT_CFG_INJ_FORMAT_CFG              GENMASK(3, 2)
949 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\
950 	FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
951 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\
952 	FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
953 
954 #define ASM_PORT_CFG_VSTAX2_AWR_ENA              BIT(1)
955 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\
956 	FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
957 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\
958 	FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
959 
960 #define ASM_PORT_CFG_PFRM_FLUSH                  BIT(0)
961 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\
962 	FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
963 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\
964 	FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
965 
966 /*      ASM:RAM_CTRL:RAM_INIT */
967 #define ASM_RAM_INIT              __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
968 
969 #define ASM_RAM_INIT_RAM_INIT                    BIT(1)
970 #define ASM_RAM_INIT_RAM_INIT_SET(x)\
971 	FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
972 #define ASM_RAM_INIT_RAM_INIT_GET(x)\
973 	FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
974 
975 #define ASM_RAM_INIT_RAM_CFG_HOOK                BIT(0)
976 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
977 	FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
978 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
979 	FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
980 
981 /*      CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */
982 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
983 
984 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV  GENMASK(7, 0)
985 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\
986 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
987 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\
988 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
989 
990 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV  GENMASK(10, 8)
991 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\
992 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
993 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\
994 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
995 
996 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR  BIT(11)
997 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\
998 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
999 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\
1000 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
1001 
1002 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL  GENMASK(13, 12)
1003 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\
1004 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1005 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\
1006 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1007 
1008 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA  BIT(14)
1009 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\
1010 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1011 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\
1012 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1013 
1014 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA  BIT(15)
1015 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\
1016 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1017 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\
1018 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1019 
1020 /*      CPU:CPU_REGS:PROC_CTRL */
1021 #define CPU_PROC_CTRL             __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
1022 
1023 #define CPU_PROC_CTRL_AARCH64_MODE_ENA           BIT(12)
1024 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\
1025 	FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1026 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\
1027 	FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1028 
1029 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS      BIT(11)
1030 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\
1031 	FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1032 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\
1033 	FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1034 
1035 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS      BIT(10)
1036 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\
1037 	FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1038 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\
1039 	FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1040 
1041 #define CPU_PROC_CTRL_BE_EXCEP_MODE              BIT(9)
1042 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\
1043 	FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1044 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\
1045 	FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1046 
1047 #define CPU_PROC_CTRL_VINITHI                    BIT(8)
1048 #define CPU_PROC_CTRL_VINITHI_SET(x)\
1049 	FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
1050 #define CPU_PROC_CTRL_VINITHI_GET(x)\
1051 	FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
1052 
1053 #define CPU_PROC_CTRL_CFGTE                      BIT(7)
1054 #define CPU_PROC_CTRL_CFGTE_SET(x)\
1055 	FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
1056 #define CPU_PROC_CTRL_CFGTE_GET(x)\
1057 	FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
1058 
1059 #define CPU_PROC_CTRL_CP15S_DISABLE              BIT(6)
1060 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\
1061 	FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
1062 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\
1063 	FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
1064 
1065 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE        BIT(5)
1066 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\
1067 	FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1068 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\
1069 	FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1070 
1071 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA        BIT(4)
1072 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\
1073 	FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1074 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\
1075 	FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1076 
1077 #define CPU_PROC_CTRL_ACP_AWCACHE                BIT(3)
1078 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\
1079 	FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
1080 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\
1081 	FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
1082 
1083 #define CPU_PROC_CTRL_ACP_ARCACHE                BIT(2)
1084 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\
1085 	FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
1086 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\
1087 	FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
1088 
1089 #define CPU_PROC_CTRL_L2_FLUSH_REQ               BIT(1)
1090 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\
1091 	FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1092 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\
1093 	FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1094 
1095 #define CPU_PROC_CTRL_ACP_DISABLE                BIT(0)
1096 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\
1097 	FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
1098 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
1099 	FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
1100 
1101 /*      DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1102 #define DEV10G_MAC_ENA_CFG(t)     __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
1103 
1104 #define DEV10G_MAC_ENA_CFG_RX_ENA                BIT(4)
1105 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\
1106 	FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1107 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\
1108 	FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1109 
1110 #define DEV10G_MAC_ENA_CFG_TX_ENA                BIT(0)
1111 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\
1112 	FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1113 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\
1114 	FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1115 
1116 /*      DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1117 #define DEV10G_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
1118 
1119 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK    BIT(16)
1120 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
1121 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1122 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
1123 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1124 
1125 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
1126 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1127 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1128 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1129 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1130 
1131 /*      DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */
1132 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
1133 
1134 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS         GENMASK(1, 0)
1135 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\
1136 	FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1137 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\
1138 	FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1139 
1140 /*      DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */
1141 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4)
1142 
1143 #define DEV10G_MAC_TAGS_CFG_TAG_ID               GENMASK(31, 16)
1144 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\
1145 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1146 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\
1147 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1148 
1149 #define DEV10G_MAC_TAGS_CFG_TAG_ENA              BIT(4)
1150 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\
1151 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1152 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\
1153 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1154 
1155 /*      DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1156 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
1157 
1158 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA   BIT(24)
1159 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
1160 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1161 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
1162 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1163 
1164 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA   BIT(20)
1165 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
1166 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1167 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
1168 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1169 
1170 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA       BIT(16)
1171 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
1172 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1173 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
1174 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1175 
1176 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS   BIT(12)
1177 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
1178 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1179 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
1180 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1181 
1182 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA       BIT(8)
1183 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
1184 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1185 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
1186 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1187 
1188 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
1189 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
1190 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1191 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
1192 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1193 
1194 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA       BIT(0)
1195 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
1196 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1197 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
1198 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1199 
1200 /*      DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */
1201 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
1202 
1203 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4)
1204 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\
1205 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1206 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\
1207 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1208 
1209 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3)
1210 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\
1211 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1212 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\
1213 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1214 
1215 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2)
1216 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\
1217 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1218 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\
1219 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1220 
1221 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
1222 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\
1223 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1224 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\
1225 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1226 
1227 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0)
1228 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\
1229 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1230 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\
1231 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1232 
1233 /*      DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
1234 #define DEV10G_DEV_RST_CTRL(t)    __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
1235 
1236 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA      BIT(28)
1237 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
1238 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1239 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
1240 	FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1241 
1242 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
1243 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1244 	FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1245 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1246 	FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1247 
1248 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
1249 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
1250 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1251 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
1252 	FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1253 
1254 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL     GENMASK(24, 23)
1255 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
1256 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1257 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
1258 	FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1259 
1260 #define DEV10G_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
1261 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1262 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1263 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1264 	FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1265 
1266 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
1267 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1268 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1269 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1270 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1271 
1272 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
1273 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1274 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1275 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1276 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1277 
1278 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1279 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1280 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1281 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1282 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1283 
1284 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
1285 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1286 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1287 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1288 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1289 
1290 /*      DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
1291 #define DEV10G_PCS25G_CFG(t)      __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
1292 
1293 #define DEV10G_PCS25G_CFG_PCS25G_ENA             BIT(0)
1294 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\
1295 	FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1296 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\
1297 	FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1298 
1299 /*      DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1300 #define DEV25G_MAC_ENA_CFG(t)     __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
1301 
1302 #define DEV25G_MAC_ENA_CFG_RX_ENA                BIT(4)
1303 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\
1304 	FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1305 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\
1306 	FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1307 
1308 #define DEV25G_MAC_ENA_CFG_TX_ENA                BIT(0)
1309 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\
1310 	FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1311 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\
1312 	FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1313 
1314 /*      DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1315 #define DEV25G_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
1316 
1317 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK    BIT(16)
1318 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
1319 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1320 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
1321 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1322 
1323 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
1324 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1325 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1326 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1327 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1328 
1329 /*      DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1330 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
1331 
1332 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA   BIT(24)
1333 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
1334 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1335 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
1336 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1337 
1338 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA   BIT(20)
1339 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
1340 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1341 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
1342 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1343 
1344 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA       BIT(16)
1345 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
1346 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1347 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
1348 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1349 
1350 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS   BIT(12)
1351 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
1352 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1353 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
1354 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1355 
1356 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA       BIT(8)
1357 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
1358 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1359 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
1360 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1361 
1362 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
1363 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
1364 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1365 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
1366 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1367 
1368 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA       BIT(0)
1369 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
1370 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1371 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
1372 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1373 
1374 /*      DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
1375 #define DEV25G_DEV_RST_CTRL(t)    __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
1376 
1377 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA      BIT(28)
1378 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
1379 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1380 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
1381 	FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1382 
1383 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
1384 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1385 	FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1386 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1387 	FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1388 
1389 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
1390 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
1391 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1392 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
1393 	FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1394 
1395 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL     GENMASK(24, 23)
1396 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
1397 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1398 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
1399 	FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1400 
1401 #define DEV25G_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
1402 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1403 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1404 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1405 	FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1406 
1407 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
1408 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1409 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1410 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1411 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1412 
1413 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
1414 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1415 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1416 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1417 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1418 
1419 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1420 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1421 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1422 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1423 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1424 
1425 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
1426 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1427 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1428 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1429 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1430 
1431 /*      DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
1432 #define DEV25G_PCS25G_CFG(t)      __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
1433 
1434 #define DEV25G_PCS25G_CFG_PCS25G_ENA             BIT(0)
1435 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\
1436 	FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1437 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\
1438 	FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1439 
1440 /*      DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */
1441 #define DEV25G_PCS25G_SD_CFG(t)   __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
1442 
1443 #define DEV25G_PCS25G_SD_CFG_SD_SEL              BIT(8)
1444 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\
1445 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1446 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\
1447 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1448 
1449 #define DEV25G_PCS25G_SD_CFG_SD_POL              BIT(4)
1450 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\
1451 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1452 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\
1453 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1454 
1455 #define DEV25G_PCS25G_SD_CFG_SD_ENA              BIT(0)
1456 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\
1457 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1458 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\
1459 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1460 
1461 /*      DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
1462 #define DEV2G5_DEV_RST_CTRL(t)    __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
1463 
1464 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23)
1465 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
1466 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1467 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
1468 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1469 
1470 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
1471 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\
1472 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1473 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\
1474 	FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1475 
1476 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST       BIT(17)
1477 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\
1478 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1479 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\
1480 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1481 
1482 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST       BIT(16)
1483 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\
1484 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1485 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\
1486 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1487 
1488 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
1489 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
1490 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1491 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
1492 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1493 
1494 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
1495 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
1496 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1497 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
1498 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1499 
1500 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1501 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
1502 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1503 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
1504 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1505 
1506 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
1507 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
1508 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1509 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
1510 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1511 
1512 /*      DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
1513 #define DEV2G5_MAC_ENA_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
1514 
1515 #define DEV2G5_MAC_ENA_CFG_RX_ENA                BIT(4)
1516 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\
1517 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1518 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\
1519 	FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1520 
1521 #define DEV2G5_MAC_ENA_CFG_TX_ENA                BIT(0)
1522 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\
1523 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1524 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\
1525 	FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1526 
1527 /*      DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */
1528 #define DEV2G5_MAC_MODE_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
1529 
1530 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA     BIT(8)
1531 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\
1532 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1533 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\
1534 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1535 
1536 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA        BIT(4)
1537 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
1538 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1539 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
1540 	FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1541 
1542 #define DEV2G5_MAC_MODE_CFG_FDX_ENA              BIT(0)
1543 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\
1544 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1545 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\
1546 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1547 
1548 /*      DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1549 #define DEV2G5_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
1550 
1551 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
1552 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
1553 	FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1554 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
1555 	FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1556 
1557 /*      DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */
1558 #define DEV2G5_MAC_TAGS_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
1559 
1560 #define DEV2G5_MAC_TAGS_CFG_TAG_ID               GENMASK(31, 16)
1561 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\
1562 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1563 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\
1564 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1565 
1566 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA     BIT(3)
1567 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
1568 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1569 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
1570 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1571 
1572 #define DEV2G5_MAC_TAGS_CFG_PB_ENA               GENMASK(2, 1)
1573 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\
1574 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1575 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\
1576 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1577 
1578 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA         BIT(0)
1579 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
1580 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1581 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
1582 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1583 
1584 /*      DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */
1585 #define DEV2G5_MAC_TAGS_CFG2(t)   __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
1586 
1587 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3             GENMASK(31, 16)
1588 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\
1589 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1590 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\
1591 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1592 
1593 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2             GENMASK(15, 0)
1594 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\
1595 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1596 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\
1597 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1598 
1599 /*      DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
1600 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
1601 
1602 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA      BIT(0)
1603 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\
1604 	FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1605 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\
1606 	FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1607 
1608 /*      DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
1609 #define DEV2G5_MAC_IFG_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
1610 
1611 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
1612 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\
1613 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1614 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\
1615 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1616 
1617 #define DEV2G5_MAC_IFG_CFG_TX_IFG                GENMASK(12, 8)
1618 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\
1619 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1620 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\
1621 	FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1622 
1623 #define DEV2G5_MAC_IFG_CFG_RX_IFG2               GENMASK(7, 4)
1624 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\
1625 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1626 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\
1627 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1628 
1629 #define DEV2G5_MAC_IFG_CFG_RX_IFG1               GENMASK(3, 0)
1630 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\
1631 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1632 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\
1633 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1634 
1635 /*      DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */
1636 #define DEV2G5_MAC_HDX_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
1637 
1638 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC       BIT(26)
1639 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\
1640 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1641 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\
1642 	FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1643 
1644 #define DEV2G5_MAC_HDX_CFG_SEED                  GENMASK(23, 16)
1645 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\
1646 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
1647 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\
1648 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
1649 
1650 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD             BIT(12)
1651 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\
1652 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1653 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\
1654 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1655 
1656 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
1657 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\
1658 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1659 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\
1660 	FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1661 
1662 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS          GENMASK(6, 0)
1663 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\
1664 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1665 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\
1666 	FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1667 
1668 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */
1669 #define DEV2G5_PCS1G_CFG(t)       __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
1670 
1671 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE        BIT(4)
1672 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\
1673 	FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1674 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\
1675 	FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1676 
1677 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA        BIT(1)
1678 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\
1679 	FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1680 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\
1681 	FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1682 
1683 #define DEV2G5_PCS1G_CFG_PCS_ENA                 BIT(0)
1684 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\
1685 	FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1686 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\
1687 	FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1688 
1689 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
1690 #define DEV2G5_PCS1G_MODE_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
1691 
1692 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA    BIT(4)
1693 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\
1694 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1695 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\
1696 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1697 
1698 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA  BIT(1)
1699 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
1700 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1701 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
1702 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1703 
1704 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA     BIT(0)
1705 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
1706 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1707 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
1708 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1709 
1710 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
1711 #define DEV2G5_PCS1G_SD_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
1712 
1713 #define DEV2G5_PCS1G_SD_CFG_SD_SEL               BIT(8)
1714 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\
1715 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1716 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\
1717 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1718 
1719 #define DEV2G5_PCS1G_SD_CFG_SD_POL               BIT(4)
1720 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\
1721 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1722 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\
1723 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1724 
1725 #define DEV2G5_PCS1G_SD_CFG_SD_ENA               BIT(0)
1726 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\
1727 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1728 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\
1729 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1730 
1731 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
1732 #define DEV2G5_PCS1G_ANEG_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
1733 
1734 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY        GENMASK(31, 16)
1735 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
1736 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1737 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
1738 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1739 
1740 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA     BIT(8)
1741 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
1742 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1743 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
1744 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1745 
1746 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
1747 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\
1748 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1749 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\
1750 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1751 
1752 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA           BIT(0)
1753 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\
1754 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1755 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\
1756 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1757 
1758 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */
1759 #define DEV2G5_PCS1G_LB_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
1760 
1761 #define DEV2G5_PCS1G_LB_CFG_RA_ENA               BIT(4)
1762 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\
1763 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1764 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\
1765 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1766 
1767 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA      BIT(1)
1768 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\
1769 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1770 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\
1771 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1772 
1773 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA      BIT(0)
1774 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\
1775 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1776 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\
1777 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1778 
1779 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
1780 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
1781 
1782 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY  GENMASK(31, 16)
1783 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\
1784 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1785 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\
1786 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1787 
1788 #define DEV2G5_PCS1G_ANEG_STATUS_PR              BIT(4)
1789 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\
1790 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1791 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\
1792 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1793 
1794 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY  BIT(3)
1795 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\
1796 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1797 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\
1798 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1799 
1800 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE   BIT(0)
1801 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
1802 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1803 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
1804 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1805 
1806 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
1807 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
1808 
1809 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR       GENMASK(15, 12)
1810 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\
1811 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1812 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\
1813 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1814 
1815 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT   BIT(8)
1816 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\
1817 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1818 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\
1819 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1820 
1821 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS     BIT(4)
1822 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
1823 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1824 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
1825 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1826 
1827 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS     BIT(0)
1828 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
1829 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1830 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
1831 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1832 
1833 /*      DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */
1834 #define DEV2G5_PCS1G_STICKY(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
1835 
1836 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY     BIT(4)
1837 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
1838 	FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1839 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
1840 	FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1841 
1842 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY   BIT(0)
1843 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\
1844 	FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1845 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\
1846 	FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1847 
1848 /*      DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */
1849 #define DEV2G5_PCS_FX100_CFG(t)   __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
1850 
1851 #define DEV2G5_PCS_FX100_CFG_SD_SEL              BIT(26)
1852 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\
1853 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1854 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\
1855 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1856 
1857 #define DEV2G5_PCS_FX100_CFG_SD_POL              BIT(25)
1858 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\
1859 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1860 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\
1861 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1862 
1863 #define DEV2G5_PCS_FX100_CFG_SD_ENA              BIT(24)
1864 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\
1865 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1866 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\
1867 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1868 
1869 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA        BIT(20)
1870 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\
1871 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1872 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\
1873 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1874 
1875 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA        BIT(16)
1876 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\
1877 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1878 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\
1879 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1880 
1881 #define DEV2G5_PCS_FX100_CFG_RXBITSEL            GENMASK(15, 12)
1882 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\
1883 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1884 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\
1885 	FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1886 
1887 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG          GENMASK(10, 9)
1888 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\
1889 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1890 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\
1891 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1892 
1893 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA     BIT(8)
1894 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\
1895 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1896 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\
1897 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1898 
1899 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER       GENMASK(7, 4)
1900 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\
1901 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1902 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\
1903 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1904 
1905 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA     BIT(3)
1906 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\
1907 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1908 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\
1909 	FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1910 
1911 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA          BIT(2)
1912 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\
1913 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1914 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\
1915 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1916 
1917 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA          BIT(1)
1918 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\
1919 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1920 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\
1921 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1922 
1923 #define DEV2G5_PCS_FX100_CFG_PCS_ENA             BIT(0)
1924 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\
1925 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1926 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\
1927 	FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1928 
1929 /*      DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */
1930 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
1931 
1932 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP     GENMASK(11, 8)
1933 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\
1934 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1935 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\
1936 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1937 
1938 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
1939 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\
1940 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1941 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\
1942 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1943 
1944 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
1945 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\
1946 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1947 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\
1948 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1949 
1950 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
1951 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\
1952 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1953 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\
1954 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1955 
1956 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
1957 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\
1958 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1959 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\
1960 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1961 
1962 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS       BIT(2)
1963 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\
1964 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1965 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\
1966 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1967 
1968 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT    BIT(1)
1969 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\
1970 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1971 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\
1972 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1973 
1974 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS      BIT(0)
1975 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\
1976 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1977 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\
1978 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1979 
1980 /*      DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
1981 #define DEV5G_MAC_ENA_CFG(t)      __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
1982 
1983 #define DEV5G_MAC_ENA_CFG_RX_ENA                 BIT(4)
1984 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\
1985 	FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1986 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\
1987 	FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1988 
1989 #define DEV5G_MAC_ENA_CFG_TX_ENA                 BIT(0)
1990 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\
1991 	FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1992 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\
1993 	FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1994 
1995 /*      DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
1996 #define DEV5G_MAC_MAXLEN_CFG(t)   __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
1997 
1998 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK     BIT(16)
1999 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2000 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2001 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2002 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2003 
2004 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN             GENMASK(15, 0)
2005 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2006 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2007 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2008 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2009 
2010 /*      DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2011 #define DEV5G_MAC_ADV_CHK_CFG(t)  __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
2012 
2013 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA    BIT(24)
2014 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2015 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2016 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2017 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2018 
2019 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA    BIT(20)
2020 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2021 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2022 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2023 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2024 
2025 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA        BIT(16)
2026 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2027 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2028 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2029 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2030 
2031 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS    BIT(12)
2032 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2033 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2034 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2035 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2036 
2037 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA        BIT(8)
2038 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2039 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2040 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2041 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2042 
2043 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA        BIT(4)
2044 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2045 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2046 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2047 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2048 
2049 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA        BIT(0)
2050 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2051 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2052 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2053 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2054 
2055 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */
2056 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
2057 
2058 /*      DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */
2059 #define DEV5G_RX_PAUSE_CNT(t)     __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
2060 
2061 /*      DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */
2062 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
2063 
2064 /*      DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */
2065 #define DEV5G_RX_UC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
2066 
2067 /*      DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */
2068 #define DEV5G_RX_MC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
2069 
2070 /*      DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */
2071 #define DEV5G_RX_BC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
2072 
2073 /*      DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */
2074 #define DEV5G_RX_CRC_ERR_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
2075 
2076 /*      DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */
2077 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
2078 
2079 /*      DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */
2080 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
2081 
2082 /*      DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */
2083 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
2084 
2085 /*      DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */
2086 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
2087 
2088 /*      DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */
2089 #define DEV5G_RX_OVERSIZE_CNT(t)  __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
2090 
2091 /*      DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */
2092 #define DEV5G_RX_JABBERS_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
2093 
2094 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */
2095 #define DEV5G_RX_SIZE64_CNT(t)    __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
2096 
2097 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */
2098 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
2099 
2100 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */
2101 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
2102 
2103 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */
2104 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
2105 
2106 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */
2107 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
2108 
2109 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */
2110 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
2111 
2112 /*      DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */
2113 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
2114 
2115 /*      DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */
2116 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
2117 
2118 /*      DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */
2119 #define DEV5G_TX_PAUSE_CNT(t)     __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
2120 
2121 /*      DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */
2122 #define DEV5G_TX_UC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
2123 
2124 /*      DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */
2125 #define DEV5G_TX_MC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
2126 
2127 /*      DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */
2128 #define DEV5G_TX_BC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
2129 
2130 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */
2131 #define DEV5G_TX_SIZE64_CNT(t)    __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
2132 
2133 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */
2134 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
2135 
2136 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */
2137 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
2138 
2139 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */
2140 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
2141 
2142 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */
2143 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
2144 
2145 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */
2146 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
2147 
2148 /*      DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */
2149 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
2150 
2151 /*      DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */
2152 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
2153 
2154 /*      DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */
2155 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
2156 
2157 /*      DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */
2158 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
2159 
2160 /*      DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */
2161 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
2162 
2163 /*      DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */
2164 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
2165 
2166 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */
2167 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
2168 
2169 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */
2170 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
2171 
2172 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */
2173 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
2174 
2175 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */
2176 #define DEV5G_PMAC_RX_UC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
2177 
2178 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */
2179 #define DEV5G_PMAC_RX_MC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
2180 
2181 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */
2182 #define DEV5G_PMAC_RX_BC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
2183 
2184 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */
2185 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
2186 
2187 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */
2188 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
2189 
2190 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */
2191 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
2192 
2193 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
2194 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2195 					t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
2196 
2197 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
2198 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
2199 					t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
2200 
2201 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */
2202 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
2203 
2204 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */
2205 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
2206 
2207 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */
2208 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
2209 
2210 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */
2211 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
2212 
2213 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */
2214 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
2215 
2216 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */
2217 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
2218 
2219 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */
2220 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
2221 
2222 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */
2223 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
2224 
2225 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */
2226 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
2227 
2228 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */
2229 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
2230 
2231 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */
2232 #define DEV5G_PMAC_TX_UC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
2233 
2234 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */
2235 #define DEV5G_PMAC_TX_MC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
2236 
2237 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */
2238 #define DEV5G_PMAC_TX_BC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
2239 
2240 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */
2241 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
2242 
2243 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */
2244 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
2245 
2246 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */
2247 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
2248 
2249 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */
2250 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
2251 
2252 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */
2253 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
2254 
2255 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */
2256 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
2257 
2258 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */
2259 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
2260 
2261 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */
2262 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
2263 
2264 /*      DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */
2265 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
2266 
2267 /*      DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */
2268 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
2269 
2270 /*      DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */
2271 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
2272 
2273 /*      DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */
2274 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
2275 
2276 /*      DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */
2277 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
2278 
2279 /*      DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */
2280 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
2281 
2282 /*      DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */
2283 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
2284 
2285 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */
2286 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
2287 
2288 /*      DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */
2289 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
2290 
2291 /*      DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */
2292 #define DEV5G_RX_IN_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
2293 
2294 /*      DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */
2295 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
2296 
2297 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0)
2298 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
2299 	FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2300 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
2301 	FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2302 
2303 /*      DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */
2304 #define DEV5G_RX_OK_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
2305 
2306 /*      DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */
2307 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
2308 
2309 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2310 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
2311 	FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2312 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
2313 	FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2314 
2315 /*      DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */
2316 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
2317 
2318 /*      DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */
2319 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
2320 
2321 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
2322 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
2323 	FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2324 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
2325 	FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2326 
2327 /*      DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */
2328 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
2329 
2330 /*      DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */
2331 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
2332 
2333 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0)
2334 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
2335 	FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2336 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
2337 	FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2338 
2339 /*      DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */
2340 #define DEV5G_TX_OK_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
2341 
2342 /*      DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */
2343 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
2344 
2345 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2346 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
2347 	FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2348 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
2349 	FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2350 
2351 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */
2352 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
2353 
2354 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */
2355 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
2356 
2357 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2358 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
2359 	FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2360 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
2361 	FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2362 
2363 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */
2364 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
2365 
2366 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */
2367 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
2368 
2369 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
2370 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
2371 	FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2372 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
2373 	FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2374 
2375 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */
2376 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
2377 
2378 /*      DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */
2379 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
2380 
2381 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
2382 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
2383 	FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2384 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
2385 	FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2386 
2387 /*      DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
2388 #define DEV5G_DEV_RST_CTRL(t)     __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
2389 
2390 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA       BIT(28)
2391 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2392 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2393 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2394 	FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2395 
2396 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
2397 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2398 	FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2399 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2400 	FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2401 
2402 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
2403 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2404 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2405 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2406 	FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2407 
2408 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL      GENMASK(24, 23)
2409 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2410 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2411 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2412 	FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2413 
2414 #define DEV5G_DEV_RST_CTRL_SPEED_SEL             GENMASK(22, 20)
2415 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2416 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2417 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2418 	FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2419 
2420 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST            BIT(12)
2421 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2422 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2423 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2424 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2425 
2426 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST            BIT(8)
2427 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2428 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2429 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2430 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2431 
2432 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST            BIT(4)
2433 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2434 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2435 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2436 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2437 
2438 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST            BIT(0)
2439 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2440 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2441 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2442 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2443 
2444 /*      DSM:RAM_CTRL:RAM_INIT */
2445 #define DSM_RAM_INIT              __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
2446 
2447 #define DSM_RAM_INIT_RAM_INIT                    BIT(1)
2448 #define DSM_RAM_INIT_RAM_INIT_SET(x)\
2449 	FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
2450 #define DSM_RAM_INIT_RAM_INIT_GET(x)\
2451 	FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
2452 
2453 #define DSM_RAM_INIT_RAM_CFG_HOOK                BIT(0)
2454 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2455 	FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2456 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2457 	FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2458 
2459 /*      DSM:CFG:BUF_CFG */
2460 #define DSM_BUF_CFG(r)            __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
2461 
2462 #define DSM_BUF_CFG_CSC_STAT_DIS                 BIT(13)
2463 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\
2464 	FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
2465 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\
2466 	FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
2467 
2468 #define DSM_BUF_CFG_AGING_ENA                    BIT(12)
2469 #define DSM_BUF_CFG_AGING_ENA_SET(x)\
2470 	FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
2471 #define DSM_BUF_CFG_AGING_ENA_GET(x)\
2472 	FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
2473 
2474 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS       BIT(11)
2475 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\
2476 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2477 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\
2478 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2479 
2480 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT   GENMASK(10, 0)
2481 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\
2482 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2483 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\
2484 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2485 
2486 /*      DSM:CFG:DEV_TX_STOP_WM_CFG */
2487 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
2488 
2489 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA  BIT(9)
2490 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\
2491 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2492 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\
2493 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2494 
2495 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)
2496 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\
2497 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2498 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\
2499 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2500 
2501 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM    GENMASK(7, 1)
2502 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\
2503 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2504 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\
2505 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2506 
2507 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR    BIT(0)
2508 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\
2509 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2510 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\
2511 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2512 
2513 /*      DSM:CFG:RX_PAUSE_CFG */
2514 #define DSM_RX_PAUSE_CFG(r)       __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
2515 
2516 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN             BIT(1)
2517 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\
2518 	FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2519 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\
2520 	FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2521 
2522 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL           BIT(0)
2523 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\
2524 	FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2525 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\
2526 	FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2527 
2528 /*      DSM:CFG:MAC_CFG */
2529 #define DSM_MAC_CFG(r)            __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
2530 
2531 #define DSM_MAC_CFG_TX_PAUSE_VAL                 GENMASK(31, 16)
2532 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\
2533 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2534 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\
2535 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2536 
2537 #define DSM_MAC_CFG_HDX_BACKPREASSURE            BIT(2)
2538 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\
2539 	FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2540 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\
2541 	FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2542 
2543 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE         BIT(1)
2544 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\
2545 	FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2546 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\
2547 	FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2548 
2549 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF            BIT(0)
2550 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\
2551 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2552 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\
2553 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2554 
2555 /*      DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */
2556 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
2557 
2558 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0)
2559 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\
2560 	FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2561 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\
2562 	FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2563 
2564 /*      DSM:CFG:MAC_ADDR_BASE_LOW_CFG */
2565 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
2566 
2567 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW   GENMASK(23, 0)
2568 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\
2569 	FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2570 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\
2571 	FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2572 
2573 /*      DSM:CFG:TAXI_CAL_CFG */
2574 #define DSM_TAXI_CAL_CFG(r)       __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
2575 
2576 #define DSM_TAXI_CAL_CFG_CAL_IDX                 GENMASK(20, 15)
2577 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
2578 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2579 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
2580 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2581 
2582 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN             GENMASK(14, 9)
2583 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
2584 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2585 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
2586 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2587 
2588 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL             GENMASK(8, 5)
2589 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
2590 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2591 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
2592 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2593 
2594 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL             GENMASK(4, 1)
2595 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
2596 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2597 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
2598 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2599 
2600 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA             BIT(0)
2601 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
2602 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2603 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
2604 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2605 
2606 /*      EACL:POL_CFG:POL_EACL_CFG */
2607 #define EACL_POL_EACL_CFG         __REG(TARGET_EACL, 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
2608 
2609 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5)
2610 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\
2611 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2612 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\
2613 	FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2614 
2615 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY     BIT(4)
2616 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\
2617 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2618 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\
2619 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2620 
2621 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY    BIT(3)
2622 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\
2623 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2624 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\
2625 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2626 
2627 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE       BIT(2)
2628 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\
2629 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2630 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\
2631 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2632 
2633 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN        BIT(1)
2634 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\
2635 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2636 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\
2637 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2638 
2639 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT        BIT(0)
2640 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\
2641 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2642 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\
2643 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2644 
2645 /*      EACL:RAM_CTRL:RAM_INIT */
2646 #define EACL_RAM_INIT             __REG(TARGET_EACL, 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
2647 
2648 #define EACL_RAM_INIT_RAM_INIT                   BIT(1)
2649 #define EACL_RAM_INIT_RAM_INIT_SET(x)\
2650 	FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
2651 #define EACL_RAM_INIT_RAM_INIT_GET(x)\
2652 	FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
2653 
2654 #define EACL_RAM_INIT_RAM_CFG_HOOK               BIT(0)
2655 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2656 	FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2657 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2658 	FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2659 
2660 /*      FDMA:FDMA:FDMA_CH_ACTIVATE */
2661 #define FDMA_CH_ACTIVATE          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
2662 
2663 #define FDMA_CH_ACTIVATE_CH_ACTIVATE             GENMASK(7, 0)
2664 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
2665 	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2666 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
2667 	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2668 
2669 /*      FDMA:FDMA:FDMA_CH_RELOAD */
2670 #define FDMA_CH_RELOAD            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
2671 
2672 #define FDMA_CH_RELOAD_CH_RELOAD                 GENMASK(7, 0)
2673 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
2674 	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
2675 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
2676 	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
2677 
2678 /*      FDMA:FDMA:FDMA_CH_DISABLE */
2679 #define FDMA_CH_DISABLE           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
2680 
2681 #define FDMA_CH_DISABLE_CH_DISABLE               GENMASK(7, 0)
2682 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
2683 	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
2684 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
2685 	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
2686 
2687 /*      FDMA:FDMA:FDMA_DCB_LLP */
2688 #define FDMA_DCB_LLP(r)           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
2689 
2690 /*      FDMA:FDMA:FDMA_DCB_LLP1 */
2691 #define FDMA_DCB_LLP1(r)          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
2692 
2693 /*      FDMA:FDMA:FDMA_DCB_LLP_PREV */
2694 #define FDMA_DCB_LLP_PREV(r)      __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
2695 
2696 /*      FDMA:FDMA:FDMA_DCB_LLP_PREV1 */
2697 #define FDMA_DCB_LLP_PREV1(r)     __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
2698 
2699 /*      FDMA:FDMA:FDMA_CH_CFG */
2700 #define FDMA_CH_CFG(r)            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
2701 
2702 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE           BIT(7)
2703 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\
2704 	FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2705 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\
2706 	FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2707 
2708 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY          BIT(6)
2709 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
2710 	FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2711 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
2712 	FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2713 
2714 #define FDMA_CH_CFG_CH_INJ_PORT                  BIT(5)
2715 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
2716 	FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
2717 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
2718 	FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
2719 
2720 #define FDMA_CH_CFG_CH_DCB_DB_CNT                GENMASK(4, 1)
2721 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
2722 	FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2723 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
2724 	FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2725 
2726 #define FDMA_CH_CFG_CH_MEM                       BIT(0)
2727 #define FDMA_CH_CFG_CH_MEM_SET(x)\
2728 	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
2729 #define FDMA_CH_CFG_CH_MEM_GET(x)\
2730 	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
2731 
2732 /*      FDMA:FDMA:FDMA_CH_TRANSLATE */
2733 #define FDMA_CH_TRANSLATE(r)      __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
2734 
2735 #define FDMA_CH_TRANSLATE_OFFSET                 GENMASK(15, 0)
2736 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\
2737 	FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
2738 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\
2739 	FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
2740 
2741 /*      FDMA:FDMA:FDMA_XTR_CFG */
2742 #define FDMA_XTR_CFG              __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
2743 
2744 #define FDMA_XTR_CFG_XTR_FIFO_WM                 GENMASK(15, 11)
2745 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\
2746 	FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2747 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\
2748 	FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2749 
2750 #define FDMA_XTR_CFG_XTR_ARB_SAT                 GENMASK(10, 0)
2751 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\
2752 	FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2753 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\
2754 	FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2755 
2756 /*      FDMA:FDMA:FDMA_PORT_CTRL */
2757 #define FDMA_PORT_CTRL(r)         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
2758 
2759 #define FDMA_PORT_CTRL_INJ_STOP                  BIT(4)
2760 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
2761 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
2762 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
2763 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
2764 
2765 #define FDMA_PORT_CTRL_INJ_STOP_FORCE            BIT(3)
2766 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\
2767 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2768 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\
2769 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2770 
2771 #define FDMA_PORT_CTRL_XTR_STOP                  BIT(2)
2772 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
2773 	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
2774 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
2775 	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
2776 
2777 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY          BIT(1)
2778 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\
2779 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2780 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\
2781 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2782 
2783 #define FDMA_PORT_CTRL_XTR_BUF_RST               BIT(0)
2784 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\
2785 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2786 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\
2787 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2788 
2789 /*      FDMA:FDMA:FDMA_INTR_DCB */
2790 #define FDMA_INTR_DCB             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
2791 
2792 #define FDMA_INTR_DCB_INTR_DCB                   GENMASK(7, 0)
2793 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\
2794 	FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
2795 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\
2796 	FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
2797 
2798 /*      FDMA:FDMA:FDMA_INTR_DCB_ENA */
2799 #define FDMA_INTR_DCB_ENA         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
2800 
2801 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA           GENMASK(7, 0)
2802 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\
2803 	FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2804 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\
2805 	FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2806 
2807 /*      FDMA:FDMA:FDMA_INTR_DB */
2808 #define FDMA_INTR_DB              __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
2809 
2810 #define FDMA_INTR_DB_INTR_DB                     GENMASK(7, 0)
2811 #define FDMA_INTR_DB_INTR_DB_SET(x)\
2812 	FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
2813 #define FDMA_INTR_DB_INTR_DB_GET(x)\
2814 	FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
2815 
2816 /*      FDMA:FDMA:FDMA_INTR_DB_ENA */
2817 #define FDMA_INTR_DB_ENA          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
2818 
2819 #define FDMA_INTR_DB_ENA_INTR_DB_ENA             GENMASK(7, 0)
2820 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
2821 	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2822 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
2823 	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2824 
2825 /*      FDMA:FDMA:FDMA_INTR_ERR */
2826 #define FDMA_INTR_ERR             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
2827 
2828 #define FDMA_INTR_ERR_INTR_PORT_ERR              GENMASK(9, 8)
2829 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\
2830 	FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2831 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\
2832 	FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2833 
2834 #define FDMA_INTR_ERR_INTR_CH_ERR                GENMASK(7, 0)
2835 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\
2836 	FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
2837 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\
2838 	FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
2839 
2840 /*      FDMA:FDMA:FDMA_ERRORS */
2841 #define FDMA_ERRORS               __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
2842 
2843 #define FDMA_ERRORS_ERR_XTR_WR                   GENMASK(31, 30)
2844 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\
2845 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
2846 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\
2847 	FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
2848 
2849 #define FDMA_ERRORS_ERR_XTR_OVF                  GENMASK(29, 28)
2850 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\
2851 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
2852 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\
2853 	FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
2854 
2855 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF           GENMASK(27, 26)
2856 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\
2857 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2858 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\
2859 	FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2860 
2861 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL            GENMASK(25, 24)
2862 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\
2863 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2864 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\
2865 	FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2866 
2867 #define FDMA_ERRORS_ERR_DCB_RD                   GENMASK(23, 16)
2868 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\
2869 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
2870 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\
2871 	FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
2872 
2873 #define FDMA_ERRORS_ERR_INJ_RD                   GENMASK(15, 10)
2874 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\
2875 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
2876 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\
2877 	FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
2878 
2879 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC          GENMASK(9, 8)
2880 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\
2881 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2882 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\
2883 	FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2884 
2885 #define FDMA_ERRORS_ERR_CH_WR                    GENMASK(7, 0)
2886 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\
2887 	FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
2888 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\
2889 	FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
2890 
2891 /*      FDMA:FDMA:FDMA_ERRORS_2 */
2892 #define FDMA_ERRORS_2             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
2893 
2894 #define FDMA_ERRORS_2_ERR_XTR_FRAG               GENMASK(1, 0)
2895 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\
2896 	FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2897 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\
2898 	FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2899 
2900 /*      FDMA:FDMA:FDMA_CTRL */
2901 #define FDMA_CTRL                 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
2902 
2903 #define FDMA_CTRL_NRESET                         BIT(0)
2904 #define FDMA_CTRL_NRESET_SET(x)\
2905 	FIELD_PREP(FDMA_CTRL_NRESET, x)
2906 #define FDMA_CTRL_NRESET_GET(x)\
2907 	FIELD_GET(FDMA_CTRL_NRESET, x)
2908 
2909 /*      DEVCPU_GCB:CHIP_REGS:CHIP_ID */
2910 #define GCB_CHIP_ID               __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
2911 
2912 #define GCB_CHIP_ID_REV_ID                       GENMASK(31, 28)
2913 #define GCB_CHIP_ID_REV_ID_SET(x)\
2914 	FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
2915 #define GCB_CHIP_ID_REV_ID_GET(x)\
2916 	FIELD_GET(GCB_CHIP_ID_REV_ID, x)
2917 
2918 #define GCB_CHIP_ID_PART_ID                      GENMASK(27, 12)
2919 #define GCB_CHIP_ID_PART_ID_SET(x)\
2920 	FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
2921 #define GCB_CHIP_ID_PART_ID_GET(x)\
2922 	FIELD_GET(GCB_CHIP_ID_PART_ID, x)
2923 
2924 #define GCB_CHIP_ID_MFG_ID                       GENMASK(11, 1)
2925 #define GCB_CHIP_ID_MFG_ID_SET(x)\
2926 	FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
2927 #define GCB_CHIP_ID_MFG_ID_GET(x)\
2928 	FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
2929 
2930 #define GCB_CHIP_ID_ONE                          BIT(0)
2931 #define GCB_CHIP_ID_ONE_SET(x)\
2932 	FIELD_PREP(GCB_CHIP_ID_ONE, x)
2933 #define GCB_CHIP_ID_ONE_GET(x)\
2934 	FIELD_GET(GCB_CHIP_ID_ONE, x)
2935 
2936 /*      DEVCPU_GCB:CHIP_REGS:SOFT_RST */
2937 #define GCB_SOFT_RST              __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
2938 
2939 #define GCB_SOFT_RST_SOFT_NON_CFG_RST            BIT(2)
2940 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\
2941 	FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2942 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\
2943 	FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2944 
2945 #define GCB_SOFT_RST_SOFT_SWC_RST                BIT(1)
2946 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\
2947 	FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
2948 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\
2949 	FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
2950 
2951 #define GCB_SOFT_RST_SOFT_CHIP_RST               BIT(0)
2952 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
2953 	FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2954 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
2955 	FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2956 
2957 /*      DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */
2958 #define GCB_HW_SGPIO_SD_CFG       __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
2959 
2960 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA          BIT(1)
2961 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\
2962 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2963 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\
2964 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2965 
2966 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL           BIT(0)
2967 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\
2968 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2969 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\
2970 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2971 
2972 /*      DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */
2973 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
2974 
2975 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0)
2976 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\
2977 	FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2978 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\
2979 	FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2980 
2981 /*      DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */
2982 #define GCB_SIO_CLOCK(g)          __REG(TARGET_GCB, 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
2983 
2984 #define GCB_SIO_CLOCK_SIO_CLK_FREQ               GENMASK(19, 8)
2985 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\
2986 	FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2987 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\
2988 	FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2989 
2990 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD             GENMASK(7, 0)
2991 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\
2992 	FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2993 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\
2994 	FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2995 
2996 /*      HSCH:HSCH_MISC:SYS_CLK_PER */
2997 #define HSCH_SYS_CLK_PER          __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
2998 
2999 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS       GENMASK(7, 0)
3000 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\
3001 	FIELD_PREP(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3002 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\
3003 	FIELD_GET(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3004 
3005 /*      HSCH:SYSTEM:FLUSH_CTRL */
3006 #define HSCH_FLUSH_CTRL           __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
3007 
3008 #define HSCH_FLUSH_CTRL_FLUSH_ENA                BIT(27)
3009 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\
3010 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3011 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\
3012 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3013 
3014 #define HSCH_FLUSH_CTRL_FLUSH_SRC                BIT(26)
3015 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\
3016 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3017 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\
3018 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3019 
3020 #define HSCH_FLUSH_CTRL_FLUSH_DST                BIT(25)
3021 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\
3022 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3023 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\
3024 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3025 
3026 #define HSCH_FLUSH_CTRL_FLUSH_PORT               GENMASK(24, 18)
3027 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\
3028 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3029 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\
3030 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3031 
3032 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE              BIT(17)
3033 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\
3034 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3035 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\
3036 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3037 
3038 #define HSCH_FLUSH_CTRL_FLUSH_SE                 BIT(16)
3039 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\
3040 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3041 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\
3042 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3043 
3044 #define HSCH_FLUSH_CTRL_FLUSH_HIER               GENMASK(15, 0)
3045 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\
3046 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3047 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\
3048 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3049 
3050 /*      HSCH:SYSTEM:PORT_MODE */
3051 #define HSCH_PORT_MODE(r)         __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
3052 
3053 #define HSCH_PORT_MODE_DEQUEUE_DIS               BIT(4)
3054 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\
3055 	FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3056 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\
3057 	FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3058 
3059 #define HSCH_PORT_MODE_AGE_DIS                   BIT(3)
3060 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\
3061 	FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
3062 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\
3063 	FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
3064 
3065 #define HSCH_PORT_MODE_TRUNC_ENA                 BIT(2)
3066 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\
3067 	FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
3068 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\
3069 	FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
3070 
3071 #define HSCH_PORT_MODE_EIR_REMARK_ENA            BIT(1)
3072 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\
3073 	FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3074 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\
3075 	FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3076 
3077 #define HSCH_PORT_MODE_CPU_PRIO_MODE             BIT(0)
3078 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\
3079 	FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3080 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\
3081 	FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3082 
3083 /*      HSCH:SYSTEM:OUTB_SHARE_ENA */
3084 #define HSCH_OUTB_SHARE_ENA(r)    __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
3085 
3086 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA       GENMASK(7, 0)
3087 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\
3088 	FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3089 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\
3090 	FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3091 
3092 /*      HSCH:MMGT:RESET_CFG */
3093 #define HSCH_RESET_CFG            __REG(TARGET_HSCH, 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
3094 
3095 #define HSCH_RESET_CFG_CORE_ENA                  BIT(0)
3096 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\
3097 	FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
3098 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\
3099 	FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
3100 
3101 /*      HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */
3102 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH, 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
3103 
3104 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY    GENMASK(7, 0)
3105 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\
3106 	FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3107 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
3108 	FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3109 
3110 /*      LRN:COMMON:COMMON_ACCESS_CTRL */
3111 #define LRN_COMMON_ACCESS_CTRL    __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
3112 
3113 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20)
3114 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\
3115 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3116 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\
3117 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3118 
3119 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19)
3120 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\
3121 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3122 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\
3123 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3124 
3125 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5)
3126 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\
3127 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3128 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\
3129 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3130 
3131 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD    GENMASK(4, 1)
3132 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\
3133 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3134 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\
3135 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3136 
3137 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
3138 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\
3139 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3140 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\
3141 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3142 
3143 /*      LRN:COMMON:MAC_ACCESS_CFG_0 */
3144 #define LRN_MAC_ACCESS_CFG_0      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
3145 
3146 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID       GENMASK(28, 16)
3147 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\
3148 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3149 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\
3150 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3151 
3152 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB   GENMASK(15, 0)
3153 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\
3154 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3155 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\
3156 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3157 
3158 /*      LRN:COMMON:MAC_ACCESS_CFG_1 */
3159 #define LRN_MAC_ACCESS_CFG_1      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
3160 
3161 /*      LRN:COMMON:MAC_ACCESS_CFG_2 */
3162 #define LRN_MAC_ACCESS_CFG_2      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
3163 
3164 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28)
3165 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\
3166 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3167 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\
3168 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3169 
3170 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27)
3171 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\
3172 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3173 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\
3174 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3175 
3176 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU    GENMASK(26, 24)
3177 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\
3178 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3179 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\
3180 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3181 
3182 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY  BIT(23)
3183 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\
3184 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3185 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\
3186 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3187 
3188 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22)
3189 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\
3190 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3191 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\
3192 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3193 
3194 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR    BIT(21)
3195 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\
3196 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3197 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\
3198 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3199 
3200 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG  GENMASK(20, 19)
3201 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\
3202 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3203 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\
3204 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3205 
3206 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17)
3207 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\
3208 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3209 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\
3210 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3211 
3212 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED    BIT(16)
3213 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\
3214 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3215 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\
3216 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3217 
3218 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD       BIT(15)
3219 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\
3220 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3221 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\
3222 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3223 
3224 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)
3225 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\
3226 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3227 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\
3228 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3229 
3230 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR      GENMASK(11, 0)
3231 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\
3232 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3233 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\
3234 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3235 
3236 /*      LRN:COMMON:MAC_ACCESS_CFG_3 */
3237 #define LRN_MAC_ACCESS_CFG_3      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
3238 
3239 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0)
3240 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\
3241 	FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3242 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\
3243 	FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3244 
3245 /*      LRN:COMMON:SCAN_NEXT_CFG */
3246 #define LRN_SCAN_NEXT_CFG         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
3247 
3248 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19)
3249 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\
3250 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3251 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\
3252 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3253 
3254 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17)
3255 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\
3256 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3257 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\
3258 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3259 
3260 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL    GENMASK(16, 15)
3261 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\
3262 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3263 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\
3264 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3265 
3266 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14)
3267 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\
3268 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3269 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\
3270 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3271 
3272 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13)
3273 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\
3274 	FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3275 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\
3276 	FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3277 
3278 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12)
3279 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\
3280 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3281 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\
3282 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3283 
3284 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11)
3285 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\
3286 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3287 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\
3288 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3289 
3290 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)
3291 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\
3292 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3293 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\
3294 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3295 
3296 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9)
3297 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\
3298 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3299 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\
3300 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3301 
3302 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8)
3303 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\
3304 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3305 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\
3306 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3307 
3308 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)
3309 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\
3310 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3311 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\
3312 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3313 
3314 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3)
3315 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\
3316 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3317 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\
3318 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3319 
3320 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2)
3321 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\
3322 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3323 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\
3324 	FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3325 
3326 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA         BIT(1)
3327 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\
3328 	FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3329 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\
3330 	FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3331 
3332 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA        BIT(0)
3333 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\
3334 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3335 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\
3336 	FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3337 
3338 /*      LRN:COMMON:SCAN_NEXT_CFG_1 */
3339 #define LRN_SCAN_NEXT_CFG_1       __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
3340 
3341 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR   GENMASK(30, 16)
3342 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\
3343 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3344 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\
3345 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3346 
3347 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0)
3348 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\
3349 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3350 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\
3351 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3352 
3353 /*      LRN:COMMON:AUTOAGE_CFG */
3354 #define LRN_AUTOAGE_CFG(r)        __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
3355 
3356 #define LRN_AUTOAGE_CFG_UNIT_SIZE                GENMASK(29, 28)
3357 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\
3358 	FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3359 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\
3360 	FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3361 
3362 #define LRN_AUTOAGE_CFG_PERIOD_VAL               GENMASK(27, 0)
3363 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\
3364 	FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3365 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\
3366 	FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3367 
3368 /*      LRN:COMMON:AUTOAGE_CFG_1 */
3369 #define LRN_AUTOAGE_CFG_1         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
3370 
3371 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA     BIT(25)
3372 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\
3373 	FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3374 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\
3375 	FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3376 
3377 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15)
3378 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\
3379 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3380 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\
3381 	FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3382 
3383 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS        GENMASK(14, 7)
3384 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\
3385 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3386 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\
3387 	FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3388 
3389 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA    BIT(6)
3390 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\
3391 	FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3392 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\
3393 	FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3394 
3395 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT     GENMASK(5, 2)
3396 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\
3397 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3398 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\
3399 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3400 
3401 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
3402 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\
3403 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3404 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\
3405 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3406 
3407 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA         BIT(0)
3408 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\
3409 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3410 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\
3411 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3412 
3413 /*      LRN:COMMON:AUTOAGE_CFG_2 */
3414 #define LRN_AUTOAGE_CFG_2         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
3415 
3416 #define LRN_AUTOAGE_CFG_2_NEXT_ROW               GENMASK(17, 4)
3417 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\
3418 	FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3419 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\
3420 	FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3421 
3422 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS    GENMASK(3, 0)
3423 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\
3424 	FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3425 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\
3426 	FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3427 
3428 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */
3429 #define PCEP_RCTRL_2_OUT_0        __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
3430 
3431 #define PCEP_RCTRL_2_OUT_0_MSG_CODE              GENMASK(7, 0)
3432 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\
3433 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3434 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\
3435 	FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3436 
3437 #define PCEP_RCTRL_2_OUT_0_TAG                   GENMASK(15, 8)
3438 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\
3439 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
3440 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\
3441 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
3442 
3443 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN     BIT(16)
3444 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\
3445 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3446 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\
3447 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3448 
3449 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS           BIT(19)
3450 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\
3451 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3452 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\
3453 	FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3454 
3455 #define PCEP_RCTRL_2_OUT_0_SNP                   BIT(20)
3456 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\
3457 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
3458 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\
3459 	FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
3460 
3461 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD       BIT(22)
3462 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\
3463 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3464 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\
3465 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3466 
3467 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN  BIT(23)
3468 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\
3469 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3470 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\
3471 	FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3472 
3473 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE        BIT(28)
3474 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\
3475 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3476 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\
3477 	FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3478 
3479 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE           BIT(29)
3480 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\
3481 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3482 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\
3483 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3484 
3485 #define PCEP_RCTRL_2_OUT_0_REGION_EN             BIT(31)
3486 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\
3487 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3488 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\
3489 	FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3490 
3491 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */
3492 #define PCEP_ADDR_LWR_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
3493 
3494 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW          GENMASK(15, 0)
3495 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\
3496 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3497 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\
3498 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3499 
3500 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW          GENMASK(31, 16)
3501 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\
3502 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3503 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\
3504 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3505 
3506 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */
3507 #define PCEP_ADDR_UPR_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
3508 
3509 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */
3510 #define PCEP_ADDR_LIM_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
3511 
3512 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW        GENMASK(15, 0)
3513 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\
3514 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3515 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\
3516 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3517 
3518 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW        GENMASK(31, 16)
3519 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\
3520 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3521 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\
3522 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3523 
3524 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */
3525 #define PCEP_ADDR_LWR_TGT_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
3526 
3527 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */
3528 #define PCEP_ADDR_UPR_TGT_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
3529 
3530 /*      PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */
3531 #define PCEP_ADDR_UPR_LIM_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
3532 
3533 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
3534 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\
3535 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3536 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\
3537 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3538 
3539 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2)
3540 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\
3541 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3542 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\
3543 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3544 
3545 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3546 #define PCS10G_BR_PCS_CFG(t)      __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
3547 
3548 #define PCS10G_BR_PCS_CFG_PCS_ENA                BIT(31)
3549 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\
3550 	FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3551 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\
3552 	FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3553 
3554 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA       BIT(30)
3555 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3556 	FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3557 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3558 	FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3559 
3560 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX             GENMASK(29, 24)
3561 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3562 	FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3563 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3564 	FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3565 
3566 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP           BIT(18)
3567 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3568 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3569 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3570 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3571 
3572 #define PCS10G_BR_PCS_CFG_RESYNC_ENA             BIT(15)
3573 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3574 	FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3575 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3576 	FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3577 
3578 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS             BIT(14)
3579 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3580 	FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3581 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3582 	FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3583 
3584 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE           BIT(13)
3585 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3586 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3587 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3588 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3589 
3590 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE         BIT(12)
3591 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3592 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3593 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3594 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3595 
3596 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP           BIT(7)
3597 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3598 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3599 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3600 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3601 
3602 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA       BIT(6)
3603 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3604 	FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3605 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3606 	FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3607 
3608 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
3609 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3610 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3611 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3612 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3613 
3614 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE         BIT(3)
3615 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3616 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3617 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3618 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3619 
3620 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3621 #define PCS10G_BR_PCS_SD_CFG(t)   __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
3622 
3623 #define PCS10G_BR_PCS_SD_CFG_SD_SEL              BIT(8)
3624 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3625 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3626 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3627 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3628 
3629 #define PCS10G_BR_PCS_SD_CFG_SD_POL              BIT(4)
3630 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3631 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3632 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3633 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3634 
3635 #define PCS10G_BR_PCS_SD_CFG_SD_ENA              BIT(0)
3636 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3637 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3638 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3639 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3640 
3641 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3642 #define PCS25G_BR_PCS_CFG(t)      __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
3643 
3644 #define PCS25G_BR_PCS_CFG_PCS_ENA                BIT(31)
3645 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\
3646 	FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3647 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\
3648 	FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3649 
3650 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA       BIT(30)
3651 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3652 	FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3653 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3654 	FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3655 
3656 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX             GENMASK(29, 24)
3657 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3658 	FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3659 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3660 	FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3661 
3662 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP           BIT(18)
3663 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3664 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3665 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3666 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3667 
3668 #define PCS25G_BR_PCS_CFG_RESYNC_ENA             BIT(15)
3669 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3670 	FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3671 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3672 	FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3673 
3674 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS             BIT(14)
3675 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3676 	FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3677 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3678 	FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3679 
3680 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE           BIT(13)
3681 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3682 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3683 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3684 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3685 
3686 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE         BIT(12)
3687 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3688 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3689 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3690 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3691 
3692 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP           BIT(7)
3693 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3694 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3695 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3696 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3697 
3698 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA       BIT(6)
3699 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3700 	FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3701 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3702 	FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3703 
3704 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
3705 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3706 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3707 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3708 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3709 
3710 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE         BIT(3)
3711 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3712 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3713 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3714 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3715 
3716 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3717 #define PCS25G_BR_PCS_SD_CFG(t)   __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
3718 
3719 #define PCS25G_BR_PCS_SD_CFG_SD_SEL              BIT(8)
3720 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3721 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3722 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3723 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3724 
3725 #define PCS25G_BR_PCS_SD_CFG_SD_POL              BIT(4)
3726 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3727 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3728 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3729 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3730 
3731 #define PCS25G_BR_PCS_SD_CFG_SD_ENA              BIT(0)
3732 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3733 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3734 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3735 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3736 
3737 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
3738 #define PCS5G_BR_PCS_CFG(t)       __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
3739 
3740 #define PCS5G_BR_PCS_CFG_PCS_ENA                 BIT(31)
3741 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\
3742 	FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3743 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\
3744 	FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3745 
3746 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA        BIT(30)
3747 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
3748 	FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3749 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
3750 	FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3751 
3752 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX              GENMASK(29, 24)
3753 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
3754 	FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3755 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
3756 	FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3757 
3758 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP            BIT(18)
3759 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
3760 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3761 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
3762 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3763 
3764 #define PCS5G_BR_PCS_CFG_RESYNC_ENA              BIT(15)
3765 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
3766 	FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3767 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
3768 	FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3769 
3770 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS              BIT(14)
3771 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
3772 	FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3773 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
3774 	FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3775 
3776 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE            BIT(13)
3777 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
3778 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3779 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
3780 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3781 
3782 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE          BIT(12)
3783 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
3784 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3785 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
3786 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3787 
3788 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP            BIT(7)
3789 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
3790 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3791 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
3792 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3793 
3794 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA        BIT(6)
3795 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
3796 	FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3797 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
3798 	FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3799 
3800 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE            BIT(4)
3801 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
3802 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3803 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
3804 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3805 
3806 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE          BIT(3)
3807 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
3808 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3809 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
3810 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3811 
3812 /*      PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
3813 #define PCS5G_BR_PCS_SD_CFG(t)    __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
3814 
3815 #define PCS5G_BR_PCS_SD_CFG_SD_SEL               BIT(8)
3816 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
3817 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3818 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
3819 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3820 
3821 #define PCS5G_BR_PCS_SD_CFG_SD_POL               BIT(4)
3822 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\
3823 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3824 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\
3825 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3826 
3827 #define PCS5G_BR_PCS_SD_CFG_SD_ENA               BIT(0)
3828 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
3829 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3830 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
3831 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3832 
3833 /*      PORT_CONF:HW_CFG:DEV5G_MODES */
3834 #define PORT_CONF_DEV5G_MODES     __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
3835 
3836 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE      BIT(0)
3837 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\
3838 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3839 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\
3840 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3841 
3842 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE      BIT(1)
3843 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\
3844 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3845 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\
3846 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3847 
3848 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE      BIT(2)
3849 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\
3850 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3851 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\
3852 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3853 
3854 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE      BIT(3)
3855 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\
3856 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3857 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\
3858 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3859 
3860 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE      BIT(4)
3861 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\
3862 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3863 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\
3864 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3865 
3866 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE      BIT(5)
3867 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\
3868 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3869 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\
3870 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3871 
3872 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE      BIT(6)
3873 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\
3874 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3875 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\
3876 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3877 
3878 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE      BIT(7)
3879 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\
3880 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3881 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\
3882 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3883 
3884 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE      BIT(8)
3885 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\
3886 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3887 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\
3888 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3889 
3890 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE      BIT(9)
3891 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\
3892 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3893 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\
3894 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3895 
3896 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE     BIT(10)
3897 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\
3898 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3899 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\
3900 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3901 
3902 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE     BIT(11)
3903 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\
3904 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3905 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\
3906 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3907 
3908 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE     BIT(12)
3909 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\
3910 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3911 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\
3912 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3913 
3914 /*      PORT_CONF:HW_CFG:DEV10G_MODES */
3915 #define PORT_CONF_DEV10G_MODES    __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
3916 
3917 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE   BIT(0)
3918 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\
3919 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3920 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\
3921 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3922 
3923 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE   BIT(1)
3924 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\
3925 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3926 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\
3927 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3928 
3929 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE   BIT(2)
3930 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\
3931 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3932 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\
3933 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3934 
3935 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE   BIT(3)
3936 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\
3937 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3938 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\
3939 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3940 
3941 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE   BIT(4)
3942 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\
3943 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3944 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\
3945 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3946 
3947 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE   BIT(5)
3948 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\
3949 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3950 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\
3951 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3952 
3953 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE   BIT(6)
3954 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\
3955 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3956 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\
3957 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3958 
3959 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE   BIT(7)
3960 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\
3961 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3962 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\
3963 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3964 
3965 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE   BIT(8)
3966 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\
3967 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3968 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\
3969 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3970 
3971 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE   BIT(9)
3972 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\
3973 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3974 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\
3975 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3976 
3977 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE   BIT(10)
3978 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\
3979 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3980 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\
3981 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3982 
3983 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE   BIT(11)
3984 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\
3985 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3986 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\
3987 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3988 
3989 /*      PORT_CONF:HW_CFG:DEV25G_MODES */
3990 #define PORT_CONF_DEV25G_MODES    __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
3991 
3992 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE   BIT(0)
3993 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\
3994 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3995 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\
3996 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3997 
3998 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE   BIT(1)
3999 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\
4000 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4001 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\
4002 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4003 
4004 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE   BIT(2)
4005 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\
4006 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4007 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\
4008 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4009 
4010 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE   BIT(3)
4011 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\
4012 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4013 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\
4014 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4015 
4016 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE   BIT(4)
4017 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\
4018 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4019 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\
4020 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4021 
4022 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE   BIT(5)
4023 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\
4024 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4025 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\
4026 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4027 
4028 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE   BIT(6)
4029 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\
4030 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4031 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\
4032 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4033 
4034 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE   BIT(7)
4035 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\
4036 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4037 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\
4038 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4039 
4040 /*      PORT_CONF:HW_CFG:QSGMII_ENA */
4041 #define PORT_CONF_QSGMII_ENA      __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
4042 
4043 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0        BIT(0)
4044 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\
4045 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4046 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\
4047 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4048 
4049 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1        BIT(1)
4050 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\
4051 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4052 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\
4053 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4054 
4055 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2        BIT(2)
4056 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\
4057 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4058 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\
4059 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4060 
4061 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3        BIT(3)
4062 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\
4063 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4064 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\
4065 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4066 
4067 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4        BIT(4)
4068 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\
4069 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4070 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\
4071 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4072 
4073 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5        BIT(5)
4074 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\
4075 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4076 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\
4077 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4078 
4079 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6        BIT(6)
4080 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\
4081 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4082 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\
4083 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4084 
4085 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7        BIT(7)
4086 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\
4087 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4088 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\
4089 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4090 
4091 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8        BIT(8)
4092 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\
4093 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4094 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\
4095 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4096 
4097 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9        BIT(9)
4098 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\
4099 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4100 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\
4101 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4102 
4103 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10       BIT(10)
4104 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\
4105 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4106 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\
4107 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4108 
4109 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11       BIT(11)
4110 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\
4111 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4112 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\
4113 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4114 
4115 /*      PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */
4116 #define PORT_CONF_USGMII_CFG(g)   __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
4117 
4118 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM        BIT(9)
4119 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\
4120 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4121 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\
4122 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4123 
4124 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM      BIT(8)
4125 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\
4126 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4127 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\
4128 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4129 
4130 #define PORT_CONF_USGMII_CFG_FLIP_LANES          BIT(7)
4131 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\
4132 	FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4133 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\
4134 	FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4135 
4136 #define PORT_CONF_USGMII_CFG_SHYST_DIS           BIT(6)
4137 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\
4138 	FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4139 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\
4140 	FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4141 
4142 #define PORT_CONF_USGMII_CFG_E_DET_ENA           BIT(5)
4143 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\
4144 	FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4145 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\
4146 	FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4147 
4148 #define PORT_CONF_USGMII_CFG_USE_I1_ENA          BIT(4)
4149 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\
4150 	FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4151 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\
4152 	FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4153 
4154 #define PORT_CONF_USGMII_CFG_QUAD_MODE           BIT(1)
4155 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\
4156 	FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4157 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
4158 	FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4159 
4160 /*      DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */
4161 #define PTP_PTP_PIN_INTR          __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
4162 
4163 #define PTP_PTP_PIN_INTR_INTR_PTP                GENMASK(4, 0)
4164 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\
4165 	FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x)
4166 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\
4167 	FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x)
4168 
4169 /*      DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */
4170 #define PTP_PTP_PIN_INTR_ENA      __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
4171 
4172 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA        GENMASK(4, 0)
4173 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\
4174 	FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
4175 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\
4176 	FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
4177 
4178 /*      DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */
4179 #define PTP_PTP_INTR_IDENT        __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
4180 
4181 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT        GENMASK(4, 0)
4182 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\
4183 	FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
4184 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\
4185 	FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
4186 
4187 /*      DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */
4188 #define PTP_PTP_DOM_CFG           __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
4189 
4190 #define PTP_PTP_DOM_CFG_PTP_ENA                  GENMASK(11, 9)
4191 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
4192 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
4193 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
4194 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
4195 
4196 #define PTP_PTP_DOM_CFG_PTP_HOLD                 GENMASK(8, 6)
4197 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\
4198 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
4199 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\
4200 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
4201 
4202 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE           GENMASK(5, 3)
4203 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\
4204 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
4205 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\
4206 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
4207 
4208 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS           GENMASK(2, 0)
4209 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\
4210 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
4211 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\
4212 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
4213 
4214 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
4215 #define PTP_CLK_PER_CFG(g, r)     __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 0, r, 2, 4)
4216 
4217 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */
4218 #define PTP_PTP_CUR_NSEC(g)       __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
4219 
4220 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC            GENMASK(29, 0)
4221 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\
4222 	FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
4223 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\
4224 	FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
4225 
4226 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */
4227 #define PTP_PTP_CUR_NSEC_FRAC(g)  __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
4228 
4229 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC  GENMASK(7, 0)
4230 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\
4231 	FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
4232 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\
4233 	FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
4234 
4235 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */
4236 #define PTP_PTP_CUR_SEC_LSB(g)    __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
4237 
4238 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */
4239 #define PTP_PTP_CUR_SEC_MSB(g)    __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
4240 
4241 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB      GENMASK(15, 0)
4242 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\
4243 	FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
4244 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\
4245 	FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
4246 
4247 /*      DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */
4248 #define PTP_NTP_CUR_NSEC(g)       __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
4249 
4250 /*      DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */
4251 #define PTP_PTP_PIN_CFG(g)        __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
4252 
4253 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION           GENMASK(28, 26)
4254 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\
4255 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
4256 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\
4257 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
4258 
4259 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC             GENMASK(25, 24)
4260 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\
4261 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
4262 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\
4263 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
4264 
4265 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL          BIT(23)
4266 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\
4267 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
4268 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\
4269 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
4270 
4271 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT           GENMASK(22, 21)
4272 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\
4273 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
4274 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\
4275 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
4276 
4277 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT           GENMASK(20, 18)
4278 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\
4279 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
4280 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\
4281 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
4282 
4283 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM              GENMASK(17, 16)
4284 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\
4285 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
4286 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\
4287 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
4288 
4289 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT              GENMASK(15, 14)
4290 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\
4291 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
4292 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\
4293 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
4294 
4295 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK     BIT(13)
4296 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\
4297 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
4298 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\
4299 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
4300 
4301 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS         GENMASK(12, 0)
4302 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\
4303 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
4304 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\
4305 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
4306 
4307 /*      DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */
4308 #define PTP_PTP_TOD_SEC_MSB(g)    __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
4309 
4310 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB      GENMASK(15, 0)
4311 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\
4312 	FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
4313 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\
4314 	FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
4315 
4316 /*      DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */
4317 #define PTP_PTP_TOD_SEC_LSB(g)    __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
4318 
4319 /*      DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */
4320 #define PTP_PTP_TOD_NSEC(g)       __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
4321 
4322 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC            GENMASK(29, 0)
4323 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\
4324 	FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
4325 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\
4326 	FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
4327 
4328 /*      DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */
4329 #define PTP_PTP_TOD_NSEC_FRAC(g)  __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
4330 
4331 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC  GENMASK(7, 0)
4332 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\
4333 	FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
4334 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\
4335 	FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
4336 
4337 /*      DEVCPU_PTP:PTP_PINS:NTP_NSEC */
4338 #define PTP_NTP_NSEC(g)           __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
4339 
4340 /*      DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */
4341 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
4342 
4343 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH           GENMASK(29, 0)
4344 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\
4345 	FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
4346 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\
4347 	FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
4348 
4349 /*      DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */
4350 #define PTP_PIN_WF_LOW_PERIOD(g)  __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
4351 
4352 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL            GENMASK(29, 0)
4353 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\
4354 	FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
4355 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\
4356 	FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
4357 
4358 /*      DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */
4359 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
4360 
4361 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL  GENMASK(18, 3)
4362 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\
4363 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
4364 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\
4365 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
4366 
4367 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG  GENMASK(2, 0)
4368 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\
4369 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
4370 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\
4371 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
4372 
4373 /*      DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */
4374 #define PTP_PHAD_CTRL(g)          __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
4375 
4376 #define PTP_PHAD_CTRL_PHAD_ENA                   BIT(7)
4377 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\
4378 	FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x)
4379 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\
4380 	FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x)
4381 
4382 #define PTP_PHAD_CTRL_PHAD_FAILED                BIT(6)
4383 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\
4384 	FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x)
4385 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\
4386 	FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x)
4387 
4388 #define PTP_PHAD_CTRL_REDUCED_RES                GENMASK(5, 3)
4389 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\
4390 	FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
4391 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\
4392 	FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
4393 
4394 #define PTP_PHAD_CTRL_LOCK_ACC                   GENMASK(2, 0)
4395 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\
4396 	FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
4397 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\
4398 	FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
4399 
4400 /*      DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */
4401 #define PTP_PHAD_CYC_STAT(g)      __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
4402 
4403 /*      QFWD:SYSTEM:SWITCH_PORT_MODE */
4404 #define QFWD_SWITCH_PORT_MODE(r)  __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
4405 
4406 #define QFWD_SWITCH_PORT_MODE_PORT_ENA           BIT(19)
4407 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\
4408 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4409 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\
4410 	FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4411 
4412 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY        GENMASK(18, 10)
4413 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\
4414 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4415 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\
4416 	FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4417 
4418 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD          GENMASK(9, 6)
4419 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\
4420 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4421 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\
4422 	FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4423 
4424 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE  BIT(5)
4425 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
4426 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4427 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
4428 	FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4429 
4430 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING     BIT(4)
4431 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\
4432 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4433 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\
4434 	FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4435 
4436 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING     BIT(3)
4437 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\
4438 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4439 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\
4440 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4441 
4442 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE   BIT(2)
4443 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\
4444 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4445 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\
4446 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4447 
4448 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS    BIT(1)
4449 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\
4450 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4451 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\
4452 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4453 
4454 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE      BIT(0)
4455 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\
4456 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4457 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\
4458 	FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4459 
4460 /*      QRES:RES_CTRL:RES_CFG */
4461 #define QRES_RES_CFG(g)           __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
4462 
4463 #define QRES_RES_CFG_WM_HIGH                     GENMASK(11, 0)
4464 #define QRES_RES_CFG_WM_HIGH_SET(x)\
4465 	FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
4466 #define QRES_RES_CFG_WM_HIGH_GET(x)\
4467 	FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
4468 
4469 /*      QRES:RES_CTRL:RES_STAT */
4470 #define QRES_RES_STAT(g)          __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
4471 
4472 #define QRES_RES_STAT_MAXUSE                     GENMASK(20, 0)
4473 #define QRES_RES_STAT_MAXUSE_SET(x)\
4474 	FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
4475 #define QRES_RES_STAT_MAXUSE_GET(x)\
4476 	FIELD_GET(QRES_RES_STAT_MAXUSE, x)
4477 
4478 /*      QRES:RES_CTRL:RES_STAT_CUR */
4479 #define QRES_RES_STAT_CUR(g)      __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
4480 
4481 #define QRES_RES_STAT_CUR_INUSE                  GENMASK(20, 0)
4482 #define QRES_RES_STAT_CUR_INUSE_SET(x)\
4483 	FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
4484 #define QRES_RES_STAT_CUR_INUSE_GET(x)\
4485 	FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
4486 
4487 /*      DEVCPU_QS:XTR:XTR_GRP_CFG */
4488 #define QS_XTR_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
4489 
4490 #define QS_XTR_GRP_CFG_MODE                      GENMASK(3, 2)
4491 #define QS_XTR_GRP_CFG_MODE_SET(x)\
4492 	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
4493 #define QS_XTR_GRP_CFG_MODE_GET(x)\
4494 	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
4495 
4496 #define QS_XTR_GRP_CFG_STATUS_WORD_POS           BIT(1)
4497 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\
4498 	FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4499 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\
4500 	FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4501 
4502 #define QS_XTR_GRP_CFG_BYTE_SWAP                 BIT(0)
4503 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
4504 	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4505 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
4506 	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4507 
4508 /*      DEVCPU_QS:XTR:XTR_RD */
4509 #define QS_XTR_RD(r)              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
4510 
4511 /*      DEVCPU_QS:XTR:XTR_FLUSH */
4512 #define QS_XTR_FLUSH              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
4513 
4514 #define QS_XTR_FLUSH_FLUSH                       GENMASK(1, 0)
4515 #define QS_XTR_FLUSH_FLUSH_SET(x)\
4516 	FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
4517 #define QS_XTR_FLUSH_FLUSH_GET(x)\
4518 	FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
4519 
4520 /*      DEVCPU_QS:XTR:XTR_DATA_PRESENT */
4521 #define QS_XTR_DATA_PRESENT       __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
4522 
4523 #define QS_XTR_DATA_PRESENT_DATA_PRESENT         GENMASK(1, 0)
4524 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\
4525 	FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4526 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\
4527 	FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4528 
4529 /*      DEVCPU_QS:INJ:INJ_GRP_CFG */
4530 #define QS_INJ_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
4531 
4532 #define QS_INJ_GRP_CFG_MODE                      GENMASK(3, 2)
4533 #define QS_INJ_GRP_CFG_MODE_SET(x)\
4534 	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
4535 #define QS_INJ_GRP_CFG_MODE_GET(x)\
4536 	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
4537 
4538 #define QS_INJ_GRP_CFG_BYTE_SWAP                 BIT(0)
4539 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
4540 	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4541 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
4542 	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4543 
4544 /*      DEVCPU_QS:INJ:INJ_WR */
4545 #define QS_INJ_WR(r)              __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
4546 
4547 /*      DEVCPU_QS:INJ:INJ_CTRL */
4548 #define QS_INJ_CTRL(r)            __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
4549 
4550 #define QS_INJ_CTRL_GAP_SIZE                     GENMASK(24, 21)
4551 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
4552 	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
4553 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
4554 	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
4555 
4556 #define QS_INJ_CTRL_ABORT                        BIT(20)
4557 #define QS_INJ_CTRL_ABORT_SET(x)\
4558 	FIELD_PREP(QS_INJ_CTRL_ABORT, x)
4559 #define QS_INJ_CTRL_ABORT_GET(x)\
4560 	FIELD_GET(QS_INJ_CTRL_ABORT, x)
4561 
4562 #define QS_INJ_CTRL_EOF                          BIT(19)
4563 #define QS_INJ_CTRL_EOF_SET(x)\
4564 	FIELD_PREP(QS_INJ_CTRL_EOF, x)
4565 #define QS_INJ_CTRL_EOF_GET(x)\
4566 	FIELD_GET(QS_INJ_CTRL_EOF, x)
4567 
4568 #define QS_INJ_CTRL_SOF                          BIT(18)
4569 #define QS_INJ_CTRL_SOF_SET(x)\
4570 	FIELD_PREP(QS_INJ_CTRL_SOF, x)
4571 #define QS_INJ_CTRL_SOF_GET(x)\
4572 	FIELD_GET(QS_INJ_CTRL_SOF, x)
4573 
4574 #define QS_INJ_CTRL_VLD_BYTES                    GENMASK(17, 16)
4575 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
4576 	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
4577 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
4578 	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
4579 
4580 /*      DEVCPU_QS:INJ:INJ_STATUS */
4581 #define QS_INJ_STATUS             __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
4582 
4583 #define QS_INJ_STATUS_WMARK_REACHED              GENMASK(5, 4)
4584 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
4585 	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
4586 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
4587 	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
4588 
4589 #define QS_INJ_STATUS_FIFO_RDY                   GENMASK(3, 2)
4590 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
4591 	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
4592 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
4593 	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
4594 
4595 #define QS_INJ_STATUS_INJ_IN_PROGRESS            GENMASK(1, 0)
4596 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\
4597 	FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4598 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\
4599 	FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4600 
4601 /*      QSYS:PAUSE_CFG:PAUSE_CFG */
4602 #define QSYS_PAUSE_CFG(r)         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
4603 
4604 #define QSYS_PAUSE_CFG_PAUSE_START               GENMASK(25, 14)
4605 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\
4606 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
4607 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\
4608 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
4609 
4610 #define QSYS_PAUSE_CFG_PAUSE_STOP                GENMASK(13, 2)
4611 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
4612 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4613 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
4614 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4615 
4616 #define QSYS_PAUSE_CFG_PAUSE_ENA                 BIT(1)
4617 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
4618 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4619 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
4620 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4621 
4622 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA   BIT(0)
4623 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\
4624 	FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4625 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\
4626 	FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4627 
4628 /*      QSYS:PAUSE_CFG:ATOP */
4629 #define QSYS_ATOP(r)              __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
4630 
4631 #define QSYS_ATOP_ATOP                           GENMASK(11, 0)
4632 #define QSYS_ATOP_ATOP_SET(x)\
4633 	FIELD_PREP(QSYS_ATOP_ATOP, x)
4634 #define QSYS_ATOP_ATOP_GET(x)\
4635 	FIELD_GET(QSYS_ATOP_ATOP, x)
4636 
4637 /*      QSYS:PAUSE_CFG:FWD_PRESSURE */
4638 #define QSYS_FWD_PRESSURE(r)      __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
4639 
4640 #define QSYS_FWD_PRESSURE_FWD_PRESSURE           GENMASK(11, 1)
4641 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\
4642 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4643 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\
4644 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4645 
4646 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS       BIT(0)
4647 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\
4648 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4649 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\
4650 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4651 
4652 /*      QSYS:PAUSE_CFG:ATOP_TOT_CFG */
4653 #define QSYS_ATOP_TOT_CFG         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
4654 
4655 #define QSYS_ATOP_TOT_CFG_ATOP_TOT               GENMASK(11, 0)
4656 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\
4657 	FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4658 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\
4659 	FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4660 
4661 /*      QSYS:CALCFG:CAL_AUTO */
4662 #define QSYS_CAL_AUTO(r)          __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
4663 
4664 #define QSYS_CAL_AUTO_CAL_AUTO                   GENMASK(29, 0)
4665 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\
4666 	FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
4667 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\
4668 	FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
4669 
4670 /*      QSYS:CALCFG:CAL_CTRL */
4671 #define QSYS_CAL_CTRL             __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
4672 
4673 #define QSYS_CAL_CTRL_CAL_MODE                   GENMASK(14, 11)
4674 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\
4675 	FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
4676 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\
4677 	FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
4678 
4679 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE        GENMASK(10, 1)
4680 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\
4681 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4682 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\
4683 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4684 
4685 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR             BIT(0)
4686 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\
4687 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4688 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\
4689 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4690 
4691 /*      QSYS:RAM_CTRL:RAM_INIT */
4692 #define QSYS_RAM_INIT             __REG(TARGET_QSYS, 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
4693 
4694 #define QSYS_RAM_INIT_RAM_INIT                   BIT(1)
4695 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\
4696 	FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
4697 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\
4698 	FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
4699 
4700 #define QSYS_RAM_INIT_RAM_CFG_HOOK               BIT(0)
4701 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4702 	FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4703 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4704 	FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4705 
4706 /*      REW:COMMON:OWN_UPSID */
4707 #define REW_OWN_UPSID(r)          __REG(TARGET_REW, 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
4708 
4709 #define REW_OWN_UPSID_OWN_UPSID                  GENMASK(4, 0)
4710 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\
4711 	FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
4712 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\
4713 	FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
4714 
4715 /*      REW:PORT:PORT_VLAN_CFG */
4716 #define REW_PORT_VLAN_CFG(g)      __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
4717 
4718 #define REW_PORT_VLAN_CFG_PORT_PCP               GENMASK(15, 13)
4719 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\
4720 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
4721 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\
4722 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
4723 
4724 #define REW_PORT_VLAN_CFG_PORT_DEI               BIT(12)
4725 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\
4726 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
4727 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\
4728 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
4729 
4730 #define REW_PORT_VLAN_CFG_PORT_VID               GENMASK(11, 0)
4731 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
4732 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
4733 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
4734 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
4735 
4736 /*      REW:PORT:TAG_CTRL */
4737 #define REW_TAG_CTRL(g)           __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
4738 
4739 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED     BIT(13)
4740 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\
4741 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4742 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\
4743 	FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4744 
4745 #define REW_TAG_CTRL_TAG_CFG                     GENMASK(12, 11)
4746 #define REW_TAG_CTRL_TAG_CFG_SET(x)\
4747 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
4748 #define REW_TAG_CTRL_TAG_CFG_GET(x)\
4749 	FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
4750 
4751 #define REW_TAG_CTRL_TAG_TPID_CFG                GENMASK(10, 8)
4752 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\
4753 	FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
4754 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\
4755 	FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
4756 
4757 #define REW_TAG_CTRL_TAG_VID_CFG                 GENMASK(7, 6)
4758 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\
4759 	FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
4760 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\
4761 	FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
4762 
4763 #define REW_TAG_CTRL_TAG_PCP_CFG                 GENMASK(5, 3)
4764 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\
4765 	FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
4766 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\
4767 	FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
4768 
4769 #define REW_TAG_CTRL_TAG_DEI_CFG                 GENMASK(2, 0)
4770 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\
4771 	FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
4772 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
4773 	FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
4774 
4775 /*      REW:PTP_CTRL:PTP_TWOSTEP_CTRL */
4776 #define REW_PTP_TWOSTEP_CTRL      __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
4777 
4778 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA        BIT(12)
4779 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
4780 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
4781 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
4782 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
4783 
4784 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT             BIT(11)
4785 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
4786 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
4787 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
4788 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
4789 
4790 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD             BIT(10)
4791 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
4792 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
4793 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
4794 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
4795 
4796 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX            BIT(9)
4797 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
4798 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
4799 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
4800 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
4801 
4802 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT          GENMASK(8, 1)
4803 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
4804 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
4805 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
4806 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
4807 
4808 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL            BIT(0)
4809 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
4810 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
4811 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
4812 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
4813 
4814 /*      REW:PTP_CTRL:PTP_TWOSTEP_STAMP */
4815 #define REW_PTP_TWOSTEP_STAMP     __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
4816 
4817 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC         GENMASK(29, 0)
4818 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
4819 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
4820 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
4821 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
4822 
4823 /*      REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */
4824 #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
4825 
4826 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)
4827 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
4828 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
4829 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
4830 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
4831 
4832 /*      REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */
4833 #define REW_PTP_RSRV_NOT_ZERO     __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
4834 
4835 /*      REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */
4836 #define REW_PTP_RSRV_NOT_ZERO1    __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
4837 
4838 /*      REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */
4839 #define REW_PTP_RSRV_NOT_ZERO2    __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
4840 
4841 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0)
4842 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\
4843 	FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
4844 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\
4845 	FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
4846 
4847 /*      REW:PTP_CTRL:PTP_GEN_STAMP_FMT */
4848 #define REW_PTP_GEN_STAMP_FMT(r)  __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
4849 
4850 #define REW_PTP_GEN_STAMP_FMT_RT_OFS             GENMASK(6, 2)
4851 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\
4852 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
4853 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\
4854 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
4855 
4856 #define REW_PTP_GEN_STAMP_FMT_RT_FMT             GENMASK(1, 0)
4857 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\
4858 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
4859 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\
4860 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
4861 
4862 /*      REW:RAM_CTRL:RAM_INIT */
4863 #define REW_RAM_INIT              __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
4864 
4865 #define REW_RAM_INIT_RAM_INIT                    BIT(1)
4866 #define REW_RAM_INIT_RAM_INIT_SET(x)\
4867 	FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
4868 #define REW_RAM_INIT_RAM_INIT_GET(x)\
4869 	FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
4870 
4871 #define REW_RAM_INIT_RAM_CFG_HOOK                BIT(0)
4872 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4873 	FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
4874 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4875 	FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
4876 
4877 /*      VCAP_SUPER:RAM_CTRL:RAM_INIT */
4878 #define VCAP_SUPER_RAM_INIT       __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
4879 
4880 #define VCAP_SUPER_RAM_INIT_RAM_INIT             BIT(1)
4881 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\
4882 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4883 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\
4884 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4885 
4886 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK         BIT(0)
4887 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4888 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4889 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4890 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4891 
4892 /*      VOP:RAM_CTRL:RAM_INIT */
4893 #define VOP_RAM_INIT              __REG(TARGET_VOP, 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
4894 
4895 #define VOP_RAM_INIT_RAM_INIT                    BIT(1)
4896 #define VOP_RAM_INIT_RAM_INIT_SET(x)\
4897 	FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
4898 #define VOP_RAM_INIT_RAM_INIT_GET(x)\
4899 	FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
4900 
4901 #define VOP_RAM_INIT_RAM_CFG_HOOK                BIT(0)
4902 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4903 	FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4904 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4905 	FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4906 
4907 /*      XQS:SYSTEM:STAT_CFG */
4908 #define XQS_STAT_CFG              __REG(TARGET_XQS, 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
4909 
4910 #define XQS_STAT_CFG_STAT_CLEAR_SHOT             GENMASK(21, 18)
4911 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\
4912 	FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4913 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\
4914 	FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4915 
4916 #define XQS_STAT_CFG_STAT_VIEW                   GENMASK(17, 5)
4917 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\
4918 	FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
4919 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\
4920 	FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
4921 
4922 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY           BIT(4)
4923 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\
4924 	FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4925 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\
4926 	FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4927 
4928 #define XQS_STAT_CFG_STAT_WRAP_DIS               GENMASK(3, 0)
4929 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\
4930 	FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4931 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\
4932 	FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4933 
4934 /*      XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */
4935 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
4936 
4937 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP    GENMASK(14, 0)
4938 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\
4939 	FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4940 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\
4941 	FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4942 
4943 /*      XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */
4944 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
4945 
4946 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP  GENMASK(14, 0)
4947 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\
4948 	FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4949 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\
4950 	FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4951 
4952 /*      XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */
4953 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
4954 
4955 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP  GENMASK(14, 0)
4956 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\
4957 	FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4958 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\
4959 	FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4960 
4961 /*      XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */
4962 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
4963 
4964 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM  GENMASK(14, 0)
4965 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\
4966 	FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
4967 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\
4968 	FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
4969 
4970 /*      XQS:STAT:CNT */
4971 #define XQS_CNT(g)                __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
4972 
4973 #endif /* _SPARX5_MAIN_REGS_H_ */
4974