1 /* SPDX-License-Identifier: GPL-2.0+ 2 * Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2023-01-17 17:04:43 +0100. 8 * Commit ID: cc027a9bd71002aebf074df5ad8584fe1545e05e 9 */ 10 11 #ifndef _SPARX5_MAIN_REGS_H_ 12 #define _SPARX5_MAIN_REGS_H_ 13 14 #include <linux/bitfield.h> 15 #include <linux/types.h> 16 #include <linux/bug.h> 17 18 enum sparx5_target { 19 TARGET_ANA_AC = 1, 20 TARGET_ANA_ACL = 2, 21 TARGET_ANA_AC_POL = 4, 22 TARGET_ANA_AC_SDLB = 5, 23 TARGET_ANA_CL = 6, 24 TARGET_ANA_L2 = 7, 25 TARGET_ANA_L3 = 8, 26 TARGET_ASM = 9, 27 TARGET_CLKGEN = 11, 28 TARGET_CPU = 12, 29 TARGET_DEV10G = 17, 30 TARGET_DEV25G = 29, 31 TARGET_DEV2G5 = 37, 32 TARGET_DEV5G = 102, 33 TARGET_DSM = 115, 34 TARGET_EACL = 116, 35 TARGET_FDMA = 117, 36 TARGET_GCB = 118, 37 TARGET_HSCH = 119, 38 TARGET_LRN = 122, 39 TARGET_PCEP = 129, 40 TARGET_PCS10G_BR = 132, 41 TARGET_PCS25G_BR = 144, 42 TARGET_PCS5G_BR = 160, 43 TARGET_PORT_CONF = 173, 44 TARGET_PTP = 174, 45 TARGET_QFWD = 175, 46 TARGET_QRES = 176, 47 TARGET_QS = 177, 48 TARGET_QSYS = 178, 49 TARGET_REW = 179, 50 TARGET_VCAP_ES2 = 324, 51 TARGET_VCAP_SUPER = 326, 52 TARGET_VOP = 327, 53 TARGET_XQS = 331, 54 NUM_TARGETS = 332 55 }; 56 57 #define __REG(...) __VA_ARGS__ 58 59 /* ANA_AC:RAM_CTRL:RAM_INIT */ 60 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) 61 62 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 63 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ 64 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 65 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ 66 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 67 68 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) 69 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 70 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 72 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 73 74 /* ANA_AC:PS_COMMON:OWN_UPSID */ 75 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) 76 77 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 78 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ 79 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 80 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 81 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 82 83 /* ANA_AC:SRC:SRC_CFG */ 84 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) 85 86 /* ANA_AC:SRC:SRC_CFG1 */ 87 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) 88 89 /* ANA_AC:SRC:SRC_CFG2 */ 90 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) 91 92 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 93 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ 94 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 95 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 96 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 97 98 /* ANA_AC:PGID:PGID_CFG */ 99 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) 100 101 /* ANA_AC:PGID:PGID_CFG1 */ 102 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) 103 104 /* ANA_AC:PGID:PGID_CFG2 */ 105 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) 106 107 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 108 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ 109 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 110 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 111 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 112 113 /* ANA_AC:PGID:PGID_MISC_CFG */ 114 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) 115 116 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 117 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ 118 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 119 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ 120 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 121 122 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) 123 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ 124 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 125 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ 126 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 127 128 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) 129 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ 130 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 131 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 132 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 133 134 /* ANA_AC:TSN_SF:TSN_SF */ 135 #define ANA_AC_TSN_SF \ 136 __REG(TARGET_ANA_AC, 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4) 137 138 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) 139 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ 140 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 141 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ 142 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 143 144 #define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0) 145 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ 146 FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x) 147 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ 148 FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x) 149 150 /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 151 #define ANA_AC_TSN_SF_CFG(g) \ 152 __REG(TARGET_ANA_AC, 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4) 153 154 #define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16) 155 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ 156 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 157 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ 158 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 159 160 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) 161 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ 162 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 163 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\ 164 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 165 166 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1) 167 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x) \ 168 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 169 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x) \ 170 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 171 172 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE BIT(0) 173 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x) \ 174 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 175 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x) \ 176 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 177 178 /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 179 #define ANA_AC_TSN_SF_STATUS \ 180 __REG(TARGET_ANA_AC, 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4) 181 182 #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) 183 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ 184 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 185 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\ 186 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 187 188 #define ANA_AC_TSN_SF_STATUS_DLB_DROP BIT(11) 189 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\ 190 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 191 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ 192 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 193 194 #define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1) 195 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ 196 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 197 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ 198 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 199 200 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) 201 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ 202 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 203 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ 204 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 205 206 /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 207 #define ANA_AC_SG_ACCESS_CTRL \ 208 __REG(TARGET_ANA_AC, 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4) 209 210 #define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0) 211 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ 212 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x) 213 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ 214 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x) 215 216 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) 217 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ 218 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 219 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ 220 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 221 222 /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 223 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ 224 __REG(TARGET_ANA_AC, 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4) 225 226 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) 227 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ 228 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 229 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\ 230 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 231 232 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31) 233 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\ 234 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 235 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ 236 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 237 238 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 239 #define ANA_AC_SG_CONFIG_REG_1 \ 240 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4) 241 242 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 243 #define ANA_AC_SG_CONFIG_REG_2 \ 244 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4) 245 246 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 247 #define ANA_AC_SG_CONFIG_REG_3 \ 248 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4) 249 250 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) 251 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ 252 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 253 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\ 254 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 255 256 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16) 257 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\ 258 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 259 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\ 260 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 261 262 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) 263 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\ 264 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 265 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\ 266 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 267 268 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21) 269 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\ 270 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 271 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\ 272 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 273 274 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) 275 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\ 276 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 277 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\ 278 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 279 280 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA BIT(26) 281 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\ 282 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 283 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\ 284 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 285 286 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX BIT(27) 287 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\ 288 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 289 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\ 290 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 291 292 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28) 293 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\ 294 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 295 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\ 296 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 297 298 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED BIT(29) 299 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\ 300 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 301 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ 302 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 303 304 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 305 #define ANA_AC_SG_CONFIG_REG_4 \ 306 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4) 307 308 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 309 #define ANA_AC_SG_CONFIG_REG_5 \ 310 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4) 311 312 /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 313 #define ANA_AC_SG_GCL_GS_CONFIG(r) \ 314 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 0, r, 4, 4) 315 316 #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) 317 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ 318 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 319 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\ 320 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 321 322 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) 323 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\ 324 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 325 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ 326 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 327 328 /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 329 #define ANA_AC_SG_GCL_TI_CONFIG(r) \ 330 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 16, r, 4, 4) 331 332 /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 333 #define ANA_AC_SG_GCL_OCT_CONFIG(r) \ 334 __REG(TARGET_ANA_AC, 0, 1, 851584, 0, 1, 128, 32, r, 4, 4) 335 336 /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 337 #define ANA_AC_SG_STATUS_REG_1 \ 338 __REG(TARGET_ANA_AC, 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4) 339 340 /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 341 #define ANA_AC_SG_STATUS_REG_2 \ 342 __REG(TARGET_ANA_AC, 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4) 343 344 /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 345 #define ANA_AC_SG_STATUS_REG_3 \ 346 __REG(TARGET_ANA_AC, 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4) 347 348 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) 349 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ 350 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 351 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\ 352 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 353 354 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE BIT(16) 355 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\ 356 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 357 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\ 358 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 359 360 #define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20) 361 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\ 362 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x) 363 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\ 364 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x) 365 366 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) 367 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\ 368 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 369 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\ 370 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 371 372 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25) 373 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\ 374 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 375 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ 376 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 377 378 /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 379 #define ANA_AC_SG_STATUS_REG_4 \ 380 __REG(TARGET_ANA_AC, 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4) 381 382 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 383 #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) 384 385 #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) 386 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 387 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) 388 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 389 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) 390 391 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 392 #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) 393 394 #define ANA_AC_STAT_RESET_RESET BIT(0) 395 #define ANA_AC_STAT_RESET_RESET_SET(x)\ 396 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) 397 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 398 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 399 400 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 401 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4) 402 403 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 404 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ 405 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 406 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ 407 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 408 409 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) 410 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ 411 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 412 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ 413 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 414 415 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) 416 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ 417 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 418 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 419 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 420 421 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 422 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4) 423 424 /* ANA_ACL:COMMON:VCAP_S2_CFG */ 425 #define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) 426 427 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 428 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ 429 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 430 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ 431 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 432 433 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26) 434 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ 435 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 436 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ 437 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 438 439 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24) 440 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ 441 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 442 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ 443 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 444 445 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22) 446 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ 447 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 448 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ 449 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 450 451 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20) 452 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ 453 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 454 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ 455 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 456 457 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18) 458 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ 459 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 460 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ 461 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 462 463 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16) 464 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ 465 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 466 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ 467 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 468 469 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14) 470 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ 471 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 472 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ 473 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 474 475 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12) 476 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ 477 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 478 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ 479 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 480 481 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10) 482 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ 483 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 484 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ 485 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 486 487 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8) 488 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ 489 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 490 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ 491 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 492 493 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6) 494 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ 495 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 496 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ 497 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 498 499 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4) 500 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ 501 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 502 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ 503 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 504 505 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0) 506 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ 507 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 508 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 509 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 510 511 /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 512 #define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) 513 514 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 515 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ 516 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 517 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ 518 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 519 520 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10) 521 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ 522 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 523 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ 524 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 525 526 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2) 527 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ 528 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 529 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ 530 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 531 532 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1) 533 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ 534 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 535 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ 536 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 537 538 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0) 539 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ 540 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 541 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 542 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 543 544 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 545 #define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) 546 547 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 548 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ 549 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 550 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ 551 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 552 553 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0) 554 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ 555 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 556 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 557 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 558 559 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 560 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) 561 562 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 563 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ 564 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 565 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ 566 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 567 568 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4) 569 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ 570 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 571 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ 572 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 573 574 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0) 575 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ 576 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 577 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 578 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 579 580 /* ANA_ACL:COMMON:OWN_UPSID */ 581 #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) 582 583 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 584 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ 585 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 586 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 587 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 588 589 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 590 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL, 0, 1, 34200, g, 134, 16, 0, r, 4, 4) 591 592 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 593 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ 594 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 595 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ 596 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 597 598 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12) 599 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ 600 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 601 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ 602 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 603 604 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10) 605 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ 606 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 607 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ 608 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 609 610 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8) 611 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ 612 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 613 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ 614 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 615 616 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6) 617 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ 618 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 619 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ 620 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 621 622 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3) 623 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ 624 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 625 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ 626 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 627 628 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1) 629 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ 630 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 631 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ 632 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 633 634 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0) 635 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 636 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 637 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 638 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 639 640 /* ANA_ACL:CNT_A:CNT_A */ 641 #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL, 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) 642 643 /* ANA_ACL:CNT_B:CNT_B */ 644 #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL, 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) 645 646 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 647 #define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL, 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) 648 649 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 650 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ 651 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 652 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ 653 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 654 655 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16) 656 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ 657 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 658 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ 659 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 660 661 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15) 662 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ 663 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 664 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ 665 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 666 667 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14) 668 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ 669 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 670 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ 671 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 672 673 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13) 674 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ 675 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 676 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ 677 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 678 679 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12) 680 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ 681 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 682 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ 683 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 684 685 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11) 686 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ 687 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 688 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ 689 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 690 691 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10) 692 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 693 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 694 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 695 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 696 697 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9) 698 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 699 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 700 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 701 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 702 703 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8) 704 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ 705 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 706 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ 707 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 708 709 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 710 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 711 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 712 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 713 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 714 715 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6) 716 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 717 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 718 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 719 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 720 721 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5) 722 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 723 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 724 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 725 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 726 727 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4) 728 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 729 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 730 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 731 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 732 733 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3) 734 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 735 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 736 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 737 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 738 739 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2) 740 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ 741 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 742 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ 743 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 744 745 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1) 746 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ 747 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 748 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ 749 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 750 751 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 752 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 753 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 754 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 755 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 756 757 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 758 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) 759 760 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 761 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ 762 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 763 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 764 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 765 766 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 767 #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) 768 769 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 770 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 771 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 772 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 773 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 774 775 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 776 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 777 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 778 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 779 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 780 781 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) 782 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ 783 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 784 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ 785 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 786 787 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 788 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 789 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 790 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 791 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 792 793 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 794 #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) 795 796 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 797 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 798 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 799 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 800 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 801 802 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 803 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 804 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 805 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 806 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 807 808 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) 809 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ 810 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 811 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ 812 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 813 814 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 815 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 816 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 817 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 818 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 819 820 /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 821 #define ANA_AC_SDLB_XLB_START(g) \ 822 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 0, 0, 1, 4) 823 824 #define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0) 825 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ 826 FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x) 827 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ 828 FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x) 829 830 /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 831 #define ANA_AC_SDLB_PUP_INTERVAL(g) \ 832 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 4, 0, 1, 4) 833 834 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) 835 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ 836 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 837 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ 838 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 839 840 /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 841 #define ANA_AC_SDLB_PUP_CTRL(g) \ 842 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 8, 0, 1, 4) 843 844 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) 845 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ 846 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 847 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\ 848 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 849 850 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA BIT(24) 851 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\ 852 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 853 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ 854 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 855 856 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 857 #define ANA_AC_SDLB_LBGRP_MISC(g)\ 858 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 12, 0, 1, 4) 859 860 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8) 861 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ 862 FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 863 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ 864 FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 865 866 /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 867 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ 868 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 16, 0, 1, 4) 869 870 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) 871 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ 872 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 873 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ 874 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 875 876 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 877 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ 878 __REG(TARGET_ANA_AC_SDLB, 0, 1, 295468, g, 10, 24, 20, 0, 1, 4) 879 880 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) 881 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ 882 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 883 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\ 884 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 885 886 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1) 887 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\ 888 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 889 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ 890 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 891 892 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16) 893 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ 894 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 895 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ 896 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 897 898 /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 899 #define ANA_AC_SDLB_PUP_TOKENS(g, r) \ 900 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 0, r, 2, 4) 901 902 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) 903 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ 904 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 905 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ 906 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 907 908 /* ANA_AC_SDLB:LBSET_TBL:THRES */ 909 #define ANA_AC_SDLB_THRES(g, r) \ 910 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 8, r, 2, 4) 911 912 #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) 913 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ 914 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x) 915 #define ANA_AC_SDLB_THRES_THRES_GET(x)\ 916 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x) 917 918 #define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16) 919 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\ 920 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x) 921 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ 922 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) 923 924 /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 925 #define ANA_AC_SDLB_XLB_NEXT(g) \ 926 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 16, 0, 1, 4) 927 928 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0) 929 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ 930 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 931 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ 932 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 933 934 #define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24) 935 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ 936 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 937 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ 938 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 939 940 /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 941 #define ANA_AC_SDLB_INH_CTRL(g, r) \ 942 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 20, r, 2, 4) 943 944 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) 945 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ 946 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 947 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\ 948 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 949 950 #define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20) 951 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\ 952 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 953 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\ 954 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 955 956 #define ANA_AC_SDLB_INH_CTRL_INH_LB BIT(24) 957 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\ 958 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 959 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ 960 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 961 962 /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 963 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ 964 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 28, 0, 1, 4) 965 966 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0) 967 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ 968 FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 969 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ 970 FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 971 972 /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 973 #define ANA_AC_SDLB_DLB_MISC(g) \ 974 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 32, 0, 1, 4) 975 976 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) 977 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ 978 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 979 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\ 980 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 981 982 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6) 983 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\ 984 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 985 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\ 986 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 987 988 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8) 989 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\ 990 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 991 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ 992 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 993 994 /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 995 #define ANA_AC_SDLB_DLB_CFG(g) \ 996 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, 4616, 64, 36, 0, 1, 4) 997 998 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) 999 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ 1000 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1001 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\ 1002 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1003 1004 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9) 1005 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\ 1006 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1007 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\ 1008 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1009 1010 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS BIT(8) 1011 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\ 1012 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1013 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\ 1014 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1015 1016 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS BIT(7) 1017 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\ 1018 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1019 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\ 1020 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1021 1022 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5) 1023 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\ 1024 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1025 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\ 1026 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1027 1028 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3) 1029 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\ 1030 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1031 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\ 1032 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1033 1034 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE BIT(2) 1035 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\ 1036 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1037 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\ 1038 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1039 1040 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0) 1041 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\ 1042 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1043 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ 1044 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1045 1046 /* ANA_CL:PORT:FILTER_CTRL */ 1047 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) 1048 1049 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 1050 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ 1051 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1052 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ 1053 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1054 1055 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) 1056 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ 1057 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1058 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ 1059 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1060 1061 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) 1062 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ 1063 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1064 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 1065 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1066 1067 /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1068 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4) 1069 1070 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 1071 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ 1072 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1073 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ 1074 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1075 1076 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) 1077 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ 1078 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1079 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ 1080 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1081 1082 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) 1083 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ 1084 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1085 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ 1086 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1087 1088 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) 1089 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ 1090 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1091 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ 1092 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1093 1094 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) 1095 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ 1096 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1097 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ 1098 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1099 1100 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) 1101 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ 1102 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1103 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ 1104 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1105 1106 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) 1107 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ 1108 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1109 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ 1110 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1111 1112 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) 1113 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ 1114 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1115 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ 1116 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1117 1118 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) 1119 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ 1120 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1121 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ 1122 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1123 1124 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) 1125 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ 1126 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1127 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ 1128 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1129 1130 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) 1131 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ 1132 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1133 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 1134 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1135 1136 /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1137 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) 1138 1139 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 1140 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ 1141 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1142 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ 1143 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1144 1145 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) 1146 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ 1147 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1148 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 1149 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1150 1151 /* ANA_CL:PORT:VLAN_CTRL */ 1152 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) 1153 1154 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 1155 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ 1156 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1157 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ 1158 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1159 1160 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) 1161 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ 1162 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1163 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ 1164 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1165 1166 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) 1167 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ 1168 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1169 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ 1170 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1171 1172 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) 1173 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ 1174 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1175 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ 1176 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1177 1178 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) 1179 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ 1180 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1181 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ 1182 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1183 1184 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) 1185 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ 1186 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1187 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ 1188 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1189 1190 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) 1191 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ 1192 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1193 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ 1194 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1195 1196 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) 1197 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ 1198 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1199 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ 1200 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1201 1202 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) 1203 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ 1204 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1205 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ 1206 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1207 1208 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) 1209 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ 1210 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1211 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ 1212 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1213 1214 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) 1215 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ 1216 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) 1217 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 1218 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 1219 1220 /* ANA_CL:PORT:VLAN_CTRL_2 */ 1221 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) 1222 1223 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 1224 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ 1225 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1226 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 1227 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1228 1229 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1230 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 108, r, 16, 4) 1231 1232 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 1233 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ 1234 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1235 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ 1236 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1237 1238 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0) 1239 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ 1240 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1241 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 1242 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1243 1244 /* ANA_CL:PORT:QOS_CFG */ 1245 #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) 1246 1247 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 1248 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ 1249 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1250 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ 1251 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1252 1253 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14) 1254 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ 1255 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1256 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ 1257 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1258 1259 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12) 1260 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ 1261 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1262 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ 1263 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1264 1265 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11) 1266 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ 1267 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1268 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ 1269 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1270 1271 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10) 1272 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ 1273 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1274 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ 1275 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1276 1277 #define ANA_CL_QOS_CFG_KEEP_ENA BIT(9) 1278 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ 1279 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x) 1280 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ 1281 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x) 1282 1283 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8) 1284 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ 1285 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1286 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ 1287 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1288 1289 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7) 1290 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ 1291 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1292 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ 1293 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1294 1295 #define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6) 1296 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ 1297 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1298 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ 1299 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1300 1301 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5) 1302 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ 1303 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1304 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ 1305 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1306 1307 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3) 1308 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ 1309 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1310 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ 1311 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1312 1313 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0) 1314 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ 1315 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1316 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 1317 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1318 1319 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1320 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) 1321 1322 /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1323 #define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 200, r, 6, 4) 1324 1325 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) 1326 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ 1327 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1328 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\ 1329 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1330 1331 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA BIT(0) 1332 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\ 1333 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1334 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ 1335 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1336 1337 /* ANA_CL:PORT:ADV_CL_CFG */ 1338 #define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 224, r, 6, 4) 1339 1340 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) 1341 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ 1342 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1343 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\ 1344 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1345 1346 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21) 1347 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\ 1348 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1349 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\ 1350 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1351 1352 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16) 1353 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\ 1354 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1355 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\ 1356 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1357 1358 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11) 1359 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\ 1360 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1361 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\ 1362 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1363 1364 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6) 1365 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\ 1366 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1367 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\ 1368 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1369 1370 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1) 1371 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\ 1372 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1373 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\ 1374 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1375 1376 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA BIT(0) 1377 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\ 1378 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1379 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ 1380 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1381 1382 /* ANA_CL:COMMON:OWN_UPSID */ 1383 #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) 1384 1385 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1386 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ 1387 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1388 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 1389 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1390 1391 /* ANA_CL:COMMON:DSCP_CFG */ 1392 #define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) 1393 1394 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 1395 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ 1396 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1397 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ 1398 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1399 1400 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4) 1401 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ 1402 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1403 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ 1404 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1405 1406 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2) 1407 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ 1408 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1409 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ 1410 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1411 1412 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1) 1413 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 1414 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1415 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 1416 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1417 1418 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0) 1419 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 1420 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1421 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 1422 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1423 1424 /* ANA_CL:COMMON:QOS_MAP_CFG */ 1425 #define ANA_CL_QOS_MAP_CFG(r) \ 1426 __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 512, r, 32, 4) 1427 1428 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) 1429 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ 1430 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1431 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ 1432 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1433 1434 /* ANA_L2:COMMON:FWD_CFG */ 1435 #define ANA_L2_FWD_CFG \ 1436 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4) 1437 1438 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) 1439 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ 1440 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1441 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\ 1442 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1443 1444 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA BIT(18) 1445 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\ 1446 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1447 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\ 1448 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1449 1450 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA BIT(17) 1451 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\ 1452 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1453 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\ 1454 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1455 1456 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA BIT(16) 1457 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\ 1458 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1459 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\ 1460 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1461 1462 #define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8) 1463 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\ 1464 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1465 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\ 1466 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1467 1468 #define ANA_L2_FWD_CFG_LOOPBACK_ENA BIT(7) 1469 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\ 1470 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1471 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\ 1472 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1473 1474 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) 1475 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\ 1476 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1477 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\ 1478 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1479 1480 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL BIT(4) 1481 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\ 1482 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1483 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\ 1484 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1485 1486 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA BIT(3) 1487 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\ 1488 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1489 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\ 1490 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1491 1492 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA BIT(2) 1493 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\ 1494 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1495 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\ 1496 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1497 1498 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1) 1499 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\ 1500 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1501 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\ 1502 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1503 1504 #define ANA_L2_FWD_CFG_FWD_ENA BIT(0) 1505 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\ 1506 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x) 1507 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ 1508 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) 1509 1510 /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1511 #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) 1512 1513 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1514 #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) 1515 1516 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1517 #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) 1518 1519 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 1520 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ 1521 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1522 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 1523 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1524 1525 /* ANA_L2:COMMON:OWN_UPSID */ 1526 #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) 1527 1528 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1529 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ 1530 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1531 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 1532 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1533 1534 /* ANA_L2:ISDX:DLB_CFG */ 1535 #define ANA_L2_DLB_CFG(g) \ 1536 __REG(TARGET_ANA_L2, 0, 1, 0, g, 4096, 128, 56, 0, 1, 4) 1537 1538 #define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0) 1539 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ 1540 FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x) 1541 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ 1542 FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x) 1543 1544 /* ANA_L2:ISDX:TSN_CFG */ 1545 #define ANA_L2_TSN_CFG(g) \ 1546 __REG(TARGET_ANA_L2, 0, 1, 0, g, 4096, 128, 100, 0, 1, 4) 1547 1548 #define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0) 1549 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ 1550 FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x) 1551 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ 1552 FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x) 1553 1554 /* ANA_L3:COMMON:VLAN_CTRL */ 1555 #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) 1556 1557 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 1558 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ 1559 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1560 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 1561 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1562 1563 /* ANA_L3:VLAN:VLAN_CFG */ 1564 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) 1565 1566 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 1567 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ 1568 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1569 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ 1570 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1571 1572 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) 1573 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ 1574 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) 1575 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ 1576 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) 1577 1578 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) 1579 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ 1580 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1581 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ 1582 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1583 1584 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) 1585 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ 1586 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1587 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ 1588 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1589 1590 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) 1591 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ 1592 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1593 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ 1594 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1595 1596 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) 1597 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ 1598 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1599 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ 1600 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1601 1602 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) 1603 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ 1604 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1605 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ 1606 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1607 1608 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) 1609 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ 1610 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1611 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ 1612 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1613 1614 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) 1615 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ 1616 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1617 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 1618 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1619 1620 /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1621 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) 1622 1623 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1624 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) 1625 1626 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1627 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) 1628 1629 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 1630 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ 1631 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1632 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 1633 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1634 1635 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1636 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4) 1637 1638 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1639 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4) 1640 1641 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1642 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4) 1643 1644 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1645 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4) 1646 1647 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1648 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4) 1649 1650 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1651 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4) 1652 1653 /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1654 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4) 1655 1656 /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1657 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4) 1658 1659 /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1660 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4) 1661 1662 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1663 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4) 1664 1665 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1666 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4) 1667 1668 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1669 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4) 1670 1671 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1672 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4) 1673 1674 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1675 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4) 1676 1677 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1678 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4) 1679 1680 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1681 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4) 1682 1683 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1684 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4) 1685 1686 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1687 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4) 1688 1689 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1690 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4) 1691 1692 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1693 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4) 1694 1695 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1696 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4) 1697 1698 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 1699 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4) 1700 1701 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 1702 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4) 1703 1704 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 1705 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4) 1706 1707 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 1708 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4) 1709 1710 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 1711 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4) 1712 1713 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 1714 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4) 1715 1716 /* ASM:DEV_STATISTICS:TX_UC_CNT */ 1717 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4) 1718 1719 /* ASM:DEV_STATISTICS:TX_MC_CNT */ 1720 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4) 1721 1722 /* ASM:DEV_STATISTICS:TX_BC_CNT */ 1723 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4) 1724 1725 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 1726 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4) 1727 1728 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 1729 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4) 1730 1731 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 1732 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4) 1733 1734 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 1735 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4) 1736 1737 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 1738 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4) 1739 1740 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 1741 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4) 1742 1743 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 1744 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4) 1745 1746 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 1747 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4) 1748 1749 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 1750 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4) 1751 1752 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 1753 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4) 1754 1755 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 1756 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4) 1757 1758 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 1759 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4) 1760 1761 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 1762 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4) 1763 1764 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 1765 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4) 1766 1767 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 1768 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4) 1769 1770 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 1771 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4) 1772 1773 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 1774 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4) 1775 1776 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 1777 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4) 1778 1779 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 1780 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4) 1781 1782 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 1783 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4) 1784 1785 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 1786 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4) 1787 1788 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 1789 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4) 1790 1791 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 1792 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4) 1793 1794 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 1795 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4) 1796 1797 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1798 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4) 1799 1800 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 1801 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4) 1802 1803 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 1804 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4) 1805 1806 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 1807 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4) 1808 1809 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 1810 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4) 1811 1812 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 1813 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4) 1814 1815 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 1816 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4) 1817 1818 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 1819 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4) 1820 1821 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 1822 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4) 1823 1824 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 1825 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4) 1826 1827 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 1828 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4) 1829 1830 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 1831 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4) 1832 1833 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 1834 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4) 1835 1836 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 1837 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4) 1838 1839 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 1840 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4) 1841 1842 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 1843 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4) 1844 1845 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 1846 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4) 1847 1848 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 1849 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4) 1850 1851 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 1852 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4) 1853 1854 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 1855 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4) 1856 1857 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 1858 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4) 1859 1860 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 1861 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4) 1862 1863 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 1864 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4) 1865 1866 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 1867 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4) 1868 1869 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 1870 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4) 1871 1872 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 1873 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4) 1874 1875 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 1876 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4) 1877 1878 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 1879 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4) 1880 1881 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 1882 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4) 1883 1884 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 1885 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4) 1886 1887 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 1888 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4) 1889 1890 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 1891 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4) 1892 1893 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 1894 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4) 1895 1896 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 1897 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4) 1898 1899 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 1900 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4) 1901 1902 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 1903 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4) 1904 1905 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 1906 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 1907 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 1908 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 1909 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 1910 1911 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 1912 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4) 1913 1914 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1915 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 1916 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 1917 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 1918 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 1919 1920 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 1921 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4) 1922 1923 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1924 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 1925 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 1926 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 1927 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 1928 1929 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 1930 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4) 1931 1932 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 1933 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 1934 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 1935 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 1936 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 1937 1938 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 1939 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4) 1940 1941 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 1942 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 1943 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 1944 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 1945 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 1946 1947 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 1948 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4) 1949 1950 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 1951 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 1952 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 1953 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 1954 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 1955 1956 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 1957 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4) 1958 1959 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1960 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 1961 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 1962 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 1963 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 1964 1965 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 1966 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4) 1967 1968 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1969 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 1970 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 1971 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 1972 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 1973 1974 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 1975 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4) 1976 1977 /* ASM:CFG:STAT_CFG */ 1978 #define ASM_STAT_CFG __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) 1979 1980 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 1981 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ 1982 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 1983 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 1984 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 1985 1986 /* ASM:CFG:PORT_CFG */ 1987 #define ASM_PORT_CFG(r) __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) 1988 1989 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 1990 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ 1991 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) 1992 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ 1993 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) 1994 1995 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) 1996 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ 1997 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 1998 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ 1999 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2000 2001 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) 2002 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ 2003 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2004 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ 2005 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2006 2007 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) 2008 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ 2009 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2010 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ 2011 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2012 2013 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) 2014 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ 2015 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2016 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ 2017 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2018 2019 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) 2020 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ 2021 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) 2022 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ 2023 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) 2024 2025 #define ASM_PORT_CFG_PAD_ENA BIT(6) 2026 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ 2027 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) 2028 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ 2029 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) 2030 2031 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) 2032 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ 2033 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2034 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ 2035 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2036 2037 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) 2038 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ 2039 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2040 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ 2041 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2042 2043 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) 2044 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ 2045 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2046 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ 2047 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2048 2049 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) 2050 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ 2051 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) 2052 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 2053 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 2054 2055 /* ASM:RAM_CTRL:RAM_INIT */ 2056 #define ASM_RAM_INIT __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) 2057 2058 #define ASM_RAM_INIT_RAM_INIT BIT(1) 2059 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ 2060 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) 2061 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ 2062 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) 2063 2064 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) 2065 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 2066 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2067 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2068 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2069 2070 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2071 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2072 2073 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 2074 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ 2075 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2076 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ 2077 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2078 2079 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) 2080 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ 2081 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2082 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ 2083 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2084 2085 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) 2086 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ 2087 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2088 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ 2089 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2090 2091 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) 2092 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ 2093 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2094 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ 2095 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2096 2097 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) 2098 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ 2099 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2100 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ 2101 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2102 2103 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) 2104 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ 2105 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2106 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 2107 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2108 2109 /* CPU:CPU_REGS:PROC_CTRL */ 2110 #define CPU_PROC_CTRL __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) 2111 2112 #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) 2113 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 2114 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2115 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 2116 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2117 2118 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) 2119 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 2120 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2121 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 2122 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2123 2124 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) 2125 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 2126 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2127 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 2128 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2129 2130 #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) 2131 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 2132 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2133 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 2134 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2135 2136 #define CPU_PROC_CTRL_VINITHI BIT(8) 2137 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 2138 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) 2139 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 2140 FIELD_GET(CPU_PROC_CTRL_VINITHI, x) 2141 2142 #define CPU_PROC_CTRL_CFGTE BIT(7) 2143 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 2144 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) 2145 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 2146 FIELD_GET(CPU_PROC_CTRL_CFGTE, x) 2147 2148 #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) 2149 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 2150 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) 2151 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 2152 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) 2153 2154 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) 2155 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 2156 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2157 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 2158 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2159 2160 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 2161 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 2162 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2163 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 2164 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2165 2166 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 2167 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 2168 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 2169 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 2170 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 2171 2172 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 2173 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 2174 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 2175 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 2176 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 2177 2178 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) 2179 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 2180 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2181 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 2182 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2183 2184 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 2185 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 2186 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 2187 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 2188 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 2189 2190 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2191 #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4) 2192 2193 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 2194 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2195 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2196 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2197 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2198 2199 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) 2200 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2201 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2202 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2203 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2204 2205 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2206 #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4) 2207 2208 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2209 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2210 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2211 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2212 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2213 2214 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2215 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2216 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2217 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2218 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2219 2220 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2221 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4) 2222 2223 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 2224 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ 2225 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2226 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 2227 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2228 2229 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2230 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4) 2231 2232 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2233 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2234 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2235 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2236 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2237 2238 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) 2239 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ 2240 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2241 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 2242 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2243 2244 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2245 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4) 2246 2247 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2248 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2249 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2250 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2251 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2252 2253 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2254 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2255 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2256 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2257 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2258 2259 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2260 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2261 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2262 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2263 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2264 2265 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2266 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2267 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2268 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2269 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2270 2271 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2272 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2273 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2274 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2275 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2276 2277 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2278 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2279 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2280 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2281 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2282 2283 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2284 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2285 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2286 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2287 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2288 2289 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2290 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4) 2291 2292 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 2293 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ 2294 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2295 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ 2296 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2297 2298 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) 2299 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ 2300 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2301 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ 2302 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2303 2304 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) 2305 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ 2306 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2307 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ 2308 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2309 2310 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) 2311 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ 2312 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2313 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ 2314 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2315 2316 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) 2317 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ 2318 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2319 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 2320 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2321 2322 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2323 #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4) 2324 2325 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2326 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2327 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2328 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2329 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2330 2331 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2332 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2333 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2334 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2335 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2336 2337 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2338 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2339 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2340 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2341 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2342 2343 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2344 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2345 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2346 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2347 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2348 2349 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2350 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2351 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2352 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2353 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2354 2355 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2356 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2357 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2358 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2359 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2360 2361 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2362 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2363 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2364 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2365 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2366 2367 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2368 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2369 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2370 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2371 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2372 2373 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2374 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2375 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2376 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2377 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2378 2379 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2380 #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4) 2381 2382 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 2383 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2384 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2385 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2386 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2387 2388 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2389 #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2390 2391 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 2392 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2393 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2394 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2395 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2396 2397 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) 2398 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2399 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2400 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2401 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2402 2403 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2404 #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2405 2406 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2407 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2408 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2409 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2410 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2411 2412 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2413 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2414 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2415 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2416 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2417 2418 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2419 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2420 2421 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2422 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2423 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2424 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2425 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2426 2427 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2428 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2429 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2430 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2431 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2432 2433 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2434 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2435 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2436 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2437 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2438 2439 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2440 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2441 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2442 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2443 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2444 2445 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2446 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2447 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2448 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2449 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2450 2451 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2452 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2453 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2454 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2455 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2456 2457 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2458 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2459 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2460 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2461 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2462 2463 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2464 #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 2465 2466 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2467 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2468 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2469 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2470 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2471 2472 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2473 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2474 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2475 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2476 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2477 2478 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2479 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2480 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2481 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2482 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2483 2484 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2485 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2486 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2487 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2488 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2489 2490 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2491 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2492 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2493 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2494 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2495 2496 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2497 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2498 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 2499 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2500 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 2501 2502 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2503 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2504 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 2505 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2506 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 2507 2508 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2509 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2510 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 2511 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2512 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 2513 2514 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2515 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2516 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 2517 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2518 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 2519 2520 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2521 #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 2522 2523 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 2524 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2525 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 2526 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2527 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 2528 2529 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 2530 #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 2531 2532 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 2533 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ 2534 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 2535 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ 2536 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 2537 2538 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) 2539 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ 2540 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) 2541 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ 2542 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) 2543 2544 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) 2545 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ 2546 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 2547 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 2548 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 2549 2550 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2551 #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4) 2552 2553 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 2554 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2555 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2556 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2557 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2558 2559 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2560 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2561 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 2562 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2563 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 2564 2565 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) 2566 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ 2567 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 2568 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ 2569 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 2570 2571 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) 2572 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ 2573 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 2574 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ 2575 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 2576 2577 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2578 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2579 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 2580 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2581 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 2582 2583 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2584 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2585 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 2586 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2587 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 2588 2589 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2590 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2591 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 2592 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2593 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 2594 2595 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2596 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2597 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 2598 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2599 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 2600 2601 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2602 #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4) 2603 2604 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 2605 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ 2606 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 2607 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ 2608 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 2609 2610 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) 2611 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ 2612 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 2613 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 2614 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 2615 2616 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 2617 #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4) 2618 2619 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 2620 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ 2621 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 2622 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ 2623 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 2624 2625 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 2626 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 2627 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 2628 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 2629 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 2630 2631 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) 2632 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ 2633 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 2634 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 2635 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 2636 2637 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2638 #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4) 2639 2640 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2641 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2642 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2643 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2644 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2645 2646 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2647 #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4) 2648 2649 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2650 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2651 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2652 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2653 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2654 2655 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 2656 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 2657 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2658 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 2659 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2660 2661 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 2662 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ 2663 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2664 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ 2665 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2666 2667 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 2668 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 2669 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2670 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 2671 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2672 2673 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 2674 #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4) 2675 2676 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 2677 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ 2678 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2679 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ 2680 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2681 2682 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) 2683 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ 2684 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2685 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 2686 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2687 2688 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2689 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4) 2690 2691 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 2692 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ 2693 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2694 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 2695 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2696 2697 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 2698 #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4) 2699 2700 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 2701 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ 2702 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2703 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ 2704 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2705 2706 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 2707 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ 2708 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2709 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ 2710 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2711 2712 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 2713 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ 2714 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2715 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ 2716 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2717 2718 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 2719 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ 2720 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2721 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 2722 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2723 2724 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 2725 #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4) 2726 2727 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 2728 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ 2729 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2730 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ 2731 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2732 2733 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) 2734 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ 2735 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) 2736 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ 2737 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) 2738 2739 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) 2740 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 2741 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 2742 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 2743 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 2744 2745 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) 2746 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ 2747 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 2748 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ 2749 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 2750 2751 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) 2752 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ 2753 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 2754 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 2755 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 2756 2757 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 2758 #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4) 2759 2760 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 2761 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ 2762 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 2763 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ 2764 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 2765 2766 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) 2767 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ 2768 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 2769 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ 2770 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 2771 2772 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) 2773 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ 2774 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) 2775 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 2776 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 2777 2778 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 2779 #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4) 2780 2781 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 2782 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ 2783 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 2784 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ 2785 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 2786 2787 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 2788 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 2789 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 2790 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 2791 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 2792 2793 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 2794 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 2795 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 2796 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 2797 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 2798 2799 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 2800 #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4) 2801 2802 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 2803 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ 2804 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 2805 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ 2806 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 2807 2808 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) 2809 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ 2810 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 2811 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ 2812 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 2813 2814 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) 2815 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ 2816 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 2817 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 2818 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 2819 2820 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 2821 #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4) 2822 2823 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 2824 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 2825 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 2826 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 2827 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 2828 2829 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 2830 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 2831 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 2832 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 2833 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 2834 2835 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) 2836 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ 2837 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 2838 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ 2839 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 2840 2841 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) 2842 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ 2843 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 2844 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 2845 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 2846 2847 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 2848 #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4) 2849 2850 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 2851 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ 2852 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 2853 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ 2854 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 2855 2856 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) 2857 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ 2858 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 2859 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ 2860 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 2861 2862 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) 2863 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ 2864 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 2865 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 2866 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 2867 2868 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 2869 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4) 2870 2871 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 2872 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ 2873 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 2874 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ 2875 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 2876 2877 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) 2878 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ 2879 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 2880 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ 2881 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 2882 2883 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) 2884 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ 2885 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 2886 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ 2887 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 2888 2889 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 2890 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 2891 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 2892 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 2893 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 2894 2895 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 2896 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4) 2897 2898 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 2899 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ 2900 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 2901 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ 2902 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 2903 2904 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) 2905 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ 2906 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 2907 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ 2908 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 2909 2910 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 2911 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 2912 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 2913 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 2914 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 2915 2916 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 2917 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 2918 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 2919 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 2920 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 2921 2922 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 2923 #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4) 2924 2925 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 2926 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 2927 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 2928 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 2929 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 2930 2931 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) 2932 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ 2933 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 2934 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 2935 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 2936 2937 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 2938 #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4) 2939 2940 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 2941 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ 2942 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 2943 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ 2944 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 2945 2946 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) 2947 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ 2948 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) 2949 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ 2950 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) 2951 2952 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) 2953 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ 2954 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 2955 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ 2956 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 2957 2958 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) 2959 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ 2960 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 2961 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ 2962 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 2963 2964 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) 2965 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ 2966 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 2967 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ 2968 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 2969 2970 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) 2971 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ 2972 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 2973 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ 2974 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 2975 2976 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) 2977 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ 2978 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 2979 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ 2980 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 2981 2982 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) 2983 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ 2984 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 2985 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ 2986 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 2987 2988 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) 2989 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ 2990 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 2991 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ 2992 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 2993 2994 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) 2995 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ 2996 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 2997 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ 2998 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 2999 3000 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) 3001 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ 3002 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3003 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ 3004 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3005 3006 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) 3007 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ 3008 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3009 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ 3010 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3011 3012 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) 3013 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ 3014 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3015 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 3016 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3017 3018 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3019 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4) 3020 3021 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 3022 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ 3023 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3024 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ 3025 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3026 3027 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) 3028 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ 3029 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3030 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ 3031 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3032 3033 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) 3034 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ 3035 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3036 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ 3037 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3038 3039 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) 3040 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ 3041 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3042 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ 3043 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3044 3045 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) 3046 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ 3047 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3048 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ 3049 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3050 3051 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) 3052 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ 3053 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3054 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ 3055 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3056 3057 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) 3058 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ 3059 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3060 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ 3061 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3062 3063 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) 3064 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ 3065 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3066 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 3067 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3068 3069 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3070 #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4) 3071 3072 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 3073 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ 3074 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3075 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ 3076 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3077 3078 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) 3079 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ 3080 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3081 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 3082 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3083 3084 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3085 #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4) 3086 3087 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 3088 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 3089 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3090 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 3091 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3092 3093 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3094 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3095 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3096 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3097 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3098 3099 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3100 #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4) 3101 3102 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 3103 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 3104 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3105 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 3106 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3107 3108 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 3109 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 3110 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3111 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 3112 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3113 3114 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 3115 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 3116 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3117 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 3118 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3119 3120 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 3121 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 3122 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3123 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 3124 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3125 3126 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 3127 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 3128 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3129 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 3130 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3131 3132 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 3133 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 3134 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3135 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 3136 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3137 3138 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 3139 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 3140 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3141 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3142 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3143 3144 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3145 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4) 3146 3147 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3148 #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4) 3149 3150 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3151 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4) 3152 3153 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3154 #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4) 3155 3156 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3157 #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4) 3158 3159 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3160 #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4) 3161 3162 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3163 #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4) 3164 3165 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3166 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4) 3167 3168 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3169 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4) 3170 3171 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3172 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4) 3173 3174 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3175 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4) 3176 3177 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3178 #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4) 3179 3180 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3181 #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4) 3182 3183 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3184 #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4) 3185 3186 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3187 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4) 3188 3189 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3190 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4) 3191 3192 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3193 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4) 3194 3195 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3196 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4) 3197 3198 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3199 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4) 3200 3201 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3202 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4) 3203 3204 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3205 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4) 3206 3207 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3208 #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4) 3209 3210 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3211 #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4) 3212 3213 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3214 #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4) 3215 3216 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3217 #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4) 3218 3219 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3220 #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4) 3221 3222 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3223 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4) 3224 3225 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3226 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4) 3227 3228 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3229 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4) 3230 3231 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3232 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4) 3233 3234 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3235 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4) 3236 3237 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3238 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4) 3239 3240 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3241 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4) 3242 3243 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3244 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4) 3245 3246 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3247 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4) 3248 3249 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3250 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4) 3251 3252 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3253 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4) 3254 3255 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3256 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4) 3257 3258 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3259 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4) 3260 3261 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3262 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4) 3263 3264 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3265 #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4) 3266 3267 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3268 #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4) 3269 3270 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3271 #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4) 3272 3273 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3274 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4) 3275 3276 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3277 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4) 3278 3279 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3280 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4) 3281 3282 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3283 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3284 t, 13, 60, 0, 1, 312, 184, 0, 1, 4) 3285 3286 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3287 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 3288 t, 13, 60, 0, 1, 312, 188, 0, 1, 4) 3289 3290 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3291 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4) 3292 3293 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3294 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4) 3295 3296 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3297 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4) 3298 3299 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3300 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4) 3301 3302 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3303 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4) 3304 3305 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 3306 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4) 3307 3308 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 3309 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4) 3310 3311 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 3312 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4) 3313 3314 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 3315 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4) 3316 3317 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 3318 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4) 3319 3320 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 3321 #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4) 3322 3323 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 3324 #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4) 3325 3326 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 3327 #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4) 3328 3329 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 3330 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4) 3331 3332 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 3333 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4) 3334 3335 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 3336 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4) 3337 3338 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 3339 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4) 3340 3341 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 3342 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4) 3343 3344 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 3345 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4) 3346 3347 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 3348 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4) 3349 3350 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 3351 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4) 3352 3353 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 3354 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4) 3355 3356 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 3357 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4) 3358 3359 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 3360 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4) 3361 3362 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 3363 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4) 3364 3365 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 3366 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4) 3367 3368 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 3369 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4) 3370 3371 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 3372 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4) 3373 3374 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 3375 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4) 3376 3377 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 3378 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4) 3379 3380 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 3381 #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4) 3382 3383 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 3384 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4) 3385 3386 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 3387 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 3388 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 3389 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 3390 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 3391 3392 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 3393 #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4) 3394 3395 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 3396 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4) 3397 3398 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3399 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 3400 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 3401 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 3402 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 3403 3404 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 3405 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4) 3406 3407 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 3408 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4) 3409 3410 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 3411 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 3412 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 3413 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 3414 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 3415 3416 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 3417 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4) 3418 3419 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 3420 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4) 3421 3422 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 3423 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 3424 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 3425 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 3426 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 3427 3428 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 3429 #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4) 3430 3431 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 3432 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4) 3433 3434 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3435 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 3436 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 3437 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 3438 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 3439 3440 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 3441 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4) 3442 3443 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 3444 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4) 3445 3446 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3447 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 3448 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 3449 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 3450 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 3451 3452 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 3453 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4) 3454 3455 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 3456 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4) 3457 3458 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 3459 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 3460 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 3461 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 3462 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 3463 3464 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 3465 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4) 3466 3467 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 3468 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4) 3469 3470 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 3471 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 3472 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 3473 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 3474 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 3475 3476 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3477 #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4) 3478 3479 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 3480 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 3481 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3482 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 3483 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 3484 3485 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 3486 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 3487 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3488 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 3489 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3490 3491 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 3492 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 3493 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3494 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 3495 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 3496 3497 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 3498 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 3499 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3500 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 3501 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 3502 3503 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 3504 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 3505 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 3506 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 3507 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 3508 3509 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3510 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3511 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 3512 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3513 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 3514 3515 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3516 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3517 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 3518 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3519 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 3520 3521 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3522 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3523 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 3524 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3525 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 3526 3527 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3528 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3529 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 3530 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3531 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 3532 3533 /* DSM:RAM_CTRL:RAM_INIT */ 3534 #define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 3535 3536 #define DSM_RAM_INIT_RAM_INIT BIT(1) 3537 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ 3538 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) 3539 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ 3540 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) 3541 3542 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) 3543 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 3544 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) 3545 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 3546 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 3547 3548 /* DSM:CFG:BUF_CFG */ 3549 #define DSM_BUF_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) 3550 3551 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 3552 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ 3553 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) 3554 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ 3555 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) 3556 3557 #define DSM_BUF_CFG_AGING_ENA BIT(12) 3558 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ 3559 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) 3560 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ 3561 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) 3562 3563 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) 3564 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ 3565 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 3566 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ 3567 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 3568 3569 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) 3570 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ 3571 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 3572 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 3573 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 3574 3575 /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 3576 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) 3577 3578 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 3579 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ 3580 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 3581 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ 3582 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 3583 3584 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8) 3585 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ 3586 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 3587 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ 3588 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 3589 3590 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1) 3591 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ 3592 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 3593 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ 3594 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 3595 3596 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0) 3597 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ 3598 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 3599 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 3600 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 3601 3602 /* DSM:CFG:RX_PAUSE_CFG */ 3603 #define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) 3604 3605 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 3606 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ 3607 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 3608 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ 3609 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 3610 3611 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0) 3612 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ 3613 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 3614 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 3615 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 3616 3617 /* DSM:CFG:MAC_CFG */ 3618 #define DSM_MAC_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) 3619 3620 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 3621 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ 3622 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x) 3623 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ 3624 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x) 3625 3626 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2) 3627 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ 3628 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 3629 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ 3630 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 3631 3632 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1) 3633 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ 3634 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 3635 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ 3636 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 3637 3638 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0) 3639 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ 3640 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 3641 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 3642 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 3643 3644 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 3645 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) 3646 3647 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 3648 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ 3649 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 3650 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 3651 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 3652 3653 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 3654 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) 3655 3656 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 3657 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ 3658 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 3659 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 3660 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 3661 3662 /* DSM:CFG:TAXI_CAL_CFG */ 3663 #define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) 3664 3665 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 3666 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ 3667 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x) 3668 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ 3669 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x) 3670 3671 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9) 3672 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ 3673 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 3674 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ 3675 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 3676 3677 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5) 3678 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ 3679 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 3680 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ 3681 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 3682 3683 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1) 3684 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ 3685 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 3686 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ 3687 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 3688 3689 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0) 3690 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ 3691 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 3692 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 3693 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 3694 3695 /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 3696 #define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL, 0, 1, 149504, g, 138, 8, 0, r, 2, 4) 3697 3698 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) 3699 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ 3700 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 3701 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\ 3702 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 3703 3704 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2) 3705 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\ 3706 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 3707 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\ 3708 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 3709 3710 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1) 3711 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 3712 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 3713 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 3714 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 3715 3716 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA BIT(0) 3717 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\ 3718 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 3719 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ 3720 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 3721 3722 /* EACL:CNT_TBL:ES2_CNT */ 3723 #define EACL_ES2_CNT(g) __REG(TARGET_EACL, 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4) 3724 3725 /* EACL:POL_CFG:POL_EACL_CFG */ 3726 #define EACL_POL_EACL_CFG __REG(TARGET_EACL, 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) 3727 3728 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 3729 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ 3730 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 3731 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ 3732 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 3733 3734 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4) 3735 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ 3736 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 3737 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ 3738 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 3739 3740 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3) 3741 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ 3742 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 3743 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ 3744 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 3745 3746 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2) 3747 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ 3748 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 3749 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ 3750 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 3751 3752 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1) 3753 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ 3754 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 3755 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ 3756 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 3757 3758 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0) 3759 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ 3760 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 3761 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 3762 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 3763 3764 /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 3765 #define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL, 0, 1, 118696, 0, 1, 8, 0, r, 2, 4) 3766 3767 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 3768 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 3769 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 3770 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 3771 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 3772 3773 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6) 3774 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 3775 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 3776 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 3777 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 3778 3779 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5) 3780 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 3781 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 3782 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 3783 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 3784 3785 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4) 3786 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 3787 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 3788 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 3789 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 3790 3791 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3) 3792 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 3793 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 3794 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 3795 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 3796 3797 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2) 3798 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 3799 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 3800 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 3801 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 3802 3803 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1) 3804 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 3805 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 3806 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 3807 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 3808 3809 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 3810 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 3811 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 3812 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 3813 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 3814 3815 /* EACL:RAM_CTRL:RAM_INIT */ 3816 #define EACL_RAM_INIT __REG(TARGET_EACL, 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) 3817 3818 #define EACL_RAM_INIT_RAM_INIT BIT(1) 3819 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ 3820 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x) 3821 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ 3822 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x) 3823 3824 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0) 3825 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 3826 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x) 3827 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 3828 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 3829 3830 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 3831 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 3832 3833 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 3834 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 3835 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 3836 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 3837 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 3838 3839 /* FDMA:FDMA:FDMA_CH_RELOAD */ 3840 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 3841 3842 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 3843 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 3844 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 3845 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 3846 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 3847 3848 /* FDMA:FDMA:FDMA_CH_DISABLE */ 3849 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 3850 3851 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 3852 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 3853 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 3854 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 3855 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 3856 3857 /* FDMA:FDMA:FDMA_DCB_LLP */ 3858 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 3859 3860 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 3861 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 3862 3863 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 3864 #define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 116, r, 8, 4) 3865 3866 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 3867 #define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 148, r, 8, 4) 3868 3869 /* FDMA:FDMA:FDMA_CH_CFG */ 3870 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 3871 3872 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) 3873 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 3874 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 3875 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 3876 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 3877 3878 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) 3879 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 3880 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 3881 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 3882 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 3883 3884 #define FDMA_CH_CFG_CH_INJ_PORT BIT(5) 3885 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 3886 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 3887 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 3888 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 3889 3890 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) 3891 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 3892 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 3893 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 3894 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 3895 3896 #define FDMA_CH_CFG_CH_MEM BIT(0) 3897 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 3898 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 3899 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 3900 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 3901 3902 /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 3903 #define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 256, r, 8, 4) 3904 3905 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 3906 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ 3907 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x) 3908 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 3909 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 3910 3911 /* FDMA:FDMA:FDMA_XTR_CFG */ 3912 #define FDMA_XTR_CFG __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) 3913 3914 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 3915 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ 3916 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x) 3917 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ 3918 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x) 3919 3920 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0) 3921 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ 3922 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x) 3923 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 3924 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 3925 3926 /* FDMA:FDMA:FDMA_PORT_CTRL */ 3927 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 3928 3929 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 3930 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 3931 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 3932 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 3933 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 3934 3935 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3) 3936 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ 3937 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 3938 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ 3939 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 3940 3941 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 3942 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 3943 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 3944 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 3945 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 3946 3947 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1) 3948 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ 3949 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 3950 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ 3951 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 3952 3953 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0) 3954 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ 3955 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x) 3956 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 3957 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 3958 3959 /* FDMA:FDMA:FDMA_INTR_DCB */ 3960 #define FDMA_INTR_DCB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) 3961 3962 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 3963 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ 3964 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x) 3965 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 3966 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 3967 3968 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 3969 #define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) 3970 3971 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 3972 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ 3973 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 3974 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 3975 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 3976 3977 /* FDMA:FDMA:FDMA_INTR_DB */ 3978 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 3979 3980 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 3981 #define FDMA_INTR_DB_INTR_DB_SET(x)\ 3982 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x) 3983 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 3984 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 3985 3986 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 3987 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 3988 3989 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 3990 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 3991 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 3992 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 3993 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 3994 3995 /* FDMA:FDMA:FDMA_INTR_ERR */ 3996 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 3997 3998 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 3999 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ 4000 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4001 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ 4002 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4003 4004 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0) 4005 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ 4006 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x) 4007 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 4008 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 4009 4010 /* FDMA:FDMA:FDMA_ERRORS */ 4011 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 4012 4013 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 4014 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ 4015 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x) 4016 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ 4017 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x) 4018 4019 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28) 4020 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ 4021 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x) 4022 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ 4023 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x) 4024 4025 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26) 4026 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ 4027 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4028 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ 4029 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4030 4031 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24) 4032 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ 4033 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4034 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ 4035 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4036 4037 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16) 4038 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ 4039 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x) 4040 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ 4041 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x) 4042 4043 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10) 4044 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ 4045 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x) 4046 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ 4047 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x) 4048 4049 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8) 4050 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ 4051 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4052 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ 4053 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4054 4055 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0) 4056 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ 4057 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x) 4058 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 4059 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 4060 4061 /* FDMA:FDMA:FDMA_ERRORS_2 */ 4062 #define FDMA_ERRORS_2 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) 4063 4064 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 4065 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ 4066 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4067 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 4068 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4069 4070 /* FDMA:FDMA:FDMA_CTRL */ 4071 #define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) 4072 4073 #define FDMA_CTRL_NRESET BIT(0) 4074 #define FDMA_CTRL_NRESET_SET(x)\ 4075 FIELD_PREP(FDMA_CTRL_NRESET, x) 4076 #define FDMA_CTRL_NRESET_GET(x)\ 4077 FIELD_GET(FDMA_CTRL_NRESET, x) 4078 4079 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4080 #define GCB_CHIP_ID __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) 4081 4082 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 4083 #define GCB_CHIP_ID_REV_ID_SET(x)\ 4084 FIELD_PREP(GCB_CHIP_ID_REV_ID, x) 4085 #define GCB_CHIP_ID_REV_ID_GET(x)\ 4086 FIELD_GET(GCB_CHIP_ID_REV_ID, x) 4087 4088 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12) 4089 #define GCB_CHIP_ID_PART_ID_SET(x)\ 4090 FIELD_PREP(GCB_CHIP_ID_PART_ID, x) 4091 #define GCB_CHIP_ID_PART_ID_GET(x)\ 4092 FIELD_GET(GCB_CHIP_ID_PART_ID, x) 4093 4094 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1) 4095 #define GCB_CHIP_ID_MFG_ID_SET(x)\ 4096 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x) 4097 #define GCB_CHIP_ID_MFG_ID_GET(x)\ 4098 FIELD_GET(GCB_CHIP_ID_MFG_ID, x) 4099 4100 #define GCB_CHIP_ID_ONE BIT(0) 4101 #define GCB_CHIP_ID_ONE_SET(x)\ 4102 FIELD_PREP(GCB_CHIP_ID_ONE, x) 4103 #define GCB_CHIP_ID_ONE_GET(x)\ 4104 FIELD_GET(GCB_CHIP_ID_ONE, x) 4105 4106 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4107 #define GCB_SOFT_RST __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) 4108 4109 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 4110 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 4111 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4112 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ 4113 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4114 4115 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1) 4116 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ 4117 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x) 4118 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ 4119 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x) 4120 4121 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0) 4122 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ 4123 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4124 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 4125 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4126 4127 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 4128 #define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) 4129 4130 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 4131 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ 4132 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4133 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ 4134 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4135 4136 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0) 4137 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ 4138 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4139 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 4140 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4141 4142 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 4143 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 24, r, 65, 4) 4144 4145 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) 4146 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 4147 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4148 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 4149 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4150 4151 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 4152 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB, 0, 1, 876, g, 3, 280, 20, 0, 1, 4) 4153 4154 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 4155 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ 4156 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4157 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ 4158 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4159 4160 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0) 4161 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ 4162 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4163 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 4164 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4165 4166 /* HSCH:HSCH_CFG:CIR_CFG */ 4167 #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) 4168 4169 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 4170 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ 4171 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x) 4172 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ 4173 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x) 4174 4175 #define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0) 4176 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ 4177 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x) 4178 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 4179 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 4180 4181 /* HSCH:HSCH_CFG:EIR_CFG */ 4182 #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) 4183 4184 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 4185 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ 4186 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x) 4187 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ 4188 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x) 4189 4190 #define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0) 4191 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ 4192 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x) 4193 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 4194 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 4195 4196 /* HSCH:HSCH_CFG:SE_CFG */ 4197 #define HSCH_SE_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) 4198 4199 #define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) 4200 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 4201 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) 4202 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 4203 FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) 4204 4205 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 4206 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ 4207 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x) 4208 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ 4209 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x) 4210 4211 #define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3) 4212 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ 4213 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x) 4214 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ 4215 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x) 4216 4217 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1) 4218 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ 4219 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 4220 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ 4221 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 4222 4223 #define HSCH_SE_CFG_SE_STOP BIT(0) 4224 #define HSCH_SE_CFG_SE_STOP_SET(x)\ 4225 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x) 4226 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 4227 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 4228 4229 /* HSCH:HSCH_CFG:SE_CONNECT */ 4230 #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) 4231 4232 #define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) 4233 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 4234 FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4235 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 4236 FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 4237 4238 /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 4239 #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) 4240 4241 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 4242 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ 4243 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 4244 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 4245 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 4246 4247 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) 4248 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 4249 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4250 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 4251 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 4252 4253 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 4254 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ 4255 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 4256 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ 4257 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 4258 4259 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1) 4260 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ 4261 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 4262 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ 4263 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 4264 4265 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 4266 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ 4267 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 4268 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 4269 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 4270 4271 /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 4272 #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH, 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) 4273 4274 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 4275 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ 4276 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) 4277 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ 4278 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) 4279 4280 #define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) 4281 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ 4282 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 4283 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 4284 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 4285 4286 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 4287 #define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) 4288 4289 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) 4290 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 4291 FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4292 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 4293 FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 4294 4295 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 4296 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ 4297 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 4298 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ 4299 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 4300 4301 #define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0) 4302 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ 4303 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 4304 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 4305 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 4306 4307 /* HSCH:HSCH_MISC:SYS_CLK_PER */ 4308 #define HSCH_SYS_CLK_PER __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) 4309 4310 #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) 4311 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ 4312 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x) 4313 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ 4314 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) 4315 4316 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 4317 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 0, r, 4, 4) 4318 4319 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 4320 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ 4321 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 4322 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 4323 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 4324 4325 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 4326 #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 16, r, 4, 4) 4327 4328 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) 4329 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 4330 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4331 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 4332 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 4333 4334 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 4335 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ 4336 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 4337 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 4338 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 4339 4340 /* HSCH:SYSTEM:FLUSH_CTRL */ 4341 #define HSCH_FLUSH_CTRL __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) 4342 4343 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 4344 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ 4345 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 4346 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ 4347 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 4348 4349 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26) 4350 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ 4351 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 4352 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ 4353 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 4354 4355 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25) 4356 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ 4357 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x) 4358 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 4359 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 4360 4361 #define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) 4362 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 4363 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4364 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 4365 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 4366 4367 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 4368 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ 4369 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 4370 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ 4371 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 4372 4373 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16) 4374 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ 4375 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x) 4376 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 4377 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 4378 4379 #define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) 4380 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 4381 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4382 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 4383 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 4384 4385 /* HSCH:SYSTEM:PORT_MODE */ 4386 #define HSCH_PORT_MODE(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) 4387 4388 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 4389 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ 4390 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x) 4391 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ 4392 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x) 4393 4394 #define HSCH_PORT_MODE_AGE_DIS BIT(3) 4395 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ 4396 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x) 4397 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ 4398 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x) 4399 4400 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2) 4401 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ 4402 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x) 4403 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ 4404 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x) 4405 4406 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1) 4407 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ 4408 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 4409 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ 4410 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 4411 4412 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0) 4413 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ 4414 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 4415 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 4416 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 4417 4418 /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 4419 #define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) 4420 4421 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 4422 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ 4423 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 4424 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 4425 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 4426 4427 /* HSCH:MMGT:RESET_CFG */ 4428 #define HSCH_RESET_CFG __REG(TARGET_HSCH, 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) 4429 4430 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 4431 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ 4432 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x) 4433 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 4434 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 4435 4436 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 4437 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH, 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) 4438 4439 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 4440 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ 4441 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 4442 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 4443 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 4444 4445 /* LRN:COMMON:COMMON_ACCESS_CTRL */ 4446 #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 4447 4448 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 4449 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ 4450 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 4451 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ 4452 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 4453 4454 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19) 4455 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ 4456 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 4457 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 4458 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 4459 4460 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) 4461 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 4462 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4463 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 4464 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 4465 4466 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 4467 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ 4468 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 4469 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ 4470 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 4471 4472 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0) 4473 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ 4474 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 4475 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 4476 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 4477 4478 /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 4479 #define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 4480 4481 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 4482 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ 4483 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 4484 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ 4485 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 4486 4487 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0) 4488 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ 4489 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 4490 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 4491 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 4492 4493 /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 4494 #define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 4495 4496 /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 4497 #define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 4498 4499 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 4500 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ 4501 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 4502 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ 4503 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 4504 4505 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27) 4506 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ 4507 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 4508 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ 4509 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 4510 4511 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24) 4512 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ 4513 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 4514 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ 4515 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 4516 4517 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23) 4518 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ 4519 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 4520 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ 4521 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 4522 4523 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22) 4524 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ 4525 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 4526 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ 4527 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 4528 4529 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21) 4530 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ 4531 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 4532 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ 4533 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 4534 4535 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19) 4536 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ 4537 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 4538 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ 4539 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 4540 4541 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17) 4542 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ 4543 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 4544 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ 4545 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 4546 4547 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16) 4548 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ 4549 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 4550 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ 4551 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 4552 4553 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15) 4554 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ 4555 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 4556 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ 4557 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 4558 4559 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12) 4560 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ 4561 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 4562 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ 4563 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 4564 4565 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0) 4566 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ 4567 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 4568 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 4569 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 4570 4571 /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 4572 #define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 4573 4574 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) 4575 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 4576 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 4577 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 4578 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 4579 4580 /* LRN:COMMON:SCAN_NEXT_CFG */ 4581 #define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 4582 4583 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 4584 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ 4585 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 4586 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ 4587 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 4588 4589 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17) 4590 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ 4591 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 4592 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ 4593 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 4594 4595 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15) 4596 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ 4597 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 4598 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ 4599 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 4600 4601 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14) 4602 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ 4603 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 4604 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ 4605 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 4606 4607 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13) 4608 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ 4609 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 4610 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ 4611 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 4612 4613 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12) 4614 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ 4615 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 4616 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ 4617 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 4618 4619 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11) 4620 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ 4621 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 4622 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ 4623 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 4624 4625 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10) 4626 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ 4627 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 4628 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ 4629 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 4630 4631 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9) 4632 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ 4633 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 4634 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ 4635 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 4636 4637 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8) 4638 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ 4639 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 4640 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ 4641 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 4642 4643 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7) 4644 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ 4645 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 4646 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ 4647 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 4648 4649 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3) 4650 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ 4651 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 4652 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ 4653 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 4654 4655 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2) 4656 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ 4657 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 4658 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ 4659 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 4660 4661 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1) 4662 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ 4663 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 4664 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ 4665 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 4666 4667 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0) 4668 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ 4669 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 4670 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 4671 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 4672 4673 /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 4674 #define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 4675 4676 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 4677 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ 4678 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 4679 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ 4680 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 4681 4682 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0) 4683 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ 4684 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 4685 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 4686 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 4687 4688 /* LRN:COMMON:AUTOAGE_CFG */ 4689 #define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 4690 4691 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 4692 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ 4693 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 4694 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ 4695 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 4696 4697 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0) 4698 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ 4699 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 4700 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 4701 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 4702 4703 /* LRN:COMMON:AUTOAGE_CFG_1 */ 4704 #define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 4705 4706 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 4707 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ 4708 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 4709 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ 4710 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 4711 4712 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15) 4713 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ 4714 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 4715 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ 4716 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 4717 4718 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7) 4719 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ 4720 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 4721 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ 4722 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 4723 4724 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6) 4725 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ 4726 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 4727 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ 4728 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 4729 4730 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2) 4731 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ 4732 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 4733 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ 4734 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 4735 4736 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1) 4737 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ 4738 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 4739 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ 4740 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 4741 4742 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0) 4743 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ 4744 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 4745 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 4746 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 4747 4748 /* LRN:COMMON:AUTOAGE_CFG_2 */ 4749 #define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 4750 4751 #define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) 4752 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 4753 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 4754 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 4755 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 4756 4757 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 4758 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ 4759 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 4760 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 4761 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 4762 4763 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 4764 #define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 4765 4766 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 4767 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ 4768 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 4769 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ 4770 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 4771 4772 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8) 4773 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ 4774 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x) 4775 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ 4776 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x) 4777 4778 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16) 4779 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ 4780 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 4781 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ 4782 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 4783 4784 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19) 4785 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ 4786 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 4787 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ 4788 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 4789 4790 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20) 4791 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ 4792 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x) 4793 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ 4794 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x) 4795 4796 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22) 4797 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ 4798 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 4799 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ 4800 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 4801 4802 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23) 4803 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ 4804 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 4805 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ 4806 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 4807 4808 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28) 4809 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ 4810 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 4811 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ 4812 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 4813 4814 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29) 4815 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ 4816 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 4817 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ 4818 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 4819 4820 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31) 4821 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ 4822 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 4823 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 4824 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 4825 4826 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 4827 #define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 4828 4829 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 4830 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ 4831 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 4832 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ 4833 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 4834 4835 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16) 4836 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ 4837 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 4838 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 4839 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 4840 4841 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 4842 #define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 4843 4844 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 4845 #define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 4846 4847 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 4848 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ 4849 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 4850 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ 4851 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 4852 4853 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16) 4854 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ 4855 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 4856 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 4857 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 4858 4859 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 4860 #define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 4861 4862 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 4863 #define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 4864 4865 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 4866 #define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 4867 4868 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 4869 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ 4870 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 4871 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ 4872 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 4873 4874 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2) 4875 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ 4876 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 4877 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 4878 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 4879 4880 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 4881 #define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 0, 0, 1, 4) 4882 4883 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 4884 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ 4885 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x) 4886 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ 4887 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x) 4888 4889 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 4890 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 4891 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4892 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 4893 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4894 4895 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 4896 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 4897 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 4898 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 4899 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 4900 4901 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 4902 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 4903 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 4904 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 4905 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 4906 4907 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15) 4908 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 4909 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 4910 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 4911 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 4912 4913 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 4914 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 4915 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 4916 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 4917 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 4918 4919 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 4920 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 4921 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 4922 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 4923 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 4924 4925 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 4926 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 4927 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4928 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 4929 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4930 4931 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 4932 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 4933 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 4934 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 4935 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 4936 4937 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 4938 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 4939 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4940 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 4941 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4942 4943 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 4944 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 4945 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 4946 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 4947 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 4948 4949 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 4950 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 4951 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4952 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 4953 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4954 4955 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 4956 #define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 4, 0, 1, 4) 4957 4958 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 4959 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 4960 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 4961 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 4962 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 4963 4964 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4) 4965 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 4966 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 4967 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 4968 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 4969 4970 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0) 4971 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 4972 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 4973 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 4974 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 4975 4976 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 4977 #define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 4978 4979 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 4980 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ 4981 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x) 4982 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ 4983 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x) 4984 4985 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 4986 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 4987 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4988 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 4989 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4990 4991 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 4992 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 4993 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 4994 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 4995 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 4996 4997 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 4998 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 4999 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5000 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5001 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5002 5003 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5004 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5005 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5006 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5007 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5008 5009 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5010 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5011 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5012 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5013 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5014 5015 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5016 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5017 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5018 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5019 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5020 5021 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5022 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5023 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5024 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5025 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5026 5027 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5028 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5029 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5030 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5031 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5032 5033 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5034 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5035 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5036 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5037 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5038 5039 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5040 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5041 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5042 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5043 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5044 5045 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5046 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5047 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5048 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5049 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5050 5051 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5052 #define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 5053 5054 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5055 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5056 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5057 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5058 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5059 5060 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4) 5061 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5062 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5063 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5064 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5065 5066 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5067 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5068 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5069 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5070 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5071 5072 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5073 #define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 0, 0, 1, 4) 5074 5075 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 5076 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5077 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5078 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5079 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5080 5081 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5082 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5083 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5084 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5085 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5086 5087 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5088 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5089 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5090 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5091 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5092 5093 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5094 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5095 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5096 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5097 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5098 5099 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5100 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5101 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5102 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5103 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5104 5105 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5106 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5107 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 5108 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5109 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 5110 5111 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5112 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5113 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 5114 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5115 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 5116 5117 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5118 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5119 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5120 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5121 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5122 5123 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5124 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5125 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 5126 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5127 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 5128 5129 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5130 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5131 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5132 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5133 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5134 5135 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5136 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5137 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 5138 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5139 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 5140 5141 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5142 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5143 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5144 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5145 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5146 5147 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5148 #define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 4, 0, 1, 4) 5149 5150 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5151 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5152 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 5153 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5154 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 5155 5156 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4) 5157 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5158 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 5159 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5160 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 5161 5162 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5163 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5164 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 5165 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5166 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 5167 5168 /* PORT_CONF:HW_CFG:DEV5G_MODES */ 5169 #define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 5170 5171 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 5172 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 5173 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 5174 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 5175 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 5176 5177 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 5178 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 5179 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 5180 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 5181 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 5182 5183 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 5184 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 5185 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 5186 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 5187 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 5188 5189 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 5190 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 5191 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 5192 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 5193 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 5194 5195 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 5196 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 5197 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 5198 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 5199 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 5200 5201 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 5202 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 5203 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 5204 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 5205 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 5206 5207 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 5208 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 5209 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 5210 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 5211 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 5212 5213 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 5214 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 5215 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 5216 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 5217 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 5218 5219 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 5220 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 5221 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 5222 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ 5223 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 5224 5225 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9) 5226 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ 5227 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 5228 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 5229 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 5230 5231 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 5232 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 5233 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 5234 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 5235 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 5236 5237 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 5238 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 5239 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 5240 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 5241 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 5242 5243 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 5244 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 5245 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 5246 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 5247 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 5248 5249 /* PORT_CONF:HW_CFG:DEV10G_MODES */ 5250 #define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 5251 5252 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 5253 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ 5254 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 5255 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 5256 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 5257 5258 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 5259 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 5260 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 5261 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 5262 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 5263 5264 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 5265 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 5266 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 5267 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 5268 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 5269 5270 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 5271 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 5272 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 5273 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 5274 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 5275 5276 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 5277 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 5278 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 5279 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 5280 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 5281 5282 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 5283 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 5284 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 5285 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 5286 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 5287 5288 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 5289 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 5290 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 5291 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 5292 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 5293 5294 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 5295 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 5296 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 5297 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 5298 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 5299 5300 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 5301 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 5302 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 5303 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 5304 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 5305 5306 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 5307 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 5308 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 5309 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 5310 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 5311 5312 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 5313 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 5314 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 5315 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 5316 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 5317 5318 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 5319 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 5320 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 5321 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 5322 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 5323 5324 /* PORT_CONF:HW_CFG:DEV25G_MODES */ 5325 #define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 5326 5327 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 5328 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ 5329 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 5330 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ 5331 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 5332 5333 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1) 5334 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ 5335 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 5336 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ 5337 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 5338 5339 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2) 5340 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ 5341 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 5342 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ 5343 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 5344 5345 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3) 5346 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ 5347 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 5348 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ 5349 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 5350 5351 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4) 5352 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ 5353 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 5354 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ 5355 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 5356 5357 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5) 5358 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ 5359 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 5360 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ 5361 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 5362 5363 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6) 5364 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ 5365 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 5366 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ 5367 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 5368 5369 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7) 5370 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ 5371 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 5372 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 5373 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 5374 5375 /* PORT_CONF:HW_CFG:QSGMII_ENA */ 5376 #define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 5377 5378 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 5379 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ 5380 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 5381 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ 5382 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 5383 5384 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1) 5385 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ 5386 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 5387 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ 5388 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 5389 5390 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2) 5391 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ 5392 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 5393 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ 5394 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 5395 5396 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3) 5397 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ 5398 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 5399 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ 5400 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 5401 5402 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4) 5403 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ 5404 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 5405 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ 5406 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 5407 5408 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5) 5409 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ 5410 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 5411 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 5412 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 5413 5414 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 5415 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 5416 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 5417 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 5418 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 5419 5420 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 5421 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 5422 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 5423 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 5424 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 5425 5426 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 5427 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 5428 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 5429 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 5430 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 5431 5432 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 5433 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 5434 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 5435 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 5436 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 5437 5438 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 5439 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 5440 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 5441 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 5442 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 5443 5444 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 5445 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 5446 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 5447 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 5448 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 5449 5450 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 5451 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 5452 5453 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 5454 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ 5455 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 5456 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ 5457 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 5458 5459 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8) 5460 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ 5461 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 5462 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ 5463 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 5464 5465 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7) 5466 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ 5467 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 5468 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ 5469 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 5470 5471 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6) 5472 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ 5473 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 5474 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ 5475 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 5476 5477 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5) 5478 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ 5479 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 5480 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ 5481 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 5482 5483 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4) 5484 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ 5485 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 5486 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ 5487 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 5488 5489 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1) 5490 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ 5491 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 5492 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 5493 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 5494 5495 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 5496 #define PTP_PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) 5497 5498 #define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) 5499 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 5500 FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) 5501 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 5502 FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) 5503 5504 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 5505 #define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) 5506 5507 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) 5508 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 5509 FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5510 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 5511 FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 5512 5513 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 5514 #define PTP_PTP_INTR_IDENT __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) 5515 5516 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) 5517 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 5518 FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5519 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 5520 FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 5521 5522 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 5523 #define PTP_PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) 5524 5525 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 5526 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ 5527 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x) 5528 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ 5529 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x) 5530 5531 #define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6) 5532 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ 5533 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x) 5534 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ 5535 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x) 5536 5537 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3) 5538 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ 5539 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 5540 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ 5541 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 5542 5543 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0) 5544 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ 5545 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 5546 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 5547 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 5548 5549 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 5550 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 0, r, 2, 4) 5551 5552 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 5553 #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 8, 0, 1, 4) 5554 5555 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 5556 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ 5557 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 5558 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 5559 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 5560 5561 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 5562 #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 12, 0, 1, 4) 5563 5564 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 5565 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ 5566 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 5567 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 5568 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 5569 5570 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 5571 #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 16, 0, 1, 4) 5572 5573 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 5574 #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 20, 0, 1, 4) 5575 5576 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 5577 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ 5578 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 5579 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 5580 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 5581 5582 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 5583 #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 24, 0, 1, 4) 5584 5585 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 5586 #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 0, 0, 1, 4) 5587 5588 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) 5589 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 5590 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 5591 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 5592 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 5593 5594 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) 5595 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 5596 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 5597 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 5598 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 5599 5600 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) 5601 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 5602 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 5603 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 5604 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 5605 5606 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) 5607 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 5608 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 5609 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 5610 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 5611 5612 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 5613 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ 5614 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 5615 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ 5616 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 5617 5618 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16) 5619 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ 5620 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 5621 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ 5622 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 5623 5624 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14) 5625 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ 5626 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 5627 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ 5628 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 5629 5630 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13) 5631 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ 5632 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 5633 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ 5634 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 5635 5636 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0) 5637 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ 5638 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 5639 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 5640 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 5641 5642 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 5643 #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 4, 0, 1, 4) 5644 5645 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 5646 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ 5647 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 5648 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 5649 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 5650 5651 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 5652 #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 8, 0, 1, 4) 5653 5654 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 5655 #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 12, 0, 1, 4) 5656 5657 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 5658 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ 5659 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 5660 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 5661 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 5662 5663 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 5664 #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 16, 0, 1, 4) 5665 5666 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 5667 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ 5668 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 5669 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 5670 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 5671 5672 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 5673 #define PTP_NTP_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 20, 0, 1, 4) 5674 5675 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 5676 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 24, 0, 1, 4) 5677 5678 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 5679 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ 5680 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 5681 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 5682 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 5683 5684 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 5685 #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 28, 0, 1, 4) 5686 5687 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 5688 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ 5689 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 5690 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 5691 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 5692 5693 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 5694 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 32, 0, 1, 4) 5695 5696 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 5697 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ 5698 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 5699 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ 5700 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 5701 5702 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0) 5703 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ 5704 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 5705 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 5706 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 5707 5708 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 5709 #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 0, 0, 1, 4) 5710 5711 #define PTP_PHAD_CTRL_PHAD_ENA BIT(7) 5712 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 5713 FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) 5714 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 5715 FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) 5716 5717 #define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) 5718 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 5719 FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) 5720 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 5721 FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) 5722 5723 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 5724 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 5725 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) 5726 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ 5727 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x) 5728 5729 #define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0) 5730 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ 5731 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x) 5732 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 5733 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 5734 5735 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 5736 #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 4, 0, 1, 4) 5737 5738 /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 5739 #define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4) 5740 5741 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 5742 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ 5743 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 5744 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ 5745 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 5746 5747 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10) 5748 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ 5749 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 5750 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ 5751 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 5752 5753 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6) 5754 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ 5755 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 5756 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ 5757 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 5758 5759 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5) 5760 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 5761 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 5762 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 5763 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 5764 5765 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4) 5766 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ 5767 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 5768 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ 5769 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 5770 5771 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3) 5772 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ 5773 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 5774 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ 5775 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 5776 5777 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2) 5778 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ 5779 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 5780 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ 5781 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 5782 5783 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1) 5784 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ 5785 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 5786 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ 5787 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 5788 5789 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0) 5790 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ 5791 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 5792 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 5793 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 5794 5795 /* QRES:RES_CTRL:RES_CFG */ 5796 #define QRES_RES_CFG(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 5797 5798 #define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) 5799 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 5800 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) 5801 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 5802 FIELD_GET(QRES_RES_CFG_WM_HIGH, x) 5803 5804 /* QRES:RES_CTRL:RES_STAT */ 5805 #define QRES_RES_STAT(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 5806 5807 #define QRES_RES_STAT_MAXUSE GENMASK(20, 0) 5808 #define QRES_RES_STAT_MAXUSE_SET(x)\ 5809 FIELD_PREP(QRES_RES_STAT_MAXUSE, x) 5810 #define QRES_RES_STAT_MAXUSE_GET(x)\ 5811 FIELD_GET(QRES_RES_STAT_MAXUSE, x) 5812 5813 /* QRES:RES_CTRL:RES_STAT_CUR */ 5814 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 5815 5816 #define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) 5817 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 5818 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) 5819 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 5820 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) 5821 5822 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 5823 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 5824 5825 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 5826 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 5827 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 5828 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 5829 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 5830 5831 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 5832 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ 5833 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 5834 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ 5835 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 5836 5837 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 5838 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 5839 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 5840 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 5841 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 5842 5843 /* DEVCPU_QS:XTR:XTR_RD */ 5844 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 5845 5846 /* DEVCPU_QS:XTR:XTR_FLUSH */ 5847 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 5848 5849 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 5850 #define QS_XTR_FLUSH_FLUSH_SET(x)\ 5851 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x) 5852 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 5853 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 5854 5855 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 5856 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 5857 5858 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 5859 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ 5860 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 5861 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 5862 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 5863 5864 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 5865 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 5866 5867 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 5868 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 5869 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 5870 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 5871 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 5872 5873 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 5874 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 5875 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 5876 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 5877 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 5878 5879 /* DEVCPU_QS:INJ:INJ_WR */ 5880 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 5881 5882 /* DEVCPU_QS:INJ:INJ_CTRL */ 5883 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 5884 5885 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 5886 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 5887 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 5888 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 5889 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 5890 5891 #define QS_INJ_CTRL_ABORT BIT(20) 5892 #define QS_INJ_CTRL_ABORT_SET(x)\ 5893 FIELD_PREP(QS_INJ_CTRL_ABORT, x) 5894 #define QS_INJ_CTRL_ABORT_GET(x)\ 5895 FIELD_GET(QS_INJ_CTRL_ABORT, x) 5896 5897 #define QS_INJ_CTRL_EOF BIT(19) 5898 #define QS_INJ_CTRL_EOF_SET(x)\ 5899 FIELD_PREP(QS_INJ_CTRL_EOF, x) 5900 #define QS_INJ_CTRL_EOF_GET(x)\ 5901 FIELD_GET(QS_INJ_CTRL_EOF, x) 5902 5903 #define QS_INJ_CTRL_SOF BIT(18) 5904 #define QS_INJ_CTRL_SOF_SET(x)\ 5905 FIELD_PREP(QS_INJ_CTRL_SOF, x) 5906 #define QS_INJ_CTRL_SOF_GET(x)\ 5907 FIELD_GET(QS_INJ_CTRL_SOF, x) 5908 5909 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 5910 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 5911 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 5912 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 5913 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 5914 5915 /* DEVCPU_QS:INJ:INJ_STATUS */ 5916 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 5917 5918 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 5919 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 5920 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 5921 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 5922 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 5923 5924 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 5925 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 5926 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 5927 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 5928 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 5929 5930 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0) 5931 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ 5932 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 5933 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 5934 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 5935 5936 /* QSYS:PAUSE_CFG:PAUSE_CFG */ 5937 #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) 5938 5939 #define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) 5940 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 5941 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) 5942 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 5943 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) 5944 5945 #define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) 5946 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 5947 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) 5948 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 5949 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) 5950 5951 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 5952 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 5953 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x) 5954 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 5955 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x) 5956 5957 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0) 5958 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ 5959 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 5960 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 5961 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 5962 5963 /* QSYS:PAUSE_CFG:ATOP */ 5964 #define QSYS_ATOP(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) 5965 5966 #define QSYS_ATOP_ATOP GENMASK(11, 0) 5967 #define QSYS_ATOP_ATOP_SET(x)\ 5968 FIELD_PREP(QSYS_ATOP_ATOP, x) 5969 #define QSYS_ATOP_ATOP_GET(x)\ 5970 FIELD_GET(QSYS_ATOP_ATOP, x) 5971 5972 /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 5973 #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) 5974 5975 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 5976 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ 5977 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 5978 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ 5979 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 5980 5981 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0) 5982 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ 5983 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 5984 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 5985 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 5986 5987 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 5988 #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) 5989 5990 #define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) 5991 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 5992 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 5993 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 5994 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 5995 5996 /* QSYS:CALCFG:CAL_AUTO */ 5997 #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) 5998 5999 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 6000 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ 6001 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x) 6002 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 6003 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 6004 6005 /* QSYS:CALCFG:CAL_CTRL */ 6006 #define QSYS_CAL_CTRL __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) 6007 6008 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 6009 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ 6010 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x) 6011 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ 6012 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x) 6013 6014 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1) 6015 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ 6016 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 6017 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ 6018 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 6019 6020 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0) 6021 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ 6022 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 6023 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 6024 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 6025 6026 /* QSYS:RAM_CTRL:RAM_INIT */ 6027 #define QSYS_RAM_INIT __REG(TARGET_QSYS, 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) 6028 6029 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 6030 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ 6031 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x) 6032 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ 6033 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x) 6034 6035 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 6036 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6037 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 6038 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6039 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 6040 6041 /* REW:COMMON:OWN_UPSID */ 6042 #define REW_OWN_UPSID(r) __REG(TARGET_REW, 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) 6043 6044 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 6045 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ 6046 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x) 6047 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 6048 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 6049 6050 /* REW:PORT:PORT_VLAN_CFG */ 6051 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) 6052 6053 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 6054 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ 6055 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x) 6056 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ 6057 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x) 6058 6059 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12) 6060 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ 6061 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x) 6062 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ 6063 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x) 6064 6065 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 6066 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 6067 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 6068 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 6069 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 6070 6071 /* REW:PORT:PCP_MAP_DE0 */ 6072 #define REW_PCP_MAP_DE0(g, r) \ 6073 __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 4, r, 8, 4) 6074 6075 #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) 6076 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ 6077 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x) 6078 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ 6079 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) 6080 6081 /* REW:PORT:PCP_MAP_DE1 */ 6082 #define REW_PCP_MAP_DE1(g, r) \ 6083 __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 36, r, 8, 4) 6084 6085 #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) 6086 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ 6087 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x) 6088 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ 6089 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) 6090 6091 /* REW:PORT:DEI_MAP_DE0 */ 6092 #define REW_DEI_MAP_DE0(g, r) \ 6093 __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 68, r, 8, 4) 6094 6095 #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) 6096 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ 6097 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x) 6098 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ 6099 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) 6100 6101 /* REW:PORT:DEI_MAP_DE1 */ 6102 #define REW_DEI_MAP_DE1(g, r) \ 6103 __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 100, r, 8, 4) 6104 6105 #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) 6106 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ 6107 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x) 6108 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ 6109 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) 6110 6111 /* REW:PORT:DSCP_MAP */ 6112 #define REW_DSCP_MAP(g) \ 6113 __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 136, 0, 1, 4) 6114 6115 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) 6116 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ 6117 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 6118 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\ 6119 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 6120 6121 #define REW_DSCP_MAP_DSCP_REMAP_ENA BIT(0) 6122 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\ 6123 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 6124 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ 6125 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 6126 6127 /* REW:PORT:TAG_CTRL */ 6128 #define REW_TAG_CTRL(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) 6129 6130 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 6131 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ 6132 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 6133 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ 6134 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 6135 6136 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11) 6137 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ 6138 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x) 6139 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ 6140 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x) 6141 6142 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8) 6143 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ 6144 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x) 6145 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ 6146 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x) 6147 6148 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6) 6149 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ 6150 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x) 6151 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ 6152 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x) 6153 6154 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3) 6155 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ 6156 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x) 6157 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ 6158 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x) 6159 6160 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0) 6161 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ 6162 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x) 6163 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 6164 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 6165 6166 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 6167 #define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 6168 6169 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 6170 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 6171 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6172 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 6173 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 6174 6175 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 6176 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 6177 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 6178 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 6179 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 6180 6181 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 6182 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 6183 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 6184 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 6185 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 6186 6187 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 6188 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 6189 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 6190 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 6191 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 6192 6193 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 6194 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 6195 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6196 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 6197 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 6198 6199 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 6200 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 6201 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6202 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 6203 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 6204 6205 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 6206 #define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 6207 6208 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 6209 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 6210 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 6211 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 6212 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 6213 6214 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 6215 #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 6216 6217 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 6218 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ 6219 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 6220 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 6221 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 6222 6223 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 6224 #define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 6225 6226 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 6227 #define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 6228 6229 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 6230 #define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 6231 6232 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 6233 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ 6234 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 6235 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 6236 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 6237 6238 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 6239 #define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 6240 6241 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 6242 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ 6243 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 6244 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ 6245 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 6246 6247 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0) 6248 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ 6249 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 6250 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 6251 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 6252 6253 /* REW:RAM_CTRL:RAM_INIT */ 6254 #define REW_RAM_INIT __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) 6255 6256 #define REW_RAM_INIT_RAM_INIT BIT(1) 6257 #define REW_RAM_INIT_RAM_INIT_SET(x)\ 6258 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x) 6259 #define REW_RAM_INIT_RAM_INIT_GET(x)\ 6260 FIELD_GET(REW_RAM_INIT_RAM_INIT, x) 6261 6262 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0) 6263 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6264 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x) 6265 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6266 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 6267 6268 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 6269 #define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 6270 6271 #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) 6272 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ 6273 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x) 6274 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\ 6275 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x) 6276 6277 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS BIT(21) 6278 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 6279 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 6280 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 6281 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 6282 6283 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS BIT(20) 6284 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\ 6285 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 6286 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\ 6287 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 6288 6289 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS BIT(19) 6290 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\ 6291 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 6292 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\ 6293 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 6294 6295 #define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3) 6296 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\ 6297 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x) 6298 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\ 6299 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x) 6300 6301 #define VCAP_ES2_CTRL_UPDATE_SHOT BIT(2) 6302 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\ 6303 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x) 6304 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\ 6305 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x) 6306 6307 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1) 6308 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\ 6309 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x) 6310 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\ 6311 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x) 6312 6313 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN BIT(0) 6314 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\ 6315 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 6316 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ 6317 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 6318 6319 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 6320 #define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 6321 6322 #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) 6323 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ 6324 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x) 6325 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\ 6326 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x) 6327 6328 #define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0) 6329 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\ 6330 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x) 6331 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ 6332 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) 6333 6334 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 6335 #define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 6336 6337 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 6338 #define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 6339 6340 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 6341 #define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 6342 6343 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 6344 #define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 6345 6346 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 6347 #define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 6348 6349 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 6350 #define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 6351 6352 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 6353 #define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 6354 6355 #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) 6356 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ 6357 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x) 6358 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ 6359 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) 6360 6361 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 6362 #define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 6363 6364 #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) 6365 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ 6366 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x) 6367 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ 6368 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) 6369 6370 /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 6371 #define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 6372 6373 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 6374 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 6375 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 6376 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 6377 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 6378 6379 /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 6380 #define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 6381 6382 /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 6383 #define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 6384 6385 /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 6386 #define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 6387 6388 /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 6389 #define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 6390 6391 /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 6392 #define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 6393 6394 /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 6395 #define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 6396 6397 /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 6398 #define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 6399 6400 /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 6401 #define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 6402 6403 /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 6404 #define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 6405 6406 /* VCAP_ES2:VCAP_CONST:IF_CNT */ 6407 #define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 6408 6409 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 6410 #define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 6411 6412 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 6413 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ 6414 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x) 6415 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ 6416 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x) 6417 6418 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21) 6419 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 6420 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 6421 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 6422 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 6423 6424 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20) 6425 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ 6426 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 6427 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ 6428 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 6429 6430 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19) 6431 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ 6432 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 6433 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ 6434 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 6435 6436 #define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3) 6437 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ 6438 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 6439 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ 6440 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 6441 6442 #define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2) 6443 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ 6444 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 6445 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ 6446 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 6447 6448 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1) 6449 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ 6450 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 6451 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ 6452 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 6453 6454 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0) 6455 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ 6456 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 6457 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 6458 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 6459 6460 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 6461 #define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 6462 6463 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 6464 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ 6465 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x) 6466 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ 6467 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x) 6468 6469 #define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0) 6470 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ 6471 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x) 6472 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 6473 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 6474 6475 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 6476 #define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 6477 6478 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 6479 #define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 6480 6481 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 6482 #define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 6483 6484 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 6485 #define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 6486 6487 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 6488 #define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 6489 6490 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 6491 #define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 6492 6493 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 6494 #define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 6495 6496 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 6497 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ 6498 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x) 6499 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 6500 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 6501 6502 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 6503 #define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 6504 6505 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 6506 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ 6507 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x) 6508 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 6509 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 6510 6511 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 6512 #define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 6513 6514 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 6515 #define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 6516 6517 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 6518 #define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 6519 6520 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 6521 #define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 6522 6523 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 6524 #define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 6525 6526 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 6527 #define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 6528 6529 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 6530 #define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 6531 6532 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 6533 #define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 6534 6535 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 6536 #define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 6537 6538 /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 6539 #define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 6540 6541 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 6542 #define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 6543 6544 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 6545 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ 6546 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 6547 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ 6548 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 6549 6550 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0) 6551 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6552 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 6553 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6554 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 6555 6556 /* VOP:RAM_CTRL:RAM_INIT */ 6557 #define VOP_RAM_INIT __REG(TARGET_VOP, 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) 6558 6559 #define VOP_RAM_INIT_RAM_INIT BIT(1) 6560 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ 6561 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x) 6562 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ 6563 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x) 6564 6565 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0) 6566 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 6567 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x) 6568 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 6569 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 6570 6571 /* XQS:SYSTEM:STAT_CFG */ 6572 #define XQS_STAT_CFG __REG(TARGET_XQS, 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) 6573 6574 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 6575 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ 6576 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 6577 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 6578 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 6579 6580 #define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) 6581 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 6582 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) 6583 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 6584 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) 6585 6586 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 6587 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ 6588 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 6589 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ 6590 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 6591 6592 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0) 6593 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ 6594 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x) 6595 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 6596 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 6597 6598 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 6599 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) 6600 6601 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) 6602 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 6603 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 6604 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 6605 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 6606 6607 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 6608 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) 6609 6610 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) 6611 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 6612 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 6613 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 6614 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 6615 6616 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 6617 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) 6618 6619 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) 6620 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 6621 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 6622 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 6623 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 6624 6625 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 6626 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) 6627 6628 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) 6629 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 6630 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 6631 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 6632 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 6633 6634 /* XQS:STAT:CNT */ 6635 #define XQS_CNT(g) __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 6636 6637 #endif /* _SPARX5_MAIN_REGS_H_ */ 6638