1 /* SPDX-License-Identifier: GPL-2.0+ 2 * Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2022-09-28 11:17:02 +0200. 8 * Commit ID: 385c8a11d71a9f6a60368d3a3cb648fa257b479a 9 */ 10 11 #ifndef _SPARX5_MAIN_REGS_H_ 12 #define _SPARX5_MAIN_REGS_H_ 13 14 #include <linux/bitfield.h> 15 #include <linux/types.h> 16 #include <linux/bug.h> 17 18 enum sparx5_target { 19 TARGET_ANA_AC = 1, 20 TARGET_ANA_ACL = 2, 21 TARGET_ANA_AC_POL = 4, 22 TARGET_ANA_CL = 6, 23 TARGET_ANA_L2 = 7, 24 TARGET_ANA_L3 = 8, 25 TARGET_ASM = 9, 26 TARGET_CLKGEN = 11, 27 TARGET_CPU = 12, 28 TARGET_DEV10G = 17, 29 TARGET_DEV25G = 29, 30 TARGET_DEV2G5 = 37, 31 TARGET_DEV5G = 102, 32 TARGET_DSM = 115, 33 TARGET_EACL = 116, 34 TARGET_FDMA = 117, 35 TARGET_GCB = 118, 36 TARGET_HSCH = 119, 37 TARGET_LRN = 122, 38 TARGET_PCEP = 129, 39 TARGET_PCS10G_BR = 132, 40 TARGET_PCS25G_BR = 144, 41 TARGET_PCS5G_BR = 160, 42 TARGET_PORT_CONF = 173, 43 TARGET_PTP = 174, 44 TARGET_QFWD = 175, 45 TARGET_QRES = 176, 46 TARGET_QS = 177, 47 TARGET_QSYS = 178, 48 TARGET_REW = 179, 49 TARGET_VCAP_SUPER = 326, 50 TARGET_VOP = 327, 51 TARGET_XQS = 331, 52 NUM_TARGETS = 332 53 }; 54 55 #define __REG(...) __VA_ARGS__ 56 57 /* ANA_AC:RAM_CTRL:RAM_INIT */ 58 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) 59 60 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 61 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ 62 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 63 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ 64 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 65 66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) 67 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 68 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 69 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 70 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 71 72 /* ANA_AC:PS_COMMON:OWN_UPSID */ 73 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) 74 75 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 76 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ 77 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 78 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 79 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 80 81 /* ANA_AC:SRC:SRC_CFG */ 82 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) 83 84 /* ANA_AC:SRC:SRC_CFG1 */ 85 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) 86 87 /* ANA_AC:SRC:SRC_CFG2 */ 88 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) 89 90 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 91 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ 92 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 93 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 94 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 95 96 /* ANA_AC:PGID:PGID_CFG */ 97 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) 98 99 /* ANA_AC:PGID:PGID_CFG1 */ 100 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) 101 102 /* ANA_AC:PGID:PGID_CFG2 */ 103 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) 104 105 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 106 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ 107 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 108 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 109 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 110 111 /* ANA_AC:PGID:PGID_MISC_CFG */ 112 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) 113 114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 115 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ 116 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 117 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ 118 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 119 120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) 121 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ 122 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 123 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ 124 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 125 126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) 127 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ 128 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 129 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 130 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 131 132 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 133 #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) 134 135 #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) 136 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 137 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) 138 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 139 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) 140 141 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 142 #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) 143 144 #define ANA_AC_STAT_RESET_RESET BIT(0) 145 #define ANA_AC_STAT_RESET_RESET_SET(x)\ 146 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) 147 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 148 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 149 150 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 151 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4) 152 153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 154 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ 155 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 156 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ 157 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 158 159 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) 160 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ 161 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 162 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ 163 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 164 165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) 166 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ 167 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 168 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 169 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 170 171 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 172 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4) 173 174 /* ANA_ACL:COMMON:VCAP_S2_CFG */ 175 #define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) 176 177 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 178 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ 179 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 180 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ 181 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 182 183 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26) 184 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ 185 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 186 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ 187 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 188 189 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24) 190 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ 191 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 192 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ 193 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 194 195 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22) 196 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ 197 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 198 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ 199 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 200 201 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20) 202 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ 203 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 204 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ 205 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 206 207 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18) 208 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ 209 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 210 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ 211 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 212 213 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16) 214 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ 215 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 216 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ 217 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 218 219 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14) 220 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ 221 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 222 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ 223 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 224 225 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12) 226 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ 227 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 228 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ 229 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 230 231 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10) 232 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ 233 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 234 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ 235 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 236 237 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8) 238 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ 239 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 240 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ 241 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 242 243 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6) 244 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ 245 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 246 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ 247 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 248 249 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4) 250 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ 251 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 252 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ 253 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 254 255 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0) 256 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ 257 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 258 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 259 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 260 261 /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 262 #define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) 263 264 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 265 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ 266 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 267 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ 268 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 269 270 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10) 271 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ 272 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 273 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ 274 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 275 276 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2) 277 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ 278 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 279 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ 280 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 281 282 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1) 283 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ 284 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 285 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ 286 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 287 288 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0) 289 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ 290 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 291 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 292 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 293 294 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 295 #define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) 296 297 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 298 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ 299 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 300 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ 301 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 302 303 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0) 304 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ 305 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 306 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 307 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 308 309 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 310 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) 311 312 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 313 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ 314 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 315 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ 316 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 317 318 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4) 319 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ 320 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 321 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ 322 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 323 324 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0) 325 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ 326 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 327 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 328 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 329 330 /* ANA_ACL:COMMON:OWN_UPSID */ 331 #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) 332 333 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 334 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ 335 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 336 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 337 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 338 339 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 340 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL, 0, 1, 34200, g, 134, 16, 0, r, 4, 4) 341 342 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 343 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ 344 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 345 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ 346 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 347 348 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12) 349 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ 350 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 351 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ 352 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 353 354 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10) 355 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ 356 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 357 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ 358 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 359 360 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8) 361 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ 362 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 363 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ 364 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 365 366 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6) 367 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ 368 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 369 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ 370 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 371 372 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3) 373 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ 374 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 375 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ 376 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 377 378 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1) 379 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ 380 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 381 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ 382 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 383 384 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0) 385 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 386 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 387 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 388 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 389 390 /* ANA_ACL:CNT_A:CNT_A */ 391 #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL, 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) 392 393 /* ANA_ACL:CNT_B:CNT_B */ 394 #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL, 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) 395 396 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 397 #define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL, 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) 398 399 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 400 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ 401 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 402 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ 403 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 404 405 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16) 406 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ 407 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 408 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ 409 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 410 411 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15) 412 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ 413 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 414 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ 415 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 416 417 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14) 418 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ 419 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 420 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ 421 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 422 423 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13) 424 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ 425 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 426 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ 427 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 428 429 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12) 430 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ 431 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 432 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ 433 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 434 435 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11) 436 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ 437 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 438 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ 439 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 440 441 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10) 442 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 443 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 444 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 445 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 446 447 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9) 448 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 449 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 450 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 451 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 452 453 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8) 454 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ 455 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 456 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ 457 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 458 459 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 460 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 461 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 462 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 463 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 464 465 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6) 466 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 467 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 468 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 469 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 470 471 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5) 472 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 473 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 474 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 475 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 476 477 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4) 478 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 479 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 480 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 481 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 482 483 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3) 484 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 485 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 486 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 487 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 488 489 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2) 490 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ 491 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 492 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ 493 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 494 495 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1) 496 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ 497 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 498 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ 499 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 500 501 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 502 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 503 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 504 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 505 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 506 507 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 508 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) 509 510 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 511 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ 512 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 513 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 514 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 515 516 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 517 #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) 518 519 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 520 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 521 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 522 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 523 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 524 525 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 526 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 527 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 528 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 529 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 530 531 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) 532 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ 533 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 534 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ 535 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 536 537 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 538 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 539 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 540 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 541 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 542 543 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 544 #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) 545 546 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 547 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 548 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 549 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 550 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 551 552 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 553 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 554 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 555 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 556 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 557 558 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) 559 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ 560 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 561 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ 562 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 563 564 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 565 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 566 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 567 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 568 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 569 570 /* ANA_CL:PORT:FILTER_CTRL */ 571 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) 572 573 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 574 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ 575 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 576 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ 577 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 578 579 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) 580 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ 581 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 582 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ 583 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 584 585 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) 586 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ 587 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 588 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 589 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 590 591 /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 592 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4) 593 594 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 595 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ 596 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 597 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ 598 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 599 600 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) 601 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ 602 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 603 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ 604 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 605 606 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) 607 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ 608 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 609 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ 610 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 611 612 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) 613 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ 614 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 615 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ 616 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 617 618 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) 619 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ 620 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 621 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ 622 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 623 624 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) 625 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ 626 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 627 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ 628 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 629 630 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) 631 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ 632 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 633 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ 634 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 635 636 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) 637 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ 638 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 639 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ 640 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 641 642 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) 643 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ 644 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 645 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ 646 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 647 648 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) 649 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ 650 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 651 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ 652 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 653 654 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) 655 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ 656 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 657 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 658 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 659 660 /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 661 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) 662 663 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 664 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ 665 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 666 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ 667 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 668 669 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) 670 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ 671 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 672 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 673 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 674 675 /* ANA_CL:PORT:VLAN_CTRL */ 676 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) 677 678 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 679 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ 680 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 681 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ 682 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 683 684 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) 685 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ 686 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 687 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ 688 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 689 690 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) 691 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ 692 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 693 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ 694 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 695 696 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) 697 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ 698 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 699 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ 700 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 701 702 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) 703 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ 704 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 705 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ 706 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 707 708 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) 709 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ 710 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 711 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ 712 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 713 714 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) 715 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ 716 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 717 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ 718 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 719 720 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) 721 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ 722 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 723 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ 724 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 725 726 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) 727 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ 728 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) 729 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ 730 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) 731 732 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) 733 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ 734 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) 735 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ 736 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) 737 738 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) 739 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ 740 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) 741 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 742 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 743 744 /* ANA_CL:PORT:VLAN_CTRL_2 */ 745 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) 746 747 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 748 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ 749 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 750 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 751 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 752 753 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 754 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 108, r, 16, 4) 755 756 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 757 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ 758 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 759 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ 760 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 761 762 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0) 763 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ 764 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 765 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 766 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 767 768 /* ANA_CL:PORT:QOS_CFG */ 769 #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) 770 771 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 772 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ 773 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 774 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ 775 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 776 777 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14) 778 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ 779 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 780 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ 781 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 782 783 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12) 784 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ 785 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 786 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ 787 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 788 789 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11) 790 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ 791 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 792 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ 793 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 794 795 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10) 796 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ 797 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 798 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ 799 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 800 801 #define ANA_CL_QOS_CFG_KEEP_ENA BIT(9) 802 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ 803 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x) 804 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ 805 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x) 806 807 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8) 808 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ 809 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 810 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ 811 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 812 813 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7) 814 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ 815 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 816 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ 817 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 818 819 #define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6) 820 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ 821 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 822 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ 823 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 824 825 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5) 826 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ 827 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 828 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ 829 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 830 831 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3) 832 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ 833 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 834 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ 835 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 836 837 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0) 838 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ 839 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 840 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 841 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 842 843 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 844 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) 845 846 /* ANA_CL:COMMON:OWN_UPSID */ 847 #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) 848 849 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 850 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ 851 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) 852 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 853 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 854 855 /* ANA_CL:COMMON:DSCP_CFG */ 856 #define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) 857 858 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 859 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ 860 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 861 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ 862 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 863 864 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4) 865 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ 866 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 867 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ 868 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 869 870 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2) 871 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ 872 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 873 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ 874 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 875 876 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1) 877 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 878 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 879 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 880 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 881 882 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0) 883 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 884 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 885 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 886 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 887 888 /* ANA_L2:COMMON:AUTO_LRN_CFG */ 889 #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) 890 891 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 892 #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) 893 894 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 895 #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) 896 897 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 898 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ 899 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 900 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 901 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 902 903 /* ANA_L2:COMMON:OWN_UPSID */ 904 #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) 905 906 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 907 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ 908 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) 909 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 910 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 911 912 /* ANA_L3:COMMON:VLAN_CTRL */ 913 #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) 914 915 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 916 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ 917 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 918 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 919 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 920 921 /* ANA_L3:VLAN:VLAN_CFG */ 922 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) 923 924 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 925 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ 926 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 927 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ 928 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 929 930 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) 931 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ 932 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) 933 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ 934 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) 935 936 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) 937 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ 938 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 939 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ 940 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 941 942 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) 943 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ 944 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 945 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ 946 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 947 948 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) 949 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ 950 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 951 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ 952 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 953 954 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) 955 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ 956 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 957 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ 958 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 959 960 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) 961 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ 962 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 963 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ 964 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 965 966 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) 967 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ 968 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 969 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ 970 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 971 972 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) 973 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ 974 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 975 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 976 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 977 978 /* ANA_L3:VLAN:VLAN_MASK_CFG */ 979 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) 980 981 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 982 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) 983 984 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 985 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) 986 987 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 988 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ 989 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 990 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 991 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 992 993 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 994 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4) 995 996 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 997 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4) 998 999 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1000 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4) 1001 1002 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1003 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4) 1004 1005 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1006 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4) 1007 1008 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1009 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4) 1010 1011 /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1012 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4) 1013 1014 /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1015 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4) 1016 1017 /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1018 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4) 1019 1020 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1021 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4) 1022 1023 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1024 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4) 1025 1026 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1027 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4) 1028 1029 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1030 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4) 1031 1032 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1033 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4) 1034 1035 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1036 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4) 1037 1038 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1039 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4) 1040 1041 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1042 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4) 1043 1044 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1045 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4) 1046 1047 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1048 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4) 1049 1050 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1051 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4) 1052 1053 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1054 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4) 1055 1056 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 1057 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4) 1058 1059 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 1060 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4) 1061 1062 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 1063 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4) 1064 1065 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 1066 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4) 1067 1068 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 1069 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4) 1070 1071 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 1072 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4) 1073 1074 /* ASM:DEV_STATISTICS:TX_UC_CNT */ 1075 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4) 1076 1077 /* ASM:DEV_STATISTICS:TX_MC_CNT */ 1078 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4) 1079 1080 /* ASM:DEV_STATISTICS:TX_BC_CNT */ 1081 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4) 1082 1083 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 1084 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4) 1085 1086 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 1087 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4) 1088 1089 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 1090 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4) 1091 1092 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 1093 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4) 1094 1095 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 1096 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4) 1097 1098 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 1099 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4) 1100 1101 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 1102 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4) 1103 1104 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 1105 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4) 1106 1107 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 1108 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4) 1109 1110 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 1111 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4) 1112 1113 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 1114 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4) 1115 1116 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 1117 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4) 1118 1119 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 1120 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4) 1121 1122 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 1123 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4) 1124 1125 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 1126 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4) 1127 1128 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 1129 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4) 1130 1131 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 1132 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4) 1133 1134 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 1135 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4) 1136 1137 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 1138 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4) 1139 1140 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 1141 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4) 1142 1143 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 1144 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4) 1145 1146 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 1147 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4) 1148 1149 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 1150 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4) 1151 1152 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 1153 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4) 1154 1155 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1156 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4) 1157 1158 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 1159 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4) 1160 1161 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 1162 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4) 1163 1164 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 1165 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4) 1166 1167 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 1168 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4) 1169 1170 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 1171 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4) 1172 1173 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 1174 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4) 1175 1176 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 1177 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4) 1178 1179 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 1180 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4) 1181 1182 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 1183 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4) 1184 1185 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 1186 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4) 1187 1188 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 1189 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4) 1190 1191 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 1192 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4) 1193 1194 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 1195 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4) 1196 1197 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 1198 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4) 1199 1200 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 1201 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4) 1202 1203 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 1204 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4) 1205 1206 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 1207 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4) 1208 1209 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 1210 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4) 1211 1212 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 1213 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4) 1214 1215 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 1216 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4) 1217 1218 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 1219 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4) 1220 1221 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 1222 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4) 1223 1224 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 1225 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4) 1226 1227 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 1228 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4) 1229 1230 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 1231 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4) 1232 1233 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 1234 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4) 1235 1236 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 1237 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4) 1238 1239 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 1240 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4) 1241 1242 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 1243 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4) 1244 1245 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 1246 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4) 1247 1248 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 1249 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4) 1250 1251 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 1252 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4) 1253 1254 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 1255 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4) 1256 1257 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 1258 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4) 1259 1260 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 1261 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4) 1262 1263 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 1264 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 1265 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 1266 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 1267 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 1268 1269 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 1270 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4) 1271 1272 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1273 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 1274 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 1275 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 1276 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 1277 1278 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 1279 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4) 1280 1281 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1282 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 1283 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 1284 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 1285 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 1286 1287 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 1288 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4) 1289 1290 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 1291 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 1292 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 1293 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 1294 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 1295 1296 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 1297 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4) 1298 1299 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 1300 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 1301 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 1302 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 1303 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 1304 1305 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 1306 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4) 1307 1308 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 1309 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 1310 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 1311 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 1312 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 1313 1314 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 1315 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4) 1316 1317 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1318 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 1319 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 1320 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 1321 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 1322 1323 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 1324 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4) 1325 1326 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 1327 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 1328 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 1329 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 1330 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 1331 1332 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 1333 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4) 1334 1335 /* ASM:CFG:STAT_CFG */ 1336 #define ASM_STAT_CFG __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) 1337 1338 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 1339 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ 1340 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 1341 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 1342 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 1343 1344 /* ASM:CFG:PORT_CFG */ 1345 #define ASM_PORT_CFG(r) __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) 1346 1347 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 1348 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ 1349 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) 1350 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ 1351 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) 1352 1353 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) 1354 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ 1355 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 1356 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ 1357 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 1358 1359 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) 1360 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ 1361 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 1362 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ 1363 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 1364 1365 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) 1366 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ 1367 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 1368 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ 1369 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 1370 1371 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) 1372 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ 1373 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 1374 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ 1375 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 1376 1377 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) 1378 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ 1379 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) 1380 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ 1381 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) 1382 1383 #define ASM_PORT_CFG_PAD_ENA BIT(6) 1384 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ 1385 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) 1386 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ 1387 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) 1388 1389 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) 1390 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ 1391 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 1392 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ 1393 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 1394 1395 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) 1396 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ 1397 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 1398 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ 1399 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 1400 1401 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) 1402 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ 1403 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 1404 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ 1405 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 1406 1407 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) 1408 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ 1409 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) 1410 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 1411 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 1412 1413 /* ASM:RAM_CTRL:RAM_INIT */ 1414 #define ASM_RAM_INIT __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) 1415 1416 #define ASM_RAM_INIT_RAM_INIT BIT(1) 1417 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ 1418 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) 1419 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ 1420 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) 1421 1422 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) 1423 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 1424 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) 1425 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 1426 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 1427 1428 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 1429 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 1430 1431 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 1432 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ 1433 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 1434 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ 1435 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 1436 1437 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) 1438 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ 1439 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 1440 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ 1441 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 1442 1443 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) 1444 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ 1445 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 1446 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ 1447 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 1448 1449 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) 1450 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ 1451 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 1452 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ 1453 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 1454 1455 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) 1456 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ 1457 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 1458 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ 1459 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 1460 1461 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) 1462 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ 1463 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 1464 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 1465 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 1466 1467 /* CPU:CPU_REGS:PROC_CTRL */ 1468 #define CPU_PROC_CTRL __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) 1469 1470 #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) 1471 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 1472 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 1473 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 1474 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 1475 1476 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) 1477 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 1478 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 1479 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 1480 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 1481 1482 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) 1483 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 1484 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 1485 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 1486 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 1487 1488 #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) 1489 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 1490 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 1491 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 1492 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 1493 1494 #define CPU_PROC_CTRL_VINITHI BIT(8) 1495 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 1496 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) 1497 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 1498 FIELD_GET(CPU_PROC_CTRL_VINITHI, x) 1499 1500 #define CPU_PROC_CTRL_CFGTE BIT(7) 1501 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 1502 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) 1503 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 1504 FIELD_GET(CPU_PROC_CTRL_CFGTE, x) 1505 1506 #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) 1507 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 1508 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) 1509 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 1510 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) 1511 1512 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) 1513 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 1514 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 1515 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 1516 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 1517 1518 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 1519 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 1520 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 1521 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 1522 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 1523 1524 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 1525 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 1526 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 1527 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 1528 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 1529 1530 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 1531 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 1532 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 1533 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 1534 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 1535 1536 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) 1537 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 1538 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 1539 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 1540 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 1541 1542 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 1543 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 1544 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 1545 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 1546 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 1547 1548 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 1549 #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4) 1550 1551 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 1552 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ 1553 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) 1554 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ 1555 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) 1556 1557 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) 1558 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ 1559 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) 1560 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 1561 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 1562 1563 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 1564 #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4) 1565 1566 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 1567 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 1568 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 1569 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 1570 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 1571 1572 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 1573 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 1574 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 1575 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 1576 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 1577 1578 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 1579 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4) 1580 1581 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 1582 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ 1583 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 1584 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 1585 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 1586 1587 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 1588 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4) 1589 1590 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 1591 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ 1592 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 1593 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ 1594 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 1595 1596 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) 1597 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ 1598 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 1599 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 1600 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 1601 1602 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 1603 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4) 1604 1605 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 1606 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 1607 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 1608 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 1609 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 1610 1611 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 1612 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 1613 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 1614 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 1615 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 1616 1617 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 1618 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 1619 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 1620 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 1621 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 1622 1623 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 1624 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 1625 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 1626 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 1627 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 1628 1629 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 1630 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 1631 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 1632 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 1633 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 1634 1635 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 1636 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 1637 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 1638 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 1639 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 1640 1641 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 1642 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 1643 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 1644 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 1645 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 1646 1647 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 1648 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4) 1649 1650 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 1651 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ 1652 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 1653 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ 1654 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 1655 1656 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) 1657 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ 1658 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 1659 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ 1660 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 1661 1662 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) 1663 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ 1664 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 1665 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ 1666 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 1667 1668 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) 1669 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ 1670 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 1671 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ 1672 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 1673 1674 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) 1675 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ 1676 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 1677 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 1678 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 1679 1680 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 1681 #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4) 1682 1683 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 1684 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 1685 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 1686 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 1687 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 1688 1689 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 1690 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 1691 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1692 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 1693 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1694 1695 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 1696 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 1697 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 1698 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 1699 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 1700 1701 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 1702 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 1703 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 1704 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 1705 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 1706 1707 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 1708 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 1709 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 1710 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 1711 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 1712 1713 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 1714 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 1715 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 1716 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 1717 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 1718 1719 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 1720 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 1721 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 1722 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 1723 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 1724 1725 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 1726 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 1727 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 1728 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 1729 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 1730 1731 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 1732 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 1733 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 1734 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 1735 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 1736 1737 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 1738 #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4) 1739 1740 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 1741 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 1742 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 1743 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 1744 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 1745 1746 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 1747 #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 1748 1749 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 1750 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ 1751 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) 1752 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ 1753 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) 1754 1755 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) 1756 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ 1757 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) 1758 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 1759 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 1760 1761 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 1762 #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 1763 1764 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 1765 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 1766 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 1767 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 1768 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 1769 1770 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 1771 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 1772 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 1773 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 1774 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 1775 1776 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 1777 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 1778 1779 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 1780 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 1781 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 1782 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 1783 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 1784 1785 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 1786 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 1787 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 1788 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 1789 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 1790 1791 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 1792 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 1793 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 1794 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 1795 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 1796 1797 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 1798 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 1799 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 1800 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 1801 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 1802 1803 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 1804 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 1805 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 1806 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 1807 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 1808 1809 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 1810 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 1811 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 1812 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 1813 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 1814 1815 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 1816 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 1817 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 1818 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 1819 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 1820 1821 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 1822 #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 1823 1824 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 1825 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 1826 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 1827 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 1828 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 1829 1830 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 1831 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 1832 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1833 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 1834 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1835 1836 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 1837 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 1838 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 1839 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 1840 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 1841 1842 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 1843 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 1844 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 1845 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 1846 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 1847 1848 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 1849 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 1850 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 1851 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 1852 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 1853 1854 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 1855 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 1856 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 1857 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 1858 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 1859 1860 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 1861 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 1862 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 1863 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 1864 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 1865 1866 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 1867 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 1868 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 1869 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 1870 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 1871 1872 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 1873 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 1874 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 1875 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 1876 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 1877 1878 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 1879 #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 1880 1881 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 1882 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 1883 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 1884 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 1885 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 1886 1887 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 1888 #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 1889 1890 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 1891 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ 1892 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 1893 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ 1894 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 1895 1896 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) 1897 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ 1898 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) 1899 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ 1900 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) 1901 1902 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) 1903 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ 1904 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 1905 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 1906 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 1907 1908 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 1909 #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4) 1910 1911 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 1912 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 1913 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1914 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 1915 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 1916 1917 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 1918 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 1919 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 1920 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 1921 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 1922 1923 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) 1924 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ 1925 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 1926 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ 1927 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 1928 1929 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) 1930 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ 1931 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 1932 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ 1933 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 1934 1935 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) 1936 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 1937 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 1938 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 1939 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 1940 1941 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) 1942 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 1943 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 1944 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 1945 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 1946 1947 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) 1948 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 1949 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 1950 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 1951 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 1952 1953 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) 1954 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 1955 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 1956 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 1957 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 1958 1959 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 1960 #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4) 1961 1962 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 1963 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ 1964 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 1965 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ 1966 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 1967 1968 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) 1969 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ 1970 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 1971 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 1972 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 1973 1974 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 1975 #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4) 1976 1977 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 1978 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ 1979 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 1980 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ 1981 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 1982 1983 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 1984 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 1985 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 1986 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 1987 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 1988 1989 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) 1990 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ 1991 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 1992 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 1993 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 1994 1995 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 1996 #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4) 1997 1998 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 1999 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2000 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2001 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2002 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 2003 2004 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2005 #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4) 2006 2007 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2008 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2009 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2010 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2011 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 2012 2013 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 2014 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 2015 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2016 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 2017 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 2018 2019 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 2020 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ 2021 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2022 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ 2023 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 2024 2025 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 2026 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 2027 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2028 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 2029 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 2030 2031 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 2032 #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4) 2033 2034 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 2035 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ 2036 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2037 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ 2038 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 2039 2040 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) 2041 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ 2042 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2043 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 2044 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 2045 2046 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2047 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4) 2048 2049 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 2050 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ 2051 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2052 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 2053 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 2054 2055 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 2056 #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4) 2057 2058 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 2059 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ 2060 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2061 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ 2062 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 2063 2064 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 2065 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ 2066 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2067 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ 2068 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 2069 2070 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 2071 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ 2072 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2073 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ 2074 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 2075 2076 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 2077 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ 2078 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2079 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 2080 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 2081 2082 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 2083 #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4) 2084 2085 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 2086 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ 2087 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2088 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ 2089 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 2090 2091 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) 2092 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ 2093 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) 2094 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ 2095 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) 2096 2097 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) 2098 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 2099 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 2100 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 2101 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 2102 2103 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) 2104 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ 2105 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 2106 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ 2107 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 2108 2109 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) 2110 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ 2111 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 2112 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 2113 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 2114 2115 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 2116 #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4) 2117 2118 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 2119 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ 2120 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 2121 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ 2122 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 2123 2124 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) 2125 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ 2126 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 2127 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ 2128 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 2129 2130 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) 2131 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ 2132 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) 2133 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 2134 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 2135 2136 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 2137 #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4) 2138 2139 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 2140 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ 2141 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 2142 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ 2143 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 2144 2145 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 2146 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 2147 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 2148 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 2149 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 2150 2151 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 2152 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 2153 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 2154 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 2155 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 2156 2157 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 2158 #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4) 2159 2160 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 2161 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ 2162 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 2163 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ 2164 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 2165 2166 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) 2167 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ 2168 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 2169 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ 2170 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 2171 2172 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) 2173 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ 2174 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 2175 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 2176 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 2177 2178 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 2179 #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4) 2180 2181 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 2182 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 2183 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 2184 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 2185 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 2186 2187 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 2188 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 2189 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 2190 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 2191 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 2192 2193 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) 2194 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ 2195 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 2196 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ 2197 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 2198 2199 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) 2200 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ 2201 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 2202 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 2203 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 2204 2205 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 2206 #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4) 2207 2208 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 2209 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ 2210 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 2211 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ 2212 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 2213 2214 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) 2215 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ 2216 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 2217 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ 2218 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 2219 2220 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) 2221 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ 2222 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 2223 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 2224 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 2225 2226 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 2227 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4) 2228 2229 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 2230 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ 2231 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 2232 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ 2233 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 2234 2235 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) 2236 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ 2237 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 2238 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ 2239 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 2240 2241 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) 2242 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ 2243 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 2244 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ 2245 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 2246 2247 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 2248 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 2249 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 2250 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 2251 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 2252 2253 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 2254 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4) 2255 2256 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 2257 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ 2258 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 2259 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ 2260 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 2261 2262 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) 2263 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ 2264 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 2265 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ 2266 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 2267 2268 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 2269 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 2270 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 2271 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 2272 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 2273 2274 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 2275 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 2276 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 2277 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 2278 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 2279 2280 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 2281 #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4) 2282 2283 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 2284 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 2285 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 2286 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 2287 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 2288 2289 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) 2290 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ 2291 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 2292 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 2293 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 2294 2295 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 2296 #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4) 2297 2298 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 2299 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ 2300 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 2301 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ 2302 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 2303 2304 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) 2305 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ 2306 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) 2307 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ 2308 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) 2309 2310 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) 2311 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ 2312 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 2313 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ 2314 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 2315 2316 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) 2317 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ 2318 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 2319 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ 2320 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 2321 2322 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) 2323 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ 2324 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 2325 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ 2326 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 2327 2328 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) 2329 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ 2330 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 2331 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ 2332 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 2333 2334 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) 2335 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ 2336 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 2337 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ 2338 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 2339 2340 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) 2341 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ 2342 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 2343 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ 2344 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 2345 2346 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) 2347 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ 2348 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 2349 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ 2350 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 2351 2352 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) 2353 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ 2354 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 2355 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ 2356 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 2357 2358 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) 2359 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ 2360 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 2361 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ 2362 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 2363 2364 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) 2365 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ 2366 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 2367 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ 2368 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 2369 2370 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) 2371 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ 2372 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 2373 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 2374 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 2375 2376 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 2377 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4) 2378 2379 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 2380 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ 2381 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 2382 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ 2383 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 2384 2385 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) 2386 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ 2387 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 2388 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ 2389 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 2390 2391 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) 2392 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ 2393 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 2394 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ 2395 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 2396 2397 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) 2398 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ 2399 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 2400 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ 2401 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 2402 2403 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) 2404 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ 2405 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 2406 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ 2407 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 2408 2409 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) 2410 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ 2411 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 2412 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ 2413 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 2414 2415 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) 2416 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ 2417 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 2418 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ 2419 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 2420 2421 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) 2422 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ 2423 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 2424 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 2425 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 2426 2427 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2428 #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4) 2429 2430 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 2431 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2432 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) 2433 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2434 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) 2435 2436 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) 2437 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2438 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) 2439 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2440 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 2441 2442 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2443 #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4) 2444 2445 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2446 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2447 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2448 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2449 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2450 2451 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2452 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2453 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 2454 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2455 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 2456 2457 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2458 #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4) 2459 2460 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2461 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2462 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2463 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2464 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2465 2466 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2467 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2468 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2469 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2470 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2471 2472 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2473 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2474 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2475 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2476 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2477 2478 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2479 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2480 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2481 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2482 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2483 2484 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2485 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2486 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2487 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2488 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2489 2490 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2491 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2492 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2493 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2494 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2495 2496 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2497 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2498 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2499 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2500 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2501 2502 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 2503 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4) 2504 2505 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 2506 #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4) 2507 2508 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 2509 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4) 2510 2511 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 2512 #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4) 2513 2514 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 2515 #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4) 2516 2517 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 2518 #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4) 2519 2520 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 2521 #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4) 2522 2523 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 2524 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4) 2525 2526 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 2527 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4) 2528 2529 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 2530 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4) 2531 2532 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2533 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4) 2534 2535 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 2536 #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4) 2537 2538 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 2539 #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4) 2540 2541 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 2542 #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4) 2543 2544 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 2545 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4) 2546 2547 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 2548 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4) 2549 2550 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 2551 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4) 2552 2553 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 2554 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4) 2555 2556 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 2557 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4) 2558 2559 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 2560 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4) 2561 2562 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 2563 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4) 2564 2565 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 2566 #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4) 2567 2568 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 2569 #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4) 2570 2571 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 2572 #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4) 2573 2574 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 2575 #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4) 2576 2577 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 2578 #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4) 2579 2580 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 2581 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4) 2582 2583 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 2584 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4) 2585 2586 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 2587 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4) 2588 2589 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 2590 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4) 2591 2592 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 2593 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4) 2594 2595 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 2596 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4) 2597 2598 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 2599 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4) 2600 2601 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 2602 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4) 2603 2604 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 2605 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4) 2606 2607 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 2608 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4) 2609 2610 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 2611 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4) 2612 2613 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 2614 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4) 2615 2616 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 2617 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4) 2618 2619 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 2620 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4) 2621 2622 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 2623 #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4) 2624 2625 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 2626 #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4) 2627 2628 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 2629 #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4) 2630 2631 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 2632 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4) 2633 2634 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 2635 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4) 2636 2637 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 2638 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4) 2639 2640 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 2641 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 2642 t, 13, 60, 0, 1, 312, 184, 0, 1, 4) 2643 2644 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2645 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ 2646 t, 13, 60, 0, 1, 312, 188, 0, 1, 4) 2647 2648 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 2649 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4) 2650 2651 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 2652 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4) 2653 2654 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 2655 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4) 2656 2657 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 2658 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4) 2659 2660 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 2661 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4) 2662 2663 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 2664 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4) 2665 2666 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 2667 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4) 2668 2669 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 2670 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4) 2671 2672 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 2673 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4) 2674 2675 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 2676 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4) 2677 2678 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 2679 #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4) 2680 2681 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 2682 #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4) 2683 2684 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 2685 #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4) 2686 2687 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 2688 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4) 2689 2690 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 2691 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4) 2692 2693 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 2694 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4) 2695 2696 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 2697 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4) 2698 2699 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 2700 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4) 2701 2702 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 2703 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4) 2704 2705 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 2706 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4) 2707 2708 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 2709 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4) 2710 2711 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 2712 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4) 2713 2714 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 2715 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4) 2716 2717 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 2718 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4) 2719 2720 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 2721 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4) 2722 2723 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 2724 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4) 2725 2726 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 2727 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4) 2728 2729 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 2730 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4) 2731 2732 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 2733 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4) 2734 2735 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 2736 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4) 2737 2738 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 2739 #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4) 2740 2741 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 2742 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4) 2743 2744 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 2745 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 2746 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2747 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 2748 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2749 2750 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 2751 #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4) 2752 2753 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 2754 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4) 2755 2756 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 2757 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 2758 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2759 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 2760 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2761 2762 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 2763 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4) 2764 2765 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 2766 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4) 2767 2768 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 2769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2770 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2771 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2772 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2773 2774 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 2775 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4) 2776 2777 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 2778 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4) 2779 2780 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 2781 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 2782 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 2784 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2785 2786 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 2787 #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4) 2788 2789 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 2790 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4) 2791 2792 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 2793 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 2794 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2795 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 2796 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2797 2798 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 2799 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4) 2800 2801 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 2802 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4) 2803 2804 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 2805 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 2806 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2807 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 2808 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2809 2810 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 2811 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4) 2812 2813 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 2814 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4) 2815 2816 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 2817 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2818 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2819 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2820 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2821 2822 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 2823 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4) 2824 2825 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 2826 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4) 2827 2828 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 2829 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 2830 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2831 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 2832 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2833 2834 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2835 #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4) 2836 2837 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2838 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2839 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2840 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2841 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2842 2843 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2844 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2845 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2846 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2847 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2848 2849 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2850 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2851 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2852 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2853 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2854 2855 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2856 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2857 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2858 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2859 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2860 2861 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2862 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2863 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 2864 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2865 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 2866 2867 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2868 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2869 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 2870 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2871 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 2872 2873 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2874 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2875 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 2876 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2877 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 2878 2879 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2880 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2881 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 2882 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2883 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 2884 2885 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2886 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2887 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 2888 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2889 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 2890 2891 /* DSM:RAM_CTRL:RAM_INIT */ 2892 #define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 2893 2894 #define DSM_RAM_INIT_RAM_INIT BIT(1) 2895 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ 2896 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) 2897 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ 2898 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) 2899 2900 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) 2901 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 2902 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) 2903 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2904 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 2905 2906 /* DSM:CFG:BUF_CFG */ 2907 #define DSM_BUF_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) 2908 2909 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 2910 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ 2911 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) 2912 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ 2913 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) 2914 2915 #define DSM_BUF_CFG_AGING_ENA BIT(12) 2916 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ 2917 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) 2918 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ 2919 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) 2920 2921 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) 2922 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ 2923 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 2924 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ 2925 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 2926 2927 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) 2928 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ 2929 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 2930 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 2931 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 2932 2933 /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 2934 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) 2935 2936 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 2937 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ 2938 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 2939 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ 2940 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 2941 2942 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8) 2943 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ 2944 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 2945 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ 2946 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 2947 2948 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1) 2949 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ 2950 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 2951 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ 2952 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 2953 2954 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0) 2955 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ 2956 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 2957 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 2958 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 2959 2960 /* DSM:CFG:RX_PAUSE_CFG */ 2961 #define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) 2962 2963 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 2964 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ 2965 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 2966 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ 2967 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 2968 2969 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0) 2970 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ 2971 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 2972 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 2973 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 2974 2975 /* DSM:CFG:MAC_CFG */ 2976 #define DSM_MAC_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) 2977 2978 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 2979 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ 2980 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x) 2981 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ 2982 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x) 2983 2984 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2) 2985 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ 2986 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 2987 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ 2988 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 2989 2990 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1) 2991 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ 2992 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 2993 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ 2994 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 2995 2996 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0) 2997 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ 2998 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 2999 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 3000 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 3001 3002 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 3003 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) 3004 3005 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 3006 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ 3007 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 3008 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 3009 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 3010 3011 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 3012 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) 3013 3014 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 3015 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ 3016 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 3017 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 3018 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 3019 3020 /* DSM:CFG:TAXI_CAL_CFG */ 3021 #define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) 3022 3023 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 3024 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ 3025 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x) 3026 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ 3027 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x) 3028 3029 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9) 3030 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ 3031 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 3032 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ 3033 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 3034 3035 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5) 3036 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ 3037 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 3038 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ 3039 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 3040 3041 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1) 3042 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ 3043 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 3044 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ 3045 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 3046 3047 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0) 3048 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ 3049 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 3050 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 3051 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 3052 3053 /* EACL:POL_CFG:POL_EACL_CFG */ 3054 #define EACL_POL_EACL_CFG __REG(TARGET_EACL, 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) 3055 3056 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 3057 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ 3058 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 3059 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ 3060 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 3061 3062 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4) 3063 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ 3064 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 3065 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ 3066 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 3067 3068 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3) 3069 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ 3070 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 3071 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ 3072 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 3073 3074 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2) 3075 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ 3076 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 3077 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ 3078 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 3079 3080 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1) 3081 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ 3082 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 3083 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ 3084 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 3085 3086 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0) 3087 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ 3088 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 3089 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 3090 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 3091 3092 /* EACL:RAM_CTRL:RAM_INIT */ 3093 #define EACL_RAM_INIT __REG(TARGET_EACL, 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) 3094 3095 #define EACL_RAM_INIT_RAM_INIT BIT(1) 3096 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ 3097 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x) 3098 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ 3099 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x) 3100 3101 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0) 3102 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 3103 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x) 3104 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 3105 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 3106 3107 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 3108 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 3109 3110 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 3111 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 3112 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 3113 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 3114 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 3115 3116 /* FDMA:FDMA:FDMA_CH_RELOAD */ 3117 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 3118 3119 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 3120 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 3121 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 3122 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 3123 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 3124 3125 /* FDMA:FDMA:FDMA_CH_DISABLE */ 3126 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 3127 3128 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 3129 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 3130 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 3131 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 3132 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 3133 3134 /* FDMA:FDMA:FDMA_DCB_LLP */ 3135 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 3136 3137 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 3138 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 3139 3140 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 3141 #define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 116, r, 8, 4) 3142 3143 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 3144 #define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 148, r, 8, 4) 3145 3146 /* FDMA:FDMA:FDMA_CH_CFG */ 3147 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 3148 3149 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) 3150 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 3151 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 3152 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 3153 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 3154 3155 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) 3156 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 3157 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 3158 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 3159 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 3160 3161 #define FDMA_CH_CFG_CH_INJ_PORT BIT(5) 3162 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 3163 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 3164 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 3165 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 3166 3167 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) 3168 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 3169 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 3170 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 3171 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 3172 3173 #define FDMA_CH_CFG_CH_MEM BIT(0) 3174 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 3175 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 3176 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 3177 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 3178 3179 /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 3180 #define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 256, r, 8, 4) 3181 3182 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 3183 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ 3184 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x) 3185 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 3186 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 3187 3188 /* FDMA:FDMA:FDMA_XTR_CFG */ 3189 #define FDMA_XTR_CFG __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) 3190 3191 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 3192 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ 3193 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x) 3194 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ 3195 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x) 3196 3197 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0) 3198 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ 3199 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x) 3200 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 3201 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 3202 3203 /* FDMA:FDMA:FDMA_PORT_CTRL */ 3204 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 3205 3206 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 3207 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 3208 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 3209 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 3210 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 3211 3212 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3) 3213 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ 3214 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 3215 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ 3216 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 3217 3218 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 3219 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 3220 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 3221 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 3222 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 3223 3224 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1) 3225 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ 3226 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 3227 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ 3228 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 3229 3230 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0) 3231 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ 3232 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x) 3233 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 3234 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 3235 3236 /* FDMA:FDMA:FDMA_INTR_DCB */ 3237 #define FDMA_INTR_DCB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) 3238 3239 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 3240 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ 3241 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x) 3242 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 3243 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 3244 3245 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 3246 #define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) 3247 3248 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 3249 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ 3250 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 3251 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 3252 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 3253 3254 /* FDMA:FDMA:FDMA_INTR_DB */ 3255 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 3256 3257 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 3258 #define FDMA_INTR_DB_INTR_DB_SET(x)\ 3259 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x) 3260 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 3261 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 3262 3263 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 3264 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 3265 3266 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 3267 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 3268 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 3269 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 3270 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 3271 3272 /* FDMA:FDMA:FDMA_INTR_ERR */ 3273 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 3274 3275 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 3276 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ 3277 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x) 3278 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ 3279 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x) 3280 3281 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0) 3282 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ 3283 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x) 3284 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 3285 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 3286 3287 /* FDMA:FDMA:FDMA_ERRORS */ 3288 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 3289 3290 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 3291 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ 3292 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x) 3293 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ 3294 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x) 3295 3296 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28) 3297 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ 3298 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x) 3299 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ 3300 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x) 3301 3302 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26) 3303 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ 3304 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 3305 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ 3306 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 3307 3308 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24) 3309 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ 3310 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 3311 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ 3312 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 3313 3314 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16) 3315 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ 3316 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x) 3317 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ 3318 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x) 3319 3320 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10) 3321 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ 3322 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x) 3323 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ 3324 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x) 3325 3326 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8) 3327 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ 3328 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 3329 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ 3330 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 3331 3332 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0) 3333 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ 3334 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x) 3335 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 3336 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 3337 3338 /* FDMA:FDMA:FDMA_ERRORS_2 */ 3339 #define FDMA_ERRORS_2 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) 3340 3341 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 3342 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ 3343 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 3344 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 3345 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 3346 3347 /* FDMA:FDMA:FDMA_CTRL */ 3348 #define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) 3349 3350 #define FDMA_CTRL_NRESET BIT(0) 3351 #define FDMA_CTRL_NRESET_SET(x)\ 3352 FIELD_PREP(FDMA_CTRL_NRESET, x) 3353 #define FDMA_CTRL_NRESET_GET(x)\ 3354 FIELD_GET(FDMA_CTRL_NRESET, x) 3355 3356 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 3357 #define GCB_CHIP_ID __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) 3358 3359 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 3360 #define GCB_CHIP_ID_REV_ID_SET(x)\ 3361 FIELD_PREP(GCB_CHIP_ID_REV_ID, x) 3362 #define GCB_CHIP_ID_REV_ID_GET(x)\ 3363 FIELD_GET(GCB_CHIP_ID_REV_ID, x) 3364 3365 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12) 3366 #define GCB_CHIP_ID_PART_ID_SET(x)\ 3367 FIELD_PREP(GCB_CHIP_ID_PART_ID, x) 3368 #define GCB_CHIP_ID_PART_ID_GET(x)\ 3369 FIELD_GET(GCB_CHIP_ID_PART_ID, x) 3370 3371 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1) 3372 #define GCB_CHIP_ID_MFG_ID_SET(x)\ 3373 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x) 3374 #define GCB_CHIP_ID_MFG_ID_GET(x)\ 3375 FIELD_GET(GCB_CHIP_ID_MFG_ID, x) 3376 3377 #define GCB_CHIP_ID_ONE BIT(0) 3378 #define GCB_CHIP_ID_ONE_SET(x)\ 3379 FIELD_PREP(GCB_CHIP_ID_ONE, x) 3380 #define GCB_CHIP_ID_ONE_GET(x)\ 3381 FIELD_GET(GCB_CHIP_ID_ONE, x) 3382 3383 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 3384 #define GCB_SOFT_RST __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) 3385 3386 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 3387 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 3388 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 3389 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ 3390 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 3391 3392 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1) 3393 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ 3394 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x) 3395 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ 3396 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x) 3397 3398 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0) 3399 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ 3400 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x) 3401 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 3402 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 3403 3404 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 3405 #define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) 3406 3407 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 3408 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ 3409 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 3410 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ 3411 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 3412 3413 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0) 3414 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ 3415 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 3416 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 3417 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 3418 3419 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 3420 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 24, r, 65, 4) 3421 3422 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) 3423 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 3424 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 3425 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 3426 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 3427 3428 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 3429 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB, 0, 1, 876, g, 3, 280, 20, 0, 1, 4) 3430 3431 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 3432 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ 3433 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 3434 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ 3435 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 3436 3437 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0) 3438 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ 3439 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 3440 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 3441 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 3442 3443 /* HSCH:HSCH_CFG:CIR_CFG */ 3444 #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) 3445 3446 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 3447 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ 3448 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x) 3449 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ 3450 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x) 3451 3452 #define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0) 3453 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ 3454 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x) 3455 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 3456 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 3457 3458 /* HSCH:HSCH_CFG:EIR_CFG */ 3459 #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) 3460 3461 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 3462 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ 3463 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x) 3464 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ 3465 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x) 3466 3467 #define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0) 3468 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ 3469 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x) 3470 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 3471 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 3472 3473 /* HSCH:HSCH_CFG:SE_CFG */ 3474 #define HSCH_SE_CFG(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) 3475 3476 #define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) 3477 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 3478 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) 3479 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 3480 FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) 3481 3482 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 3483 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ 3484 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x) 3485 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ 3486 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x) 3487 3488 #define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3) 3489 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ 3490 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x) 3491 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ 3492 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x) 3493 3494 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1) 3495 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ 3496 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 3497 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ 3498 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 3499 3500 #define HSCH_SE_CFG_SE_STOP BIT(0) 3501 #define HSCH_SE_CFG_SE_STOP_SET(x)\ 3502 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x) 3503 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 3504 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 3505 3506 /* HSCH:HSCH_CFG:SE_CONNECT */ 3507 #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) 3508 3509 #define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) 3510 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 3511 FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 3512 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 3513 FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 3514 3515 /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 3516 #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) 3517 3518 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 3519 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ 3520 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 3521 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 3522 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 3523 3524 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) 3525 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 3526 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 3527 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 3528 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 3529 3530 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 3531 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ 3532 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 3533 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ 3534 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 3535 3536 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1) 3537 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ 3538 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 3539 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ 3540 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 3541 3542 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 3543 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ 3544 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 3545 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 3546 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 3547 3548 /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 3549 #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH, 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) 3550 3551 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 3552 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ 3553 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) 3554 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ 3555 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) 3556 3557 #define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) 3558 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ 3559 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 3560 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 3561 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 3562 3563 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 3564 #define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) 3565 3566 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) 3567 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 3568 FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 3569 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 3570 FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 3571 3572 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 3573 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ 3574 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 3575 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ 3576 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 3577 3578 #define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0) 3579 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ 3580 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 3581 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 3582 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 3583 3584 /* HSCH:HSCH_MISC:SYS_CLK_PER */ 3585 #define HSCH_SYS_CLK_PER __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) 3586 3587 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS GENMASK(7, 0) 3588 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\ 3589 FIELD_PREP(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x) 3590 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\ 3591 FIELD_GET(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x) 3592 3593 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 3594 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 0, r, 4, 4) 3595 3596 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 3597 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ 3598 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 3599 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 3600 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 3601 3602 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 3603 #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 16, r, 4, 4) 3604 3605 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) 3606 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 3607 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 3608 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 3609 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 3610 3611 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 3612 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ 3613 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 3614 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 3615 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 3616 3617 /* HSCH:SYSTEM:FLUSH_CTRL */ 3618 #define HSCH_FLUSH_CTRL __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) 3619 3620 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 3621 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ 3622 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 3623 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ 3624 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 3625 3626 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26) 3627 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ 3628 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 3629 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ 3630 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 3631 3632 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25) 3633 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ 3634 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x) 3635 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 3636 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 3637 3638 #define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) 3639 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 3640 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 3641 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 3642 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 3643 3644 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 3645 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ 3646 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 3647 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ 3648 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 3649 3650 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16) 3651 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ 3652 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x) 3653 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 3654 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 3655 3656 #define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) 3657 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 3658 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 3659 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 3660 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 3661 3662 /* HSCH:SYSTEM:PORT_MODE */ 3663 #define HSCH_PORT_MODE(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) 3664 3665 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 3666 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ 3667 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x) 3668 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ 3669 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x) 3670 3671 #define HSCH_PORT_MODE_AGE_DIS BIT(3) 3672 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ 3673 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x) 3674 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ 3675 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x) 3676 3677 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2) 3678 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ 3679 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x) 3680 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ 3681 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x) 3682 3683 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1) 3684 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ 3685 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 3686 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ 3687 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 3688 3689 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0) 3690 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ 3691 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 3692 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 3693 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 3694 3695 /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 3696 #define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) 3697 3698 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 3699 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ 3700 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 3701 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 3702 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 3703 3704 /* HSCH:MMGT:RESET_CFG */ 3705 #define HSCH_RESET_CFG __REG(TARGET_HSCH, 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) 3706 3707 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 3708 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ 3709 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x) 3710 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 3711 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 3712 3713 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 3714 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH, 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) 3715 3716 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 3717 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ 3718 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 3719 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 3720 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 3721 3722 /* LRN:COMMON:COMMON_ACCESS_CTRL */ 3723 #define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 3724 3725 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 3726 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ 3727 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 3728 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ 3729 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 3730 3731 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19) 3732 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ 3733 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 3734 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 3735 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 3736 3737 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) 3738 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 3739 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 3740 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 3741 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 3742 3743 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 3744 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ 3745 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 3746 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ 3747 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 3748 3749 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0) 3750 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ 3751 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 3752 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 3753 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 3754 3755 /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 3756 #define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 3757 3758 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 3759 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ 3760 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 3761 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ 3762 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 3763 3764 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0) 3765 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ 3766 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 3767 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 3768 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 3769 3770 /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 3771 #define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 3772 3773 /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 3774 #define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 3775 3776 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 3777 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ 3778 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 3779 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ 3780 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 3781 3782 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27) 3783 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ 3784 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 3785 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ 3786 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 3787 3788 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24) 3789 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ 3790 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 3791 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ 3792 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 3793 3794 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23) 3795 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ 3796 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 3797 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ 3798 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 3799 3800 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22) 3801 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ 3802 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 3803 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ 3804 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 3805 3806 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21) 3807 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ 3808 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 3809 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ 3810 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 3811 3812 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19) 3813 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ 3814 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 3815 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ 3816 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 3817 3818 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17) 3819 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ 3820 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 3821 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ 3822 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 3823 3824 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16) 3825 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ 3826 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 3827 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ 3828 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 3829 3830 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15) 3831 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ 3832 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 3833 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ 3834 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 3835 3836 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12) 3837 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ 3838 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 3839 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ 3840 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 3841 3842 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0) 3843 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ 3844 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 3845 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 3846 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 3847 3848 /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 3849 #define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 3850 3851 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) 3852 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 3853 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 3854 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 3855 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 3856 3857 /* LRN:COMMON:SCAN_NEXT_CFG */ 3858 #define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 3859 3860 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 3861 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ 3862 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 3863 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ 3864 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 3865 3866 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17) 3867 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ 3868 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 3869 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ 3870 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 3871 3872 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15) 3873 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ 3874 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 3875 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ 3876 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 3877 3878 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14) 3879 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ 3880 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 3881 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ 3882 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 3883 3884 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13) 3885 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ 3886 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 3887 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ 3888 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 3889 3890 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12) 3891 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ 3892 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 3893 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ 3894 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 3895 3896 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11) 3897 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ 3898 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 3899 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ 3900 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 3901 3902 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10) 3903 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ 3904 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 3905 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ 3906 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 3907 3908 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9) 3909 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ 3910 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 3911 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ 3912 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 3913 3914 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8) 3915 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ 3916 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 3917 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ 3918 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 3919 3920 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7) 3921 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ 3922 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 3923 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ 3924 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 3925 3926 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3) 3927 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ 3928 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 3929 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ 3930 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 3931 3932 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2) 3933 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ 3934 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 3935 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ 3936 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 3937 3938 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1) 3939 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ 3940 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 3941 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ 3942 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 3943 3944 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0) 3945 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ 3946 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 3947 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 3948 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 3949 3950 /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 3951 #define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 3952 3953 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 3954 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ 3955 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 3956 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ 3957 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 3958 3959 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0) 3960 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ 3961 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 3962 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 3963 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 3964 3965 /* LRN:COMMON:AUTOAGE_CFG */ 3966 #define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 3967 3968 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 3969 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ 3970 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 3971 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ 3972 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 3973 3974 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0) 3975 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ 3976 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 3977 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 3978 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 3979 3980 /* LRN:COMMON:AUTOAGE_CFG_1 */ 3981 #define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 3982 3983 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 3984 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ 3985 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 3986 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ 3987 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 3988 3989 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15) 3990 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ 3991 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 3992 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ 3993 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 3994 3995 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7) 3996 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ 3997 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 3998 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ 3999 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 4000 4001 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6) 4002 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ 4003 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 4004 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ 4005 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 4006 4007 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2) 4008 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ 4009 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 4010 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ 4011 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 4012 4013 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1) 4014 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ 4015 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 4016 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ 4017 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 4018 4019 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0) 4020 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ 4021 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 4022 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 4023 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 4024 4025 /* LRN:COMMON:AUTOAGE_CFG_2 */ 4026 #define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 4027 4028 #define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) 4029 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 4030 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 4031 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 4032 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 4033 4034 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 4035 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ 4036 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 4037 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 4038 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 4039 4040 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 4041 #define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 4042 4043 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 4044 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ 4045 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 4046 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ 4047 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 4048 4049 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8) 4050 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ 4051 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x) 4052 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ 4053 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x) 4054 4055 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16) 4056 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ 4057 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 4058 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ 4059 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 4060 4061 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19) 4062 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ 4063 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 4064 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ 4065 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 4066 4067 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20) 4068 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ 4069 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x) 4070 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ 4071 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x) 4072 4073 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22) 4074 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ 4075 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 4076 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ 4077 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 4078 4079 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23) 4080 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ 4081 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 4082 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ 4083 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 4084 4085 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28) 4086 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ 4087 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 4088 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ 4089 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 4090 4091 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29) 4092 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ 4093 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 4094 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ 4095 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 4096 4097 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31) 4098 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ 4099 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 4100 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 4101 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 4102 4103 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 4104 #define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 4105 4106 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 4107 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ 4108 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 4109 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ 4110 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 4111 4112 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16) 4113 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ 4114 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 4115 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 4116 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 4117 4118 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 4119 #define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 4120 4121 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 4122 #define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 4123 4124 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 4125 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ 4126 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 4127 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ 4128 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 4129 4130 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16) 4131 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ 4132 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 4133 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 4134 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 4135 4136 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 4137 #define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 4138 4139 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 4140 #define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 4141 4142 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 4143 #define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 4144 4145 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 4146 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ 4147 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 4148 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ 4149 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 4150 4151 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2) 4152 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ 4153 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 4154 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 4155 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 4156 4157 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 4158 #define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 0, 0, 1, 4) 4159 4160 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 4161 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ 4162 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x) 4163 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ 4164 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x) 4165 4166 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 4167 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 4168 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4169 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 4170 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4171 4172 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 4173 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 4174 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 4175 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 4176 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 4177 4178 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 4179 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 4180 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 4181 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 4182 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 4183 4184 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15) 4185 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 4186 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 4187 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 4188 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 4189 4190 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 4191 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 4192 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 4193 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 4194 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 4195 4196 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 4197 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 4198 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 4199 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 4200 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 4201 4202 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 4203 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 4204 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4205 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 4206 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4207 4208 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 4209 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 4210 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 4211 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 4212 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 4213 4214 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 4215 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 4216 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4217 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 4218 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4219 4220 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 4221 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 4222 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 4223 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 4224 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 4225 4226 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 4227 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 4228 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4229 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 4230 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4231 4232 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 4233 #define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 4, 0, 1, 4) 4234 4235 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 4236 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 4237 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 4238 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 4239 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 4240 4241 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4) 4242 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 4243 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 4244 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 4245 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 4246 4247 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0) 4248 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 4249 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 4250 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 4251 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 4252 4253 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 4254 #define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 4255 4256 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 4257 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ 4258 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x) 4259 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ 4260 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x) 4261 4262 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 4263 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 4264 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4265 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 4266 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4267 4268 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 4269 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 4270 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 4271 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 4272 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 4273 4274 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 4275 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 4276 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 4277 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 4278 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 4279 4280 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15) 4281 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 4282 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 4283 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 4284 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 4285 4286 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 4287 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 4288 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 4289 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 4290 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 4291 4292 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 4293 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 4294 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 4295 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 4296 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 4297 4298 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 4299 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 4300 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4301 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 4302 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4303 4304 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 4305 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 4306 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 4307 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 4308 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 4309 4310 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 4311 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 4312 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4313 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 4314 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4315 4316 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 4317 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 4318 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 4319 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 4320 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 4321 4322 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 4323 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 4324 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4325 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 4326 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4327 4328 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 4329 #define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 4330 4331 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 4332 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 4333 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 4334 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 4335 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 4336 4337 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4) 4338 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 4339 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 4340 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 4341 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 4342 4343 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0) 4344 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 4345 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 4346 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 4347 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 4348 4349 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 4350 #define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 0, 0, 1, 4) 4351 4352 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 4353 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ 4354 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x) 4355 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ 4356 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x) 4357 4358 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 4359 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 4360 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4361 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 4362 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 4363 4364 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 4365 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 4366 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 4367 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 4368 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 4369 4370 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 4371 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 4372 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 4373 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 4374 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 4375 4376 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15) 4377 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 4378 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 4379 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 4380 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 4381 4382 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 4383 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 4384 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 4385 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 4386 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 4387 4388 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 4389 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 4390 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 4391 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 4392 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 4393 4394 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 4395 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 4396 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4397 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 4398 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 4399 4400 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 4401 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 4402 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 4403 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 4404 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 4405 4406 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 4407 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 4408 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4409 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 4410 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 4411 4412 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 4413 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 4414 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 4415 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 4416 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 4417 4418 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 4419 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 4420 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4421 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 4422 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 4423 4424 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 4425 #define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 4, 0, 1, 4) 4426 4427 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 4428 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 4429 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 4430 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 4431 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 4432 4433 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4) 4434 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 4435 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 4436 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 4437 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 4438 4439 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0) 4440 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 4441 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 4442 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 4443 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 4444 4445 /* PORT_CONF:HW_CFG:DEV5G_MODES */ 4446 #define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 4447 4448 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 4449 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 4450 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 4451 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 4452 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 4453 4454 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 4455 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 4456 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 4457 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 4458 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 4459 4460 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 4461 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 4462 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 4463 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 4464 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 4465 4466 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 4467 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 4468 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 4469 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 4470 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 4471 4472 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 4473 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 4474 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 4475 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 4476 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 4477 4478 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 4479 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 4480 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 4481 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 4482 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 4483 4484 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 4485 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 4486 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 4487 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 4488 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 4489 4490 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 4491 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 4492 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 4493 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 4494 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 4495 4496 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 4497 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 4498 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 4499 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ 4500 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 4501 4502 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9) 4503 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ 4504 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 4505 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 4506 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 4507 4508 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 4509 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 4510 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 4511 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 4512 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 4513 4514 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 4515 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 4516 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 4517 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 4518 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 4519 4520 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 4521 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 4522 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 4523 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 4524 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 4525 4526 /* PORT_CONF:HW_CFG:DEV10G_MODES */ 4527 #define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 4528 4529 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 4530 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ 4531 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 4532 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 4533 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 4534 4535 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 4536 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 4537 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 4538 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 4539 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 4540 4541 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 4542 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 4543 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 4544 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 4545 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 4546 4547 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 4548 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 4549 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 4550 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 4551 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 4552 4553 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 4554 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 4555 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 4556 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 4557 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 4558 4559 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 4560 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 4561 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 4562 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 4563 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 4564 4565 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 4566 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 4567 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 4568 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 4569 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 4570 4571 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 4572 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 4573 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 4574 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 4575 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 4576 4577 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 4578 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 4579 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 4580 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 4581 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 4582 4583 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 4584 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 4585 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 4586 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 4587 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 4588 4589 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 4590 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 4591 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 4592 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 4593 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 4594 4595 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 4596 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 4597 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 4598 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 4599 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 4600 4601 /* PORT_CONF:HW_CFG:DEV25G_MODES */ 4602 #define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 4603 4604 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 4605 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ 4606 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 4607 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ 4608 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 4609 4610 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1) 4611 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ 4612 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 4613 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ 4614 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 4615 4616 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2) 4617 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ 4618 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 4619 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ 4620 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 4621 4622 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3) 4623 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ 4624 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 4625 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ 4626 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 4627 4628 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4) 4629 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ 4630 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 4631 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ 4632 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 4633 4634 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5) 4635 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ 4636 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 4637 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ 4638 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 4639 4640 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6) 4641 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ 4642 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 4643 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ 4644 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 4645 4646 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7) 4647 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ 4648 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 4649 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 4650 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 4651 4652 /* PORT_CONF:HW_CFG:QSGMII_ENA */ 4653 #define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 4654 4655 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 4656 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ 4657 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 4658 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ 4659 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 4660 4661 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1) 4662 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ 4663 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 4664 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ 4665 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 4666 4667 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2) 4668 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ 4669 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 4670 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ 4671 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 4672 4673 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3) 4674 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ 4675 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 4676 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ 4677 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 4678 4679 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4) 4680 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ 4681 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 4682 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ 4683 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 4684 4685 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5) 4686 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ 4687 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 4688 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 4689 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 4690 4691 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 4692 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 4693 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 4694 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 4695 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 4696 4697 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 4698 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 4699 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 4700 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 4701 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 4702 4703 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 4704 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 4705 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 4706 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 4707 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 4708 4709 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 4710 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 4711 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 4712 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 4713 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 4714 4715 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 4716 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 4717 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 4718 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 4719 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 4720 4721 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 4722 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 4723 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 4724 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 4725 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 4726 4727 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 4728 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 4729 4730 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 4731 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ 4732 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 4733 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ 4734 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 4735 4736 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8) 4737 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ 4738 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 4739 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ 4740 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 4741 4742 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7) 4743 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ 4744 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 4745 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ 4746 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 4747 4748 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6) 4749 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ 4750 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 4751 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ 4752 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 4753 4754 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5) 4755 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ 4756 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 4757 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ 4758 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 4759 4760 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4) 4761 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ 4762 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 4763 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ 4764 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 4765 4766 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1) 4767 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ 4768 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 4769 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 4770 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 4771 4772 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 4773 #define PTP_PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) 4774 4775 #define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) 4776 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 4777 FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) 4778 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 4779 FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) 4780 4781 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 4782 #define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) 4783 4784 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) 4785 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 4786 FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 4787 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 4788 FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 4789 4790 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 4791 #define PTP_PTP_INTR_IDENT __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) 4792 4793 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) 4794 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 4795 FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 4796 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 4797 FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 4798 4799 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 4800 #define PTP_PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) 4801 4802 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 4803 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ 4804 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x) 4805 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ 4806 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x) 4807 4808 #define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6) 4809 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ 4810 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x) 4811 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ 4812 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x) 4813 4814 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3) 4815 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ 4816 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 4817 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ 4818 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 4819 4820 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0) 4821 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ 4822 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 4823 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 4824 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 4825 4826 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 4827 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 0, r, 2, 4) 4828 4829 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 4830 #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 8, 0, 1, 4) 4831 4832 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 4833 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ 4834 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 4835 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 4836 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 4837 4838 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 4839 #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 12, 0, 1, 4) 4840 4841 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 4842 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ 4843 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 4844 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 4845 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 4846 4847 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 4848 #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 16, 0, 1, 4) 4849 4850 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 4851 #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 20, 0, 1, 4) 4852 4853 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 4854 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ 4855 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 4856 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 4857 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 4858 4859 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 4860 #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 24, 0, 1, 4) 4861 4862 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 4863 #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 0, 0, 1, 4) 4864 4865 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) 4866 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 4867 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 4868 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 4869 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 4870 4871 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) 4872 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 4873 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 4874 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 4875 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 4876 4877 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) 4878 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 4879 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 4880 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 4881 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 4882 4883 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) 4884 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 4885 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 4886 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 4887 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 4888 4889 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 4890 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ 4891 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 4892 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ 4893 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 4894 4895 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16) 4896 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ 4897 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 4898 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ 4899 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 4900 4901 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14) 4902 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ 4903 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 4904 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ 4905 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 4906 4907 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13) 4908 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ 4909 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 4910 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ 4911 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 4912 4913 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0) 4914 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ 4915 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 4916 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 4917 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 4918 4919 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 4920 #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 4, 0, 1, 4) 4921 4922 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 4923 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ 4924 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 4925 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 4926 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 4927 4928 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 4929 #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 8, 0, 1, 4) 4930 4931 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 4932 #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 12, 0, 1, 4) 4933 4934 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 4935 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ 4936 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 4937 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 4938 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 4939 4940 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 4941 #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 16, 0, 1, 4) 4942 4943 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 4944 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ 4945 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 4946 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 4947 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 4948 4949 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 4950 #define PTP_NTP_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 20, 0, 1, 4) 4951 4952 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 4953 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 24, 0, 1, 4) 4954 4955 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 4956 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ 4957 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 4958 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 4959 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 4960 4961 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 4962 #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 28, 0, 1, 4) 4963 4964 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 4965 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ 4966 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 4967 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 4968 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 4969 4970 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 4971 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 32, 0, 1, 4) 4972 4973 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 4974 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ 4975 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 4976 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ 4977 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 4978 4979 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0) 4980 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ 4981 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 4982 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 4983 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 4984 4985 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 4986 #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 0, 0, 1, 4) 4987 4988 #define PTP_PHAD_CTRL_PHAD_ENA BIT(7) 4989 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 4990 FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) 4991 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 4992 FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) 4993 4994 #define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) 4995 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 4996 FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) 4997 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 4998 FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) 4999 5000 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 5001 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 5002 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) 5003 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ 5004 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x) 5005 5006 #define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0) 5007 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ 5008 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x) 5009 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 5010 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 5011 5012 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 5013 #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 4, 0, 1, 4) 5014 5015 /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 5016 #define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4) 5017 5018 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 5019 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ 5020 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 5021 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ 5022 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 5023 5024 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10) 5025 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ 5026 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 5027 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ 5028 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 5029 5030 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6) 5031 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ 5032 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 5033 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ 5034 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 5035 5036 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5) 5037 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 5038 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 5039 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 5040 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 5041 5042 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4) 5043 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ 5044 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 5045 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ 5046 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 5047 5048 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3) 5049 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ 5050 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 5051 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ 5052 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 5053 5054 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2) 5055 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ 5056 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 5057 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ 5058 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 5059 5060 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1) 5061 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ 5062 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 5063 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ 5064 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 5065 5066 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0) 5067 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ 5068 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 5069 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 5070 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 5071 5072 /* QRES:RES_CTRL:RES_CFG */ 5073 #define QRES_RES_CFG(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 5074 5075 #define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) 5076 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 5077 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) 5078 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 5079 FIELD_GET(QRES_RES_CFG_WM_HIGH, x) 5080 5081 /* QRES:RES_CTRL:RES_STAT */ 5082 #define QRES_RES_STAT(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 5083 5084 #define QRES_RES_STAT_MAXUSE GENMASK(20, 0) 5085 #define QRES_RES_STAT_MAXUSE_SET(x)\ 5086 FIELD_PREP(QRES_RES_STAT_MAXUSE, x) 5087 #define QRES_RES_STAT_MAXUSE_GET(x)\ 5088 FIELD_GET(QRES_RES_STAT_MAXUSE, x) 5089 5090 /* QRES:RES_CTRL:RES_STAT_CUR */ 5091 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 5092 5093 #define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) 5094 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 5095 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) 5096 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 5097 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) 5098 5099 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 5100 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 5101 5102 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 5103 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 5104 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 5105 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 5106 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 5107 5108 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 5109 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ 5110 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 5111 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ 5112 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 5113 5114 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 5115 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 5116 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 5117 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 5118 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 5119 5120 /* DEVCPU_QS:XTR:XTR_RD */ 5121 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 5122 5123 /* DEVCPU_QS:XTR:XTR_FLUSH */ 5124 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 5125 5126 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 5127 #define QS_XTR_FLUSH_FLUSH_SET(x)\ 5128 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x) 5129 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 5130 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 5131 5132 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 5133 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 5134 5135 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 5136 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ 5137 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 5138 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 5139 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 5140 5141 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 5142 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 5143 5144 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 5145 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 5146 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 5147 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 5148 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 5149 5150 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 5151 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 5152 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 5153 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 5154 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 5155 5156 /* DEVCPU_QS:INJ:INJ_WR */ 5157 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 5158 5159 /* DEVCPU_QS:INJ:INJ_CTRL */ 5160 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 5161 5162 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 5163 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 5164 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 5165 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 5166 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 5167 5168 #define QS_INJ_CTRL_ABORT BIT(20) 5169 #define QS_INJ_CTRL_ABORT_SET(x)\ 5170 FIELD_PREP(QS_INJ_CTRL_ABORT, x) 5171 #define QS_INJ_CTRL_ABORT_GET(x)\ 5172 FIELD_GET(QS_INJ_CTRL_ABORT, x) 5173 5174 #define QS_INJ_CTRL_EOF BIT(19) 5175 #define QS_INJ_CTRL_EOF_SET(x)\ 5176 FIELD_PREP(QS_INJ_CTRL_EOF, x) 5177 #define QS_INJ_CTRL_EOF_GET(x)\ 5178 FIELD_GET(QS_INJ_CTRL_EOF, x) 5179 5180 #define QS_INJ_CTRL_SOF BIT(18) 5181 #define QS_INJ_CTRL_SOF_SET(x)\ 5182 FIELD_PREP(QS_INJ_CTRL_SOF, x) 5183 #define QS_INJ_CTRL_SOF_GET(x)\ 5184 FIELD_GET(QS_INJ_CTRL_SOF, x) 5185 5186 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 5187 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 5188 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 5189 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 5190 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 5191 5192 /* DEVCPU_QS:INJ:INJ_STATUS */ 5193 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 5194 5195 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 5196 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 5197 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 5198 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 5199 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 5200 5201 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 5202 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 5203 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 5204 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 5205 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 5206 5207 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0) 5208 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ 5209 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 5210 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 5211 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 5212 5213 /* QSYS:PAUSE_CFG:PAUSE_CFG */ 5214 #define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) 5215 5216 #define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) 5217 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 5218 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) 5219 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 5220 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) 5221 5222 #define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) 5223 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 5224 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) 5225 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 5226 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) 5227 5228 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 5229 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 5230 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x) 5231 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 5232 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x) 5233 5234 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0) 5235 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ 5236 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 5237 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 5238 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 5239 5240 /* QSYS:PAUSE_CFG:ATOP */ 5241 #define QSYS_ATOP(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) 5242 5243 #define QSYS_ATOP_ATOP GENMASK(11, 0) 5244 #define QSYS_ATOP_ATOP_SET(x)\ 5245 FIELD_PREP(QSYS_ATOP_ATOP, x) 5246 #define QSYS_ATOP_ATOP_GET(x)\ 5247 FIELD_GET(QSYS_ATOP_ATOP, x) 5248 5249 /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 5250 #define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) 5251 5252 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 5253 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ 5254 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 5255 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ 5256 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 5257 5258 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0) 5259 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ 5260 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 5261 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 5262 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 5263 5264 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 5265 #define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) 5266 5267 #define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) 5268 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 5269 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 5270 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 5271 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 5272 5273 /* QSYS:CALCFG:CAL_AUTO */ 5274 #define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) 5275 5276 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 5277 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ 5278 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x) 5279 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 5280 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 5281 5282 /* QSYS:CALCFG:CAL_CTRL */ 5283 #define QSYS_CAL_CTRL __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) 5284 5285 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 5286 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ 5287 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x) 5288 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ 5289 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x) 5290 5291 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1) 5292 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ 5293 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 5294 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ 5295 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 5296 5297 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0) 5298 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ 5299 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 5300 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 5301 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 5302 5303 /* QSYS:RAM_CTRL:RAM_INIT */ 5304 #define QSYS_RAM_INIT __REG(TARGET_QSYS, 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) 5305 5306 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 5307 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ 5308 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x) 5309 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ 5310 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x) 5311 5312 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 5313 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 5314 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 5315 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 5316 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 5317 5318 /* REW:COMMON:OWN_UPSID */ 5319 #define REW_OWN_UPSID(r) __REG(TARGET_REW, 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) 5320 5321 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 5322 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ 5323 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x) 5324 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 5325 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 5326 5327 /* REW:PORT:PORT_VLAN_CFG */ 5328 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) 5329 5330 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 5331 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ 5332 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x) 5333 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ 5334 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x) 5335 5336 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12) 5337 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ 5338 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x) 5339 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ 5340 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x) 5341 5342 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 5343 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 5344 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 5345 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 5346 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 5347 5348 /* REW:PORT:TAG_CTRL */ 5349 #define REW_TAG_CTRL(g) __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) 5350 5351 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 5352 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ 5353 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 5354 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ 5355 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 5356 5357 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11) 5358 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ 5359 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x) 5360 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ 5361 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x) 5362 5363 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8) 5364 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ 5365 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x) 5366 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ 5367 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x) 5368 5369 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6) 5370 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ 5371 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x) 5372 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ 5373 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x) 5374 5375 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3) 5376 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ 5377 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x) 5378 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ 5379 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x) 5380 5381 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0) 5382 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ 5383 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x) 5384 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 5385 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 5386 5387 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 5388 #define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 5389 5390 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 5391 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 5392 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 5393 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 5394 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 5395 5396 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 5397 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 5398 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 5399 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 5400 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 5401 5402 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 5403 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 5404 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 5405 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 5406 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 5407 5408 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 5409 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 5410 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 5411 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 5412 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 5413 5414 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 5415 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 5416 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 5417 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 5418 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 5419 5420 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 5421 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 5422 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 5423 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 5424 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 5425 5426 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 5427 #define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 5428 5429 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 5430 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 5431 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 5432 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 5433 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 5434 5435 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 5436 #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 5437 5438 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 5439 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ 5440 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 5441 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 5442 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 5443 5444 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 5445 #define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 5446 5447 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 5448 #define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 5449 5450 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 5451 #define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 5452 5453 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 5454 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ 5455 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 5456 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 5457 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 5458 5459 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 5460 #define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 5461 5462 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 5463 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ 5464 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 5465 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ 5466 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 5467 5468 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0) 5469 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ 5470 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 5471 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 5472 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 5473 5474 /* REW:RAM_CTRL:RAM_INIT */ 5475 #define REW_RAM_INIT __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) 5476 5477 #define REW_RAM_INIT_RAM_INIT BIT(1) 5478 #define REW_RAM_INIT_RAM_INIT_SET(x)\ 5479 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x) 5480 #define REW_RAM_INIT_RAM_INIT_GET(x)\ 5481 FIELD_GET(REW_RAM_INIT_RAM_INIT, x) 5482 5483 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0) 5484 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 5485 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x) 5486 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 5487 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 5488 5489 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 5490 #define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 5491 5492 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 5493 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ 5494 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x) 5495 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ 5496 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x) 5497 5498 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21) 5499 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 5500 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 5501 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 5502 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 5503 5504 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20) 5505 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ 5506 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 5507 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ 5508 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 5509 5510 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19) 5511 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ 5512 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 5513 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ 5514 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 5515 5516 #define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3) 5517 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ 5518 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 5519 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ 5520 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 5521 5522 #define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2) 5523 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ 5524 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 5525 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ 5526 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 5527 5528 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1) 5529 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ 5530 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 5531 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ 5532 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 5533 5534 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0) 5535 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ 5536 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 5537 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 5538 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 5539 5540 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 5541 #define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 5542 5543 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 5544 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ 5545 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x) 5546 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ 5547 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x) 5548 5549 #define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0) 5550 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ 5551 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x) 5552 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 5553 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 5554 5555 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 5556 #define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 5557 5558 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 5559 #define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 5560 5561 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 5562 #define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 5563 5564 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 5565 #define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 5566 5567 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 5568 #define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 5569 5570 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 5571 #define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 5572 5573 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 5574 #define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 5575 5576 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 5577 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ 5578 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x) 5579 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 5580 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 5581 5582 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 5583 #define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 5584 5585 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 5586 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ 5587 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x) 5588 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 5589 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 5590 5591 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 5592 #define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 5593 5594 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 5595 #define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 5596 5597 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 5598 #define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 5599 5600 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 5601 #define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 5602 5603 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 5604 #define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 5605 5606 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 5607 #define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 5608 5609 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 5610 #define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 5611 5612 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 5613 #define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 5614 5615 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 5616 #define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 5617 5618 /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 5619 #define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 5620 5621 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 5622 #define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 5623 5624 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 5625 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ 5626 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 5627 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ 5628 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 5629 5630 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0) 5631 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 5632 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 5633 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 5634 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 5635 5636 /* VOP:RAM_CTRL:RAM_INIT */ 5637 #define VOP_RAM_INIT __REG(TARGET_VOP, 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) 5638 5639 #define VOP_RAM_INIT_RAM_INIT BIT(1) 5640 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ 5641 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x) 5642 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ 5643 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x) 5644 5645 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0) 5646 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 5647 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x) 5648 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 5649 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 5650 5651 /* XQS:SYSTEM:STAT_CFG */ 5652 #define XQS_STAT_CFG __REG(TARGET_XQS, 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) 5653 5654 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 5655 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ 5656 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 5657 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 5658 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 5659 5660 #define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) 5661 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 5662 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) 5663 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 5664 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) 5665 5666 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 5667 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ 5668 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 5669 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ 5670 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 5671 5672 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0) 5673 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ 5674 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x) 5675 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 5676 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 5677 5678 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 5679 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) 5680 5681 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) 5682 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 5683 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 5684 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 5685 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 5686 5687 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 5688 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) 5689 5690 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) 5691 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 5692 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 5693 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 5694 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 5695 5696 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 5697 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) 5698 5699 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) 5700 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 5701 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 5702 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 5703 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 5704 5705 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 5706 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) 5707 5708 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) 5709 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 5710 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 5711 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 5712 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 5713 5714 /* XQS:STAT:CNT */ 5715 #define XQS_CNT(g) __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 5716 5717 #endif /* _SPARX5_MAIN_REGS_H_ */ 5718