1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/hrtimer.h> 18 19 #include "sparx5_main_regs.h" 20 21 /* Target chip type */ 22 enum spx5_target_chiptype { 23 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 24 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 25 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 26 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 27 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 28 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 29 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 30 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 31 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 32 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 33 }; 34 35 enum sparx5_port_max_tags { 36 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 37 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 38 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 39 }; 40 41 enum sparx5_vlan_port_type { 42 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 43 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 44 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 45 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 46 }; 47 48 #define SPX5_PORTS 65 49 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 50 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 51 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 52 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 53 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 54 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 55 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 56 57 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 58 #define PGID_UC_FLOOD (PGID_BASE + 0) 59 #define PGID_MC_FLOOD (PGID_BASE + 1) 60 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 61 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 62 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 63 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 64 #define PGID_BCAST (PGID_BASE + 6) 65 #define PGID_CPU (PGID_BASE + 7) 66 67 #define IFH_LEN 9 /* 36 bytes */ 68 #define NULL_VID 0 69 #define SPX5_MACT_PULL_DELAY (2 * HZ) 70 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 71 #define SPX5_PRIOS 8 /* Number of priority queues */ 72 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 73 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 74 75 #define XTR_QUEUE 0 76 #define INJ_QUEUE 0 77 78 #define FDMA_DCB_MAX 64 79 #define FDMA_RX_DCB_MAX_DBS 15 80 #define FDMA_TX_DCB_MAX_DBS 1 81 82 struct sparx5; 83 84 struct sparx5_db_hw { 85 u64 dataptr; 86 u64 status; 87 }; 88 89 struct sparx5_rx_dcb_hw { 90 u64 nextptr; 91 u64 info; 92 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 93 }; 94 95 struct sparx5_tx_dcb_hw { 96 u64 nextptr; 97 u64 info; 98 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 99 }; 100 101 /* Frame DMA receive state: 102 * For each DB, there is a SKB, and the skb data pointer is mapped in 103 * the DB. Once a frame is received the skb is given to the upper layers 104 * and a new skb is added to the dcb. 105 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 106 */ 107 struct sparx5_rx { 108 struct sparx5_rx_dcb_hw *dcb_entries; 109 struct sparx5_rx_dcb_hw *last_entry; 110 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 111 int db_index; 112 int dcb_index; 113 dma_addr_t dma; 114 struct napi_struct napi; 115 u32 channel_id; 116 struct net_device *ndev; 117 u64 packets; 118 }; 119 120 /* Frame DMA transmit state: 121 * DCBs are chained using the DCBs nextptr field. 122 */ 123 struct sparx5_tx { 124 struct sparx5_tx_dcb_hw *curr_entry; 125 struct sparx5_tx_dcb_hw *first_entry; 126 struct list_head db_list; 127 dma_addr_t dma; 128 u32 channel_id; 129 u64 packets; 130 u64 dropped; 131 }; 132 133 struct sparx5_port_config { 134 phy_interface_t portmode; 135 u32 bandwidth; 136 int speed; 137 int duplex; 138 enum phy_media media; 139 bool inband; 140 bool power_down; 141 bool autoneg; 142 bool serdes_reset; 143 u32 pause; 144 u32 pause_adv; 145 phy_interface_t phy_mode; 146 u32 sd_sgpio; 147 }; 148 149 struct sparx5_port { 150 struct net_device *ndev; 151 struct sparx5 *sparx5; 152 struct device_node *of_node; 153 struct phy *serdes; 154 struct sparx5_port_config conf; 155 struct phylink_config phylink_config; 156 struct phylink *phylink; 157 struct phylink_pcs phylink_pcs; 158 u16 portno; 159 /* Ingress default VLAN (pvid) */ 160 u16 pvid; 161 /* Egress default VLAN (vid) */ 162 u16 vid; 163 bool signd_internal; 164 bool signd_active_high; 165 bool signd_enable; 166 bool flow_control; 167 enum sparx5_port_max_tags max_vlan_tags; 168 enum sparx5_vlan_port_type vlan_type; 169 u32 custom_etype; 170 u32 ifh[IFH_LEN]; 171 bool vlan_aware; 172 struct hrtimer inj_timer; 173 }; 174 175 enum sparx5_core_clockfreq { 176 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 177 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 178 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 179 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 180 }; 181 182 struct sparx5 { 183 struct platform_device *pdev; 184 struct device *dev; 185 u32 chip_id; 186 enum spx5_target_chiptype target_ct; 187 void __iomem *regs[NUM_TARGETS]; 188 int port_count; 189 struct mutex lock; /* MAC reg lock */ 190 /* port structures are in net device */ 191 struct sparx5_port *ports[SPX5_PORTS]; 192 enum sparx5_core_clockfreq coreclock; 193 /* Statistics */ 194 u32 num_stats; 195 u32 num_ethtool_stats; 196 const char * const *stats_layout; 197 u64 *stats; 198 /* Workqueue for reading stats */ 199 struct mutex queue_stats_lock; 200 struct delayed_work stats_work; 201 struct workqueue_struct *stats_queue; 202 /* Notifiers */ 203 struct notifier_block netdevice_nb; 204 struct notifier_block switchdev_nb; 205 struct notifier_block switchdev_blocking_nb; 206 /* Switch state */ 207 u8 base_mac[ETH_ALEN]; 208 /* Associated bridge device (when bridged) */ 209 struct net_device *hw_bridge_dev; 210 /* Bridged interfaces */ 211 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 212 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 213 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 214 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 215 /* SW MAC table */ 216 struct list_head mact_entries; 217 /* mac table list (mact_entries) mutex */ 218 struct mutex mact_lock; 219 struct delayed_work mact_work; 220 struct workqueue_struct *mact_queue; 221 /* Board specifics */ 222 bool sd_sgpio_remapping; 223 /* Register based inj/xtr */ 224 int xtr_irq; 225 /* Frame DMA */ 226 int fdma_irq; 227 struct sparx5_rx rx; 228 struct sparx5_tx tx; 229 }; 230 231 /* sparx5_switchdev.c */ 232 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 233 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 234 235 /* sparx5_packet.c */ 236 struct frame_info { 237 int src_port; 238 }; 239 240 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 241 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 242 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 243 int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 244 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 245 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 246 247 /* sparx5_fdma.c */ 248 int sparx5_fdma_start(struct sparx5 *sparx5); 249 int sparx5_fdma_stop(struct sparx5 *sparx5); 250 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 251 irqreturn_t sparx5_fdma_handler(int irq, void *args); 252 253 /* sparx5_mactable.c */ 254 void sparx5_mact_pull_work(struct work_struct *work); 255 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 256 const unsigned char mac[ETH_ALEN], u16 vid); 257 bool sparx5_mact_getnext(struct sparx5 *sparx5, 258 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 259 int sparx5_mact_forget(struct sparx5 *sparx5, 260 const unsigned char mac[ETH_ALEN], u16 vid); 261 int sparx5_add_mact_entry(struct sparx5 *sparx5, 262 struct sparx5_port *port, 263 const unsigned char *addr, u16 vid); 264 int sparx5_del_mact_entry(struct sparx5 *sparx5, 265 const unsigned char *addr, 266 u16 vid); 267 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 268 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 269 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 270 void sparx5_mact_init(struct sparx5 *sparx5); 271 272 /* sparx5_vlan.c */ 273 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 274 void sparx5_update_fwd(struct sparx5 *sparx5); 275 void sparx5_vlan_init(struct sparx5 *sparx5); 276 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 277 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 278 bool untagged); 279 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 280 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 281 282 /* sparx5_calendar.c */ 283 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 284 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 285 286 /* sparx5_ethtool.c */ 287 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 288 int sparx_stats_init(struct sparx5 *sparx5); 289 290 /* sparx5_netdev.c */ 291 bool sparx5_netdevice_check(const struct net_device *dev); 292 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 293 int sparx5_register_netdevs(struct sparx5 *sparx5); 294 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 295 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 296 297 /* Clock period in picoseconds */ 298 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 299 { 300 switch (cclock) { 301 case SPX5_CORE_CLOCK_250MHZ: 302 return 4000; 303 case SPX5_CORE_CLOCK_500MHZ: 304 return 2000; 305 case SPX5_CORE_CLOCK_625MHZ: 306 default: 307 return 1600; 308 } 309 } 310 311 static inline bool sparx5_is_baser(phy_interface_t interface) 312 { 313 return interface == PHY_INTERFACE_MODE_5GBASER || 314 interface == PHY_INTERFACE_MODE_10GBASER || 315 interface == PHY_INTERFACE_MODE_25GBASER; 316 } 317 318 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 319 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 320 extern const struct ethtool_ops sparx5_ethtool_ops; 321 322 /* Calculate raw offset */ 323 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 324 int gbase, int ginst, 325 int gcnt, int gwidth, 326 int raddr, int rinst, 327 int rcnt, int rwidth) 328 { 329 WARN_ON((tinst) >= tcnt); 330 WARN_ON((ginst) >= gcnt); 331 WARN_ON((rinst) >= rcnt); 332 return gbase + ((ginst) * gwidth) + 333 raddr + ((rinst) * rwidth); 334 } 335 336 /* Read, Write and modify registers content. 337 * The register definition macros start at the id 338 */ 339 static inline void __iomem *spx5_addr(void __iomem *base[], 340 int id, int tinst, int tcnt, 341 int gbase, int ginst, 342 int gcnt, int gwidth, 343 int raddr, int rinst, 344 int rcnt, int rwidth) 345 { 346 WARN_ON((tinst) >= tcnt); 347 WARN_ON((ginst) >= gcnt); 348 WARN_ON((rinst) >= rcnt); 349 return base[id + (tinst)] + 350 gbase + ((ginst) * gwidth) + 351 raddr + ((rinst) * rwidth); 352 } 353 354 static inline void __iomem *spx5_inst_addr(void __iomem *base, 355 int gbase, int ginst, 356 int gcnt, int gwidth, 357 int raddr, int rinst, 358 int rcnt, int rwidth) 359 { 360 WARN_ON((ginst) >= gcnt); 361 WARN_ON((rinst) >= rcnt); 362 return base + 363 gbase + ((ginst) * gwidth) + 364 raddr + ((rinst) * rwidth); 365 } 366 367 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 368 int gbase, int ginst, int gcnt, int gwidth, 369 int raddr, int rinst, int rcnt, int rwidth) 370 { 371 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 372 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 373 } 374 375 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 376 int gbase, int ginst, int gcnt, int gwidth, 377 int raddr, int rinst, int rcnt, int rwidth) 378 { 379 return readl(spx5_inst_addr(iomem, gbase, ginst, 380 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 381 } 382 383 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 384 int id, int tinst, int tcnt, 385 int gbase, int ginst, int gcnt, int gwidth, 386 int raddr, int rinst, int rcnt, int rwidth) 387 { 388 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 389 gbase, ginst, gcnt, gwidth, 390 raddr, rinst, rcnt, rwidth)); 391 } 392 393 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 394 int id, int tinst, int tcnt, 395 int gbase, int ginst, int gcnt, int gwidth, 396 int raddr, int rinst, int rcnt, int rwidth) 397 { 398 writel(val, spx5_inst_addr(iomem, 399 gbase, ginst, gcnt, gwidth, 400 raddr, rinst, rcnt, rwidth)); 401 } 402 403 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 404 int id, int tinst, int tcnt, 405 int gbase, int ginst, int gcnt, int gwidth, 406 int raddr, int rinst, int rcnt, int rwidth) 407 { 408 u32 nval; 409 410 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 411 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 412 nval = (nval & ~mask) | (val & mask); 413 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 414 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 415 } 416 417 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 418 int id, int tinst, int tcnt, 419 int gbase, int ginst, int gcnt, int gwidth, 420 int raddr, int rinst, int rcnt, int rwidth) 421 { 422 u32 nval; 423 424 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 425 rinst, rcnt, rwidth)); 426 nval = (nval & ~mask) | (val & mask); 427 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 428 rinst, rcnt, rwidth)); 429 } 430 431 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 432 { 433 return sparx5->regs[id + tinst]; 434 } 435 436 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 437 int id, int tinst, int tcnt, 438 int gbase, int ginst, int gcnt, int gwidth, 439 int raddr, int rinst, int rcnt, int rwidth) 440 { 441 return spx5_addr(sparx5->regs, id, tinst, tcnt, 442 gbase, ginst, gcnt, gwidth, 443 raddr, rinst, rcnt, rwidth); 444 } 445 446 #endif /* __SPARX5_MAIN_H__ */ 447