1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 #include <linux/debugfs.h> 21 22 #include "sparx5_main_regs.h" 23 24 /* Target chip type */ 25 enum spx5_target_chiptype { 26 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 27 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 28 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 29 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 30 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 31 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 32 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 33 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 34 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 35 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 36 }; 37 38 enum sparx5_port_max_tags { 39 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 40 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 41 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 42 }; 43 44 enum sparx5_vlan_port_type { 45 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 46 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 47 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 48 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 49 }; 50 51 #define SPX5_PORTS 65 52 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 53 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 54 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 55 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 56 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 57 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 58 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 59 60 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 61 #define PGID_UC_FLOOD (PGID_BASE + 0) 62 #define PGID_MC_FLOOD (PGID_BASE + 1) 63 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 64 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 65 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 66 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 67 #define PGID_BCAST (PGID_BASE + 6) 68 #define PGID_CPU (PGID_BASE + 7) 69 #define PGID_MCAST_START (PGID_BASE + 8) 70 71 #define PGID_TABLE_SIZE 3290 72 73 #define IFH_LEN 9 /* 36 bytes */ 74 #define NULL_VID 0 75 #define SPX5_MACT_PULL_DELAY (2 * HZ) 76 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 77 #define SPX5_PRIOS 8 /* Number of priority queues */ 78 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 79 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 80 81 #define XTR_QUEUE 0 82 #define INJ_QUEUE 0 83 84 #define FDMA_DCB_MAX 64 85 #define FDMA_RX_DCB_MAX_DBS 15 86 #define FDMA_TX_DCB_MAX_DBS 1 87 88 #define SPARX5_PHC_COUNT 3 89 #define SPARX5_PHC_PORT 0 90 91 #define IFH_REW_OP_NOOP 0x0 92 #define IFH_REW_OP_ONE_STEP_PTP 0x3 93 #define IFH_REW_OP_TWO_STEP_PTP 0x4 94 95 #define IFH_PDU_TYPE_NONE 0x0 96 #define IFH_PDU_TYPE_PTP 0x5 97 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 98 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 99 100 struct sparx5; 101 102 struct sparx5_db_hw { 103 u64 dataptr; 104 u64 status; 105 }; 106 107 struct sparx5_rx_dcb_hw { 108 u64 nextptr; 109 u64 info; 110 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 111 }; 112 113 struct sparx5_tx_dcb_hw { 114 u64 nextptr; 115 u64 info; 116 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 117 }; 118 119 /* Frame DMA receive state: 120 * For each DB, there is a SKB, and the skb data pointer is mapped in 121 * the DB. Once a frame is received the skb is given to the upper layers 122 * and a new skb is added to the dcb. 123 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 124 */ 125 struct sparx5_rx { 126 struct sparx5_rx_dcb_hw *dcb_entries; 127 struct sparx5_rx_dcb_hw *last_entry; 128 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 129 int db_index; 130 int dcb_index; 131 dma_addr_t dma; 132 struct napi_struct napi; 133 u32 channel_id; 134 struct net_device *ndev; 135 u64 packets; 136 }; 137 138 /* Frame DMA transmit state: 139 * DCBs are chained using the DCBs nextptr field. 140 */ 141 struct sparx5_tx { 142 struct sparx5_tx_dcb_hw *curr_entry; 143 struct sparx5_tx_dcb_hw *first_entry; 144 struct list_head db_list; 145 dma_addr_t dma; 146 u32 channel_id; 147 u64 packets; 148 u64 dropped; 149 }; 150 151 struct sparx5_port_config { 152 phy_interface_t portmode; 153 u32 bandwidth; 154 int speed; 155 int duplex; 156 enum phy_media media; 157 bool inband; 158 bool power_down; 159 bool autoneg; 160 bool serdes_reset; 161 u32 pause; 162 u32 pause_adv; 163 phy_interface_t phy_mode; 164 u32 sd_sgpio; 165 }; 166 167 struct sparx5_port { 168 struct net_device *ndev; 169 struct sparx5 *sparx5; 170 struct device_node *of_node; 171 struct phy *serdes; 172 struct sparx5_port_config conf; 173 struct phylink_config phylink_config; 174 struct phylink *phylink; 175 struct phylink_pcs phylink_pcs; 176 u16 portno; 177 /* Ingress default VLAN (pvid) */ 178 u16 pvid; 179 /* Egress default VLAN (vid) */ 180 u16 vid; 181 bool signd_internal; 182 bool signd_active_high; 183 bool signd_enable; 184 bool flow_control; 185 enum sparx5_port_max_tags max_vlan_tags; 186 enum sparx5_vlan_port_type vlan_type; 187 u32 custom_etype; 188 bool vlan_aware; 189 struct hrtimer inj_timer; 190 /* ptp */ 191 u8 ptp_cmd; 192 u16 ts_id; 193 struct sk_buff_head tx_skbs; 194 bool is_mrouter; 195 struct list_head tc_templates; /* list of TC templates on this port */ 196 }; 197 198 enum sparx5_core_clockfreq { 199 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 200 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 201 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 202 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 203 }; 204 205 struct sparx5_phc { 206 struct ptp_clock *clock; 207 struct ptp_clock_info info; 208 struct kernel_hwtstamp_config hwtstamp_config; 209 struct sparx5 *sparx5; 210 u8 index; 211 }; 212 213 struct sparx5_skb_cb { 214 u8 rew_op; 215 u8 pdu_type; 216 u8 pdu_w16_offset; 217 u16 ts_id; 218 unsigned long jiffies; 219 }; 220 221 struct sparx5_mdb_entry { 222 struct list_head list; 223 DECLARE_BITMAP(port_mask, SPX5_PORTS); 224 unsigned char addr[ETH_ALEN]; 225 bool cpu_copy; 226 u16 vid; 227 u16 pgid_idx; 228 }; 229 230 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 231 #define SPARX5_SKB_CB(skb) \ 232 ((struct sparx5_skb_cb *)((skb)->cb)) 233 234 struct sparx5 { 235 struct platform_device *pdev; 236 struct device *dev; 237 u32 chip_id; 238 enum spx5_target_chiptype target_ct; 239 void __iomem *regs[NUM_TARGETS]; 240 int port_count; 241 struct mutex lock; /* MAC reg lock */ 242 /* port structures are in net device */ 243 struct sparx5_port *ports[SPX5_PORTS]; 244 enum sparx5_core_clockfreq coreclock; 245 /* Statistics */ 246 u32 num_stats; 247 u32 num_ethtool_stats; 248 const char * const *stats_layout; 249 u64 *stats; 250 /* Workqueue for reading stats */ 251 struct mutex queue_stats_lock; 252 struct delayed_work stats_work; 253 struct workqueue_struct *stats_queue; 254 /* Notifiers */ 255 struct notifier_block netdevice_nb; 256 struct notifier_block switchdev_nb; 257 struct notifier_block switchdev_blocking_nb; 258 /* Switch state */ 259 u8 base_mac[ETH_ALEN]; 260 /* Associated bridge device (when bridged) */ 261 struct net_device *hw_bridge_dev; 262 /* Bridged interfaces */ 263 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 264 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 265 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 266 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 267 /* SW MAC table */ 268 struct list_head mact_entries; 269 /* mac table list (mact_entries) mutex */ 270 struct mutex mact_lock; 271 /* SW MDB table */ 272 struct list_head mdb_entries; 273 /* mdb list mutex */ 274 struct mutex mdb_lock; 275 struct delayed_work mact_work; 276 struct workqueue_struct *mact_queue; 277 /* Board specifics */ 278 bool sd_sgpio_remapping; 279 /* Register based inj/xtr */ 280 int xtr_irq; 281 /* Frame DMA */ 282 int fdma_irq; 283 spinlock_t tx_lock; /* lock for frame transmission */ 284 struct sparx5_rx rx; 285 struct sparx5_tx tx; 286 /* PTP */ 287 bool ptp; 288 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 289 spinlock_t ptp_clock_lock; /* lock for phc */ 290 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 291 struct mutex ptp_lock; /* lock for ptp interface state */ 292 u16 ptp_skbs; 293 int ptp_irq; 294 /* VCAP */ 295 struct vcap_control *vcap_ctrl; 296 /* PGID allocation map */ 297 u8 pgid_map[PGID_TABLE_SIZE]; 298 /* Common root for debugfs */ 299 struct dentry *debugfs_root; 300 }; 301 302 /* sparx5_switchdev.c */ 303 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 304 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 305 306 /* sparx5_packet.c */ 307 struct frame_info { 308 int src_port; 309 u32 timestamp; 310 }; 311 312 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 313 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 314 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 315 netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 316 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 317 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 318 319 /* sparx5_fdma.c */ 320 int sparx5_fdma_start(struct sparx5 *sparx5); 321 int sparx5_fdma_stop(struct sparx5 *sparx5); 322 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 323 irqreturn_t sparx5_fdma_handler(int irq, void *args); 324 325 /* sparx5_mactable.c */ 326 void sparx5_mact_pull_work(struct work_struct *work); 327 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 328 const unsigned char mac[ETH_ALEN], u16 vid); 329 bool sparx5_mact_getnext(struct sparx5 *sparx5, 330 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 331 int sparx5_mact_find(struct sparx5 *sparx5, 332 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 333 int sparx5_mact_forget(struct sparx5 *sparx5, 334 const unsigned char mac[ETH_ALEN], u16 vid); 335 int sparx5_add_mact_entry(struct sparx5 *sparx5, 336 struct net_device *dev, 337 u16 portno, 338 const unsigned char *addr, u16 vid); 339 int sparx5_del_mact_entry(struct sparx5 *sparx5, 340 const unsigned char *addr, 341 u16 vid); 342 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 343 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 344 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 345 void sparx5_mact_init(struct sparx5 *sparx5); 346 347 /* sparx5_vlan.c */ 348 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 349 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid); 350 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); 351 void sparx5_update_fwd(struct sparx5 *sparx5); 352 void sparx5_vlan_init(struct sparx5 *sparx5); 353 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 354 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 355 bool untagged); 356 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 357 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 358 359 /* sparx5_calendar.c */ 360 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 361 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 362 363 /* sparx5_ethtool.c */ 364 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 365 int sparx_stats_init(struct sparx5 *sparx5); 366 367 /* sparx5_dcb.c */ 368 #ifdef CONFIG_SPARX5_DCB 369 int sparx5_dcb_init(struct sparx5 *sparx5); 370 #else 371 static inline int sparx5_dcb_init(struct sparx5 *sparx5) 372 { 373 return 0; 374 } 375 #endif 376 377 /* sparx5_netdev.c */ 378 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 379 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 380 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 381 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 382 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 383 bool sparx5_netdevice_check(const struct net_device *dev); 384 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 385 int sparx5_register_netdevs(struct sparx5 *sparx5); 386 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 387 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 388 389 /* sparx5_ptp.c */ 390 int sparx5_ptp_init(struct sparx5 *sparx5); 391 void sparx5_ptp_deinit(struct sparx5 *sparx5); 392 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, 393 struct kernel_hwtstamp_config *cfg, 394 struct netlink_ext_ack *extack); 395 void sparx5_ptp_hwtstamp_get(struct sparx5_port *port, 396 struct kernel_hwtstamp_config *cfg); 397 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 398 u64 timestamp); 399 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 400 struct sk_buff *skb); 401 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 402 struct sk_buff *skb); 403 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 404 int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); 405 406 /* sparx5_vcap_impl.c */ 407 int sparx5_vcap_init(struct sparx5 *sparx5); 408 void sparx5_vcap_destroy(struct sparx5 *sparx5); 409 410 /* sparx5_pgid.c */ 411 enum sparx5_pgid_type { 412 SPX5_PGID_FREE, 413 SPX5_PGID_RESERVED, 414 SPX5_PGID_MULTICAST, 415 }; 416 417 void sparx5_pgid_init(struct sparx5 *spx5); 418 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 419 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 420 421 /* sparx5_pool.c */ 422 struct sparx5_pool_entry { 423 u16 ref_cnt; 424 u32 idx; /* tc index */ 425 }; 426 427 u32 sparx5_pool_idx_to_id(u32 idx); 428 int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id); 429 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); 430 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 431 u32 *id); 432 433 /* sparx5_sdlb.c */ 434 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF 435 #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) 436 #define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL 437 #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13 438 #define SPX5_SDLB_CNT 4096 439 #define SPX5_SDLB_GROUP_CNT 10 440 #define SPX5_CLK_PER_100PS_DEFAULT 16 441 442 struct sparx5_sdlb_group { 443 u64 max_rate; 444 u32 min_burst; 445 u32 frame_size; 446 u32 pup_interval; 447 u32 nsets; 448 }; 449 450 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; 451 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, 452 u64 rate); 453 454 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); 455 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); 456 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); 457 458 int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx); 459 int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx); 460 461 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, 462 u32 frame_size, u32 idx); 463 464 /* sparx5_police.c */ 465 enum { 466 /* More policer types will be added later */ 467 SPX5_POL_SERVICE 468 }; 469 470 struct sparx5_policer { 471 u32 type; 472 u32 idx; 473 u64 rate; 474 u32 burst; 475 u32 group; 476 u8 event_mask; 477 }; 478 479 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol); 480 481 /* sparx5_psfp.c */ 482 #define SPX5_PSFP_GCE_CNT 4 483 #define SPX5_PSFP_SG_CNT 1024 484 #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC) 485 #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1) 486 #define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1) 487 #define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1) 488 #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000 489 #define SPX5_PSFP_SF_MAX_SDU 16383 490 491 struct sparx5_psfp_fm { 492 struct sparx5_policer pol; 493 }; 494 495 struct sparx5_psfp_gce { 496 bool gate_state; /* StreamGateState */ 497 u32 interval; /* TimeInterval */ 498 u32 ipv; /* InternalPriorityValue */ 499 u32 maxoctets; /* IntervalOctetMax */ 500 }; 501 502 struct sparx5_psfp_sg { 503 bool gate_state; /* PSFPAdminGateStates */ 504 bool gate_enabled; /* PSFPGateEnabled */ 505 u32 ipv; /* PSFPAdminIPV */ 506 struct timespec64 basetime; /* PSFPAdminBaseTime */ 507 u32 cycletime; /* PSFPAdminCycleTime */ 508 u32 cycletimeext; /* PSFPAdminCycleTimeExtension */ 509 u32 num_entries; /* PSFPAdminControlListLength */ 510 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; 511 }; 512 513 struct sparx5_psfp_sf { 514 bool sblock_osize_ena; 515 bool sblock_osize; 516 u32 max_sdu; 517 u32 sgid; /* Gate id */ 518 u32 fmid; /* Flow meter id */ 519 }; 520 521 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, 522 struct sparx5_psfp_fm *fm, u32 *id); 523 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id); 524 525 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, 526 struct sparx5_psfp_sg *sg, u32 *id); 527 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id); 528 529 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, 530 u32 *id); 531 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id); 532 533 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx); 534 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx); 535 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid); 536 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid); 537 538 void sparx5_psfp_init(struct sparx5 *sparx5); 539 540 /* sparx5_qos.c */ 541 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, 542 const ktime_t org_base_time, ktime_t *new_base_time); 543 544 /* Clock period in picoseconds */ 545 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 546 { 547 switch (cclock) { 548 case SPX5_CORE_CLOCK_250MHZ: 549 return 4000; 550 case SPX5_CORE_CLOCK_500MHZ: 551 return 2000; 552 case SPX5_CORE_CLOCK_625MHZ: 553 default: 554 return 1600; 555 } 556 } 557 558 static inline bool sparx5_is_baser(phy_interface_t interface) 559 { 560 return interface == PHY_INTERFACE_MODE_5GBASER || 561 interface == PHY_INTERFACE_MODE_10GBASER || 562 interface == PHY_INTERFACE_MODE_25GBASER; 563 } 564 565 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 566 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 567 extern const struct ethtool_ops sparx5_ethtool_ops; 568 extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops; 569 570 /* Calculate raw offset */ 571 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 572 int gbase, int ginst, 573 int gcnt, int gwidth, 574 int raddr, int rinst, 575 int rcnt, int rwidth) 576 { 577 WARN_ON((tinst) >= tcnt); 578 WARN_ON((ginst) >= gcnt); 579 WARN_ON((rinst) >= rcnt); 580 return gbase + ((ginst) * gwidth) + 581 raddr + ((rinst) * rwidth); 582 } 583 584 /* Read, Write and modify registers content. 585 * The register definition macros start at the id 586 */ 587 static inline void __iomem *spx5_addr(void __iomem *base[], 588 int id, int tinst, int tcnt, 589 int gbase, int ginst, 590 int gcnt, int gwidth, 591 int raddr, int rinst, 592 int rcnt, int rwidth) 593 { 594 WARN_ON((tinst) >= tcnt); 595 WARN_ON((ginst) >= gcnt); 596 WARN_ON((rinst) >= rcnt); 597 return base[id + (tinst)] + 598 gbase + ((ginst) * gwidth) + 599 raddr + ((rinst) * rwidth); 600 } 601 602 static inline void __iomem *spx5_inst_addr(void __iomem *base, 603 int gbase, int ginst, 604 int gcnt, int gwidth, 605 int raddr, int rinst, 606 int rcnt, int rwidth) 607 { 608 WARN_ON((ginst) >= gcnt); 609 WARN_ON((rinst) >= rcnt); 610 return base + 611 gbase + ((ginst) * gwidth) + 612 raddr + ((rinst) * rwidth); 613 } 614 615 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 616 int gbase, int ginst, int gcnt, int gwidth, 617 int raddr, int rinst, int rcnt, int rwidth) 618 { 619 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 620 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 621 } 622 623 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 624 int gbase, int ginst, int gcnt, int gwidth, 625 int raddr, int rinst, int rcnt, int rwidth) 626 { 627 return readl(spx5_inst_addr(iomem, gbase, ginst, 628 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 629 } 630 631 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 632 int id, int tinst, int tcnt, 633 int gbase, int ginst, int gcnt, int gwidth, 634 int raddr, int rinst, int rcnt, int rwidth) 635 { 636 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 637 gbase, ginst, gcnt, gwidth, 638 raddr, rinst, rcnt, rwidth)); 639 } 640 641 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 642 int id, int tinst, int tcnt, 643 int gbase, int ginst, int gcnt, int gwidth, 644 int raddr, int rinst, int rcnt, int rwidth) 645 { 646 writel(val, spx5_inst_addr(iomem, 647 gbase, ginst, gcnt, gwidth, 648 raddr, rinst, rcnt, rwidth)); 649 } 650 651 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 652 int id, int tinst, int tcnt, 653 int gbase, int ginst, int gcnt, int gwidth, 654 int raddr, int rinst, int rcnt, int rwidth) 655 { 656 u32 nval; 657 658 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 659 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 660 nval = (nval & ~mask) | (val & mask); 661 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 662 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 663 } 664 665 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 666 int id, int tinst, int tcnt, 667 int gbase, int ginst, int gcnt, int gwidth, 668 int raddr, int rinst, int rcnt, int rwidth) 669 { 670 u32 nval; 671 672 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 673 rinst, rcnt, rwidth)); 674 nval = (nval & ~mask) | (val & mask); 675 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 676 rinst, rcnt, rwidth)); 677 } 678 679 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 680 { 681 return sparx5->regs[id + tinst]; 682 } 683 684 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 685 int id, int tinst, int tcnt, 686 int gbase, int ginst, int gcnt, int gwidth, 687 int raddr, int rinst, int rcnt, int rwidth) 688 { 689 return spx5_addr(sparx5->regs, id, tinst, tcnt, 690 gbase, ginst, gcnt, gwidth, 691 raddr, rinst, rcnt, rwidth); 692 } 693 694 #endif /* __SPARX5_MAIN_H__ */ 695