1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 21 #include "sparx5_main_regs.h" 22 23 /* Target chip type */ 24 enum spx5_target_chiptype { 25 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 26 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 27 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 28 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 29 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 30 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 31 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 32 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 33 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 34 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 35 }; 36 37 enum sparx5_port_max_tags { 38 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 39 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 40 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 41 }; 42 43 enum sparx5_vlan_port_type { 44 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 45 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 46 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 47 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 48 }; 49 50 #define SPX5_PORTS 65 51 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 52 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 53 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 54 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 55 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 56 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 57 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 58 59 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 60 #define PGID_UC_FLOOD (PGID_BASE + 0) 61 #define PGID_MC_FLOOD (PGID_BASE + 1) 62 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 63 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 64 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 65 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 66 #define PGID_BCAST (PGID_BASE + 6) 67 #define PGID_CPU (PGID_BASE + 7) 68 69 #define IFH_LEN 9 /* 36 bytes */ 70 #define NULL_VID 0 71 #define SPX5_MACT_PULL_DELAY (2 * HZ) 72 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 73 #define SPX5_PRIOS 8 /* Number of priority queues */ 74 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 75 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 76 77 #define XTR_QUEUE 0 78 #define INJ_QUEUE 0 79 80 #define FDMA_DCB_MAX 64 81 #define FDMA_RX_DCB_MAX_DBS 15 82 #define FDMA_TX_DCB_MAX_DBS 1 83 84 #define SPARX5_PHC_COUNT 3 85 #define SPARX5_PHC_PORT 0 86 87 #define IFH_REW_OP_NOOP 0x0 88 #define IFH_REW_OP_ONE_STEP_PTP 0x3 89 #define IFH_REW_OP_TWO_STEP_PTP 0x4 90 91 #define IFH_PDU_TYPE_NONE 0x0 92 #define IFH_PDU_TYPE_PTP 0x5 93 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 94 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 95 96 struct sparx5; 97 98 struct sparx5_db_hw { 99 u64 dataptr; 100 u64 status; 101 }; 102 103 struct sparx5_rx_dcb_hw { 104 u64 nextptr; 105 u64 info; 106 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 107 }; 108 109 struct sparx5_tx_dcb_hw { 110 u64 nextptr; 111 u64 info; 112 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 113 }; 114 115 /* Frame DMA receive state: 116 * For each DB, there is a SKB, and the skb data pointer is mapped in 117 * the DB. Once a frame is received the skb is given to the upper layers 118 * and a new skb is added to the dcb. 119 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 120 */ 121 struct sparx5_rx { 122 struct sparx5_rx_dcb_hw *dcb_entries; 123 struct sparx5_rx_dcb_hw *last_entry; 124 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 125 int db_index; 126 int dcb_index; 127 dma_addr_t dma; 128 struct napi_struct napi; 129 u32 channel_id; 130 struct net_device *ndev; 131 u64 packets; 132 }; 133 134 /* Frame DMA transmit state: 135 * DCBs are chained using the DCBs nextptr field. 136 */ 137 struct sparx5_tx { 138 struct sparx5_tx_dcb_hw *curr_entry; 139 struct sparx5_tx_dcb_hw *first_entry; 140 struct list_head db_list; 141 dma_addr_t dma; 142 u32 channel_id; 143 u64 packets; 144 u64 dropped; 145 }; 146 147 struct sparx5_port_config { 148 phy_interface_t portmode; 149 u32 bandwidth; 150 int speed; 151 int duplex; 152 enum phy_media media; 153 bool inband; 154 bool power_down; 155 bool autoneg; 156 bool serdes_reset; 157 u32 pause; 158 u32 pause_adv; 159 phy_interface_t phy_mode; 160 u32 sd_sgpio; 161 }; 162 163 struct sparx5_port { 164 struct net_device *ndev; 165 struct sparx5 *sparx5; 166 struct device_node *of_node; 167 struct phy *serdes; 168 struct sparx5_port_config conf; 169 struct phylink_config phylink_config; 170 struct phylink *phylink; 171 struct phylink_pcs phylink_pcs; 172 u16 portno; 173 /* Ingress default VLAN (pvid) */ 174 u16 pvid; 175 /* Egress default VLAN (vid) */ 176 u16 vid; 177 bool signd_internal; 178 bool signd_active_high; 179 bool signd_enable; 180 bool flow_control; 181 enum sparx5_port_max_tags max_vlan_tags; 182 enum sparx5_vlan_port_type vlan_type; 183 u32 custom_etype; 184 bool vlan_aware; 185 struct hrtimer inj_timer; 186 /* ptp */ 187 u8 ptp_cmd; 188 u16 ts_id; 189 struct sk_buff_head tx_skbs; 190 }; 191 192 enum sparx5_core_clockfreq { 193 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 194 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 195 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 196 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 197 }; 198 199 struct sparx5_phc { 200 struct ptp_clock *clock; 201 struct ptp_clock_info info; 202 struct hwtstamp_config hwtstamp_config; 203 struct sparx5 *sparx5; 204 u8 index; 205 }; 206 207 struct sparx5_skb_cb { 208 u8 rew_op; 209 u8 pdu_type; 210 u8 pdu_w16_offset; 211 u16 ts_id; 212 unsigned long jiffies; 213 }; 214 215 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 216 #define SPARX5_SKB_CB(skb) \ 217 ((struct sparx5_skb_cb *)((skb)->cb)) 218 219 struct sparx5 { 220 struct platform_device *pdev; 221 struct device *dev; 222 u32 chip_id; 223 enum spx5_target_chiptype target_ct; 224 void __iomem *regs[NUM_TARGETS]; 225 int port_count; 226 struct mutex lock; /* MAC reg lock */ 227 /* port structures are in net device */ 228 struct sparx5_port *ports[SPX5_PORTS]; 229 enum sparx5_core_clockfreq coreclock; 230 /* Statistics */ 231 u32 num_stats; 232 u32 num_ethtool_stats; 233 const char * const *stats_layout; 234 u64 *stats; 235 /* Workqueue for reading stats */ 236 struct mutex queue_stats_lock; 237 struct delayed_work stats_work; 238 struct workqueue_struct *stats_queue; 239 /* Notifiers */ 240 struct notifier_block netdevice_nb; 241 struct notifier_block switchdev_nb; 242 struct notifier_block switchdev_blocking_nb; 243 /* Switch state */ 244 u8 base_mac[ETH_ALEN]; 245 /* Associated bridge device (when bridged) */ 246 struct net_device *hw_bridge_dev; 247 /* Bridged interfaces */ 248 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 249 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 250 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 251 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 252 /* SW MAC table */ 253 struct list_head mact_entries; 254 /* mac table list (mact_entries) mutex */ 255 struct mutex mact_lock; 256 struct delayed_work mact_work; 257 struct workqueue_struct *mact_queue; 258 /* Board specifics */ 259 bool sd_sgpio_remapping; 260 /* Register based inj/xtr */ 261 int xtr_irq; 262 /* Frame DMA */ 263 int fdma_irq; 264 struct sparx5_rx rx; 265 struct sparx5_tx tx; 266 /* PTP */ 267 bool ptp; 268 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 269 spinlock_t ptp_clock_lock; /* lock for phc */ 270 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 271 struct mutex ptp_lock; /* lock for ptp interface state */ 272 u16 ptp_skbs; 273 int ptp_irq; 274 }; 275 276 /* sparx5_switchdev.c */ 277 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 278 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 279 280 /* sparx5_packet.c */ 281 struct frame_info { 282 int src_port; 283 u32 timestamp; 284 }; 285 286 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 287 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 288 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 289 int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 290 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 291 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 292 293 /* sparx5_fdma.c */ 294 int sparx5_fdma_start(struct sparx5 *sparx5); 295 int sparx5_fdma_stop(struct sparx5 *sparx5); 296 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 297 irqreturn_t sparx5_fdma_handler(int irq, void *args); 298 299 /* sparx5_mactable.c */ 300 void sparx5_mact_pull_work(struct work_struct *work); 301 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 302 const unsigned char mac[ETH_ALEN], u16 vid); 303 bool sparx5_mact_getnext(struct sparx5 *sparx5, 304 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 305 int sparx5_mact_forget(struct sparx5 *sparx5, 306 const unsigned char mac[ETH_ALEN], u16 vid); 307 int sparx5_add_mact_entry(struct sparx5 *sparx5, 308 struct net_device *dev, 309 u16 portno, 310 const unsigned char *addr, u16 vid); 311 int sparx5_del_mact_entry(struct sparx5 *sparx5, 312 const unsigned char *addr, 313 u16 vid); 314 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 315 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 316 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 317 void sparx5_mact_init(struct sparx5 *sparx5); 318 319 /* sparx5_vlan.c */ 320 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 321 void sparx5_update_fwd(struct sparx5 *sparx5); 322 void sparx5_vlan_init(struct sparx5 *sparx5); 323 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 324 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 325 bool untagged); 326 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 327 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 328 329 /* sparx5_calendar.c */ 330 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 331 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 332 333 /* sparx5_ethtool.c */ 334 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 335 int sparx_stats_init(struct sparx5 *sparx5); 336 337 /* sparx5_netdev.c */ 338 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 339 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 340 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 341 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 342 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 343 bool sparx5_netdevice_check(const struct net_device *dev); 344 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 345 int sparx5_register_netdevs(struct sparx5 *sparx5); 346 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 347 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 348 349 /* sparx5_ptp.c */ 350 int sparx5_ptp_init(struct sparx5 *sparx5); 351 void sparx5_ptp_deinit(struct sparx5 *sparx5); 352 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr); 353 int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr); 354 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 355 u64 timestamp); 356 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 357 struct sk_buff *skb); 358 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 359 struct sk_buff *skb); 360 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 361 362 /* Clock period in picoseconds */ 363 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 364 { 365 switch (cclock) { 366 case SPX5_CORE_CLOCK_250MHZ: 367 return 4000; 368 case SPX5_CORE_CLOCK_500MHZ: 369 return 2000; 370 case SPX5_CORE_CLOCK_625MHZ: 371 default: 372 return 1600; 373 } 374 } 375 376 static inline bool sparx5_is_baser(phy_interface_t interface) 377 { 378 return interface == PHY_INTERFACE_MODE_5GBASER || 379 interface == PHY_INTERFACE_MODE_10GBASER || 380 interface == PHY_INTERFACE_MODE_25GBASER; 381 } 382 383 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 384 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 385 extern const struct ethtool_ops sparx5_ethtool_ops; 386 387 /* Calculate raw offset */ 388 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 389 int gbase, int ginst, 390 int gcnt, int gwidth, 391 int raddr, int rinst, 392 int rcnt, int rwidth) 393 { 394 WARN_ON((tinst) >= tcnt); 395 WARN_ON((ginst) >= gcnt); 396 WARN_ON((rinst) >= rcnt); 397 return gbase + ((ginst) * gwidth) + 398 raddr + ((rinst) * rwidth); 399 } 400 401 /* Read, Write and modify registers content. 402 * The register definition macros start at the id 403 */ 404 static inline void __iomem *spx5_addr(void __iomem *base[], 405 int id, int tinst, int tcnt, 406 int gbase, int ginst, 407 int gcnt, int gwidth, 408 int raddr, int rinst, 409 int rcnt, int rwidth) 410 { 411 WARN_ON((tinst) >= tcnt); 412 WARN_ON((ginst) >= gcnt); 413 WARN_ON((rinst) >= rcnt); 414 return base[id + (tinst)] + 415 gbase + ((ginst) * gwidth) + 416 raddr + ((rinst) * rwidth); 417 } 418 419 static inline void __iomem *spx5_inst_addr(void __iomem *base, 420 int gbase, int ginst, 421 int gcnt, int gwidth, 422 int raddr, int rinst, 423 int rcnt, int rwidth) 424 { 425 WARN_ON((ginst) >= gcnt); 426 WARN_ON((rinst) >= rcnt); 427 return base + 428 gbase + ((ginst) * gwidth) + 429 raddr + ((rinst) * rwidth); 430 } 431 432 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 433 int gbase, int ginst, int gcnt, int gwidth, 434 int raddr, int rinst, int rcnt, int rwidth) 435 { 436 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 437 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 438 } 439 440 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 441 int gbase, int ginst, int gcnt, int gwidth, 442 int raddr, int rinst, int rcnt, int rwidth) 443 { 444 return readl(spx5_inst_addr(iomem, gbase, ginst, 445 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 446 } 447 448 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 449 int id, int tinst, int tcnt, 450 int gbase, int ginst, int gcnt, int gwidth, 451 int raddr, int rinst, int rcnt, int rwidth) 452 { 453 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 454 gbase, ginst, gcnt, gwidth, 455 raddr, rinst, rcnt, rwidth)); 456 } 457 458 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 459 int id, int tinst, int tcnt, 460 int gbase, int ginst, int gcnt, int gwidth, 461 int raddr, int rinst, int rcnt, int rwidth) 462 { 463 writel(val, spx5_inst_addr(iomem, 464 gbase, ginst, gcnt, gwidth, 465 raddr, rinst, rcnt, rwidth)); 466 } 467 468 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 469 int id, int tinst, int tcnt, 470 int gbase, int ginst, int gcnt, int gwidth, 471 int raddr, int rinst, int rcnt, int rwidth) 472 { 473 u32 nval; 474 475 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 476 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 477 nval = (nval & ~mask) | (val & mask); 478 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 479 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 480 } 481 482 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 483 int id, int tinst, int tcnt, 484 int gbase, int ginst, int gcnt, int gwidth, 485 int raddr, int rinst, int rcnt, int rwidth) 486 { 487 u32 nval; 488 489 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 490 rinst, rcnt, rwidth)); 491 nval = (nval & ~mask) | (val & mask); 492 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 493 rinst, rcnt, rwidth)); 494 } 495 496 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 497 { 498 return sparx5->regs[id + tinst]; 499 } 500 501 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 502 int id, int tinst, int tcnt, 503 int gbase, int ginst, int gcnt, int gwidth, 504 int raddr, int rinst, int rcnt, int rwidth) 505 { 506 return spx5_addr(sparx5->regs, id, tinst, tcnt, 507 gbase, ginst, gcnt, gwidth, 508 raddr, rinst, rcnt, rwidth); 509 } 510 511 #endif /* __SPARX5_MAIN_H__ */ 512