1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 21 #include "sparx5_main_regs.h" 22 23 /* Target chip type */ 24 enum spx5_target_chiptype { 25 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 26 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 27 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 28 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 29 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 30 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 31 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 32 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 33 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 34 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 35 }; 36 37 enum sparx5_port_max_tags { 38 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 39 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 40 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 41 }; 42 43 enum sparx5_vlan_port_type { 44 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 45 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 46 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 47 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 48 }; 49 50 #define SPX5_PORTS 65 51 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 52 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 53 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 54 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 55 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 56 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 57 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 58 59 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 60 #define PGID_UC_FLOOD (PGID_BASE + 0) 61 #define PGID_MC_FLOOD (PGID_BASE + 1) 62 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 63 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 64 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 65 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 66 #define PGID_BCAST (PGID_BASE + 6) 67 #define PGID_CPU (PGID_BASE + 7) 68 #define PGID_MCAST_START (PGID_BASE + 8) 69 70 #define PGID_TABLE_SIZE 3290 71 72 #define IFH_LEN 9 /* 36 bytes */ 73 #define NULL_VID 0 74 #define SPX5_MACT_PULL_DELAY (2 * HZ) 75 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 76 #define SPX5_PRIOS 8 /* Number of priority queues */ 77 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 78 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 79 80 #define XTR_QUEUE 0 81 #define INJ_QUEUE 0 82 83 #define FDMA_DCB_MAX 64 84 #define FDMA_RX_DCB_MAX_DBS 15 85 #define FDMA_TX_DCB_MAX_DBS 1 86 87 #define SPARX5_PHC_COUNT 3 88 #define SPARX5_PHC_PORT 0 89 90 #define IFH_REW_OP_NOOP 0x0 91 #define IFH_REW_OP_ONE_STEP_PTP 0x3 92 #define IFH_REW_OP_TWO_STEP_PTP 0x4 93 94 #define IFH_PDU_TYPE_NONE 0x0 95 #define IFH_PDU_TYPE_PTP 0x5 96 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 97 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 98 99 struct sparx5; 100 101 struct sparx5_db_hw { 102 u64 dataptr; 103 u64 status; 104 }; 105 106 struct sparx5_rx_dcb_hw { 107 u64 nextptr; 108 u64 info; 109 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 110 }; 111 112 struct sparx5_tx_dcb_hw { 113 u64 nextptr; 114 u64 info; 115 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 116 }; 117 118 /* Frame DMA receive state: 119 * For each DB, there is a SKB, and the skb data pointer is mapped in 120 * the DB. Once a frame is received the skb is given to the upper layers 121 * and a new skb is added to the dcb. 122 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 123 */ 124 struct sparx5_rx { 125 struct sparx5_rx_dcb_hw *dcb_entries; 126 struct sparx5_rx_dcb_hw *last_entry; 127 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 128 int db_index; 129 int dcb_index; 130 dma_addr_t dma; 131 struct napi_struct napi; 132 u32 channel_id; 133 struct net_device *ndev; 134 u64 packets; 135 }; 136 137 /* Frame DMA transmit state: 138 * DCBs are chained using the DCBs nextptr field. 139 */ 140 struct sparx5_tx { 141 struct sparx5_tx_dcb_hw *curr_entry; 142 struct sparx5_tx_dcb_hw *first_entry; 143 struct list_head db_list; 144 dma_addr_t dma; 145 u32 channel_id; 146 u64 packets; 147 u64 dropped; 148 }; 149 150 struct sparx5_port_config { 151 phy_interface_t portmode; 152 u32 bandwidth; 153 int speed; 154 int duplex; 155 enum phy_media media; 156 bool inband; 157 bool power_down; 158 bool autoneg; 159 bool serdes_reset; 160 u32 pause; 161 u32 pause_adv; 162 phy_interface_t phy_mode; 163 u32 sd_sgpio; 164 }; 165 166 struct sparx5_port { 167 struct net_device *ndev; 168 struct sparx5 *sparx5; 169 struct device_node *of_node; 170 struct phy *serdes; 171 struct sparx5_port_config conf; 172 struct phylink_config phylink_config; 173 struct phylink *phylink; 174 struct phylink_pcs phylink_pcs; 175 u16 portno; 176 /* Ingress default VLAN (pvid) */ 177 u16 pvid; 178 /* Egress default VLAN (vid) */ 179 u16 vid; 180 bool signd_internal; 181 bool signd_active_high; 182 bool signd_enable; 183 bool flow_control; 184 enum sparx5_port_max_tags max_vlan_tags; 185 enum sparx5_vlan_port_type vlan_type; 186 u32 custom_etype; 187 bool vlan_aware; 188 struct hrtimer inj_timer; 189 /* ptp */ 190 u8 ptp_cmd; 191 u16 ts_id; 192 struct sk_buff_head tx_skbs; 193 }; 194 195 enum sparx5_core_clockfreq { 196 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 197 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 198 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 199 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 200 }; 201 202 struct sparx5_phc { 203 struct ptp_clock *clock; 204 struct ptp_clock_info info; 205 struct hwtstamp_config hwtstamp_config; 206 struct sparx5 *sparx5; 207 u8 index; 208 }; 209 210 struct sparx5_skb_cb { 211 u8 rew_op; 212 u8 pdu_type; 213 u8 pdu_w16_offset; 214 u16 ts_id; 215 unsigned long jiffies; 216 }; 217 218 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 219 #define SPARX5_SKB_CB(skb) \ 220 ((struct sparx5_skb_cb *)((skb)->cb)) 221 222 struct sparx5 { 223 struct platform_device *pdev; 224 struct device *dev; 225 u32 chip_id; 226 enum spx5_target_chiptype target_ct; 227 void __iomem *regs[NUM_TARGETS]; 228 int port_count; 229 struct mutex lock; /* MAC reg lock */ 230 /* port structures are in net device */ 231 struct sparx5_port *ports[SPX5_PORTS]; 232 enum sparx5_core_clockfreq coreclock; 233 /* Statistics */ 234 u32 num_stats; 235 u32 num_ethtool_stats; 236 const char * const *stats_layout; 237 u64 *stats; 238 /* Workqueue for reading stats */ 239 struct mutex queue_stats_lock; 240 struct delayed_work stats_work; 241 struct workqueue_struct *stats_queue; 242 /* Notifiers */ 243 struct notifier_block netdevice_nb; 244 struct notifier_block switchdev_nb; 245 struct notifier_block switchdev_blocking_nb; 246 /* Switch state */ 247 u8 base_mac[ETH_ALEN]; 248 /* Associated bridge device (when bridged) */ 249 struct net_device *hw_bridge_dev; 250 /* Bridged interfaces */ 251 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 252 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 253 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 254 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 255 /* SW MAC table */ 256 struct list_head mact_entries; 257 /* mac table list (mact_entries) mutex */ 258 struct mutex mact_lock; 259 struct delayed_work mact_work; 260 struct workqueue_struct *mact_queue; 261 /* Board specifics */ 262 bool sd_sgpio_remapping; 263 /* Register based inj/xtr */ 264 int xtr_irq; 265 /* Frame DMA */ 266 int fdma_irq; 267 struct sparx5_rx rx; 268 struct sparx5_tx tx; 269 /* PTP */ 270 bool ptp; 271 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 272 spinlock_t ptp_clock_lock; /* lock for phc */ 273 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 274 struct mutex ptp_lock; /* lock for ptp interface state */ 275 u16 ptp_skbs; 276 int ptp_irq; 277 /* PGID allocation map */ 278 u8 pgid_map[PGID_TABLE_SIZE]; 279 }; 280 281 /* sparx5_switchdev.c */ 282 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 283 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 284 285 /* sparx5_packet.c */ 286 struct frame_info { 287 int src_port; 288 u32 timestamp; 289 }; 290 291 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 292 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 293 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 294 int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 295 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 296 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 297 298 /* sparx5_fdma.c */ 299 int sparx5_fdma_start(struct sparx5 *sparx5); 300 int sparx5_fdma_stop(struct sparx5 *sparx5); 301 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 302 irqreturn_t sparx5_fdma_handler(int irq, void *args); 303 304 /* sparx5_mactable.c */ 305 void sparx5_mact_pull_work(struct work_struct *work); 306 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 307 const unsigned char mac[ETH_ALEN], u16 vid); 308 bool sparx5_mact_getnext(struct sparx5 *sparx5, 309 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 310 bool sparx5_mact_find(struct sparx5 *sparx5, 311 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 312 int sparx5_mact_forget(struct sparx5 *sparx5, 313 const unsigned char mac[ETH_ALEN], u16 vid); 314 int sparx5_add_mact_entry(struct sparx5 *sparx5, 315 struct net_device *dev, 316 u16 portno, 317 const unsigned char *addr, u16 vid); 318 int sparx5_del_mact_entry(struct sparx5 *sparx5, 319 const unsigned char *addr, 320 u16 vid); 321 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 322 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 323 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 324 void sparx5_mact_init(struct sparx5 *sparx5); 325 326 /* sparx5_vlan.c */ 327 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 328 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); 329 void sparx5_update_fwd(struct sparx5 *sparx5); 330 void sparx5_vlan_init(struct sparx5 *sparx5); 331 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 332 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 333 bool untagged); 334 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 335 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 336 337 /* sparx5_calendar.c */ 338 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 339 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 340 341 /* sparx5_ethtool.c */ 342 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 343 int sparx_stats_init(struct sparx5 *sparx5); 344 345 /* sparx5_netdev.c */ 346 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 347 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 348 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 349 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 350 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 351 bool sparx5_netdevice_check(const struct net_device *dev); 352 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 353 int sparx5_register_netdevs(struct sparx5 *sparx5); 354 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 355 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 356 357 /* sparx5_ptp.c */ 358 int sparx5_ptp_init(struct sparx5 *sparx5); 359 void sparx5_ptp_deinit(struct sparx5 *sparx5); 360 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr); 361 int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr); 362 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 363 u64 timestamp); 364 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 365 struct sk_buff *skb); 366 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 367 struct sk_buff *skb); 368 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 369 370 /* sparx5_pgid.c */ 371 enum sparx5_pgid_type { 372 SPX5_PGID_FREE, 373 SPX5_PGID_RESERVED, 374 SPX5_PGID_MULTICAST, 375 }; 376 377 void sparx5_pgid_init(struct sparx5 *spx5); 378 int sparx5_pgid_alloc_glag(struct sparx5 *spx5, u16 *idx); 379 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 380 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 381 382 /* Clock period in picoseconds */ 383 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 384 { 385 switch (cclock) { 386 case SPX5_CORE_CLOCK_250MHZ: 387 return 4000; 388 case SPX5_CORE_CLOCK_500MHZ: 389 return 2000; 390 case SPX5_CORE_CLOCK_625MHZ: 391 default: 392 return 1600; 393 } 394 } 395 396 static inline bool sparx5_is_baser(phy_interface_t interface) 397 { 398 return interface == PHY_INTERFACE_MODE_5GBASER || 399 interface == PHY_INTERFACE_MODE_10GBASER || 400 interface == PHY_INTERFACE_MODE_25GBASER; 401 } 402 403 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 404 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 405 extern const struct ethtool_ops sparx5_ethtool_ops; 406 407 /* Calculate raw offset */ 408 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 409 int gbase, int ginst, 410 int gcnt, int gwidth, 411 int raddr, int rinst, 412 int rcnt, int rwidth) 413 { 414 WARN_ON((tinst) >= tcnt); 415 WARN_ON((ginst) >= gcnt); 416 WARN_ON((rinst) >= rcnt); 417 return gbase + ((ginst) * gwidth) + 418 raddr + ((rinst) * rwidth); 419 } 420 421 /* Read, Write and modify registers content. 422 * The register definition macros start at the id 423 */ 424 static inline void __iomem *spx5_addr(void __iomem *base[], 425 int id, int tinst, int tcnt, 426 int gbase, int ginst, 427 int gcnt, int gwidth, 428 int raddr, int rinst, 429 int rcnt, int rwidth) 430 { 431 WARN_ON((tinst) >= tcnt); 432 WARN_ON((ginst) >= gcnt); 433 WARN_ON((rinst) >= rcnt); 434 return base[id + (tinst)] + 435 gbase + ((ginst) * gwidth) + 436 raddr + ((rinst) * rwidth); 437 } 438 439 static inline void __iomem *spx5_inst_addr(void __iomem *base, 440 int gbase, int ginst, 441 int gcnt, int gwidth, 442 int raddr, int rinst, 443 int rcnt, int rwidth) 444 { 445 WARN_ON((ginst) >= gcnt); 446 WARN_ON((rinst) >= rcnt); 447 return base + 448 gbase + ((ginst) * gwidth) + 449 raddr + ((rinst) * rwidth); 450 } 451 452 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 453 int gbase, int ginst, int gcnt, int gwidth, 454 int raddr, int rinst, int rcnt, int rwidth) 455 { 456 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 457 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 458 } 459 460 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 461 int gbase, int ginst, int gcnt, int gwidth, 462 int raddr, int rinst, int rcnt, int rwidth) 463 { 464 return readl(spx5_inst_addr(iomem, gbase, ginst, 465 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 466 } 467 468 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 469 int id, int tinst, int tcnt, 470 int gbase, int ginst, int gcnt, int gwidth, 471 int raddr, int rinst, int rcnt, int rwidth) 472 { 473 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 474 gbase, ginst, gcnt, gwidth, 475 raddr, rinst, rcnt, rwidth)); 476 } 477 478 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 479 int id, int tinst, int tcnt, 480 int gbase, int ginst, int gcnt, int gwidth, 481 int raddr, int rinst, int rcnt, int rwidth) 482 { 483 writel(val, spx5_inst_addr(iomem, 484 gbase, ginst, gcnt, gwidth, 485 raddr, rinst, rcnt, rwidth)); 486 } 487 488 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 489 int id, int tinst, int tcnt, 490 int gbase, int ginst, int gcnt, int gwidth, 491 int raddr, int rinst, int rcnt, int rwidth) 492 { 493 u32 nval; 494 495 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 496 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 497 nval = (nval & ~mask) | (val & mask); 498 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 499 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 500 } 501 502 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 503 int id, int tinst, int tcnt, 504 int gbase, int ginst, int gcnt, int gwidth, 505 int raddr, int rinst, int rcnt, int rwidth) 506 { 507 u32 nval; 508 509 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 510 rinst, rcnt, rwidth)); 511 nval = (nval & ~mask) | (val & mask); 512 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 513 rinst, rcnt, rwidth)); 514 } 515 516 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 517 { 518 return sparx5->regs[id + tinst]; 519 } 520 521 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 522 int id, int tinst, int tcnt, 523 int gbase, int ginst, int gcnt, int gwidth, 524 int raddr, int rinst, int rcnt, int rwidth) 525 { 526 return spx5_addr(sparx5->regs, id, tinst, tcnt, 527 gbase, ginst, gcnt, gwidth, 528 raddr, rinst, rcnt, rwidth); 529 } 530 531 #endif /* __SPARX5_MAIN_H__ */ 532