1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 21 #include "sparx5_main_regs.h" 22 23 /* Target chip type */ 24 enum spx5_target_chiptype { 25 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 26 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 27 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 28 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 29 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 30 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 31 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 32 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 33 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 34 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 35 }; 36 37 enum sparx5_port_max_tags { 38 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 39 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 40 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 41 }; 42 43 enum sparx5_vlan_port_type { 44 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 45 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 46 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 47 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 48 }; 49 50 #define SPX5_PORTS 65 51 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 52 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 53 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 54 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 55 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 56 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 57 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 58 59 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 60 #define PGID_UC_FLOOD (PGID_BASE + 0) 61 #define PGID_MC_FLOOD (PGID_BASE + 1) 62 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 63 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 64 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 65 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 66 #define PGID_BCAST (PGID_BASE + 6) 67 #define PGID_CPU (PGID_BASE + 7) 68 69 #define PGID_TABLE_SIZE 3290 70 71 #define PGID_MCAST_START 65 72 #define PGID_GLAG_START 833 73 #define PGID_GLAG_END 1088 74 75 #define IFH_LEN 9 /* 36 bytes */ 76 #define NULL_VID 0 77 #define SPX5_MACT_PULL_DELAY (2 * HZ) 78 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 79 #define SPX5_PRIOS 8 /* Number of priority queues */ 80 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 81 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 82 83 #define XTR_QUEUE 0 84 #define INJ_QUEUE 0 85 86 #define FDMA_DCB_MAX 64 87 #define FDMA_RX_DCB_MAX_DBS 15 88 #define FDMA_TX_DCB_MAX_DBS 1 89 90 #define SPARX5_PHC_COUNT 3 91 #define SPARX5_PHC_PORT 0 92 93 #define IFH_REW_OP_NOOP 0x0 94 #define IFH_REW_OP_ONE_STEP_PTP 0x3 95 #define IFH_REW_OP_TWO_STEP_PTP 0x4 96 97 #define IFH_PDU_TYPE_NONE 0x0 98 #define IFH_PDU_TYPE_PTP 0x5 99 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 100 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 101 102 struct sparx5; 103 104 struct sparx5_db_hw { 105 u64 dataptr; 106 u64 status; 107 }; 108 109 struct sparx5_rx_dcb_hw { 110 u64 nextptr; 111 u64 info; 112 struct sparx5_db_hw db[FDMA_RX_DCB_MAX_DBS]; 113 }; 114 115 struct sparx5_tx_dcb_hw { 116 u64 nextptr; 117 u64 info; 118 struct sparx5_db_hw db[FDMA_TX_DCB_MAX_DBS]; 119 }; 120 121 /* Frame DMA receive state: 122 * For each DB, there is a SKB, and the skb data pointer is mapped in 123 * the DB. Once a frame is received the skb is given to the upper layers 124 * and a new skb is added to the dcb. 125 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 126 */ 127 struct sparx5_rx { 128 struct sparx5_rx_dcb_hw *dcb_entries; 129 struct sparx5_rx_dcb_hw *last_entry; 130 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 131 int db_index; 132 int dcb_index; 133 dma_addr_t dma; 134 struct napi_struct napi; 135 u32 channel_id; 136 struct net_device *ndev; 137 u64 packets; 138 }; 139 140 /* Frame DMA transmit state: 141 * DCBs are chained using the DCBs nextptr field. 142 */ 143 struct sparx5_tx { 144 struct sparx5_tx_dcb_hw *curr_entry; 145 struct sparx5_tx_dcb_hw *first_entry; 146 struct list_head db_list; 147 dma_addr_t dma; 148 u32 channel_id; 149 u64 packets; 150 u64 dropped; 151 }; 152 153 struct sparx5_port_config { 154 phy_interface_t portmode; 155 u32 bandwidth; 156 int speed; 157 int duplex; 158 enum phy_media media; 159 bool inband; 160 bool power_down; 161 bool autoneg; 162 bool serdes_reset; 163 u32 pause; 164 u32 pause_adv; 165 phy_interface_t phy_mode; 166 u32 sd_sgpio; 167 }; 168 169 struct sparx5_port { 170 struct net_device *ndev; 171 struct sparx5 *sparx5; 172 struct device_node *of_node; 173 struct phy *serdes; 174 struct sparx5_port_config conf; 175 struct phylink_config phylink_config; 176 struct phylink *phylink; 177 struct phylink_pcs phylink_pcs; 178 u16 portno; 179 /* Ingress default VLAN (pvid) */ 180 u16 pvid; 181 /* Egress default VLAN (vid) */ 182 u16 vid; 183 bool signd_internal; 184 bool signd_active_high; 185 bool signd_enable; 186 bool flow_control; 187 enum sparx5_port_max_tags max_vlan_tags; 188 enum sparx5_vlan_port_type vlan_type; 189 u32 custom_etype; 190 bool vlan_aware; 191 struct hrtimer inj_timer; 192 /* ptp */ 193 u8 ptp_cmd; 194 u16 ts_id; 195 struct sk_buff_head tx_skbs; 196 }; 197 198 enum sparx5_core_clockfreq { 199 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 200 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 201 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 202 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 203 }; 204 205 struct sparx5_phc { 206 struct ptp_clock *clock; 207 struct ptp_clock_info info; 208 struct hwtstamp_config hwtstamp_config; 209 struct sparx5 *sparx5; 210 u8 index; 211 }; 212 213 struct sparx5_skb_cb { 214 u8 rew_op; 215 u8 pdu_type; 216 u8 pdu_w16_offset; 217 u16 ts_id; 218 unsigned long jiffies; 219 }; 220 221 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 222 #define SPARX5_SKB_CB(skb) \ 223 ((struct sparx5_skb_cb *)((skb)->cb)) 224 225 struct sparx5 { 226 struct platform_device *pdev; 227 struct device *dev; 228 u32 chip_id; 229 enum spx5_target_chiptype target_ct; 230 void __iomem *regs[NUM_TARGETS]; 231 int port_count; 232 struct mutex lock; /* MAC reg lock */ 233 /* port structures are in net device */ 234 struct sparx5_port *ports[SPX5_PORTS]; 235 enum sparx5_core_clockfreq coreclock; 236 /* Statistics */ 237 u32 num_stats; 238 u32 num_ethtool_stats; 239 const char * const *stats_layout; 240 u64 *stats; 241 /* Workqueue for reading stats */ 242 struct mutex queue_stats_lock; 243 struct delayed_work stats_work; 244 struct workqueue_struct *stats_queue; 245 /* Notifiers */ 246 struct notifier_block netdevice_nb; 247 struct notifier_block switchdev_nb; 248 struct notifier_block switchdev_blocking_nb; 249 /* Switch state */ 250 u8 base_mac[ETH_ALEN]; 251 /* Associated bridge device (when bridged) */ 252 struct net_device *hw_bridge_dev; 253 /* Bridged interfaces */ 254 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 255 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 256 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 257 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 258 /* SW MAC table */ 259 struct list_head mact_entries; 260 /* mac table list (mact_entries) mutex */ 261 struct mutex mact_lock; 262 struct delayed_work mact_work; 263 struct workqueue_struct *mact_queue; 264 /* Board specifics */ 265 bool sd_sgpio_remapping; 266 /* Register based inj/xtr */ 267 int xtr_irq; 268 /* Frame DMA */ 269 int fdma_irq; 270 struct sparx5_rx rx; 271 struct sparx5_tx tx; 272 /* PTP */ 273 bool ptp; 274 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 275 spinlock_t ptp_clock_lock; /* lock for phc */ 276 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 277 struct mutex ptp_lock; /* lock for ptp interface state */ 278 u16 ptp_skbs; 279 int ptp_irq; 280 /* PGID allocation map */ 281 u8 pgid_map[PGID_TABLE_SIZE]; 282 }; 283 284 /* sparx5_switchdev.c */ 285 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 286 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 287 288 /* sparx5_packet.c */ 289 struct frame_info { 290 int src_port; 291 u32 timestamp; 292 }; 293 294 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 295 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 296 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 297 int sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 298 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 299 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 300 301 /* sparx5_fdma.c */ 302 int sparx5_fdma_start(struct sparx5 *sparx5); 303 int sparx5_fdma_stop(struct sparx5 *sparx5); 304 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 305 irqreturn_t sparx5_fdma_handler(int irq, void *args); 306 307 /* sparx5_mactable.c */ 308 void sparx5_mact_pull_work(struct work_struct *work); 309 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 310 const unsigned char mac[ETH_ALEN], u16 vid); 311 bool sparx5_mact_getnext(struct sparx5 *sparx5, 312 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 313 bool sparx5_mact_find(struct sparx5 *sparx5, 314 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 315 int sparx5_mact_forget(struct sparx5 *sparx5, 316 const unsigned char mac[ETH_ALEN], u16 vid); 317 int sparx5_add_mact_entry(struct sparx5 *sparx5, 318 struct net_device *dev, 319 u16 portno, 320 const unsigned char *addr, u16 vid); 321 int sparx5_del_mact_entry(struct sparx5 *sparx5, 322 const unsigned char *addr, 323 u16 vid); 324 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 325 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 326 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 327 void sparx5_mact_init(struct sparx5 *sparx5); 328 329 /* sparx5_vlan.c */ 330 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 331 void sparx5_update_fwd(struct sparx5 *sparx5); 332 void sparx5_vlan_init(struct sparx5 *sparx5); 333 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 334 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 335 bool untagged); 336 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 337 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 338 339 /* sparx5_calendar.c */ 340 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 341 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 342 343 /* sparx5_ethtool.c */ 344 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 345 int sparx_stats_init(struct sparx5 *sparx5); 346 347 /* sparx5_netdev.c */ 348 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 349 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 350 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 351 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 352 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 353 bool sparx5_netdevice_check(const struct net_device *dev); 354 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 355 int sparx5_register_netdevs(struct sparx5 *sparx5); 356 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 357 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 358 359 /* sparx5_ptp.c */ 360 int sparx5_ptp_init(struct sparx5 *sparx5); 361 void sparx5_ptp_deinit(struct sparx5 *sparx5); 362 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr); 363 int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr); 364 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 365 u64 timestamp); 366 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 367 struct sk_buff *skb); 368 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 369 struct sk_buff *skb); 370 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 371 372 /* sparx5_pgid.c */ 373 enum sparx5_pgid_type { 374 SPX5_PGID_FREE, 375 SPX5_PGID_RESERVED, 376 SPX5_PGID_MULTICAST, 377 SPX5_PGID_GLAG 378 }; 379 380 void sparx5_pgid_init(struct sparx5 *spx5); 381 int sparx5_pgid_alloc_glag(struct sparx5 *spx5, u16 *idx); 382 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 383 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 384 385 /* Clock period in picoseconds */ 386 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 387 { 388 switch (cclock) { 389 case SPX5_CORE_CLOCK_250MHZ: 390 return 4000; 391 case SPX5_CORE_CLOCK_500MHZ: 392 return 2000; 393 case SPX5_CORE_CLOCK_625MHZ: 394 default: 395 return 1600; 396 } 397 } 398 399 static inline bool sparx5_is_baser(phy_interface_t interface) 400 { 401 return interface == PHY_INTERFACE_MODE_5GBASER || 402 interface == PHY_INTERFACE_MODE_10GBASER || 403 interface == PHY_INTERFACE_MODE_25GBASER; 404 } 405 406 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 407 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 408 extern const struct ethtool_ops sparx5_ethtool_ops; 409 410 /* Calculate raw offset */ 411 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 412 int gbase, int ginst, 413 int gcnt, int gwidth, 414 int raddr, int rinst, 415 int rcnt, int rwidth) 416 { 417 WARN_ON((tinst) >= tcnt); 418 WARN_ON((ginst) >= gcnt); 419 WARN_ON((rinst) >= rcnt); 420 return gbase + ((ginst) * gwidth) + 421 raddr + ((rinst) * rwidth); 422 } 423 424 /* Read, Write and modify registers content. 425 * The register definition macros start at the id 426 */ 427 static inline void __iomem *spx5_addr(void __iomem *base[], 428 int id, int tinst, int tcnt, 429 int gbase, int ginst, 430 int gcnt, int gwidth, 431 int raddr, int rinst, 432 int rcnt, int rwidth) 433 { 434 WARN_ON((tinst) >= tcnt); 435 WARN_ON((ginst) >= gcnt); 436 WARN_ON((rinst) >= rcnt); 437 return base[id + (tinst)] + 438 gbase + ((ginst) * gwidth) + 439 raddr + ((rinst) * rwidth); 440 } 441 442 static inline void __iomem *spx5_inst_addr(void __iomem *base, 443 int gbase, int ginst, 444 int gcnt, int gwidth, 445 int raddr, int rinst, 446 int rcnt, int rwidth) 447 { 448 WARN_ON((ginst) >= gcnt); 449 WARN_ON((rinst) >= rcnt); 450 return base + 451 gbase + ((ginst) * gwidth) + 452 raddr + ((rinst) * rwidth); 453 } 454 455 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 456 int gbase, int ginst, int gcnt, int gwidth, 457 int raddr, int rinst, int rcnt, int rwidth) 458 { 459 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 460 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 461 } 462 463 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 464 int gbase, int ginst, int gcnt, int gwidth, 465 int raddr, int rinst, int rcnt, int rwidth) 466 { 467 return readl(spx5_inst_addr(iomem, gbase, ginst, 468 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 469 } 470 471 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 472 int id, int tinst, int tcnt, 473 int gbase, int ginst, int gcnt, int gwidth, 474 int raddr, int rinst, int rcnt, int rwidth) 475 { 476 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 477 gbase, ginst, gcnt, gwidth, 478 raddr, rinst, rcnt, rwidth)); 479 } 480 481 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 482 int id, int tinst, int tcnt, 483 int gbase, int ginst, int gcnt, int gwidth, 484 int raddr, int rinst, int rcnt, int rwidth) 485 { 486 writel(val, spx5_inst_addr(iomem, 487 gbase, ginst, gcnt, gwidth, 488 raddr, rinst, rcnt, rwidth)); 489 } 490 491 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 492 int id, int tinst, int tcnt, 493 int gbase, int ginst, int gcnt, int gwidth, 494 int raddr, int rinst, int rcnt, int rwidth) 495 { 496 u32 nval; 497 498 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 499 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 500 nval = (nval & ~mask) | (val & mask); 501 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 502 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 503 } 504 505 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 506 int id, int tinst, int tcnt, 507 int gbase, int ginst, int gcnt, int gwidth, 508 int raddr, int rinst, int rcnt, int rwidth) 509 { 510 u32 nval; 511 512 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 513 rinst, rcnt, rwidth)); 514 nval = (nval & ~mask) | (val & mask); 515 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 516 rinst, rcnt, rwidth)); 517 } 518 519 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 520 { 521 return sparx5->regs[id + tinst]; 522 } 523 524 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 525 int id, int tinst, int tcnt, 526 int gbase, int ginst, int gcnt, int gwidth, 527 int raddr, int rinst, int rcnt, int rwidth) 528 { 529 return spx5_addr(sparx5->regs, id, tinst, tcnt, 530 gbase, ginst, gcnt, gwidth, 531 raddr, rinst, rcnt, rwidth); 532 } 533 534 #endif /* __SPARX5_MAIN_H__ */ 535