1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9 #include <linux/module.h> 10 #include <linux/device.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <net/switchdev.h> 18 #include <linux/etherdevice.h> 19 #include <linux/io.h> 20 #include <linux/printk.h> 21 #include <linux/iopoll.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/reset.h> 26 27 #include "sparx5_main_regs.h" 28 #include "sparx5_main.h" 29 #include "sparx5_port.h" 30 31 #define QLIM_WM(fraction) \ 32 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) 33 #define IO_RANGES 3 34 35 struct initial_port_config { 36 u32 portno; 37 struct device_node *node; 38 struct sparx5_port_config conf; 39 struct phy *serdes; 40 }; 41 42 struct sparx5_ram_config { 43 void __iomem *init_reg; 44 u32 init_val; 45 }; 46 47 struct sparx5_main_io_resource { 48 enum sparx5_target id; 49 phys_addr_t offset; 50 int range; 51 }; 52 53 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 54 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 55 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 56 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 57 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 58 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 59 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 60 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 61 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 62 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 63 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 64 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 65 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 66 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 67 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 68 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 69 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 70 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 71 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 72 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 73 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 74 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 75 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 76 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 77 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 78 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 79 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 80 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 81 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 82 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 83 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 84 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 85 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 86 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 87 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 88 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 89 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 90 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 91 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 92 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 93 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 94 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 95 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 96 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 97 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 98 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 99 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 100 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 101 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 102 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 103 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 104 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 105 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 106 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 107 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 108 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 109 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 110 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 111 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 112 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 113 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 114 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 115 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 116 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 117 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 118 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 119 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 120 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 121 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 122 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 123 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 124 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 125 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 126 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 127 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 128 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 129 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 130 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 131 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 132 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 133 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 134 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 135 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 136 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 137 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 138 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 139 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 140 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 141 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 142 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 143 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 144 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 145 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 146 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 147 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 148 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 149 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 150 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 151 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 152 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 153 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 154 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 155 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 156 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 157 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 158 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 159 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 160 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 161 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 162 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 163 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 164 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 165 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 166 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 167 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 168 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 169 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 170 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 171 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 172 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 173 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 174 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 175 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 176 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 177 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 178 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 179 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 180 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 181 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 182 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 183 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 184 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 185 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 186 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 187 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 188 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 189 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 190 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 191 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 192 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 193 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */ 194 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 195 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 196 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 197 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 198 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 199 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 200 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 201 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 202 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 203 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 204 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 205 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 206 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 207 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 208 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 209 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 210 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 211 }; 212 213 static int sparx5_create_targets(struct sparx5 *sparx5) 214 { 215 struct resource *iores[IO_RANGES]; 216 void __iomem *iomem[IO_RANGES]; 217 void __iomem *begin[IO_RANGES]; 218 int range_id[IO_RANGES]; 219 int idx, jdx; 220 221 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 222 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 223 224 if (idx == iomap->range) { 225 range_id[idx] = jdx; 226 idx++; 227 } 228 } 229 for (idx = 0; idx < IO_RANGES; idx++) { 230 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 231 idx); 232 if (!iores[idx]) { 233 dev_err(sparx5->dev, "Invalid resource\n"); 234 return -EINVAL; 235 } 236 iomem[idx] = devm_ioremap(sparx5->dev, 237 iores[idx]->start, 238 resource_size(iores[idx])); 239 if (!iomem[idx]) { 240 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 241 iores[idx]->name); 242 return -ENOMEM; 243 } 244 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; 245 } 246 for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { 247 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; 248 249 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; 250 } 251 return 0; 252 } 253 254 static int sparx5_create_port(struct sparx5 *sparx5, 255 struct initial_port_config *config) 256 { 257 struct sparx5_port *spx5_port; 258 struct net_device *ndev; 259 struct phylink *phylink; 260 int err; 261 262 ndev = sparx5_create_netdev(sparx5, config->portno); 263 if (IS_ERR(ndev)) { 264 dev_err(sparx5->dev, "Could not create net device: %02u\n", 265 config->portno); 266 return PTR_ERR(ndev); 267 } 268 spx5_port = netdev_priv(ndev); 269 spx5_port->of_node = config->node; 270 spx5_port->serdes = config->serdes; 271 spx5_port->pvid = NULL_VID; 272 spx5_port->signd_internal = true; 273 spx5_port->signd_active_high = true; 274 spx5_port->signd_enable = true; 275 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 276 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 277 spx5_port->custom_etype = 0x8880; /* Vitesse */ 278 spx5_port->phylink_pcs.poll = true; 279 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 280 sparx5->ports[config->portno] = spx5_port; 281 282 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 283 if (err) { 284 dev_err(sparx5->dev, "port init failed\n"); 285 return err; 286 } 287 spx5_port->conf = config->conf; 288 289 /* Setup VLAN */ 290 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 291 292 /* Create a phylink for PHY management. Also handles SFPs */ 293 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 294 spx5_port->phylink_config.type = PHYLINK_NETDEV; 295 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 296 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | 297 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; 298 299 __set_bit(PHY_INTERFACE_MODE_SGMII, 300 spx5_port->phylink_config.supported_interfaces); 301 __set_bit(PHY_INTERFACE_MODE_QSGMII, 302 spx5_port->phylink_config.supported_interfaces); 303 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 304 spx5_port->phylink_config.supported_interfaces); 305 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 306 spx5_port->phylink_config.supported_interfaces); 307 308 if (spx5_port->conf.bandwidth == SPEED_5000 || 309 spx5_port->conf.bandwidth == SPEED_10000 || 310 spx5_port->conf.bandwidth == SPEED_25000) 311 __set_bit(PHY_INTERFACE_MODE_5GBASER, 312 spx5_port->phylink_config.supported_interfaces); 313 314 if (spx5_port->conf.bandwidth == SPEED_10000 || 315 spx5_port->conf.bandwidth == SPEED_25000) 316 __set_bit(PHY_INTERFACE_MODE_10GBASER, 317 spx5_port->phylink_config.supported_interfaces); 318 319 if (spx5_port->conf.bandwidth == SPEED_25000) 320 __set_bit(PHY_INTERFACE_MODE_25GBASER, 321 spx5_port->phylink_config.supported_interfaces); 322 323 phylink = phylink_create(&spx5_port->phylink_config, 324 of_fwnode_handle(config->node), 325 config->conf.phy_mode, 326 &sparx5_phylink_mac_ops); 327 if (IS_ERR(phylink)) 328 return PTR_ERR(phylink); 329 330 spx5_port->phylink = phylink; 331 332 return 0; 333 } 334 335 static int sparx5_init_ram(struct sparx5 *s5) 336 { 337 const struct sparx5_ram_config spx5_ram_cfg[] = { 338 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 339 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 340 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 341 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 342 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 343 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 344 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 345 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 346 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 347 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 348 }; 349 const struct sparx5_ram_config *cfg; 350 u32 value, pending, jdx, idx; 351 352 for (jdx = 0; jdx < 10; jdx++) { 353 pending = ARRAY_SIZE(spx5_ram_cfg); 354 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 355 cfg = &spx5_ram_cfg[idx]; 356 if (jdx == 0) { 357 writel(cfg->init_val, cfg->init_reg); 358 } else { 359 value = readl(cfg->init_reg); 360 if ((value & cfg->init_val) != cfg->init_val) 361 pending--; 362 } 363 } 364 if (!pending) 365 break; 366 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 367 } 368 369 if (pending > 0) { 370 /* Still initializing, should be complete in 371 * less than 1ms 372 */ 373 dev_err(s5->dev, "Memory initialization error\n"); 374 return -EINVAL; 375 } 376 return 0; 377 } 378 379 static int sparx5_init_switchcore(struct sparx5 *sparx5) 380 { 381 u32 value; 382 int err = 0; 383 384 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 385 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 386 sparx5, 387 EACL_POL_EACL_CFG); 388 389 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 390 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 391 sparx5, 392 EACL_POL_EACL_CFG); 393 394 /* Initialize memories, if not done already */ 395 value = spx5_rd(sparx5, HSCH_RESET_CFG); 396 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 397 err = sparx5_init_ram(sparx5); 398 if (err) 399 return err; 400 } 401 402 /* Reset counters */ 403 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 404 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 405 406 /* Enable switch-core and queue system */ 407 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 408 409 return 0; 410 } 411 412 static int sparx5_init_coreclock(struct sparx5 *sparx5) 413 { 414 enum sparx5_core_clockfreq freq = sparx5->coreclock; 415 u32 clk_div, clk_period, pol_upd_int, idx; 416 417 /* Verify if core clock frequency is supported on target. 418 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 419 * freq. is used 420 */ 421 switch (sparx5->target_ct) { 422 case SPX5_TARGET_CT_7546: 423 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 424 freq = SPX5_CORE_CLOCK_250MHZ; 425 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 426 freq = 0; /* Not supported */ 427 break; 428 case SPX5_TARGET_CT_7549: 429 case SPX5_TARGET_CT_7552: 430 case SPX5_TARGET_CT_7556: 431 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 432 freq = SPX5_CORE_CLOCK_500MHZ; 433 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 434 freq = 0; /* Not supported */ 435 break; 436 case SPX5_TARGET_CT_7558: 437 case SPX5_TARGET_CT_7558TSN: 438 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 439 freq = SPX5_CORE_CLOCK_625MHZ; 440 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 441 freq = 0; /* Not supported */ 442 break; 443 case SPX5_TARGET_CT_7546TSN: 444 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 445 freq = SPX5_CORE_CLOCK_625MHZ; 446 break; 447 case SPX5_TARGET_CT_7549TSN: 448 case SPX5_TARGET_CT_7552TSN: 449 case SPX5_TARGET_CT_7556TSN: 450 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 451 freq = SPX5_CORE_CLOCK_625MHZ; 452 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 453 freq = 0; /* Not supported */ 454 break; 455 default: 456 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 457 sparx5->target_ct); 458 return -ENODEV; 459 } 460 461 switch (freq) { 462 case SPX5_CORE_CLOCK_250MHZ: 463 clk_div = 10; 464 pol_upd_int = 312; 465 break; 466 case SPX5_CORE_CLOCK_500MHZ: 467 clk_div = 5; 468 pol_upd_int = 624; 469 break; 470 case SPX5_CORE_CLOCK_625MHZ: 471 clk_div = 4; 472 pol_upd_int = 780; 473 break; 474 default: 475 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", 476 sparx5->coreclock, sparx5->target_ct); 477 return -EINVAL; 478 } 479 480 /* Update state with chosen frequency */ 481 sparx5->coreclock = freq; 482 483 /* Configure the LCPLL */ 484 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 485 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 486 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 487 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 488 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 489 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 490 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 491 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 492 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 493 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 494 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 495 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 496 sparx5, 497 CLKGEN_LCPLL1_CORE_CLK_CFG); 498 499 clk_period = sparx5_clk_period(freq); 500 501 spx5_rmw(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(clk_period / 100), 502 HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, 503 sparx5, 504 HSCH_SYS_CLK_PER); 505 506 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 507 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 508 sparx5, 509 ANA_AC_POL_BDLB_DLB_CTRL); 510 511 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 512 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 513 sparx5, 514 ANA_AC_POL_SLB_DLB_CTRL); 515 516 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 517 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 518 sparx5, 519 LRN_AUTOAGE_CFG_1); 520 521 for (idx = 0; idx < 3; idx++) 522 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 523 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 524 sparx5, 525 GCB_SIO_CLOCK(idx)); 526 527 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 528 ((256 * 1000) / clk_period), 529 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 530 sparx5, 531 HSCH_TAS_STATEMACHINE_CFG); 532 533 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 534 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 535 sparx5, 536 ANA_AC_POL_POL_UPD_INT_CFG); 537 538 return 0; 539 } 540 541 static int sparx5_qlim_set(struct sparx5 *sparx5) 542 { 543 u32 res, dp, prio; 544 545 for (res = 0; res < 2; res++) { 546 for (prio = 0; prio < 8; prio++) 547 spx5_wr(0xFFF, sparx5, 548 QRES_RES_CFG(prio + 630 + res * 1024)); 549 550 for (dp = 0; dp < 4; dp++) 551 spx5_wr(0xFFF, sparx5, 552 QRES_RES_CFG(dp + 638 + res * 1024)); 553 } 554 555 /* Set 80,90,95,100% of memory size for top watermarks */ 556 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 557 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 558 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 559 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 560 561 return 0; 562 } 563 564 /* Some boards needs to map the SGPIO for signal detect explicitly to the 565 * port module 566 */ 567 static void sparx5_board_init(struct sparx5 *sparx5) 568 { 569 int idx; 570 571 if (!sparx5->sd_sgpio_remapping) 572 return; 573 574 /* Enable SGPIO Signal Detect remapping */ 575 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 576 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 577 sparx5, 578 GCB_HW_SGPIO_SD_CFG); 579 580 /* Refer to LOS SGPIO */ 581 for (idx = 0; idx < SPX5_PORTS; idx++) 582 if (sparx5->ports[idx]) 583 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 584 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 585 sparx5, 586 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 587 } 588 589 static int sparx5_start(struct sparx5 *sparx5) 590 { 591 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 592 char queue_name[32]; 593 u32 idx; 594 int err; 595 596 /* Setup own UPSIDs */ 597 for (idx = 0; idx < 3; idx++) { 598 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 599 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 600 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 601 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 602 } 603 604 /* Enable CPU ports */ 605 for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) 606 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 607 QFWD_SWITCH_PORT_MODE_PORT_ENA, 608 sparx5, 609 QFWD_SWITCH_PORT_MODE(idx)); 610 611 /* Init masks */ 612 sparx5_update_fwd(sparx5); 613 614 /* CPU copy CPU pgids */ 615 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 616 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); 617 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), 618 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); 619 620 /* Recalc injected frame FCS */ 621 for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) 622 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 623 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 624 sparx5, ANA_CL_FILTER_CTRL(idx)); 625 626 /* Init MAC table, ageing */ 627 sparx5_mact_init(sparx5); 628 629 /* Init PGID table arbitrator */ 630 sparx5_pgid_init(sparx5); 631 632 /* Setup VLANs */ 633 sparx5_vlan_init(sparx5); 634 635 /* Add host mode BC address (points only to CPU) */ 636 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); 637 638 /* Enable queue limitation watermarks */ 639 sparx5_qlim_set(sparx5); 640 641 err = sparx5_config_auto_calendar(sparx5); 642 if (err) 643 return err; 644 645 err = sparx5_config_dsm_calendar(sparx5); 646 if (err) 647 return err; 648 649 /* Init stats */ 650 err = sparx_stats_init(sparx5); 651 if (err) 652 return err; 653 654 /* Init mact_sw struct */ 655 mutex_init(&sparx5->mact_lock); 656 INIT_LIST_HEAD(&sparx5->mact_entries); 657 snprintf(queue_name, sizeof(queue_name), "%s-mact", 658 dev_name(sparx5->dev)); 659 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 660 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 661 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 662 SPX5_MACT_PULL_DELAY); 663 664 err = sparx5_register_netdevs(sparx5); 665 if (err) 666 return err; 667 668 sparx5_board_init(sparx5); 669 err = sparx5_register_notifier_blocks(sparx5); 670 671 /* Start Frame DMA with fallback to register based INJ/XTR */ 672 err = -ENXIO; 673 if (sparx5->fdma_irq >= 0) { 674 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) 675 err = devm_request_threaded_irq(sparx5->dev, 676 sparx5->fdma_irq, 677 NULL, 678 sparx5_fdma_handler, 679 IRQF_ONESHOT, 680 "sparx5-fdma", sparx5); 681 if (!err) 682 err = sparx5_fdma_start(sparx5); 683 if (err) 684 sparx5->fdma_irq = -ENXIO; 685 } else { 686 sparx5->fdma_irq = -ENXIO; 687 } 688 if (err && sparx5->xtr_irq >= 0) { 689 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 690 sparx5_xtr_handler, IRQF_SHARED, 691 "sparx5-xtr", sparx5); 692 if (!err) 693 err = sparx5_manual_injection_mode(sparx5); 694 if (err) 695 sparx5->xtr_irq = -ENXIO; 696 } else { 697 sparx5->xtr_irq = -ENXIO; 698 } 699 700 if (sparx5->ptp_irq >= 0) { 701 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 702 NULL, sparx5_ptp_irq_handler, 703 IRQF_ONESHOT, "sparx5-ptp", 704 sparx5); 705 if (err) 706 sparx5->ptp_irq = -ENXIO; 707 708 sparx5->ptp = 1; 709 } 710 711 return err; 712 } 713 714 static void sparx5_cleanup_ports(struct sparx5 *sparx5) 715 { 716 sparx5_unregister_netdevs(sparx5); 717 sparx5_destroy_netdevs(sparx5); 718 } 719 720 static int mchp_sparx5_probe(struct platform_device *pdev) 721 { 722 struct initial_port_config *configs, *config; 723 struct device_node *np = pdev->dev.of_node; 724 struct device_node *ports, *portnp; 725 struct reset_control *reset; 726 struct sparx5 *sparx5; 727 int idx = 0, err = 0; 728 729 if (!np && !pdev->dev.platform_data) 730 return -ENODEV; 731 732 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 733 if (!sparx5) 734 return -ENOMEM; 735 736 platform_set_drvdata(pdev, sparx5); 737 sparx5->pdev = pdev; 738 sparx5->dev = &pdev->dev; 739 740 /* Do switch core reset if available */ 741 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 742 if (IS_ERR(reset)) 743 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 744 "Failed to get switch reset controller.\n"); 745 reset_control_reset(reset); 746 747 /* Default values, some from DT */ 748 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 749 750 ports = of_get_child_by_name(np, "ethernet-ports"); 751 if (!ports) { 752 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 753 return -ENODEV; 754 } 755 sparx5->port_count = of_get_child_count(ports); 756 757 configs = kcalloc(sparx5->port_count, 758 sizeof(struct initial_port_config), GFP_KERNEL); 759 if (!configs) { 760 err = -ENOMEM; 761 goto cleanup_pnode; 762 } 763 764 for_each_available_child_of_node(ports, portnp) { 765 struct sparx5_port_config *conf; 766 struct phy *serdes; 767 u32 portno; 768 769 err = of_property_read_u32(portnp, "reg", &portno); 770 if (err) { 771 dev_err(sparx5->dev, "port reg property error\n"); 772 continue; 773 } 774 config = &configs[idx]; 775 conf = &config->conf; 776 conf->speed = SPEED_UNKNOWN; 777 conf->bandwidth = SPEED_UNKNOWN; 778 err = of_get_phy_mode(portnp, &conf->phy_mode); 779 if (err) { 780 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 781 portno); 782 continue; 783 } 784 err = of_property_read_u32(portnp, "microchip,bandwidth", 785 &conf->bandwidth); 786 if (err) { 787 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 788 portno); 789 continue; 790 } 791 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 792 if (err) 793 conf->sd_sgpio = ~0; 794 else 795 sparx5->sd_sgpio_remapping = true; 796 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 797 if (IS_ERR(serdes)) { 798 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), 799 "port %u: missing serdes\n", 800 portno); 801 of_node_put(portnp); 802 goto cleanup_config; 803 } 804 config->portno = portno; 805 config->node = portnp; 806 config->serdes = serdes; 807 808 conf->media = PHY_MEDIA_DAC; 809 conf->serdes_reset = true; 810 conf->portmode = conf->phy_mode; 811 conf->power_down = true; 812 idx++; 813 } 814 815 err = sparx5_create_targets(sparx5); 816 if (err) 817 goto cleanup_config; 818 819 if (!of_get_mac_address(np, sparx5->base_mac)) { 820 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 821 eth_random_addr(sparx5->base_mac); 822 sparx5->base_mac[5] = 0; 823 } 824 825 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 826 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 827 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); 828 829 /* Read chip ID to check CPU interface */ 830 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 831 832 sparx5->target_ct = (enum spx5_target_chiptype) 833 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 834 835 /* Initialize Switchcore and internal RAMs */ 836 err = sparx5_init_switchcore(sparx5); 837 if (err) { 838 dev_err(sparx5->dev, "Switchcore initialization error\n"); 839 goto cleanup_config; 840 } 841 842 /* Initialize the LC-PLL (core clock) and set affected registers */ 843 err = sparx5_init_coreclock(sparx5); 844 if (err) { 845 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 846 goto cleanup_config; 847 } 848 849 for (idx = 0; idx < sparx5->port_count; ++idx) { 850 config = &configs[idx]; 851 if (!config->node) 852 continue; 853 854 err = sparx5_create_port(sparx5, config); 855 if (err) { 856 dev_err(sparx5->dev, "port create error\n"); 857 goto cleanup_ports; 858 } 859 } 860 861 err = sparx5_start(sparx5); 862 if (err) { 863 dev_err(sparx5->dev, "Start failed\n"); 864 goto cleanup_ports; 865 } 866 867 err = sparx5_ptp_init(sparx5); 868 if (err) { 869 dev_err(sparx5->dev, "PTP failed\n"); 870 goto cleanup_ports; 871 } 872 goto cleanup_config; 873 874 cleanup_ports: 875 sparx5_cleanup_ports(sparx5); 876 cleanup_config: 877 kfree(configs); 878 cleanup_pnode: 879 of_node_put(ports); 880 return err; 881 } 882 883 static int mchp_sparx5_remove(struct platform_device *pdev) 884 { 885 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 886 887 if (sparx5->xtr_irq) { 888 disable_irq(sparx5->xtr_irq); 889 sparx5->xtr_irq = -ENXIO; 890 } 891 if (sparx5->fdma_irq) { 892 disable_irq(sparx5->fdma_irq); 893 sparx5->fdma_irq = -ENXIO; 894 } 895 sparx5_ptp_deinit(sparx5); 896 sparx5_fdma_stop(sparx5); 897 sparx5_cleanup_ports(sparx5); 898 /* Unregister netdevs */ 899 sparx5_unregister_notifier_blocks(sparx5); 900 901 return 0; 902 } 903 904 static const struct of_device_id mchp_sparx5_match[] = { 905 { .compatible = "microchip,sparx5-switch" }, 906 { } 907 }; 908 MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 909 910 static struct platform_driver mchp_sparx5_driver = { 911 .probe = mchp_sparx5_probe, 912 .remove = mchp_sparx5_remove, 913 .driver = { 914 .name = "sparx5-switch", 915 .of_match_table = mchp_sparx5_match, 916 }, 917 }; 918 919 module_platform_driver(mchp_sparx5_driver); 920 921 MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 922 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 923 MODULE_LICENSE("Dual MIT/GPL"); 924